Commit 7b0a9e83 authored by Dave Airlie's avatar Dave Airlie

Merge remote branch 'korg/drm-radeon-dp' into drm-linus

This merges the radeon KMS DisplayPort and hotplug detect support.

Tested on RV635 DP card with a Dell 2408 monitor.

Conflicts:
	drivers/gpu/drm/drm_fb_helper.c
parents 3f838fc5 d4877cf2
...@@ -49,7 +49,7 @@ radeon-y += radeon_device.o radeon_kms.o \ ...@@ -49,7 +49,7 @@ radeon-y += radeon_device.o radeon_kms.o \
radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
r600_blit_kms.o radeon_pm.o r600_blit_kms.o radeon_pm.o atombios_dp.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
......
...@@ -263,10 +263,10 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, ...@@ -263,10 +263,10 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
case ATOM_ARG_FB: case ATOM_ARG_FB:
idx = U8(*ptr); idx = U8(*ptr);
(*ptr)++; (*ptr)++;
val = gctx->scratch[((gctx->fb_base + idx) / 4)];
if (print) if (print)
DEBUG("FB[0x%02X]", idx); DEBUG("FB[0x%02X]", idx);
printk(KERN_INFO "FB access is not implemented.\n"); break;
return 0;
case ATOM_ARG_IMM: case ATOM_ARG_IMM:
switch (align) { switch (align) {
case ATOM_SRC_DWORD: case ATOM_SRC_DWORD:
...@@ -488,9 +488,9 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, ...@@ -488,9 +488,9 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
case ATOM_ARG_FB: case ATOM_ARG_FB:
idx = U8(*ptr); idx = U8(*ptr);
(*ptr)++; (*ptr)++;
gctx->scratch[((gctx->fb_base + idx) / 4)] = val;
DEBUG("FB[0x%02X]", idx); DEBUG("FB[0x%02X]", idx);
printk(KERN_INFO "FB access is not implemented.\n"); break;
return;
case ATOM_ARG_PLL: case ATOM_ARG_PLL:
idx = U8(*ptr); idx = U8(*ptr);
(*ptr)++; (*ptr)++;
...@@ -1214,3 +1214,28 @@ void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev, ...@@ -1214,3 +1214,28 @@ void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
*crev = CU8(idx + 3); *crev = CU8(idx + 3);
return; return;
} }
int atom_allocate_fb_scratch(struct atom_context *ctx)
{
int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
uint16_t data_offset;
int usage_bytes;
struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
DRM_DEBUG("atom firmware requested %08x %dkb\n",
firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware,
firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb);
usage_bytes = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024;
if (usage_bytes == 0)
usage_bytes = 20 * 1024;
/* allocate some scratch memory */
ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
if (!ctx->scratch)
return -ENOMEM;
return 0;
}
...@@ -132,6 +132,7 @@ struct atom_context { ...@@ -132,6 +132,7 @@ struct atom_context {
uint8_t shift; uint8_t shift;
int cs_equal, cs_above; int cs_equal, cs_above;
int io_mode; int io_mode;
uint32_t *scratch;
}; };
extern int atom_debug; extern int atom_debug;
...@@ -142,6 +143,7 @@ int atom_asic_init(struct atom_context *); ...@@ -142,6 +143,7 @@ int atom_asic_init(struct atom_context *);
void atom_destroy(struct atom_context *); void atom_destroy(struct atom_context *);
void atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size, uint8_t *frev, uint8_t *crev, uint16_t *data_start); void atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size, uint8_t *frev, uint8_t *crev, uint16_t *data_start);
void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev, uint8_t *crev); void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev, uint8_t *crev);
int atom_allocate_fb_scratch(struct atom_context *ctx);
#include "atom-types.h" #include "atom-types.h"
#include "atombios.h" #include "atombios.h"
#include "ObjectID.h" #include "ObjectID.h"
......
...@@ -2680,7 +2680,7 @@ typedef struct _ATOM_I2C_RECORD { ...@@ -2680,7 +2680,7 @@ typedef struct _ATOM_I2C_RECORD {
typedef struct _ATOM_HPD_INT_RECORD { typedef struct _ATOM_HPD_INT_RECORD {
ATOM_COMMON_RECORD_HEADER sheader; ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucHPDIntGPIOID; /* Corresponding block in GPIO_PIN_INFO table gives the pin info */ UCHAR ucHPDIntGPIOID; /* Corresponding block in GPIO_PIN_INFO table gives the pin info */
UCHAR ucPluggged_PinState; UCHAR ucPlugged_PinState;
} ATOM_HPD_INT_RECORD; } ATOM_HPD_INT_RECORD;
typedef struct _ATOM_OUTPUT_PROTECTION_RECORD { typedef struct _ATOM_OUTPUT_PROTECTION_RECORD {
......
This diff is collapsed.
...@@ -65,6 +65,95 @@ MODULE_FIRMWARE(FIRMWARE_R520); ...@@ -65,6 +65,95 @@ MODULE_FIRMWARE(FIRMWARE_R520);
* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
*/ */
/* hpd for digital panel detect/disconnect */
bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
{
bool connected = false;
switch (hpd) {
case RADEON_HPD_1:
if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
connected = true;
break;
case RADEON_HPD_2:
if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
connected = true;
break;
default:
break;
}
return connected;
}
void r100_hpd_set_polarity(struct radeon_device *rdev,
enum radeon_hpd_id hpd)
{
u32 tmp;
bool connected = r100_hpd_sense(rdev, hpd);
switch (hpd) {
case RADEON_HPD_1:
tmp = RREG32(RADEON_FP_GEN_CNTL);
if (connected)
tmp &= ~RADEON_FP_DETECT_INT_POL;
else
tmp |= RADEON_FP_DETECT_INT_POL;
WREG32(RADEON_FP_GEN_CNTL, tmp);
break;
case RADEON_HPD_2:
tmp = RREG32(RADEON_FP2_GEN_CNTL);
if (connected)
tmp &= ~RADEON_FP2_DETECT_INT_POL;
else
tmp |= RADEON_FP2_DETECT_INT_POL;
WREG32(RADEON_FP2_GEN_CNTL, tmp);
break;
default:
break;
}
}
void r100_hpd_init(struct radeon_device *rdev)
{
struct drm_device *dev = rdev->ddev;
struct drm_connector *connector;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
switch (radeon_connector->hpd.hpd) {
case RADEON_HPD_1:
rdev->irq.hpd[0] = true;
break;
case RADEON_HPD_2:
rdev->irq.hpd[1] = true;
break;
default:
break;
}
}
r100_irq_set(rdev);
}
void r100_hpd_fini(struct radeon_device *rdev)
{
struct drm_device *dev = rdev->ddev;
struct drm_connector *connector;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
switch (radeon_connector->hpd.hpd) {
case RADEON_HPD_1:
rdev->irq.hpd[0] = false;
break;
case RADEON_HPD_2:
rdev->irq.hpd[1] = false;
break;
default:
break;
}
}
}
/* /*
* PCI GART * PCI GART
*/ */
...@@ -163,6 +252,12 @@ int r100_irq_set(struct radeon_device *rdev) ...@@ -163,6 +252,12 @@ int r100_irq_set(struct radeon_device *rdev)
if (rdev->irq.crtc_vblank_int[1]) { if (rdev->irq.crtc_vblank_int[1]) {
tmp |= RADEON_CRTC2_VBLANK_MASK; tmp |= RADEON_CRTC2_VBLANK_MASK;
} }
if (rdev->irq.hpd[0]) {
tmp |= RADEON_FP_DETECT_MASK;
}
if (rdev->irq.hpd[1]) {
tmp |= RADEON_FP2_DETECT_MASK;
}
WREG32(RADEON_GEN_INT_CNTL, tmp); WREG32(RADEON_GEN_INT_CNTL, tmp);
return 0; return 0;
} }
...@@ -181,8 +276,9 @@ void r100_irq_disable(struct radeon_device *rdev) ...@@ -181,8 +276,9 @@ void r100_irq_disable(struct radeon_device *rdev)
static inline uint32_t r100_irq_ack(struct radeon_device *rdev) static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
{ {
uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT | uint32_t irq_mask = RADEON_SW_INT_TEST |
RADEON_CRTC2_VBLANK_STAT; RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
if (irqs) { if (irqs) {
WREG32(RADEON_GEN_INT_STATUS, irqs); WREG32(RADEON_GEN_INT_STATUS, irqs);
...@@ -193,6 +289,7 @@ static inline uint32_t r100_irq_ack(struct radeon_device *rdev) ...@@ -193,6 +289,7 @@ static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
int r100_irq_process(struct radeon_device *rdev) int r100_irq_process(struct radeon_device *rdev)
{ {
uint32_t status, msi_rearm; uint32_t status, msi_rearm;
bool queue_hotplug = false;
status = r100_irq_ack(rdev); status = r100_irq_ack(rdev);
if (!status) { if (!status) {
...@@ -213,8 +310,18 @@ int r100_irq_process(struct radeon_device *rdev) ...@@ -213,8 +310,18 @@ int r100_irq_process(struct radeon_device *rdev)
if (status & RADEON_CRTC2_VBLANK_STAT) { if (status & RADEON_CRTC2_VBLANK_STAT) {
drm_handle_vblank(rdev->ddev, 1); drm_handle_vblank(rdev->ddev, 1);
} }
if (status & RADEON_FP_DETECT_STAT) {
queue_hotplug = true;
DRM_DEBUG("HPD1\n");
}
if (status & RADEON_FP2_DETECT_STAT) {
queue_hotplug = true;
DRM_DEBUG("HPD2\n");
}
status = r100_irq_ack(rdev); status = r100_irq_ack(rdev);
} }
if (queue_hotplug)
queue_work(rdev->wq, &rdev->hotplug_work);
if (rdev->msi_enabled) { if (rdev->msi_enabled) {
switch (rdev->family) { switch (rdev->family) {
case CHIP_RS400: case CHIP_RS400:
......
...@@ -716,6 +716,8 @@ ...@@ -716,6 +716,8 @@
#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988
#define AVIVO_DC_GPIO_HPD_A 0x7e94
#define AVIVO_GPIO_0 0x7e30 #define AVIVO_GPIO_0 0x7e30
#define AVIVO_GPIO_1 0x7e40 #define AVIVO_GPIO_1 0x7e40
#define AVIVO_GPIO_2 0x7e50 #define AVIVO_GPIO_2 0x7e50
......
This diff is collapsed.
...@@ -558,6 +558,7 @@ ...@@ -558,6 +558,7 @@
# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)
# define DC_I2C_SW_DONE_INTERRUPT (1 << 20) # define DC_I2C_SW_DONE_INTERRUPT (1 << 20)
# define DC_I2C_HW_DONE_INTERRUPT (1 << 21) # define DC_I2C_HW_DONE_INTERRUPT (1 << 21)
#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8
#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8
# define DC_HPD4_INTERRUPT (1 << 14) # define DC_HPD4_INTERRUPT (1 << 14)
# define DC_HPD4_RX_INTERRUPT (1 << 15) # define DC_HPD4_RX_INTERRUPT (1 << 15)
...@@ -590,6 +591,18 @@ ...@@ -590,6 +591,18 @@
# define DC_HPD6_INTERRUPT (1 << 21) # define DC_HPD6_INTERRUPT (1 << 21)
# define DC_HPD6_RX_INTERRUPT (1 << 22) # define DC_HPD6_RX_INTERRUPT (1 << 22)
#define DACA_AUTO_DETECT_CONTROL 0x7828
#define DACB_AUTO_DETECT_CONTROL 0x7a28
#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028
#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128
# define DACx_AUTODETECT_MODE(x) ((x) << 0)
# define DACx_AUTODETECT_MODE_NONE 0
# define DACx_AUTODETECT_MODE_CONNECT 1
# define DACx_AUTODETECT_MODE_DISCONNECT 2
# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)
/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */
# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)
#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038
#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138
#define DACA_AUTODETECT_INT_CONTROL 0x7838 #define DACA_AUTODETECT_INT_CONTROL 0x7838
...@@ -597,23 +610,62 @@ ...@@ -597,23 +610,62 @@
# define DACx_AUTODETECT_ACK (1 << 0) # define DACx_AUTODETECT_ACK (1 << 0)
# define DACx_AUTODETECT_INT_ENABLE (1 << 16) # define DACx_AUTODETECT_INT_ENABLE (1 << 16)
#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00
#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10
#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24
# define DC_HOT_PLUG_DETECTx_EN (1 << 0)
#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04
#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14
#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28
# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)
# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)
/* DCE 3.0 */
#define DC_HPD1_INT_STATUS 0x7d00
#define DC_HPD2_INT_STATUS 0x7d0c
#define DC_HPD3_INT_STATUS 0x7d18
#define DC_HPD4_INT_STATUS 0x7d24
/* DCE 3.2 */
#define DC_HPD5_INT_STATUS 0x7dc0
#define DC_HPD6_INT_STATUS 0x7df4
# define DC_HPDx_INT_STATUS (1 << 0)
# define DC_HPDx_SENSE (1 << 1)
# define DC_HPDx_RX_INT_STATUS (1 << 8)
#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08
#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18
#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c
# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)
# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)
# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)
/* DCE 3.2 */ /* DCE 3.0 */
#define DC_HPD1_INT_CONTROL 0x7d04 #define DC_HPD1_INT_CONTROL 0x7d04
#define DC_HPD2_INT_CONTROL 0x7d10 #define DC_HPD2_INT_CONTROL 0x7d10
#define DC_HPD3_INT_CONTROL 0x7d1c #define DC_HPD3_INT_CONTROL 0x7d1c
#define DC_HPD4_INT_CONTROL 0x7d28 #define DC_HPD4_INT_CONTROL 0x7d28
/* DCE 3.2 */
#define DC_HPD5_INT_CONTROL 0x7dc4
#define DC_HPD6_INT_CONTROL 0x7df8
# define DC_HPDx_INT_ACK (1 << 0) # define DC_HPDx_INT_ACK (1 << 0)
# define DC_HPDx_INT_POLARITY (1 << 8) # define DC_HPDx_INT_POLARITY (1 << 8)
# define DC_HPDx_INT_EN (1 << 16) # define DC_HPDx_INT_EN (1 << 16)
# define DC_HPDx_RX_INT_ACK (1 << 20) # define DC_HPDx_RX_INT_ACK (1 << 20)
# define DC_HPDx_RX_INT_EN (1 << 24) # define DC_HPDx_RX_INT_EN (1 << 24)
/* DCE 3.0 */
#define DC_HPD1_CONTROL 0x7d08
#define DC_HPD2_CONTROL 0x7d14
#define DC_HPD3_CONTROL 0x7d20
#define DC_HPD4_CONTROL 0x7d2c
/* DCE 3.2 */
#define DC_HPD5_CONTROL 0x7dc8
#define DC_HPD6_CONTROL 0x7dfc
# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
/* DCE 3.2 */
# define DC_HPDx_EN (1 << 28)
/* /*
* PM4 * PM4
*/ */
......
...@@ -339,6 +339,8 @@ struct radeon_irq { ...@@ -339,6 +339,8 @@ struct radeon_irq {
bool sw_int; bool sw_int;
/* FIXME: use a define max crtc rather than hardcode it */ /* FIXME: use a define max crtc rather than hardcode it */
bool crtc_vblank_int[2]; bool crtc_vblank_int[2];
/* FIXME: use defines for max hpd/dacs */
bool hpd[6];
spinlock_t sw_lock; spinlock_t sw_lock;
int sw_refcount; int sw_refcount;
}; };
...@@ -647,6 +649,10 @@ struct radeon_asic { ...@@ -647,6 +649,10 @@ struct radeon_asic {
int (*clear_surface_reg)(struct radeon_device *rdev, int reg); int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
void (*bandwidth_update)(struct radeon_device *rdev); void (*bandwidth_update)(struct radeon_device *rdev);
void (*hdp_flush)(struct radeon_device *rdev); void (*hdp_flush)(struct radeon_device *rdev);
void (*hpd_init)(struct radeon_device *rdev);
void (*hpd_fini)(struct radeon_device *rdev);
bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
}; };
/* /*
...@@ -803,6 +809,8 @@ struct radeon_device { ...@@ -803,6 +809,8 @@ struct radeon_device {
struct r600_blit r600_blit; struct r600_blit r600_blit;
int msi_enabled; /* msi enabled */ int msi_enabled; /* msi enabled */
struct r600_ih ih; /* r6/700 interrupt ring */ struct r600_ih ih; /* r6/700 interrupt ring */
struct workqueue_struct *wq;
struct work_struct hotplug_work;
}; };
int radeon_device_init(struct radeon_device *rdev, int radeon_device_init(struct radeon_device *rdev,
...@@ -986,6 +994,10 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) ...@@ -986,6 +994,10 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev)) #define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
/* Common functions */ /* Common functions */
extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
......
...@@ -77,6 +77,11 @@ void r100_bandwidth_update(struct radeon_device *rdev); ...@@ -77,6 +77,11 @@ void r100_bandwidth_update(struct radeon_device *rdev);
void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
int r100_ring_test(struct radeon_device *rdev); int r100_ring_test(struct radeon_device *rdev);
void r100_hdp_flush(struct radeon_device *rdev); void r100_hdp_flush(struct radeon_device *rdev);
void r100_hpd_init(struct radeon_device *rdev);
void r100_hpd_fini(struct radeon_device *rdev);
bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void r100_hpd_set_polarity(struct radeon_device *rdev,
enum radeon_hpd_id hpd);
static struct radeon_asic r100_asic = { static struct radeon_asic r100_asic = {
.init = &r100_init, .init = &r100_init,
...@@ -109,6 +114,10 @@ static struct radeon_asic r100_asic = { ...@@ -109,6 +114,10 @@ static struct radeon_asic r100_asic = {
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.bandwidth_update = &r100_bandwidth_update, .bandwidth_update = &r100_bandwidth_update,
.hdp_flush = &r100_hdp_flush, .hdp_flush = &r100_hdp_flush,
.hpd_init = &r100_hpd_init,
.hpd_fini = &r100_hpd_fini,
.hpd_sense = &r100_hpd_sense,
.hpd_set_polarity = &r100_hpd_set_polarity,
}; };
...@@ -165,6 +174,10 @@ static struct radeon_asic r300_asic = { ...@@ -165,6 +174,10 @@ static struct radeon_asic r300_asic = {
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.bandwidth_update = &r100_bandwidth_update, .bandwidth_update = &r100_bandwidth_update,
.hdp_flush = &r100_hdp_flush, .hdp_flush = &r100_hdp_flush,
.hpd_init = &r100_hpd_init,
.hpd_fini = &r100_hpd_fini,
.hpd_sense = &r100_hpd_sense,
.hpd_set_polarity = &r100_hpd_set_polarity,
}; };
/* /*
...@@ -205,6 +218,10 @@ static struct radeon_asic r420_asic = { ...@@ -205,6 +218,10 @@ static struct radeon_asic r420_asic = {
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.bandwidth_update = &r100_bandwidth_update, .bandwidth_update = &r100_bandwidth_update,
.hdp_flush = &r100_hdp_flush, .hdp_flush = &r100_hdp_flush,
.hpd_init = &r100_hpd_init,
.hpd_fini = &r100_hpd_fini,
.hpd_sense = &r100_hpd_sense,
.hpd_set_polarity = &r100_hpd_set_polarity,
}; };
...@@ -250,6 +267,10 @@ static struct radeon_asic rs400_asic = { ...@@ -250,6 +267,10 @@ static struct radeon_asic rs400_asic = {
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.bandwidth_update = &r100_bandwidth_update, .bandwidth_update = &r100_bandwidth_update,
.hdp_flush = &r100_hdp_flush, .hdp_flush = &r100_hdp_flush,
.hpd_init = &r100_hpd_init,
.hpd_fini = &r100_hpd_fini,
.hpd_sense = &r100_hpd_sense,
.hpd_set_polarity = &r100_hpd_set_polarity,
}; };
...@@ -268,6 +289,12 @@ int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); ...@@ -268,6 +289,12 @@ int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void rs600_bandwidth_update(struct radeon_device *rdev); void rs600_bandwidth_update(struct radeon_device *rdev);
void rs600_hpd_init(struct radeon_device *rdev);
void rs600_hpd_fini(struct radeon_device *rdev);
bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void rs600_hpd_set_polarity(struct radeon_device *rdev,
enum radeon_hpd_id hpd);
static struct radeon_asic rs600_asic = { static struct radeon_asic rs600_asic = {
.init = &rs600_init, .init = &rs600_init,
.fini = &rs600_fini, .fini = &rs600_fini,
...@@ -297,6 +324,10 @@ static struct radeon_asic rs600_asic = { ...@@ -297,6 +324,10 @@ static struct radeon_asic rs600_asic = {
.set_clock_gating = &radeon_atom_set_clock_gating, .set_clock_gating = &radeon_atom_set_clock_gating,
.bandwidth_update = &rs600_bandwidth_update, .bandwidth_update = &rs600_bandwidth_update,
.hdp_flush = &r100_hdp_flush, .hdp_flush = &r100_hdp_flush,
.hpd_init = &rs600_hpd_init,
.hpd_fini = &rs600_hpd_fini,
.hpd_sense = &rs600_hpd_sense,
.hpd_set_polarity = &rs600_hpd_set_polarity,
}; };
...@@ -341,6 +372,10 @@ static struct radeon_asic rs690_asic = { ...@@ -341,6 +372,10 @@ static struct radeon_asic rs690_asic = {
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.bandwidth_update = &rs690_bandwidth_update, .bandwidth_update = &rs690_bandwidth_update,
.hdp_flush = &r100_hdp_flush, .hdp_flush = &r100_hdp_flush,
.hpd_init = &rs600_hpd_init,
.hpd_fini = &rs600_hpd_fini,
.hpd_sense = &rs600_hpd_sense,
.hpd_set_polarity = &rs600_hpd_set_polarity,
}; };
...@@ -389,6 +424,10 @@ static struct radeon_asic rv515_asic = { ...@@ -389,6 +424,10 @@ static struct radeon_asic rv515_asic = {
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.bandwidth_update = &rv515_bandwidth_update, .bandwidth_update = &rv515_bandwidth_update,
.hdp_flush = &r100_hdp_flush, .hdp_flush = &r100_hdp_flush,
.hpd_init = &rs600_hpd_init,
.hpd_fini = &rs600_hpd_fini,
.hpd_sense = &rs600_hpd_sense,
.hpd_set_polarity = &rs600_hpd_set_polarity,
}; };
...@@ -428,6 +467,10 @@ static struct radeon_asic r520_asic = { ...@@ -428,6 +467,10 @@ static struct radeon_asic r520_asic = {
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.bandwidth_update = &rv515_bandwidth_update, .bandwidth_update = &rv515_bandwidth_update,
.hdp_flush = &r100_hdp_flush, .hdp_flush = &r100_hdp_flush,
.hpd_init = &rs600_hpd_init,
.hpd_fini = &rs600_hpd_fini,
.hpd_sense = &rs600_hpd_sense,
.hpd_set_polarity = &rs600_hpd_set_polarity,
}; };
/* /*
...@@ -465,6 +508,11 @@ int r600_copy_blit(struct radeon_device *rdev, ...@@ -465,6 +508,11 @@ int r600_copy_blit(struct radeon_device *rdev,
uint64_t src_offset, uint64_t dst_offset, uint64_t src_offset, uint64_t dst_offset,
unsigned num_pages, struct radeon_fence *fence); unsigned num_pages, struct radeon_fence *fence);
void r600_hdp_flush(struct radeon_device *rdev); void r600_hdp_flush(struct radeon_device *rdev);
void r600_hpd_init(struct radeon_device *rdev);
void r600_hpd_fini(struct radeon_device *rdev);
bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void r600_hpd_set_polarity(struct radeon_device *rdev,
enum radeon_hpd_id hpd);
static struct radeon_asic r600_asic = { static struct radeon_asic r600_asic = {
.init = &r600_init, .init = &r600_init,
...@@ -496,6 +544,10 @@ static struct radeon_asic r600_asic = { ...@@ -496,6 +544,10 @@ static struct radeon_asic r600_asic = {
.clear_surface_reg = r600_clear_surface_reg, .clear_surface_reg = r600_clear_surface_reg,
.bandwidth_update = &rv515_bandwidth_update, .bandwidth_update = &rv515_bandwidth_update,
.hdp_flush = &r600_hdp_flush, .hdp_flush = &r600_hdp_flush,
.hpd_init = &r600_hpd_init,
.hpd_fini = &r600_hpd_fini,
.hpd_sense = &r600_hpd_sense,
.hpd_set_polarity = &r600_hpd_set_polarity,
}; };
/* /*
...@@ -537,6 +589,10 @@ static struct radeon_asic rv770_asic = { ...@@ -537,6 +589,10 @@ static struct radeon_asic rv770_asic = {
.clear_surface_reg = r600_clear_surface_reg, .clear_surface_reg = r600_clear_surface_reg,
.bandwidth_update = &rv515_bandwidth_update, .bandwidth_update = &rv515_bandwidth_update,
.hdp_flush = &r600_hdp_flush, .hdp_flush = &r600_hdp_flush,
.hpd_init = &r600_hpd_init,
.hpd_fini = &r600_hpd_fini,
.hpd_sense = &r600_hpd_sense,
.hpd_set_polarity = &r600_hpd_set_polarity,
}; };
#endif #endif
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...@@ -40,6 +40,26 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, ...@@ -40,6 +40,26 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
struct drm_encoder *encoder, struct drm_encoder *encoder,
bool connected); bool connected);
void radeon_connector_hotplug(struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
if (radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
if (radeon_dp_needs_link_train(radeon_connector)) {
if (connector->encoder)
dp_link_train(connector->encoder, connector);
}
}
}
}
static void radeon_property_change_mode(struct drm_encoder *encoder) static void radeon_property_change_mode(struct drm_encoder *encoder)
{ {
struct drm_crtc *crtc = encoder->crtc; struct drm_crtc *crtc = encoder->crtc;
...@@ -896,6 +916,91 @@ struct drm_connector_funcs radeon_dvi_connector_funcs = { ...@@ -896,6 +916,91 @@ struct drm_connector_funcs radeon_dvi_connector_funcs = {
.force = radeon_dvi_force, .force = radeon_dvi_force,
}; };
static void radeon_dp_connector_destroy(struct drm_connector *connector)
{
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
if (radeon_connector->ddc_bus)
radeon_i2c_destroy(radeon_connector->ddc_bus);
if (radeon_connector->edid)
kfree(radeon_connector->edid);
if (radeon_dig_connector->dp_i2c_bus)
radeon_i2c_destroy(radeon_dig_connector->dp_i2c_bus);
kfree(radeon_connector->con_priv);
drm_sysfs_connector_remove(connector);
drm_connector_cleanup(connector);
kfree(connector);
}
static int radeon_dp_get_modes(struct drm_connector *connector)
{
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
int ret;
ret = radeon_ddc_get_modes(radeon_connector);
return ret;
}
static enum drm_connector_status radeon_dp_detect(struct drm_connector *connector)
{
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
enum drm_connector_status ret = connector_status_disconnected;
struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
u8 sink_type;
if (radeon_connector->edid) {
kfree(radeon_connector->edid);
radeon_connector->edid = NULL;
}
sink_type = radeon_dp_getsinktype(radeon_connector);
if (sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
if (radeon_dp_getdpcd(radeon_connector)) {
radeon_dig_connector->dp_sink_type = sink_type;
ret = connector_status_connected;
}
} else {
radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
if (radeon_ddc_probe(radeon_connector)) {
radeon_dig_connector->dp_sink_type = sink_type;
ret = connector_status_connected;
}
radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
}
return ret;
}
static int radeon_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
/* XXX check mode bandwidth */
if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
return radeon_dp_mode_valid_helper(radeon_connector, mode);
else
return MODE_OK;
}
struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = {
.get_modes = radeon_dp_get_modes,
.mode_valid = radeon_dp_mode_valid,
.best_encoder = radeon_dvi_encoder,
};
struct drm_connector_funcs radeon_dp_connector_funcs = {
.dpms = drm_helper_connector_dpms,
.detect = radeon_dp_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.set_property = radeon_connector_set_property,
.destroy = radeon_dp_connector_destroy,
.force = radeon_dvi_force,
};
void void
radeon_add_atom_connector(struct drm_device *dev, radeon_add_atom_connector(struct drm_device *dev,
uint32_t connector_id, uint32_t connector_id,
...@@ -904,7 +1009,8 @@ radeon_add_atom_connector(struct drm_device *dev, ...@@ -904,7 +1009,8 @@ radeon_add_atom_connector(struct drm_device *dev,
struct radeon_i2c_bus_rec *i2c_bus, struct radeon_i2c_bus_rec *i2c_bus,
bool linkb, bool linkb,
uint32_t igp_lane_info, uint32_t igp_lane_info,
uint16_t connector_object_id) uint16_t connector_object_id,
struct radeon_hpd *hpd)
{ {
struct radeon_device *rdev = dev->dev_private; struct radeon_device *rdev = dev->dev_private;
struct drm_connector *connector; struct drm_connector *connector;
...@@ -944,6 +1050,7 @@ radeon_add_atom_connector(struct drm_device *dev, ...@@ -944,6 +1050,7 @@ radeon_add_atom_connector(struct drm_device *dev,
radeon_connector->devices = supported_device; radeon_connector->devices = supported_device;
radeon_connector->shared_ddc = shared_ddc; radeon_connector->shared_ddc = shared_ddc;
radeon_connector->connector_object_id = connector_object_id; radeon_connector->connector_object_id = connector_object_id;
radeon_connector->hpd = *hpd;
switch (connector_type) { switch (connector_type) {
case DRM_MODE_CONNECTOR_VGA: case DRM_MODE_CONNECTOR_VGA:
drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
...@@ -1030,10 +1137,12 @@ radeon_add_atom_connector(struct drm_device *dev, ...@@ -1030,10 +1137,12 @@ radeon_add_atom_connector(struct drm_device *dev,
radeon_dig_connector->linkb = linkb; radeon_dig_connector->linkb = linkb;
radeon_dig_connector->igp_lane_info = igp_lane_info; radeon_dig_connector->igp_lane_info = igp_lane_info;
radeon_connector->con_priv = radeon_dig_connector; radeon_connector->con_priv = radeon_dig_connector;
drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
if (ret) if (ret)
goto failed; goto failed;
/* add DP i2c bus */
radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
if (i2c_bus->valid) { if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP"); radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP");
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
...@@ -1099,7 +1208,8 @@ radeon_add_legacy_connector(struct drm_device *dev, ...@@ -1099,7 +1208,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
uint32_t supported_device, uint32_t supported_device,
int connector_type, int connector_type,
struct radeon_i2c_bus_rec *i2c_bus, struct radeon_i2c_bus_rec *i2c_bus,
uint16_t connector_object_id) uint16_t connector_object_id,
struct radeon_hpd *hpd)
{ {
struct radeon_device *rdev = dev->dev_private; struct radeon_device *rdev = dev->dev_private;
struct drm_connector *connector; struct drm_connector *connector;
...@@ -1129,6 +1239,7 @@ radeon_add_legacy_connector(struct drm_device *dev, ...@@ -1129,6 +1239,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
radeon_connector->connector_id = connector_id; radeon_connector->connector_id = connector_id;
radeon_connector->devices = supported_device; radeon_connector->devices = supported_device;
radeon_connector->connector_object_id = connector_object_id; radeon_connector->connector_object_id = connector_object_id;
radeon_connector->hpd = *hpd;
switch (connector_type) { switch (connector_type) {
case DRM_MODE_CONNECTOR_VGA: case DRM_MODE_CONNECTOR_VGA:
drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
......
...@@ -481,11 +481,13 @@ int radeon_atombios_init(struct radeon_device *rdev) ...@@ -481,11 +481,13 @@ int radeon_atombios_init(struct radeon_device *rdev)
rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
radeon_atom_initialize_bios_scratch_regs(rdev->ddev); radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
atom_allocate_fb_scratch(rdev->mode_info.atom_context);
return 0; return 0;
} }
void radeon_atombios_fini(struct radeon_device *rdev) void radeon_atombios_fini(struct radeon_device *rdev)
{ {
kfree(rdev->mode_info.atom_context->scratch);
kfree(rdev->mode_info.atom_context); kfree(rdev->mode_info.atom_context);
kfree(rdev->mode_info.atom_card_info); kfree(rdev->mode_info.atom_card_info);
} }
...@@ -568,6 +570,11 @@ int radeon_device_init(struct radeon_device *rdev, ...@@ -568,6 +570,11 @@ int radeon_device_init(struct radeon_device *rdev,
rwlock_init(&rdev->fence_drv.lock); rwlock_init(&rdev->fence_drv.lock);
INIT_LIST_HEAD(&rdev->gem.objects); INIT_LIST_HEAD(&rdev->gem.objects);
/* setup workqueue */
rdev->wq = create_workqueue("radeon");
if (rdev->wq == NULL)
return -ENOMEM;
/* Set asic functions */ /* Set asic functions */
r = radeon_asic_init(rdev); r = radeon_asic_init(rdev);
if (r) { if (r) {
...@@ -641,6 +648,7 @@ void radeon_device_fini(struct radeon_device *rdev) ...@@ -641,6 +648,7 @@ void radeon_device_fini(struct radeon_device *rdev)
DRM_INFO("radeon: finishing device.\n"); DRM_INFO("radeon: finishing device.\n");
rdev->shutdown = true; rdev->shutdown = true;
radeon_fini(rdev); radeon_fini(rdev);
destroy_workqueue(rdev->wq);
vga_client_register(rdev->pdev, NULL, NULL, NULL); vga_client_register(rdev->pdev, NULL, NULL, NULL);
iounmap(rdev->rmmio); iounmap(rdev->rmmio);
rdev->rmmio = NULL; rdev->rmmio = NULL;
...@@ -687,6 +695,7 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) ...@@ -687,6 +695,7 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
radeon_save_bios_scratch_regs(rdev); radeon_save_bios_scratch_regs(rdev);
radeon_suspend(rdev); radeon_suspend(rdev);
radeon_hpd_fini(rdev);
/* evict remaining vram memory */ /* evict remaining vram memory */
radeon_bo_evict_vram(rdev); radeon_bo_evict_vram(rdev);
...@@ -721,6 +730,8 @@ int radeon_resume_kms(struct drm_device *dev) ...@@ -721,6 +730,8 @@ int radeon_resume_kms(struct drm_device *dev)
fb_set_suspend(rdev->fbdev_info, 0); fb_set_suspend(rdev->fbdev_info, 0);
release_console_sem(); release_console_sem();
/* reset hpd state */
radeon_hpd_init(rdev);
/* blat the mode back in */ /* blat the mode back in */
drm_helper_resume_force_mode(dev); drm_helper_resume_force_mode(dev);
return 0; return 0;
......
...@@ -250,6 +250,16 @@ static const char *connector_names[13] = { ...@@ -250,6 +250,16 @@ static const char *connector_names[13] = {
"HDMI-B", "HDMI-B",
}; };
static const char *hpd_names[7] = {
"NONE",
"HPD1",
"HPD2",
"HPD3",
"HPD4",
"HPD5",
"HPD6",
};
static void radeon_print_display_setup(struct drm_device *dev) static void radeon_print_display_setup(struct drm_device *dev)
{ {
struct drm_connector *connector; struct drm_connector *connector;
...@@ -264,6 +274,8 @@ static void radeon_print_display_setup(struct drm_device *dev) ...@@ -264,6 +274,8 @@ static void radeon_print_display_setup(struct drm_device *dev)
radeon_connector = to_radeon_connector(connector); radeon_connector = to_radeon_connector(connector);
DRM_INFO("Connector %d:\n", i); DRM_INFO("Connector %d:\n", i);
DRM_INFO(" %s\n", connector_names[connector->connector_type]); DRM_INFO(" %s\n", connector_names[connector->connector_type]);
if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
if (radeon_connector->ddc_bus) if (radeon_connector->ddc_bus)
DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector->ddc_bus->rec.mask_clk_reg,
...@@ -337,6 +349,11 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) ...@@ -337,6 +349,11 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
{ {
int ret = 0; int ret = 0;
if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
if (dig->dp_i2c_bus)
radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
}
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
return -1; return -1;
if (!radeon_connector->edid) { if (!radeon_connector->edid) {
...@@ -724,6 +741,8 @@ int radeon_modeset_init(struct radeon_device *rdev) ...@@ -724,6 +741,8 @@ int radeon_modeset_init(struct radeon_device *rdev)
if (!ret) { if (!ret) {
return ret; return ret;
} }
/* initialize hpd */
radeon_hpd_init(rdev);
drm_helper_initial_config(rdev->ddev); drm_helper_initial_config(rdev->ddev);
return 0; return 0;
} }
...@@ -731,6 +750,7 @@ int radeon_modeset_init(struct radeon_device *rdev) ...@@ -731,6 +750,7 @@ int radeon_modeset_init(struct radeon_device *rdev)
void radeon_modeset_fini(struct radeon_device *rdev) void radeon_modeset_fini(struct radeon_device *rdev)
{ {
if (rdev->mode_info.mode_config_initialized) { if (rdev->mode_info.mode_config_initialized) {
radeon_hpd_fini(rdev);
drm_mode_config_cleanup(rdev->ddev); drm_mode_config_cleanup(rdev->ddev);
rdev->mode_info.mode_config_initialized = false; rdev->mode_info.mode_config_initialized = false;
} }
......
This diff is collapsed.
...@@ -69,6 +69,7 @@ void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) ...@@ -69,6 +69,7 @@ void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
* holds the i2c port in a bad state - switch hw i2c away before * holds the i2c port in a bad state - switch hw i2c away before
* doing DDC - do this for all r200s/r300s/r400s for safety sake * doing DDC - do this for all r200s/r300s/r400s for safety sake
*/ */
if (rec->hw_capable) {
if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
if (rec->a_clk_reg == RADEON_GPIO_MONID) { if (rec->a_clk_reg == RADEON_GPIO_MONID) {
WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
...@@ -78,6 +79,7 @@ void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) ...@@ -78,6 +79,7 @@ void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
} }
} }
}
/* clear the output pin values */ /* clear the output pin values */
temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
...@@ -86,6 +88,12 @@ void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) ...@@ -86,6 +88,12 @@ void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
WREG32(rec->a_data_reg, temp); WREG32(rec->a_data_reg, temp);
/* set the pins to input */
temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
WREG32(rec->en_clk_reg, temp);
temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
WREG32(rec->en_data_reg, temp);
/* mask the gpio pins for software use */ /* mask the gpio pins for software use */
temp = RREG32(rec->mask_clk_reg); temp = RREG32(rec->mask_clk_reg);
...@@ -172,20 +180,19 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, ...@@ -172,20 +180,19 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
return NULL; return NULL;
i2c->adapter.owner = THIS_MODULE; i2c->adapter.owner = THIS_MODULE;
i2c->adapter.algo_data = &i2c->algo;
i2c->dev = dev; i2c->dev = dev;
i2c->algo.setsda = set_data; i2c_set_adapdata(&i2c->adapter, i2c);
i2c->algo.setscl = set_clock; i2c->adapter.algo_data = &i2c->algo.bit;
i2c->algo.getsda = get_data; i2c->algo.bit.setsda = set_data;
i2c->algo.getscl = get_clock; i2c->algo.bit.setscl = set_clock;
i2c->algo.udelay = 20; i2c->algo.bit.getsda = get_data;
i2c->algo.bit.getscl = get_clock;
i2c->algo.bit.udelay = 20;
/* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
* make this, 2 jiffies is a lot more reliable */ * make this, 2 jiffies is a lot more reliable */
i2c->algo.timeout = 2; i2c->algo.bit.timeout = 2;
i2c->algo.data = i2c; i2c->algo.bit.data = i2c;
i2c->rec = *rec; i2c->rec = *rec;
i2c_set_adapdata(&i2c->adapter, i2c);
ret = i2c_bit_add_bus(&i2c->adapter); ret = i2c_bit_add_bus(&i2c->adapter);
if (ret) { if (ret) {
DRM_INFO("Failed to register i2c %s\n", name); DRM_INFO("Failed to register i2c %s\n", name);
...@@ -199,6 +206,38 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, ...@@ -199,6 +206,38 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
} }
struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
struct radeon_i2c_bus_rec *rec,
const char *name)
{
struct radeon_i2c_chan *i2c;
int ret;
i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
if (i2c == NULL)
return NULL;
i2c->rec = *rec;
i2c->adapter.owner = THIS_MODULE;
i2c->dev = dev;
i2c_set_adapdata(&i2c->adapter, i2c);
i2c->adapter.algo_data = &i2c->algo.dp;
i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
i2c->algo.dp.address = 0;
ret = i2c_dp_aux_add_bus(&i2c->adapter);
if (ret) {
DRM_INFO("Failed to register i2c %s\n", name);
goto out_free;
}
return i2c;
out_free:
kfree(i2c);
return NULL;
}
void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
{ {
if (!i2c) if (!i2c)
......
...@@ -39,11 +39,32 @@ irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS) ...@@ -39,11 +39,32 @@ irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
return radeon_irq_process(rdev); return radeon_irq_process(rdev);
} }
/*
* Handle hotplug events outside the interrupt handler proper.
*/
static void radeon_hotplug_work_func(struct work_struct *work)
{
struct radeon_device *rdev = container_of(work, struct radeon_device,
hotplug_work);
struct drm_device *dev = rdev->ddev;
struct drm_mode_config *mode_config = &dev->mode_config;
struct drm_connector *connector;
if (mode_config->num_connector) {
list_for_each_entry(connector, &mode_config->connector_list, head)
radeon_connector_hotplug(connector);
}
/* Just fire off a uevent and let userspace tell us what to do */
drm_sysfs_hotplug_event(dev);
}
void radeon_driver_irq_preinstall_kms(struct drm_device *dev) void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
{ {
struct radeon_device *rdev = dev->dev_private; struct radeon_device *rdev = dev->dev_private;
unsigned i; unsigned i;
INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
/* Disable *all* interrupts */ /* Disable *all* interrupts */
rdev->irq.sw_int = false; rdev->irq.sw_int = false;
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#include <drm_crtc.h> #include <drm_crtc.h>
#include <drm_mode.h> #include <drm_mode.h>
#include <drm_edid.h> #include <drm_edid.h>
#include <drm_dp_helper.h>
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/i2c-id.h> #include <linux/i2c-id.h>
#include <linux/i2c-algo-bit.h> #include <linux/i2c-algo-bit.h>
...@@ -105,6 +106,13 @@ enum radeon_tv_std { ...@@ -105,6 +106,13 @@ enum radeon_tv_std {
*/ */
struct radeon_i2c_bus_rec { struct radeon_i2c_bus_rec {
bool valid; bool valid;
/* id used by atom */
uint8_t i2c_id;
/* can be used with hw i2c engine */
bool hw_capable;
/* uses multi-media i2c engine */
bool mm_i2c;
/* regs and bits */
uint32_t mask_clk_reg; uint32_t mask_clk_reg;
uint32_t mask_data_reg; uint32_t mask_data_reg;
uint32_t a_clk_reg; uint32_t a_clk_reg;
...@@ -164,9 +172,12 @@ struct radeon_pll { ...@@ -164,9 +172,12 @@ struct radeon_pll {
}; };
struct radeon_i2c_chan { struct radeon_i2c_chan {
struct drm_device *dev;
struct i2c_adapter adapter; struct i2c_adapter adapter;
struct i2c_algo_bit_data algo; struct drm_device *dev;
union {
struct i2c_algo_dp_aux_data dp;
struct i2c_algo_bit_data bit;
} algo;
struct radeon_i2c_bus_rec rec; struct radeon_i2c_bus_rec rec;
}; };
...@@ -328,6 +339,35 @@ struct radeon_encoder { ...@@ -328,6 +339,35 @@ struct radeon_encoder {
struct radeon_connector_atom_dig { struct radeon_connector_atom_dig {
uint32_t igp_lane_info; uint32_t igp_lane_info;
bool linkb; bool linkb;
/* displayport */
struct radeon_i2c_chan *dp_i2c_bus;
u8 dpcd[8];
u8 dp_sink_type;
int dp_clock;
int dp_lane_count;
};
struct radeon_gpio_rec {
bool valid;
u8 id;
u32 reg;
u32 mask;
};
enum radeon_hpd_id {
RADEON_HPD_NONE = 0,
RADEON_HPD_1,
RADEON_HPD_2,
RADEON_HPD_3,
RADEON_HPD_4,
RADEON_HPD_5,
RADEON_HPD_6,
};
struct radeon_hpd {
enum radeon_hpd_id hpd;
u8 plugged_state;
struct radeon_gpio_rec gpio;
}; };
struct radeon_connector { struct radeon_connector {
...@@ -344,6 +384,7 @@ struct radeon_connector { ...@@ -344,6 +384,7 @@ struct radeon_connector {
void *con_priv; void *con_priv;
bool dac_load_detect; bool dac_load_detect;
uint16_t connector_object_id; uint16_t connector_object_id;
struct radeon_hpd hpd;
}; };
struct radeon_framebuffer { struct radeon_framebuffer {
...@@ -351,6 +392,25 @@ struct radeon_framebuffer { ...@@ -351,6 +392,25 @@ struct radeon_framebuffer {
struct drm_gem_object *obj; struct drm_gem_object *obj;
}; };
extern void radeon_connector_hotplug(struct drm_connector *connector);
extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
struct drm_display_mode *mode);
extern void radeon_dp_set_link_config(struct drm_connector *connector,
struct drm_display_mode *mode);
extern void dp_link_train(struct drm_encoder *encoder,
struct drm_connector *connector);
extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
int action, uint8_t lane_num,
uint8_t lane_set);
extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
uint8_t write_byte, uint8_t *read_byte);
extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
struct radeon_i2c_bus_rec *rec,
const char *name);
extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
struct radeon_i2c_bus_rec *rec, struct radeon_i2c_bus_rec *rec,
const char *name); const char *name);
......
...@@ -887,6 +887,7 @@ ...@@ -887,6 +887,7 @@
# define RADEON_FP_PANEL_FORMAT (1 << 3) # define RADEON_FP_PANEL_FORMAT (1 << 3)
# define RADEON_FP_EN_TMDS (1 << 7) # define RADEON_FP_EN_TMDS (1 << 7)
# define RADEON_FP_DETECT_SENSE (1 << 8) # define RADEON_FP_DETECT_SENSE (1 << 8)
# define RADEON_FP_DETECT_INT_POL (1 << 9)
# define R200_FP_SOURCE_SEL_MASK (3 << 10) # define R200_FP_SOURCE_SEL_MASK (3 << 10)
# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
...@@ -894,6 +895,7 @@ ...@@ -894,6 +895,7 @@
# define R200_FP_SOURCE_SEL_TRANS (3 << 10) # define R200_FP_SOURCE_SEL_TRANS (3 << 10)
# define RADEON_FP_SEL_CRTC1 (0 << 13) # define RADEON_FP_SEL_CRTC1 (0 << 13)
# define RADEON_FP_SEL_CRTC2 (1 << 13) # define RADEON_FP_SEL_CRTC2 (1 << 13)
# define R300_HPD_SEL(x) ((x) << 13)
# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
...@@ -909,6 +911,7 @@ ...@@ -909,6 +911,7 @@
# define RADEON_FP2_ON (1 << 2) # define RADEON_FP2_ON (1 << 2)
# define RADEON_FP2_PANEL_FORMAT (1 << 3) # define RADEON_FP2_PANEL_FORMAT (1 << 3)
# define RADEON_FP2_DETECT_SENSE (1 << 8) # define RADEON_FP2_DETECT_SENSE (1 << 8)
# define RADEON_FP2_DETECT_INT_POL (1 << 9)
# define R200_FP2_SOURCE_SEL_MASK (3 << 10) # define R200_FP2_SOURCE_SEL_MASK (3 << 10)
# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
...@@ -988,14 +991,20 @@ ...@@ -988,14 +991,20 @@
#define RADEON_GEN_INT_CNTL 0x0040 #define RADEON_GEN_INT_CNTL 0x0040
# define RADEON_CRTC_VBLANK_MASK (1 << 0) # define RADEON_CRTC_VBLANK_MASK (1 << 0)
# define RADEON_FP_DETECT_MASK (1 << 4)
# define RADEON_CRTC2_VBLANK_MASK (1 << 9) # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
# define RADEON_FP2_DETECT_MASK (1 << 10)
# define RADEON_SW_INT_ENABLE (1 << 25) # define RADEON_SW_INT_ENABLE (1 << 25)
#define RADEON_GEN_INT_STATUS 0x0044 #define RADEON_GEN_INT_STATUS 0x0044
# define AVIVO_DISPLAY_INT_STATUS (1 << 0) # define AVIVO_DISPLAY_INT_STATUS (1 << 0)
# define RADEON_CRTC_VBLANK_STAT (1 << 0) # define RADEON_CRTC_VBLANK_STAT (1 << 0)
# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
# define RADEON_FP_DETECT_STAT (1 << 4)
# define RADEON_FP_DETECT_STAT_ACK (1 << 4)
# define RADEON_CRTC2_VBLANK_STAT (1 << 9) # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
# define RADEON_FP2_DETECT_STAT (1 << 10)
# define RADEON_FP2_DETECT_STAT_ACK (1 << 10)
# define RADEON_SW_INT_FIRE (1 << 26) # define RADEON_SW_INT_FIRE (1 << 26)
# define RADEON_SW_INT_TEST (1 << 25) # define RADEON_SW_INT_TEST (1 << 25)
# define RADEON_SW_INT_TEST_ACK (1 << 25) # define RADEON_SW_INT_TEST_ACK (1 << 25)
...@@ -1148,16 +1157,16 @@ ...@@ -1148,16 +1157,16 @@
# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
#define RADEON_GPIOPAD_MASK 0x0198 #define RADEON_GPIOPAD_MASK 0x0198
#define RADEON_GPIOPAD_A 0x019c #define RADEON_GPIOPAD_A 0x019c
#define RADEON_GPIOPAD_EN 0x01a0 #define RADEON_GPIOPAD_EN 0x01a0
#define RADEON_GPIOPAD_Y 0x01a4 #define RADEON_GPIOPAD_Y 0x01a4
#define RADEON_LCD_GPIO_MASK 0x01a0 #define RADEON_MDGPIO_MASK 0x01a8
#define RADEON_LCD_GPIO_Y_REG 0x01a4 #define RADEON_MDGPIO_A 0x01ac
#define RADEON_MDGPIO_A_REG 0x01ac #define RADEON_MDGPIO_EN 0x01b0
#define RADEON_MDGPIO_EN_REG 0x01b0 #define RADEON_MDGPIO_Y 0x01b4
#define RADEON_MDGPIO_MASK 0x0198
#define RADEON_MDGPIO_Y_REG 0x01b4
#define RADEON_MEM_ADDR_CONFIG 0x0148 #define RADEON_MEM_ADDR_CONFIG 0x0148
#define RADEON_MEM_BASE 0x0f10 /* PCI */ #define RADEON_MEM_BASE 0x0f10 /* PCI */
#define RADEON_MEM_CNTL 0x0140 #define RADEON_MEM_CNTL 0x0140
......
...@@ -60,6 +60,107 @@ int rs600_mc_init(struct radeon_device *rdev) ...@@ -60,6 +60,107 @@ int rs600_mc_init(struct radeon_device *rdev)
return r; return r;
return 0; return 0;
} }
/* hpd for digital panel detect/disconnect */
bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
{
u32 tmp;
bool connected = false;
switch (hpd) {
case RADEON_HPD_1:
tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
connected = true;
break;
case RADEON_HPD_2:
tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
connected = true;
break;
default:
break;
}
return connected;
}
void rs600_hpd_set_polarity(struct radeon_device *rdev,
enum radeon_hpd_id hpd)
{
u32 tmp;
bool connected = rs600_hpd_sense(rdev, hpd);
switch (hpd) {
case RADEON_HPD_1:
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
if (connected)
tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
else
tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
break;
case RADEON_HPD_2:
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
if (connected)
tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
else
tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
break;
default:
break;
}
}
void rs600_hpd_init(struct radeon_device *rdev)
{
struct drm_device *dev = rdev->ddev;
struct drm_connector *connector;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
switch (radeon_connector->hpd.hpd) {
case RADEON_HPD_1:
WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
rdev->irq.hpd[0] = true;
break;
case RADEON_HPD_2:
WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
rdev->irq.hpd[1] = true;
break;
default:
break;
}
}
rs600_irq_set(rdev);
}
void rs600_hpd_fini(struct radeon_device *rdev)
{
struct drm_device *dev = rdev->ddev;
struct drm_connector *connector;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
switch (radeon_connector->hpd.hpd) {
case RADEON_HPD_1:
WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
rdev->irq.hpd[0] = false;
break;
case RADEON_HPD_2:
WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
rdev->irq.hpd[1] = false;
break;
default:
break;
}
}
}
/* /*
* GART. * GART.
*/ */
...@@ -209,6 +310,10 @@ int rs600_irq_set(struct radeon_device *rdev) ...@@ -209,6 +310,10 @@ int rs600_irq_set(struct radeon_device *rdev)
{ {
uint32_t tmp = 0; uint32_t tmp = 0;
uint32_t mode_int = 0; uint32_t mode_int = 0;
u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
if (rdev->irq.sw_int) { if (rdev->irq.sw_int) {
tmp |= S_000040_SW_INT_EN(1); tmp |= S_000040_SW_INT_EN(1);
...@@ -219,8 +324,16 @@ int rs600_irq_set(struct radeon_device *rdev) ...@@ -219,8 +324,16 @@ int rs600_irq_set(struct radeon_device *rdev)
if (rdev->irq.crtc_vblank_int[1]) { if (rdev->irq.crtc_vblank_int[1]) {
mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
} }
if (rdev->irq.hpd[0]) {
hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
}
if (rdev->irq.hpd[1]) {
hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
}
WREG32(R_000040_GEN_INT_CNTL, tmp); WREG32(R_000040_GEN_INT_CNTL, tmp);
WREG32(R_006540_DxMODE_INT_MASK, mode_int); WREG32(R_006540_DxMODE_INT_MASK, mode_int);
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
return 0; return 0;
} }
...@@ -228,6 +341,7 @@ static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_ ...@@ -228,6 +341,7 @@ static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_
{ {
uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
uint32_t irq_mask = ~C_000044_SW_INT; uint32_t irq_mask = ~C_000044_SW_INT;
u32 tmp;
if (G_000044_DISPLAY_INT_STAT(irqs)) { if (G_000044_DISPLAY_INT_STAT(irqs)) {
*r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
...@@ -239,6 +353,16 @@ static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_ ...@@ -239,6 +353,16 @@ static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_
WREG32(R_006D34_D2MODE_VBLANK_STATUS, WREG32(R_006D34_D2MODE_VBLANK_STATUS,
S_006D34_D2MODE_VBLANK_ACK(1)); S_006D34_D2MODE_VBLANK_ACK(1));
} }
if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
}
if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
}
} else { } else {
*r500_disp_int = 0; *r500_disp_int = 0;
} }
...@@ -264,6 +388,7 @@ int rs600_irq_process(struct radeon_device *rdev) ...@@ -264,6 +388,7 @@ int rs600_irq_process(struct radeon_device *rdev)
{ {
uint32_t status, msi_rearm; uint32_t status, msi_rearm;
uint32_t r500_disp_int; uint32_t r500_disp_int;
bool queue_hotplug = false;
status = rs600_irq_ack(rdev, &r500_disp_int); status = rs600_irq_ack(rdev, &r500_disp_int);
if (!status && !r500_disp_int) { if (!status && !r500_disp_int) {
...@@ -278,8 +403,18 @@ int rs600_irq_process(struct radeon_device *rdev) ...@@ -278,8 +403,18 @@ int rs600_irq_process(struct radeon_device *rdev)
drm_handle_vblank(rdev->ddev, 0); drm_handle_vblank(rdev->ddev, 0);
if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int))
drm_handle_vblank(rdev->ddev, 1); drm_handle_vblank(rdev->ddev, 1);
if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
queue_hotplug = true;
DRM_DEBUG("HPD1\n");
}
if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
queue_hotplug = true;
DRM_DEBUG("HPD2\n");
}
status = rs600_irq_ack(rdev, &r500_disp_int); status = rs600_irq_ack(rdev, &r500_disp_int);
} }
if (queue_hotplug)
queue_work(rdev->wq, &rdev->hotplug_work);
if (rdev->msi_enabled) { if (rdev->msi_enabled) {
switch (rdev->family) { switch (rdev->family) {
case CHIP_RS600: case CHIP_RS600:
......
...@@ -30,27 +30,12 @@ ...@@ -30,27 +30,12 @@
/* Registers */ /* Registers */
#define R_000040_GEN_INT_CNTL 0x000040 #define R_000040_GEN_INT_CNTL 0x000040
#define S_000040_DISPLAY_INT_STATUS(x) (((x) & 0x1) << 0) #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18)
#define G_000040_DISPLAY_INT_STATUS(x) (((x) >> 0) & 0x1) #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1)
#define C_000040_DISPLAY_INT_STATUS 0xFFFFFFFE #define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF
#define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19)
#define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1)
#define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF #define C_000040_GUI_IDLE_MASK 0xFFF7FFFF
#define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6)
#define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1)
#define C_000040_CRTC2_VSYNC 0xFFFFFFBF
#define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7)
#define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1)
#define C_000040_SNAPSHOT2 0xFFFFFF7F
#define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9)
#define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1)
#define C_000040_CRTC2_VBLANK 0xFFFFFDFF
#define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10)
#define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1)
#define C_000040_FP2_DETECT 0xFFFFFBFF
#define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11)
#define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1)
#define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF
#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF
...@@ -370,7 +355,90 @@ ...@@ -370,7 +355,90 @@
#define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5) #define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5)
#define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1) #define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1)
#define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF #define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF
#define S_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 16)
#define G_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) >> 16) & 0x1)
#define C_007EDC_DACA_AUTODETECT_INTERRUPT 0xFFFEFFFF
#define S_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 17)
#define G_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) >> 17) & 0x1)
#define C_007EDC_DACB_AUTODETECT_INTERRUPT 0xFFFDFFFF
#define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) & 0x1) << 18)
#define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) >> 18) & 0x1)
#define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT 0xFFFBFFFF
#define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) & 0x1) << 19)
#define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) >> 19) & 0x1)
#define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT 0xFFF7FFFF
#define R_007828_DACA_AUTODETECT_CONTROL 0x007828
#define S_007828_DACA_AUTODETECT_MODE(x) (((x) & 0x3) << 0)
#define G_007828_DACA_AUTODETECT_MODE(x) (((x) >> 0) & 0x3)
#define C_007828_DACA_AUTODETECT_MODE 0xFFFFFFFC
#define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)
#define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)
#define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF
#define S_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16)
#define G_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3)
#define C_007828_DACA_AUTODETECT_CHECK_MASK 0xFFFCFFFF
#define R_007838_DACA_AUTODETECT_INT_CONTROL 0x007838
#define S_007838_DACA_AUTODETECT_ACK(x) (((x) & 0x1) << 0)
#define C_007838_DACA_DACA_AUTODETECT_ACK 0xFFFFFFFE
#define S_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16)
#define G_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1)
#define C_007838_DACA_AUTODETECT_INT_ENABLE 0xFFFCFFFF
#define R_007A28_DACB_AUTODETECT_CONTROL 0x007A28
#define S_007A28_DACB_AUTODETECT_MODE(x) (((x) & 0x3) << 0)
#define G_007A28_DACB_AUTODETECT_MODE(x) (((x) >> 0) & 0x3)
#define C_007A28_DACB_AUTODETECT_MODE 0xFFFFFFFC
#define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)
#define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)
#define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF
#define S_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16)
#define G_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3)
#define C_007A28_DACB_AUTODETECT_CHECK_MASK 0xFFFCFFFF
#define R_007A38_DACB_AUTODETECT_INT_CONTROL 0x007A38
#define S_007A38_DACB_AUTODETECT_ACK(x) (((x) & 0x1) << 0)
#define C_007A38_DACB_DACA_AUTODETECT_ACK 0xFFFFFFFE
#define S_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16)
#define G_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1)
#define C_007A38_DACB_AUTODETECT_INT_ENABLE 0xFFFCFFFF
#define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL 0x007D00
#define S_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) & 0x1) << 0)
#define G_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) >> 0) & 0x1)
#define C_007D00_DC_HOT_PLUG_DETECT1_EN 0xFFFFFFFE
#define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0x007D04
#define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) & 0x1) << 0)
#define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) >> 0) & 0x1)
#define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0xFFFFFFFE
#define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) & 0x1) << 1)
#define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) >> 1) & 0x1)
#define C_007D04_DC_HOT_PLUG_DETECT1_SENSE 0xFFFFFFFD
#define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL 0x007D08
#define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x) (((x) & 0x1) << 0)
#define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK 0xFFFFFFFE
#define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8)
#define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1)
#define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY 0xFFFFFEFF
#define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) & 0x1) << 16)
#define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) >> 16) & 0x1)
#define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN 0xFFFEFFFF
#define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL 0x007D10
#define S_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) & 0x1) << 0)
#define G_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) >> 0) & 0x1)
#define C_007D10_DC_HOT_PLUG_DETECT2_EN 0xFFFFFFFE
#define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0x007D14
#define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) & 0x1) << 0)
#define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) >> 0) & 0x1)
#define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0xFFFFFFFE
#define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) & 0x1) << 1)
#define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) >> 1) & 0x1)
#define C_007D14_DC_HOT_PLUG_DETECT2_SENSE 0xFFFFFFFD
#define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL 0x007D18
#define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x) (((x) & 0x1) << 0)
#define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK 0xFFFFFFFE
#define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8)
#define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1)
#define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY 0xFFFFFEFF
#define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) & 0x1) << 16)
#define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) >> 16) & 0x1)
#define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN 0xFFFEFFFF
/* MC registers */ /* MC registers */
#define R_000000_MC_STATUS 0x000000 #define R_000000_MC_STATUS 0x000000
......
...@@ -43,6 +43,32 @@ ...@@ -43,6 +43,32 @@
#define AUX_I2C_REPLY_MASK (0x3 << 6) #define AUX_I2C_REPLY_MASK (0x3 << 6)
/* AUX CH addresses */ /* AUX CH addresses */
/* DPCD */
#define DP_DPCD_REV 0x000
#define DP_MAX_LINK_RATE 0x001
#define DP_MAX_LANE_COUNT 0x002
# define DP_MAX_LANE_COUNT_MASK 0x1f
# define DP_ENHANCED_FRAME_CAP (1 << 7)
#define DP_MAX_DOWNSPREAD 0x003
# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
#define DP_NORP 0x004
#define DP_DOWNSTREAMPORT_PRESENT 0x005
# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
/* 00b = DisplayPort */
/* 01b = Analog */
/* 10b = TMDS or HDMI */
/* 11b = Other */
# define DP_FORMAT_CONVERSION (1 << 3)
#define DP_MAIN_LINK_CHANNEL_CODING 0x006
/* link configuration */
#define DP_LINK_BW_SET 0x100 #define DP_LINK_BW_SET 0x100
# define DP_LINK_BW_1_62 0x06 # define DP_LINK_BW_1_62 0x06
# define DP_LINK_BW_2_7 0x0a # define DP_LINK_BW_2_7 0x0a
...@@ -52,7 +78,6 @@ ...@@ -52,7 +78,6 @@
# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
#define DP_TRAINING_PATTERN_SET 0x102 #define DP_TRAINING_PATTERN_SET 0x102
# define DP_TRAINING_PATTERN_DISABLE 0 # define DP_TRAINING_PATTERN_DISABLE 0
# define DP_TRAINING_PATTERN_1 1 # define DP_TRAINING_PATTERN_1 1
# define DP_TRAINING_PATTERN_2 2 # define DP_TRAINING_PATTERN_2 2
...@@ -102,11 +127,14 @@ ...@@ -102,11 +127,14 @@
#define DP_LANE0_1_STATUS 0x202 #define DP_LANE0_1_STATUS 0x202
#define DP_LANE2_3_STATUS 0x203 #define DP_LANE2_3_STATUS 0x203
# define DP_LANE_CR_DONE (1 << 0) # define DP_LANE_CR_DONE (1 << 0)
# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
# define DP_LANE_SYMBOL_LOCKED (1 << 2) # define DP_LANE_SYMBOL_LOCKED (1 << 2)
#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
DP_LANE_CHANNEL_EQ_DONE | \
DP_LANE_SYMBOL_LOCKED)
#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
#define DP_INTERLANE_ALIGN_DONE (1 << 0) #define DP_INTERLANE_ALIGN_DONE (1 << 0)
...@@ -120,15 +148,18 @@ ...@@ -120,15 +148,18 @@
#define DP_ADJUST_REQUEST_LANE0_1 0x206 #define DP_ADJUST_REQUEST_LANE0_1 0x206
#define DP_ADJUST_REQUEST_LANE2_3 0x207 #define DP_ADJUST_REQUEST_LANE2_3 0x207
# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
#define DP_SET_POWER 0x600
# define DP_SET_POWER_D0 0x1
# define DP_SET_POWER_D3 0x2
#define MODE_I2C_START 1 #define MODE_I2C_START 1
#define MODE_I2C_WRITE 2 #define MODE_I2C_WRITE 2
......
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