Commit 7cc77bf4 authored by Tariq Toukan's avatar Tariq Toukan Committed by David S. Miller

net/mlx4_core: Allow MTTs starting at any index

Allow obtaining MTTs starting at any index,
thus give a better cache utilization.

For this, allow setting log_mtts_per_seg to 0, and use
this in default.
Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
Signed-off-by: default avatarEli Cohen <eli@mellanox.co.il>
Signed-off-by: default avatarAnaty Rahamim Bar Kat <anaty@mellanox.com>
Reviewed-by: default avatarJack Morgenstein <jackm@dev.mellanox.co.il>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e8886643
...@@ -159,9 +159,10 @@ static bool use_prio; ...@@ -159,9 +159,10 @@ static bool use_prio;
module_param_named(use_prio, use_prio, bool, 0444); module_param_named(use_prio, use_prio, bool, 0444);
MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); int log_mtts_per_seg = ilog2(1);
module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment "
"(0-7) (default: 0)");
static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
static int arr_argc = 2; static int arr_argc = 2;
...@@ -4410,7 +4411,7 @@ static int __init mlx4_verify_params(void) ...@@ -4410,7 +4411,7 @@ static int __init mlx4_verify_params(void)
if (use_prio != 0) if (use_prio != 0)
pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) {
pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
log_mtts_per_seg); log_mtts_per_seg);
return -1; return -1;
......
...@@ -84,7 +84,6 @@ enum { ...@@ -84,7 +84,6 @@ enum {
MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
MLX4_MTT_ENTRY_PER_SEG = 8,
}; };
enum { enum {
......
...@@ -105,7 +105,8 @@ u64 mlx4_make_profile(struct mlx4_dev *dev, ...@@ -105,7 +105,8 @@ u64 mlx4_make_profile(struct mlx4_dev *dev,
request->num_mtt = request->num_mtt =
roundup_pow_of_two(max_t(unsigned, request->num_mtt, roundup_pow_of_two(max_t(unsigned, request->num_mtt,
min(1UL << (31 - log_mtts_per_seg), min(1UL << (31 - log_mtts_per_seg),
si.totalram >> (log_mtts_per_seg - 1)))); (si.totalram << 1) >> log_mtts_per_seg)));
profile[MLX4_RES_QP].size = dev_cap->qpc_entry_sz; profile[MLX4_RES_QP].size = dev_cap->qpc_entry_sz;
profile[MLX4_RES_RDMARC].size = dev_cap->rdmarc_entry_sz; profile[MLX4_RES_RDMARC].size = dev_cap->rdmarc_entry_sz;
......
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