[PATCH] sn: Remove the bridge and xbridge code - everything not PIC

From: Pat Gefre <pfg@sgi.com> Remove the bridge and xbridge code - everything not PIC

[PATCH] sn: Remove the bridge and xbridge code - everything not PIC
From: Pat Gefre <pfg@sgi.com> Remove the bridge and xbridge code - everything not PIC
7d8f7295 · Andrew Morton · Linus Torvalds · 36b94548 · 7d8f7295 · 7d8f7295
Commit 7d8f7295 authored Jan 18, 2004 by Andrew Morton Committed by Linus Torvalds Jan 18, 2004
19 changed files
--- a/arch/ia64/sn/io/machvec/pci_bus_cvlink.c
+++ b/arch/ia64/sn/io/machvec/pci_bus_cvlink.c
@@ -54,18 +54,6 @@ extern void register_pcibr_intr(int irq, pcibr_intr_t intr);
 void sn_dma_flush_init(unsigned long start, unsigned long end, int idx, int pin, int slot);
-/*
- * For the given device, initialize whether it is a PIC device.
- */
-static void
-set_isPIC(struct sn_device_sysdata *device_sysdata)
-{
-	pciio_info_t pciio_info = pciio_info_get(device_sysdata->vhdl);
-	pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-	device_sysdata->isPIC = IS_PIC_SOFT(pcibr_soft);;
-}
 /*
 * pci_bus_cvlink_init() - To be called once during initialization before 
 *	SGI IO Infrastructure init is called.
@@ -188,23 +176,11 @@ set_flush_addresses(struct pci_dev *device_dev,
 	 * Get the nasid from the bridge.
 	 */
 	nasid = NASID_GET(device_sysdata->dma_buf_sync);
-	if (IS_PIC_DEVICE(device_dev)) {
+	device_sysdata->dma_buf_sync = (volatile unsigned int *)
-		device_sysdata->dma_buf_sync = (volatile unsigned int *)
+		&bridge->b_wr_req_buf[pciio_slot].reg;
-			&bridge->b_wr_req_buf[pciio_slot].reg;
+	device_sysdata->xbow_buf_sync = (volatile unsigned int *)
-		device_sysdata->xbow_buf_sync = (volatile unsigned int *)
+		XBOW_PRIO_LINKREGS_PTR(NODE_SWIN_BASE(nasid, 0),
-			XBOW_PRIO_LINKREGS_PTR(NODE_SWIN_BASE(nasid, 0),
+		pcibr_soft->bs_xid);
-			pcibr_soft->bs_xid);
-	} else {
-		/*
-		 * Accessing Xbridge and Xbow register when SHUB swapoper is on!.
-		 */
-		device_sysdata->dma_buf_sync = (volatile unsigned int *)
-			((uint64_t)&(bridge->b_wr_req_buf[pciio_slot].reg)^4);
-		device_sysdata->xbow_buf_sync = (volatile unsigned int *)
-			((uint64_t)(XBOW_PRIO_LINKREGS_PTR(
-			NODE_SWIN_BASE(nasid, 0), pcibr_soft->bs_xid)) ^ 4);
-	}
 #ifdef DEBUG
 	printk("set_flush_addresses: dma_buf_sync %p xbow_buf_sync %p\n", 
 		device_sysdata->dma_buf_sync, device_sysdata->xbow_buf_sync);
@@ -501,7 +477,6 @@ sn_pci_fixup(int arg)
 		device_vertex = device_sysdata->vhdl;
 		device_dev->sysdata = (void *) device_sysdata;
-		set_isPIC(device_sysdata);
 		/*
 		 * Set the xbridge Device(X) Write Buffer Flush and Xbow Flush 
@@ -521,7 +496,7 @@ sn_pci_fixup(int arg)
 			size = device_dev->resource[idx].end -
 				device_dev->resource[idx].start;
 			if (size) {
-				device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(device_vertex, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, (IS_PIC_DEVICE(device_dev)) ? 0 : PCIIO_BYTE_STREAM);
+				device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(device_vertex, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, 0);
 				device_dev->resource[idx].start |= __IA64_UNCACHED_OFFSET;
 			}
 			else
@@ -824,10 +799,8 @@ pci_bus_to_hcl_cvlink(void)
 	devfs_hdl = hwgraph_path_to_vertex("hw/module");
 	for (i = 0; i < nummodules ; i++) {
-	    for ( j = 0; j < 3; j++ ) {
+	    for ( j = 0; j < 2; j++ ) {
 		if ( j == 0 )
-			brick_name = EDGE_LBL_PBRICK;
-		else if ( j == 1 )
 			brick_name = EDGE_LBL_PXBRICK;
 		else
 			brick_name = EDGE_LBL_IXBRICK;

--- a/arch/ia64/sn/io/machvec/pci_dma.c
+++ b/arch/ia64/sn/io/machvec/pci_dma.c
@@ -175,8 +175,7 @@ sn_pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_hand
 	 * attributes or to a different memory region.
 	 */
 	*dma_handle = pcibr_dmatrans_addr(vhdl, NULL, phys_addr, size,
-			((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
+							PCIIO_DMA_CMD);
-					  PCIIO_DMA_CMD);
        /*
 	 * If this device is in PCI-X mode, the system would have
@@ -193,9 +192,7 @@ sn_pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_hand
 	 * so we try to use an ATE.
 	 */
 	if (!(*dma_handle)) {
-		dma_map = pcibr_dmamap_alloc(vhdl, NULL, size,
+		dma_map = pcibr_dmamap_alloc(vhdl, NULL, size, PCIIO_DMA_CMD);
-				((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
-					     PCIIO_DMA_CMD);
 		if (!dma_map) {
 			printk(KERN_ERR "sn_pci_alloc_consistent: Unable to "
 			       "allocate anymore 32 bit page map entries.\n");
@@ -286,9 +283,7 @@ sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int dire
 		if (IS_PCIA64(hwdev)) {
 			sg->dma_address = pcibr_dmatrans_addr(vhdl, NULL, phys_addr,
 						       sg->length,
-			       ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
+						       PCIIO_DMA_DATA | PCIIO_DMA_A64);
-						       PCIIO_DMA_DATA |
-						       PCIIO_DMA_A64);
 			sg->dma_length = sg->length;
 			continue;
 		}
@@ -298,9 +293,7 @@ sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int dire
 		 */
 		if (IS_PCI32G(hwdev)) {
 			sg->dma_address = pcibr_dmatrans_addr(vhdl, NULL, phys_addr,
-						       sg->length,
+						       sg->length, PCIIO_DMA_DATA);
-					((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
-						       PCIIO_DMA_DATA);
 			sg->dma_length = sg->length;
 			/*
 			 * See if we got a direct map entry
@@ -315,9 +308,7 @@ sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int dire
 		 * It is a 32 bit card and we cannot do direct mapping,
 		 * so we use an ATE.
 		 */
-		dma_map = pcibr_dmamap_alloc(vhdl, NULL, sg->length,
+		dma_map = pcibr_dmamap_alloc(vhdl, NULL, sg->length, PCIIO_DMA_DATA);
-				((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
-					     PCIIO_DMA_DATA);
 		if (!dma_map) {
 			printk(KERN_ERR "sn_pci_map_sg: Unable to allocate "
 			       "anymore 32 bit page map entries.\n");
@@ -427,9 +418,7 @@ sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
 	if (IS_PCIA64(hwdev)) {
 		/* This device supports 64 bit DMA addresses. */
 		dma_addr = pcibr_dmatrans_addr(vhdl, NULL, phys_addr, size,
-		       ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
+					       PCIIO_DMA_DATA | PCIIO_DMA_A64);
-					       PCIIO_DMA_DATA |
-					       PCIIO_DMA_A64);
 		return dma_addr;
 	}
@@ -441,7 +430,6 @@ sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
 	 */
 	if (IS_PCI32G(hwdev)) {
 		dma_addr = pcibr_dmatrans_addr(vhdl, NULL, phys_addr, size,
-			((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
 					       PCIIO_DMA_DATA);
 		if (dma_addr)
 			return dma_addr;
@@ -452,9 +440,7 @@ sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
 	 * let's use the PMU instead.
 	 */
 	dma_map = NULL;
-	dma_map = pcibr_dmamap_alloc(vhdl, NULL, size, 
+	dma_map = pcibr_dmamap_alloc(vhdl, NULL, size, PCIIO_DMA_DATA);
-			((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
-			PCIIO_DMA_DATA);
 	if (!dma_map) {
 		printk(KERN_ERR "pci_map_single: Unable to allocate anymore "

--- a/arch/ia64/sn/io/sgi_io_sim.c
+++ b/arch/ia64/sn/io/sgi_io_sim.c
@@ -31,11 +31,8 @@ is_specified(char *s)
 /*
 * Routines provided by ml/SN/promif.c.
 */
-static __psunsigned_t master_bridge_base;
 nasid_t console_nasid = (nasid_t)-1;
 char master_baseio_wid;
-static char console_wid;
-static char console_pcislot;
 int
 check_nasid_equiv(nasid_t nasida, nasid_t nasidb)

--- a/arch/ia64/sn/io/sn2/klconflib.c
+++ b/arch/ia64/sn/io/sn2/klconflib.c
@@ -268,14 +268,6 @@ board_to_path(lboard_t *brd, char *path)
 				board_name = EDGE_LBL_PXBRICK;
 			else if (brd->brd_type == KLTYPE_IXBRICK)
 				board_name = EDGE_LBL_IXBRICK;
-			else if (brd->brd_type == KLTYPE_PBRICK)
-				board_name = EDGE_LBL_PBRICK;
-			else if (brd->brd_type == KLTYPE_IBRICK)
-				board_name = EDGE_LBL_IBRICK;
-			else if (brd->brd_type == KLTYPE_XBRICK)
-				board_name = EDGE_LBL_XBRICK;
-			else if (brd->brd_type == KLTYPE_PEBRICK)
-				board_name = EDGE_LBL_PEBRICK;
 			else if (brd->brd_type == KLTYPE_CGBRICK)
 				board_name = EDGE_LBL_CGBRICK;
 			else
@@ -438,71 +430,24 @@ board_serial_number_get(lboard_t *board,char *serial_number)
 		break;
 	}
 	case KLCLASS_IO: {	/* IO board */
-		if (KLTYPE(board->brd_type) == KLTYPE_TPU) {
+	     	klbri_t	*bridge;
-		/* Special case for TPU boards */
-			kltpu_t *tpu;	
-			/* Get the tpu component information */
+		/* Get the bridge component information */
-			tpu = (kltpu_t *)find_first_component(board,
+		bridge = (klbri_t *)find_first_component(board,
-						      KLSTRUCT_TPU);
-			/* If we don't have a tpu component on a tpu board
-			 * then we have a weird klconfig.
-			 */
-			if (!tpu)
-				return(1);
-			/* Get the serial number information from
-			 * the tpu's manufacturing nic info
-			 */
-			if (component_serial_number_get(board,
-						tpu->tpu_mfg_nic,
-						serial_number,
-						""))
-				return(1);
-			break;
-		} else  if ((KLTYPE(board->brd_type) == KLTYPE_GSN_A) ||
-		            (KLTYPE(board->brd_type) == KLTYPE_GSN_B)) {
-		/* Special case for GSN boards */
-			klgsn_t *gsn;	
-			/* Get the gsn component information */
-			gsn = (klgsn_t *)find_first_component(board,
-			      ((KLTYPE(board->brd_type) == KLTYPE_GSN_A) ?
-					KLSTRUCT_GSN_A : KLSTRUCT_GSN_B));
-			/* If we don't have a gsn component on a gsn board
-			 * then we have a weird klconfig.
-			 */
-			if (!gsn)
-				return(1);
-			/* Get the serial number information from
-			 * the gsn's manufacturing nic info
-			 */
-			if (component_serial_number_get(board,
-						gsn->gsn_mfg_nic,
-						serial_number,
-						""))
-				return(1);
-			break;
-		} else {
-		     	klbri_t	*bridge;
-			/* Get the bridge component information */
-			bridge = (klbri_t *)find_first_component(board,
 							 KLSTRUCT_BRI);
-			/* If we don't have a bridge component on an IO board
+		/* If we don't have a bridge component on an IO board
-			 * then we have a weird klconfig.
+		 * then we have a weird klconfig.
-			 */
+		 */
-			if (!bridge)
+		if (!bridge)
-				return(1);
+			return(1);
-			/* Get the serial number information from
+		/* Get the serial number information from
-		 	 * the bridge's manufacturing nic info
+	 	 * the bridge's manufacturing nic info
-			 */
+		 */
-			if (component_serial_number_get(board,
+		if (component_serial_number_get(board,
-						bridge->bri_mfg_nic,
+					bridge->bri_mfg_nic,
-						serial_number,
+					serial_number, ""))
-						""))
+			return(1);
-				return(1);
+		break;
-			break;
-		}
 	}
 	case KLCLASS_ROUTER: {	/* Router board */
 		klrou_t *router;	

--- a/arch/ia64/sn/io/sn2/l1_command.c
+++ b/arch/ia64/sn/io/sn2/l1_command.c
@@ -111,12 +111,6 @@ int iobrick_module_get(nasid_t nasid)
 	brick_type = MODULE_IXBRICK; break;
      case L1_BRICKTYPE_PX: 
 	brick_type = MODULE_PXBRICK; break;
-      case L1_BRICKTYPE_I: 
-	brick_type = MODULE_IBRICK; break;
-      case L1_BRICKTYPE_P:
-	brick_type = MODULE_PBRICK; break;
-      case L1_BRICKTYPE_X:
-	brick_type = MODULE_XBRICK; break;
    }
    ret = RBT_TO_MODULE(rack, bay, brick_type);
@@ -176,15 +170,6 @@ iobrick_L1bricktype_to_name(int type)
    default:
        return("Unknown");
-    case L1_BRICKTYPE_X:
-        return("Xbrick");
-    case L1_BRICKTYPE_I:
-        return("Ibrick");
-    case L1_BRICKTYPE_P:
-        return("Pbrick");
    case L1_BRICKTYPE_PX:
        return("PXbrick");
@@ -196,6 +181,9 @@ iobrick_L1bricktype_to_name(int type)
    case L1_BRICKTYPE_R:
        return("Rbrick");
+    case L1_BRICKTYPE_CHI_CG:
+        return(EDGE_LBL_CGBRICK);
    }
 }
--- a/arch/ia64/sn/io/sn2/ml_iograph.c
+++ b/arch/ia64/sn/io/sn2/ml_iograph.c
@@ -394,11 +394,8 @@ io_xswitch_widget_init(vertex_hdl_t  	xswitchv,
 		sprintf(pathname, EDGE_LBL_MODULE "/%s/" EDGE_LBL_SLAB "/%d" "/%s" "/%s/%d",
 			buffer,
 			geo_slab(board->brd_geoid),
-			(board->brd_type == KLTYPE_IBRICK) ? EDGE_LBL_IBRICK :
-			(board->brd_type == KLTYPE_PBRICK) ? EDGE_LBL_PBRICK :
 			(board->brd_type == KLTYPE_PXBRICK) ? EDGE_LBL_PXBRICK :
-			(board->brd_type == KLTYPE_IXBRICK) ? EDGE_LBL_IXBRICK :
+			(board->brd_type == KLTYPE_IXBRICK) ? EDGE_LBL_IXBRICK : "?brick",
-			(board->brd_type == KLTYPE_XBRICK) ? EDGE_LBL_XBRICK : "?brick",
 			EDGE_LBL_XTALK, widgetnum);
 		DBG("io_xswitch_widget_init: path= %s\n", pathname);
@@ -587,7 +584,6 @@ io_init_node(cnodeid_t cnodeid)
 	nodepda_t	*npdap;
 	struct semaphore *peer_sema = 0;
 	uint32_t	widget_partnum;
-	cpu_cookie_t	c = 0;
 	npdap = NODEPDA(cnodeid);
@@ -808,34 +804,6 @@ init_all_devices(void)
 static
 struct io_brick_map_s io_brick_tab[] = {
-/* Ibrick widget number to PCI bus number map */
- {      MODULE_IBRICK,                          /* Ibrick type    */ 
-    /*  PCI Bus #                                  Widget #       */
-    {   0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7      */
-        0,                                      /* 0x8            */
-        0,                                      /* 0x9            */
-        0, 0,                                   /* 0xa - 0xb      */
-        0,                                      /* 0xc            */
-        0,                                      /* 0xd            */
-        2,                                      /* 0xe            */
-        1                                       /* 0xf            */
-     }
- },
-/* Pbrick widget number to PCI bus number map */
- {      MODULE_PBRICK,                          /* Pbrick type    */ 
-    /*  PCI Bus #                                  Widget #       */
-    {   0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7      */
-        2,                                      /* 0x8            */
-        1,                                      /* 0x9            */
-        0, 0,                                   /* 0xa - 0xb      */
-        4,                                      /* 0xc            */
-        6,                                      /* 0xd            */
-        3,                                      /* 0xe            */
-        5                                       /* 0xf            */
-    }
- },
 /* PXbrick widget number to PCI bus number map */
 {      MODULE_PXBRICK,                         /* PXbrick type   */ 
    /*  PCI Bus #                                  Widget #       */
@@ -863,20 +831,6 @@ struct io_brick_map_s io_brick_tab[] = {
        3                                       /* 0xf            */
    }
 },
-/* Xbrick widget to XIO slot map */
- {      MODULE_XBRICK,                          /* Xbrick type    */ 
-    /*  XIO Slot #                                 Widget #       */
-    {   0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7      */
-        1,                                      /* 0x8            */
-        3,                                      /* 0x9            */
-        0, 0,                                   /* 0xa - 0xb      */
-        2,                                      /* 0xc            */
-        4,                                      /* 0xd            */
-        0,                                      /* 0xe            */
-        0                                       /* 0xf            */
-    }
- }
 };
 /*

--- a/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c
@@ -380,25 +380,9 @@ ate_write(pcibr_soft_t pcibr_soft,
 	  int ate_count,
 	  bridge_ate_t ate)
 {
-	if (IS_PIC_SOFT(pcibr_soft) ) {
+  	while (ate_count-- > 0) {
-    		while (ate_count-- > 0) {
+		*ate_ptr++ = ate;
-			*ate_ptr++ = ate;
+		ate += IOPGSIZE;
-			ate += IOPGSIZE;
-		}
-	}
-	else {
-		if (io_get_sh_swapper(NASID_GET(ate_ptr))) {
-    			while (ate_count-- > 0) {
-				*ate_ptr++ = __swab64(ate);
-				ate += IOPGSIZE;
-			}
-		}
-		else {
-    			while (ate_count-- > 0) {
-				*ate_ptr++ = ate;
-				ate += IOPGSIZE;
-			}
-		}
 	}
 }
@@ -440,19 +424,7 @@ ate_thaw(pcibr_dmamap_t pcibr_dmamap,
    for (slot = pcibr_soft->bs_min_slot; 
 		slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) {
 	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER) {
-		if ( IS_PIC_SOFT(pcibr_soft) ) {
+		pcibr_slot_config_set(bridge, slot, PCI_CFG_COMMAND/4, cmd_reg);
-			pcibr_slot_config_set(bridge, slot, PCI_CFG_COMMAND/4, cmd_reg);
-		}
-		else {
-			if (io_get_sh_swapper(NASID_GET(bridge))) {
-				bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = __swab32(cmd_reg);
-			}
-			else {
-//				BUG(); /* Does this really work if called when io_get_sh_swapper = 0? */
-//				bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
-				pcibr_slot_config_set(bridge, slot, PCI_CFG_COMMAND/4, cmd_reg);
-			}
-		}
 	}
    }
    pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;

--- a/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c
@@ -287,12 +287,10 @@ pcibr_try_set_device(pcibr_soft_t pcibr_soft,
    bridgereg_t             xmask;
    xmask = mask;
-    if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) {
+    if (mask == BRIDGE_DEV_PMU_BITS)
-    	if (mask == BRIDGE_DEV_PMU_BITS)
+	xmask = XBRIDGE_DEV_PMU_BITS;
-		xmask = XBRIDGE_DEV_PMU_BITS;
+    if (mask == BRIDGE_DEV_D64_BITS)
-	if (mask == BRIDGE_DEV_D64_BITS)
+	xmask = XBRIDGE_DEV_D64_BITS;
-		xmask = XBRIDGE_DEV_D64_BITS;
-    }
    slotp = &pcibr_soft->bs_slot[slot];
@@ -374,11 +372,9 @@ pcibr_try_set_device(pcibr_soft_t pcibr_soft,
 	new &= ~BRIDGE_DEV_WRGA_BITS;
    if (flags & PCIIO_BYTE_STREAM)
-	new |= (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) ? 
+	new |= BRIDGE_DEV_SWAP_DIR;
-			BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS;
    if (flags & PCIIO_WORD_VALUES)
-	new &= (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) ? 
+	new &= ~BRIDGE_DEV_SWAP_DIR;
-			~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS;
    /* Provider-specific flags
     */
@@ -408,7 +404,7 @@ pcibr_try_set_device(pcibr_soft_t pcibr_soft,
     * device.  The bit is only intended for 64-bit devices and, on
     * PIC, can cause problems for 32-bit devices.
     */
-    if (IS_PIC_SOFT(pcibr_soft) && mask == BRIDGE_DEV_D64_BITS &&
+    if (mask == BRIDGE_DEV_D64_BITS &&
                                PCIBR_WAR_ENABLED(PV855271, pcibr_soft)) {
        if (flags & PCIBR_VCHAN1) {
                new |= BRIDGE_DEV_VIRTUAL_EN;
@@ -423,13 +419,8 @@ pcibr_try_set_device(pcibr_soft_t pcibr_soft,
    if (chg) {
 	badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0;
-	if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) {
+	badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
-		badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
+	badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
-		badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
-	} else {
-		badpmu = slotp->bss_pmu_uctr ? (BRIDGE_DEV_PMU_BITS & chg) : 0;
-		badd64 = slotp->bss_d64_uctr ? (BRIDGE_DEV_D64_BITS & chg) : 0;
-	}
 	bad = badpmu | badd32 | badd64;
 	if (bad) {
@@ -493,22 +484,9 @@ pcibr_try_set_device(pcibr_soft_t pcibr_soft,
 	pcibr_unlock(pcibr_soft, s);
 	return 0;
    }
-    if ( IS_PIC_SOFT(pcibr_soft) ) {
+    bridge->b_device[slot].reg = new;
-	bridge->b_device[slot].reg = new;
+    slotp->bss_device = new;
-	slotp->bss_device = new;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    }
-    else {
-	if (io_get_sh_swapper(NASID_GET(bridge))) {
-		BRIDGE_REG_SET32((&bridge->b_device[slot].reg)) = __swab32(new);
-		slotp->bss_device = new;
-		BRIDGE_REG_GET32((&bridge->b_wid_tflush));  /* wait until Bridge PIO complete */
-	} else {
-		bridge->b_device[slot].reg = new;
-		slotp->bss_device = new;
-		bridge->b_wid_tflush;               /* wait until Bridge PIO complete */
-	}
-    }
    pcibr_unlock(pcibr_soft, s);
    printk("pcibr_try_set_device: Device(%d): %x\n", slot, new);
@@ -550,16 +528,7 @@ pcibr_device_write_gather_flush(pcibr_soft_t pcibr_soft,
    s = pcibr_lock(pcibr_soft);
    bridge = pcibr_soft->bs_base;
-    if ( IS_PIC_SOFT(pcibr_soft) ) {
+    wrf = bridge->b_wr_req_buf[slot].reg;
-	wrf = bridge->b_wr_req_buf[slot].reg;
-    }
-    else {
-	if (io_get_sh_swapper(NASID_GET(bridge))) {
-		wrf = BRIDGE_REG_GET32((&bridge->b_wr_req_buf[slot].reg));
-	} else {
-		wrf = bridge->b_wr_req_buf[slot].reg;
-	}
-    }
    pcibr_unlock(pcibr_soft, s);
 }
@@ -749,9 +718,6 @@ pcibr_device_unregister(vertex_hdl_t pconn_vhdl)
        s = pcibr_lock(pcibr_soft);
-	/* PIC NOTE: If this is a BRIDGE, VCHAN2 & VCHAN3 will be zero so
-	 * no need to conditionalize this (ie. "if (IS_PIC_SOFT())" ).
-	 */
        pcibr_soft->bs_rrb_res[slot] = pcibr_soft->bs_rrb_res[slot] +
                                       pcibr_soft->bs_rrb_valid[slot][VCHAN0] +
                                       pcibr_soft->bs_rrb_valid[slot][VCHAN1] +
@@ -986,7 +952,6 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
    char                    devnm[MAXDEVNAME], *s;
    pcibr_hints_t           pcibr_hints;
    uint64_t              int_enable;
-    bridgereg_t             int_enable_32;
    picreg_t                int_enable_64;
    unsigned                rrb_fixed = 0;
@@ -1121,8 +1086,7 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
    PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, pcibr_vhdl,
 		"pcibr_attach2: %s ASIC: rev %s (code=0x%x)\n",
-		IS_XBRIDGE_SOFT(pcibr_soft) ? "XBridge" :
+		"PIC",
-			IS_PIC_SOFT(pcibr_soft) ? "PIC" : "Bridge", 
 		(rev == BRIDGE_PART_REV_A) ? "A" : 
                (rev == BRIDGE_PART_REV_B) ? "B" :
                (rev == BRIDGE_PART_REV_C) ? "C" :
@@ -1277,12 +1241,8 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
     * is a wrapper routine we register that will call the real error handler
     * pcibr_error_handler() with the correct pcibr_soft struct.
     */
-    if (IS_PIC_SOFT(pcibr_soft)) {
+    if (busnum == 0) {
-	if (busnum == 0) {
+    	xwidget_error_register(xconn_vhdl, pcibr_error_handler_wrapper, pcibr_soft);
-	    xwidget_error_register(xconn_vhdl, pcibr_error_handler_wrapper, pcibr_soft);
-	}
-    } else {
-	xwidget_error_register(xconn_vhdl, pcibr_error_handler, pcibr_soft);
    }
    /*
@@ -1302,7 +1262,7 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
    bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
    /* Initialize some PIC specific registers. */
-    if (IS_PIC_SOFT(pcibr_soft)) {
+    {
 	picreg_t pic_ctrl_reg = bridge->p_wid_control_64;
 	/* Bridges Requester ID: bus = busnum, dev = 0, func = 0 */
@@ -1326,19 +1286,7 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
 	bridge->p_wid_control_64 = pic_ctrl_reg;
    }
+    bridge->b_int_device = (uint32_t) 0x006db6db;
-    /*
-     * Until otherwise set up,
-     * assume all interrupts are
-     * from slot 7(Bridge/Xbridge) or 3(PIC).
-     * XXX. Not sure why we're doing this, made change for PIC
-     * just to avoid setting reserved bits.
-     */
-    if (IS_PIC_SOFT(pcibr_soft))
-	bridge->b_int_device = (uint32_t) 0x006db6db;
-    else
-	bridge->b_int_device = (uint32_t) 0xffffffff;
    {
 	bridgereg_t             dirmap;
 	paddr_t                 paddr;
@@ -1408,17 +1356,9 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
 	 */
 	spl_level = splhi();
 #if IOPGSIZE == 4096
-        if (IS_PIC_SOFT(pcibr_soft)) {
+        bridge->p_wid_control_64 &= ~BRIDGE_CTRL_PAGE_SIZE;
-            bridge->p_wid_control_64 &= ~BRIDGE_CTRL_PAGE_SIZE;
-        } else {
-            bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
-        }
 #elif IOPGSIZE == 16384
-        if (IS_PIC_SOFT(pcibr_soft)) {
+        bridge->p_wid_control_64 |= BRIDGE_CTRL_PAGE_SIZE;
-            bridge->p_wid_control_64 |= BRIDGE_CTRL_PAGE_SIZE;
-        } else {
-            bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
-        }
 #else
 	<<<Unable to deal with IOPGSIZE >>>;
 #endif
@@ -1450,10 +1390,7 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
 	 * time.
 	 */
-	if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft))
+	num_entries = 0;
-		num_entries = 0;
-	else
-		num_entries = pcibr_init_ext_ate_ram(bridge);
 	/* we always have 128 ATEs (512 for Xbridge) inside the chip
 	 * even if disabled for debugging.
@@ -1561,24 +1498,8 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
     * enable all of them.
     * NOTE: some PCI ints may already be enabled.
     */
-    /* We read the INT_ENABLE register as a 64bit picreg_t for PIC and a
+    int_enable_64 = bridge->p_int_enable_64 | BRIDGE_ISR_ERRORS;
-     * 32bit bridgereg_t for BRIDGE, but always process the result as a
+    int_enable = (uint64_t)int_enable_64;
-     * 64bit value so the code can be "common" for both PIC and BRIDGE...
-     */
-    if (IS_PIC_SOFT(pcibr_soft)) {
-	int_enable_64 = bridge->p_int_enable_64 | BRIDGE_ISR_ERRORS;
-        int_enable = (uint64_t)int_enable_64;
-#ifdef PFG_TEST
-	int_enable = (uint64_t)0x7ffffeff7ffffeff;
-#endif
-    } else {
-	int_enable_32 = bridge->b_int_enable | (BRIDGE_ISR_ERRORS & 0xffffffff);
-	int_enable = ((uint64_t)int_enable_32 & 0xffffffff);
-#ifdef PFG_TEST
-	int_enable = (uint64_t)0x7ffffeff;
-#endif
-    }
 #if BRIDGE_ERROR_INTR_WAR
    if (pcibr_soft->bs_rev_num == BRIDGE_PART_REV_A) {
@@ -1618,7 +1539,7 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
     * locked out to be freed up sooner (by timing out) so that the
     * read tnums are never completely used up.
     */
-    if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV856864, pcibr_soft)) {
+    if (PCIBR_WAR_ENABLED(PV856864, pcibr_soft)) {
        int_enable &= ~PIC_ISR_PCIX_REQ_TOUT;
        int_enable &= ~BRIDGE_ISR_XREAD_REQ_TIMEOUT;
@@ -1630,16 +1551,12 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
     * RRB0, RRB8, RRB1, and RRB9.  Assign them to DEVICE[2|3]--VCHAN3
     * so they are not used
     */
-    if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV856866, pcibr_soft)) {
+    if (PCIBR_WAR_ENABLED(PV856866, pcibr_soft)) {
        bridge->b_even_resp |= 0x000f000f;
        bridge->b_odd_resp |= 0x000f000f;
    }
-    if (IS_PIC_SOFT(pcibr_soft)) {
+    bridge->p_int_enable_64 = (picreg_t)int_enable;
-        bridge->p_int_enable_64 = (picreg_t)int_enable;
-    } else {
-        bridge->b_int_enable = (bridgereg_t)int_enable;
-    }
    bridge->b_int_mode = 0;		/* do not send "clear interrupt" packets */
    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
@@ -1785,8 +1702,7 @@ pcibr_attach2(vertex_hdl_t xconn_vhdl, bridge_t *bridge,
    }
    /* Set up convenience links */
-    if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft))
+    pcibr_bus_cnvlink(pcibr_soft->bs_vhdl);
-	pcibr_bus_cnvlink(pcibr_soft->bs_vhdl);
    for (slot = pcibr_soft->bs_min_slot; 
 				slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot)
@@ -1890,11 +1806,7 @@ pcibr_detach(vertex_hdl_t xconn)
    s = pcibr_lock(pcibr_soft);
    /* Disable the interrupts from the bridge */
-    if (IS_PIC_SOFT(pcibr_soft)) {
+    bridge->p_int_enable_64 = 0;
-	bridge->p_int_enable_64 = 0;
-    } else {
-	bridge->b_int_enable = 0;
-    }
    pcibr_unlock(pcibr_soft, s);
    /* Detach all the PCI devices talking to this bridge */
@@ -2181,23 +2093,9 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn_vhdl,
 		devreg &= ~BRIDGE_DEV_DEV_SWAP;
 	    if (pcibr_soft->bs_slot[win].bss_device != devreg) {
-		if ( IS_PIC_SOFT(pcibr_soft) ) {
+		bridge->b_device[win].reg = devreg;
-			bridge->b_device[win].reg = devreg;
+		pcibr_soft->bs_slot[win].bss_device = devreg;
-			pcibr_soft->bs_slot[win].bss_device = devreg;
+		bridge->b_wid_tflush;   /* wait until Bridge PIO complete */
-			bridge->b_wid_tflush;   /* wait until Bridge PIO complete */
-		}
-		else {
-			if (io_get_sh_swapper(NASID_GET(bridge))) {
-				BRIDGE_REG_SET32((&bridge->b_device[win].reg)) = __swab32(devreg);
-				pcibr_soft->bs_slot[win].bss_device = devreg;
-				BRIDGE_REG_GET32((&bridge->b_wid_tflush)); /* wait until Bridge PIO complete */
-			} else {
-				bridge->b_device[win].reg = devreg;
-				pcibr_soft->bs_slot[win].bss_device = devreg;
-				bridge->b_wid_tflush;   /* wait until Bridge PIO complete */
-			}
-		}
 #ifdef PCI_LATER
 		PCIBR_DEBUG((PCIBR_DEBUG_DEVREG, pconn_vhdl, 
 			    "pcibr_addr_pci_to_xio: Device(%d): %x\n",
@@ -2310,10 +2208,8 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn_vhdl,
 	/*
 	 * PIC bridges do not support big-window aliases into PCI I/O space
 	 */
-	if (IS_PIC_SOFT(pcibr_soft)) {
+	xio_addr = XIO_NOWHERE;
-		xio_addr = XIO_NOWHERE;
+	break;
-		break;
-	}
 	/* Bridge Hardware Bug WAR #482741:
 	 * The 4G area that maps directly from
@@ -2355,31 +2251,13 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn_vhdl,
 	    }
 	    xio_addr = XIO_NOWHERE;
 	} else {			/* OK to make the change. */
+    	    picreg_t             octl, nctl;
 	    swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP;
-	    if ( IS_PIC_SOFT(pcibr_soft) ) {
+	    octl = bridge->p_wid_control_64;
-	    	picreg_t             octl, nctl;
+	    nctl = bst ? octl | (uint64_t)swb : octl & ((uint64_t)~swb);
-		octl = bridge->p_wid_control_64;
-		nctl = bst ? octl | (uint64_t)swb : octl & ((uint64_t)~swb);
-		if (octl != nctl)		/* make the change if any */
+	    if (octl != nctl)		/* make the change if any */
-			bridge->b_wid_control = nctl;
+		bridge->b_wid_control = nctl;
-	    }
-	    else {
-	    	picreg_t             octl, nctl;
-		if (io_get_sh_swapper(NASID_GET(bridge))) {
-			octl = BRIDGE_REG_GET32((&bridge->b_wid_control));
-			nctl = bst ? octl | swb : octl & ~swb;
-			if (octl != nctl)           /* make the change if any */
-				BRIDGE_REG_SET32((&bridge->b_wid_control)) = __swab32(nctl);
-		} else {
-			octl = bridge->b_wid_control;
-			nctl = bst ? octl | swb : octl & ~swb;
-			if (octl != nctl)           /* make the change if any */
-				bridge->b_wid_control = nctl;
-		}
-	    }
 	    *bfp = bfn;			/* record the assignment */
 	    if (pcibr_debug_mask & PCIBR_DEBUG_PIOMAP) {
@@ -2800,12 +2678,10 @@ pcibr_flags_to_d64(unsigned flags, pcibr_soft_t pcibr_soft)
 	attributes &= ~PCI64_ATTR_PREF;
    /* the swap bit is in the address attributes for xbridge */
-    if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) {
+    if (flags & PCIIO_BYTE_STREAM)
-    	if (flags & PCIIO_BYTE_STREAM)
+       	attributes |= PCI64_ATTR_SWAP;
-        	attributes |= PCI64_ATTR_SWAP;
+    if (flags & PCIIO_WORD_VALUES)
-    	if (flags & PCIIO_WORD_VALUES)
+       	attributes &= ~PCI64_ATTR_SWAP;
-        	attributes &= ~PCI64_ATTR_SWAP;
-    }
    /* Provider-specific flags
     */
@@ -2933,7 +2809,7 @@ pcibr_dmamap_alloc(vertex_hdl_t pconn_vhdl,
 	 * don't fall thru and try 32-bit direct mapping or 32-bit
 	 * page mapping
 	 */
-	if (IS_PIC_SOFT(pcibr_soft) && IS_PCIX(pcibr_soft)) {
+	if (IS_PCIX(pcibr_soft)) {
 	    kfree(pcibr_dmamap);
 	    return 0;
 	}
@@ -3007,19 +2883,17 @@ pcibr_dmamap_alloc(vertex_hdl_t pconn_vhdl,
 	    /*
 	     * for xbridge the byte-swap bit == bit 29 of PCI address
 	     */
-	    if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) {
+	    if (flags & PCIIO_BYTE_STREAM)
-		    if (flags & PCIIO_BYTE_STREAM)
+		    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
-			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+	    /*
-		    /*
+	     * If swap was set in bss_device in pcibr_endian_set()
-		     * If swap was set in bss_device in pcibr_endian_set()
+	     * we need to change the address bit.
-		     * we need to change the address bit.
+	     */
-		     */
+	    if (pcibr_soft->bs_slot[slot].bss_device & 
-		    if (pcibr_soft->bs_slot[slot].bss_device & 
+						BRIDGE_DEV_SWAP_PMU)
-							BRIDGE_DEV_SWAP_PMU)
+		    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
-			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+	    if (flags & PCIIO_WORD_VALUES)
-		    if (flags & PCIIO_WORD_VALUES)
+		    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
-			    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
-	    }
 	    pcibr_dmamap->bd_xio_addr = 0;
 	    pcibr_dmamap->bd_ate_ptr = pcibr_ate_addr(pcibr_soft, ate_index);
 	    pcibr_dmamap->bd_ate_index = ate_index;
@@ -3040,32 +2914,6 @@ pcibr_dmamap_alloc(vertex_hdl_t pconn_vhdl,
 					       min_rrbs - have_rrbs);
 		}
 	    }
-	    if (ate_index >= pcibr_soft->bs_int_ate_size && 
-				!IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) {
-		bridge_t               *bridge = pcibr_soft->bs_base;
-		volatile unsigned      *cmd_regp;
-		unsigned                cmd_reg;
-		unsigned long           s;
-		pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM;
-		s = pcibr_lock(pcibr_soft);
-		cmd_regp = pcibr_slot_config_addr(bridge, slot, 
-						PCI_CFG_COMMAND/4);
-		if ( IS_PIC_SOFT(pcibr_soft) ) {
-			cmd_reg = pcibr_slot_config_get(bridge, slot, PCI_CFG_COMMAND/4);
-		}
-		else {
-			if (io_get_sh_swapper(NASID_GET(bridge))) {
-				BRIDGE_REG_SET32((&cmd_reg)) = __swab32(*cmd_regp);
-			} else {
-				cmd_reg = pcibr_slot_config_get(bridge, slot, PCI_CFG_COMMAND/4);
-			}
-		}
-		pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp;
-		pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg;
-		pcibr_unlock(pcibr_soft, s);
-	    }
 	    return pcibr_dmamap;
 	}
 	PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pconn_vhdl,
@@ -3311,16 +3159,7 @@ pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
 		ATE_FREEZE();
 		ATE_WRITE();
 		ATE_THAW();
-		if ( IS_PIC_SOFT(pcibr_soft) ) {
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-			bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-		}
-		else {
-			if (io_get_sh_swapper(NASID_GET(bridge))) {
-				BRIDGE_REG_GET32((&bridge->b_wid_tflush));
-			} else {
-				bridge->b_wid_tflush;
-			}
-		}
 		PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev,
 			    "pcibr_dmamap_addr (PMU) : wanted paddr "
 			    "[0x%x..0x%x] returning PCI 0x%x\n", 
@@ -3706,22 +3545,9 @@ pcibr_endian_set(vertex_hdl_t pconn_vhdl,
    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
 	bridge_t               *bridge = pcibr_soft->bs_base;
-	if ( IS_PIC_SOFT(pcibr_soft) ) {
+	bridge->b_device[pciio_slot].reg = devreg;
-		bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-		pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-		bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-	}
-	else {
-		if (io_get_sh_swapper(NASID_GET(bridge))) {
-			BRIDGE_REG_SET32((&bridge->b_device[pciio_slot].reg)) = __swab32(devreg);
-			pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-			BRIDGE_REG_GET32((&bridge->b_wid_tflush));/* wait until Bridge PIO complete */
-		} else {
-			bridge->b_device[pciio_slot].reg = devreg;
-			pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-			bridge->b_wid_tflush;           /* wait until Bridge PIO complete */
-		}
-	}
    }
    pcibr_unlock(pcibr_soft, s);
@@ -3793,22 +3619,9 @@ pcibr_priority_bits_set(pcibr_soft_t pcibr_soft,
    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
 	bridge_t               *bridge = pcibr_soft->bs_base;
-	if ( IS_PIC_SOFT(pcibr_soft) ) {
+	bridge->b_device[pciio_slot].reg = devreg;
-		bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-		pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-		bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-	}
-	else {
-		if (io_get_sh_swapper(NASID_GET(bridge))) {
-			BRIDGE_REG_SET32((&bridge->b_device[pciio_slot].reg)) = __swab32(devreg);
-			pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-			BRIDGE_REG_GET32((&bridge->b_wid_tflush));/* wait until Bridge PIO complete */
-		} else {
-			bridge->b_device[pciio_slot].reg = devreg;
-			pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-			bridge->b_wid_tflush;           /* wait until Bridge PIO complete */
-		}
-	}
    }
    pcibr_unlock(pcibr_soft, s);
@@ -3891,22 +3704,9 @@ pcibr_device_flags_set(vertex_hdl_t pconn_vhdl,
 	if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
 	    bridge_t               *bridge = pcibr_soft->bs_base;
-	    if ( IS_PIC_SOFT(pcibr_soft) ) {
+	    bridge->b_device[pciio_slot].reg = devreg;
-		bridge->b_device[pciio_slot].reg = devreg;
+	    pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-		pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-	    }
-	    else {
-		if (io_get_sh_swapper(NASID_GET(bridge))) {
-			BRIDGE_REG_SET32((&bridge->b_device[pciio_slot].reg)) = __swab32(devreg);
-			pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-			BRIDGE_REG_GET32((&bridge->b_wid_tflush));/* wait until Bridge PIO complete */
-		} else {
-			bridge->b_device[pciio_slot].reg = devreg;
-			pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-			bridge->b_wid_tflush;       /* wait until Bridge PIO complete */
-		}
-	    }
 	}
 	pcibr_unlock(pcibr_soft, s);
 	printk("pcibr_device_flags_set: Device(%d): %x\n", pciio_slot, devreg);

--- a/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c
@@ -170,7 +170,7 @@ static struct reg_desc   device_bits[] =
 static char             *pcibr_isr_errs[] =
 {
    "", "", "", "", "", "", "", "",
-    "08: GIO non-contiguous byte enable in crosstalk packet", /* BRIDGE ONLY */
+    "08: Reserved Bit 08",
    "09: PCI to Crosstalk read request timeout",
    "10: PCI retry operation count exhausted.",
    "11: PCI bus device select timeout",
@@ -178,12 +178,12 @@ static char             *pcibr_isr_errs[] =
    "13: PCI Address/Cmd parity error ",
    "14: PCI Bridge detected parity error",
    "15: PCI abort condition",
-    "16: SSRAM parity error", /* BRIDGE ONLY */
+    "16: Reserved Bit 16",
-    "17: LLP Transmitter Retry count wrapped",
+    "17: LLP Transmitter Retry count wrapped",	/* PIC ONLY */
-    "18: LLP Transmitter side required Retry",
+    "18: LLP Transmitter side required Retry",	/* PIC ONLY */
-    "19: LLP Receiver retry count wrapped",
+    "19: LLP Receiver retry count wrapped",	/* PIC ONLY */
-    "20: LLP Receiver check bit error",
+    "20: LLP Receiver check bit error",		/* PIC ONLY */
-    "21: LLP Receiver sequence number error",
+    "21: LLP Receiver sequence number error",	/* PIC ONLY */
    "22: Request packet overflow",
    "23: Request operation not supported by bridge",
    "24: Request packet has invalid address for bridge widget",
@@ -193,9 +193,7 @@ static char             *pcibr_isr_errs[] =
    "28: Framing error, response cmd data size does not match actual",
    "29: Unexpected response arrived",
    "30: PMU Access Fault",
-    "31: Multiple errors occurred", /* BRIDGE ONLY */
+    "31: Reserved Bit 31",
-    /* bits 32-45 are PIC ONLY */
    "32: PCI-X address or attribute cycle parity error",
    "33: PCI-X data cycle parity error",
    "34: PCI-X master timeout (ie. master abort)",
@@ -336,10 +334,8 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft)
 {
    bridge_t               *bridge = pcibr_soft->bs_base;
    uint64_t		    int_status;
-    bridgereg_t             int_status_32;
    picreg_t		    int_status_64;
    uint64_t		    mult_int;
-    bridgereg_t             mult_int_32;
    picreg_t		    mult_int_64;
    uint64_t		    bit;
    int			    number_bits;
@@ -347,19 +343,9 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft)
    char		    *reg_desc;
    paddr_t		    addr = (paddr_t)0;
-    /* We read the INT_STATUS register as a 64bit picreg_t for PIC and a
+    int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK);
-     * 32bit bridgereg_t for BRIDGE, but always process the result as a
+    int_status = (uint64_t)int_status_64;
-     * 64bit value so the code can be "common" for both PIC and BRIDGE...
+    number_bits = PCIBR_ISR_MAX_ERRS_PIC;
-     */
-    if (IS_PIC_SOFT(pcibr_soft)) {
-	int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK);
-	int_status = (uint64_t)int_status_64;
-	number_bits = PCIBR_ISR_MAX_ERRS_PIC;
-    } else {
-	int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
-	int_status = ((uint64_t)int_status_32) & 0xffffffff;
-	number_bits = PCIBR_ISR_MAX_ERRS_BRIDGE;
-    }
    if (!int_status) {
 	/* No error bits set */
@@ -374,8 +360,7 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft)
    printk(KERN_ALERT "PCI BRIDGE ERROR: int_status is 0x%lx for %s\n"
 	"    Dumping relevant %s registers for each bit set...\n",
 	    int_status, pcibr_soft->bs_name,
-	    (IS_PIC_SOFT(pcibr_soft) ? "PIC" : 
+	    "PIC");
-	        (IS_BRIDGE_SOFT(pcibr_soft) ? "BRIDGE" : "XBRIDGE")));
    for (i = PCIBR_ISR_ERR_START; i < number_bits; i++) {
 	bit = 1ull << i;
@@ -384,15 +369,14 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft)
 	 * A number of int_status bits are only defined for Bridge.
 	 * Ignore them in the case of an XBridge or PIC.
 	 */
-	if ((IS_XBRIDGE_SOFT(pcibr_soft) || IS_PIC_SOFT(pcibr_soft)) &&
+	if (((bit == BRIDGE_ISR_MULTI_ERR) ||
-	    ((bit == BRIDGE_ISR_MULTI_ERR) ||
 	     (bit == BRIDGE_ISR_SSRAM_PERR) ||
 	     (bit == BRIDGE_ISR_GIO_B_ENBL_ERR))) {
 	    continue;
 	}
 	/* A number of int_status bits are only valid for PIC's bus0 */
-	if ((IS_PIC_SOFT(pcibr_soft) && (pcibr_soft->bs_busnum != 0)) && 
+	if (((pcibr_soft->bs_busnum != 0)) && 
 	    ((bit == BRIDGE_ISR_UNSUPPORTED_XOP) ||
 	     (bit == BRIDGE_ISR_LLP_REC_SNERR) ||
 	     (bit == BRIDGE_ISR_LLP_REC_CBERR) ||
@@ -458,10 +442,7 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft)
 		break;
 	    case BRIDGE_ISR_PAGE_FAULT:	    /* bit30	PMU_PAGE_FAULT */
-		if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft))
+	        reg_desc = "Map Fault Address";
-		    reg_desc = "Map Fault Address";
-		else
-		    reg_desc = "SSRAM Parity Error";
 		printk( "\t    %s Register: 0x%x\n", reg_desc,
 		    bridge->b_ram_perr_or_map_fault);
@@ -471,7 +452,7 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft)
 		print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
 		/* PIC in PCI-X mode, dump the PCIX DMA Request registers */
-		if (IS_PIC_SOFT(pcibr_soft) && IS_PCIX(pcibr_soft)) {
+		if (IS_PCIX(pcibr_soft)) {
 		    /* XXX: should breakdown meaning of attr bit */
 		    printk( 
 			"\t    PCI-X DMA Request Error Addr Reg: 0x%lx\n"
@@ -483,32 +464,14 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft)
 	    case BRIDGE_ISR_BAD_XRESP_PKT:  /* bit28	BAD_RESP_PACKET */
 	    case BRIDGE_ISR_RESP_XTLK_ERR:  /* bit26	RESP_XTALK_ERROR */
-		if (IS_PIC_SOFT(pcibr_soft)) {
+	        print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
-		    print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
-		}
-		/* If PIC in PCI-X mode, DMA Request Error registers are
+		/* XXX: should breakdown meaning of attribute bit */
-		 * valid.  But PIC in PCI mode, Response Buffer Address 
+		printk( 
-		 * register are valid.
-		 */
-		if (IS_PCIX(pcibr_soft)) {
-		    /* XXX: should breakdown meaning of attribute bit */
-		    printk( 
 			"\t    PCI-X DMA Request Error Addr Reg: 0x%lx\n"
 		        "\t    PCI-X DMA Request Error Attribute Reg: 0x%lx\n",
 		        bridge->p_pcix_dma_req_err_addr_64,
 		        bridge->p_pcix_dma_req_err_attr_64);
-		} else {
-		    addr= (((uint64_t)(bridge->b_wid_resp_upper & 0xFFFF)<<32)
-			   | bridge->b_wid_resp_lower);
-		    printk("\t    Bridge Response Buf Error Upper Addr Reg: 0x%x\n"
-		        "\t    Bridge Response Buf Error Lower Addr Reg: 0x%x\n"
-		        "\t    dev-num %d buff-num %d addr 0x%lx\n",
-		        bridge->b_wid_resp_upper, bridge->b_wid_resp_lower,
-		        ((bridge->b_wid_resp_upper >> 20) & 0x3),
-		        ((bridge->b_wid_resp_upper >> 16) & 0xF),
-		        addr);
-		}
 		if (bit == BRIDGE_ISR_RESP_XTLK_ERR) {
 			/* display memory directory associated with cacheline */
 			pcibr_show_dir_state(addr, "\t    ");
@@ -530,40 +493,17 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft)
 		break;
 	    case BRIDGE_ISR_UNSUPPORTED_XOP:/* bit23	UNSUPPORTED_XOP */
-		if (IS_PIC_SOFT(pcibr_soft)) {
+		print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
-		    print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
+		printk( 
-		    printk( 
 			"\t    Address Holding Link Side Error Reg: 0x%lx\n",
-			bridge->p_addr_lkerr_64);
+		bridge->p_addr_lkerr_64);
-		} else {
-		    print_bridge_errcmd(bridge->b_wid_err_cmdword, "");
-		    printk( 
-			"\t    Bridge Error Upper Address Register: 0x%lx\n"
-		        "\t    Bridge Error Lower Address Register: 0x%lx\n"
-		        "\t    Bridge Error Address: 0x%lx\n",
-		        (uint64_t) bridge->b_wid_err_upper,
-		        (uint64_t) bridge->b_wid_err_lower,
-		        (((uint64_t) bridge->b_wid_err_upper << 32) |
-		        bridge->b_wid_err_lower));
-		}
 		break;
 	    case BRIDGE_ISR_XREQ_FIFO_OFLOW:/* bit22	XREQ_FIFO_OFLOW */
-		/* Link side error registers are only valid for PIC */
+		print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
-		if (IS_PIC_SOFT(pcibr_soft)) {
+		printk(
-		    print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
-		    printk(
 			"\t    Address Holding Link Side Error Reg: 0x%lx\n",
-			bridge->p_addr_lkerr_64);
+		bridge->p_addr_lkerr_64);
-		}
-		break;
-	    case BRIDGE_ISR_SSRAM_PERR:	    /* bit16	SSRAM_PERR */
-		if (IS_BRIDGE_SOFT(pcibr_soft)) {
-		    printk(
-			"\t    Bridge SSRAM Parity Error Register: 0x%x\n",
-			bridge->b_ram_perr);
-		}
 		break;
 	    case BRIDGE_ISR_PCI_ABORT:	    /* bit15	PCI_ABORT */
@@ -599,23 +539,13 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft)
 	}
    }
-    /* We read the INT_MULT register as a 64bit picreg_t for PIC and a
+    mult_int_64 = (bridge->p_mult_int_64 & ~BRIDGE_ISR_INT_MSK);
-     * 32bit bridgereg_t for BRIDGE, but always process the result as a
+    mult_int = (uint64_t)mult_int_64;
-     * 64bit value so the code can be "common" for both PIC and BRIDGE...
+    number_bits = PCIBR_ISR_MAX_ERRS_PIC;
-     */
-    if (IS_PIC_SOFT(pcibr_soft)) {
-	mult_int_64 = (bridge->p_mult_int_64 & ~BRIDGE_ISR_INT_MSK);
-	mult_int = (uint64_t)mult_int_64;
-	number_bits = PCIBR_ISR_MAX_ERRS_PIC;
-    } else {
-	mult_int_32 = (bridge->b_mult_int & ~BRIDGE_ISR_INT_MSK);
-	mult_int = ((uint64_t)mult_int_32) & 0xffffffff;
-	number_bits = PCIBR_ISR_MAX_ERRS_BRIDGE;
-    }
-    if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)&&(mult_int & ~BRIDGE_ISR_INT_MSK)) {
+    if (mult_int & ~BRIDGE_ISR_INT_MSK) {
 	printk( "    %s Multiple Interrupt Register is 0x%lx\n",
-		IS_PIC_SOFT(pcibr_soft) ? "PIC" : "XBridge", mult_int);
+		"PIC", mult_int);
 	for (i = PCIBR_ISR_ERR_START; i < number_bits; i++) {
 	    if (mult_int & (1ull << i))
 		printk( "\t%s\n", pcibr_isr_errs[i]);
@@ -623,29 +553,6 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft)
    }
 }
-static uint32_t
-pcibr_errintr_group(uint32_t error)
-{
-    uint32_t              group = BRIDGE_IRR_MULTI_CLR;
-    if (error & BRIDGE_IRR_PCI_GRP)
-	group |= BRIDGE_IRR_PCI_GRP_CLR;
-    if (error & BRIDGE_IRR_SSRAM_GRP)
-	group |= BRIDGE_IRR_SSRAM_GRP_CLR;
-    if (error & BRIDGE_IRR_LLP_GRP)
-	group |= BRIDGE_IRR_LLP_GRP_CLR;
-    if (error & BRIDGE_IRR_REQ_DSP_GRP)
-	group |= BRIDGE_IRR_REQ_DSP_GRP_CLR;
-    if (error & BRIDGE_IRR_RESP_BUF_GRP)
-	group |= BRIDGE_IRR_RESP_BUF_GRP_CLR;
-    if (error & BRIDGE_IRR_CRP_GRP)
-	group |= BRIDGE_IRR_CRP_GRP_CLR;
-    return group;
-}
 /* pcibr_pioerr_check():
 *	Check to see if this pcibr has a PCI PIO
 *	TIMEOUT error; if so, bump the timeout-count
@@ -656,7 +563,6 @@ pcibr_pioerr_check(pcibr_soft_t soft)
 {
    bridge_t		   *bridge;
    uint64_t              int_status;
-    bridgereg_t             int_status_32;
    picreg_t                int_status_64;
    bridgereg_t		    pci_err_lower;
    bridgereg_t		    pci_err_upper;
@@ -669,18 +575,8 @@ pcibr_pioerr_check(pcibr_soft_t soft)
    int			    func;
    bridge = soft->bs_base;
+    int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK);
-    /* We read the INT_STATUS register as a 64bit picreg_t for PIC and a
+    int_status = (uint64_t)int_status_64;
-     * 32bit bridgereg_t for BRIDGE, but always process the result as a
-     * 64bit value so the code can be "common" for both PIC and BRIDGE...
-     */
-    if (IS_PIC_SOFT(soft)) {
-        int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK);
-        int_status = (uint64_t)int_status_64;
-    } else {
-        int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
-        int_status = ((uint64_t)int_status_32) & 0xffffffff;
-    }
    if (int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
 	pci_err_lower = bridge->b_pci_err_lower;
@@ -744,7 +640,6 @@ pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *ep)
    bridge_t               *bridge;
    uint64_t              int_status;
    uint64_t              err_status;
-    bridgereg_t             int_status_32;
    picreg_t                int_status_64;
    int			    number_bits;
    int                     i;
@@ -807,19 +702,9 @@ pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *ep)
 	return(pcibr_error_intr_handler(irq, arg, ep));
    }
-    /* We read the INT_STATUS register as a 64bit picreg_t for PIC and a
+    int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK);
-     * 32bit bridgereg_t for BRIDGE, but always process the result as a
+    int_status = (uint64_t)int_status_64;
-     * 64bit value so the code can be "common" for both PIC and BRIDGE...
+    number_bits = PCIBR_ISR_MAX_ERRS_PIC;
-     */
-    if (IS_PIC_SOFT(pcibr_soft)) {
-        int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK);
-        int_status = (uint64_t)int_status_64;
-        number_bits = PCIBR_ISR_MAX_ERRS_PIC;
-    } else {
-        int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
-        int_status = ((uint64_t)int_status_32) & 0xffffffff;
-        number_bits = PCIBR_ISR_MAX_ERRS_BRIDGE;
-    }
    PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ERROR, pcibr_soft->bs_conn,
 		"pcibr_error_intr_handler: int_status=0x%x\n", int_status));
@@ -954,8 +839,7 @@ pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *ep)
 		 * interrupt inorder to clear the DEV_BROKE bits in
 		 * b_arb register to re-enable the device.
 		 */
-		if (IS_PIC_SOFT(pcibr_soft) &&
+		if (!(err_status & PIC_ISR_PCIX_ARB_ERR) &&
-				!(err_status & PIC_ISR_PCIX_ARB_ERR) &&
 				PCIBR_WAR_ENABLED(PV856155, pcibr_soft)) {
 		if (bs_estat->bs_errcount_total > PCIBR_ERRINTR_DISABLE_LEVEL) {
@@ -983,11 +867,7 @@ pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *ep)
 	 * could eat up too much cpu time.
 	 */
 	s = pcibr_lock(pcibr_soft);
-	if (IS_PIC_SOFT(pcibr_soft)) {
+	bridge->p_int_enable_64 &= (picreg_t)(~disable_errintr_mask);
-	    bridge->p_int_enable_64 &= (picreg_t)(~disable_errintr_mask);
-	} else {
-	    bridge->b_int_enable &= (bridgereg_t)(~disable_errintr_mask);
-	}
 	pcibr_unlock(pcibr_soft, s);
    }
    /*
@@ -1032,7 +912,7 @@ pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *ep)
     * so we know we've hit the problem defined in PV 867308 that we believe
     * has only been seen in simulation
     */
-    if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV867308, pcibr_soft) &&
+    if (PCIBR_WAR_ENABLED(PV867308, pcibr_soft) &&
        (err_status & (BRIDGE_ISR_LLP_REC_SNERR | BRIDGE_ISR_LLP_REC_CBERR))) {
        printk("BRIDGE ERR_STATUS 0x%lx\n", err_status);
        pcibr_error_dump(pcibr_soft);
@@ -1053,18 +933,13 @@ pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *ep)
     * 
     * PIC doesn't require groups of interrupts to be cleared...
     */
-    if (IS_PIC_SOFT(pcibr_soft)) {
+    bridge->p_int_rst_stat_64 = (picreg_t)(int_status | BRIDGE_IRR_MULTI_CLR);
-	bridge->p_int_rst_stat_64 = (picreg_t)(int_status | BRIDGE_IRR_MULTI_CLR);
-    } else {
-	bridge->b_int_rst_stat = (bridgereg_t)pcibr_errintr_group(int_status);
-    }
    /* PIC BRINGUP WAR (PV# 856155):
     * On a PCI_X_ARB_ERR error interrupt clear the DEV_BROKE bits from
     * the b_arb register to re-enable the device.
     */
-    if (IS_PIC_SOFT(pcibr_soft) &&
+    if ((err_status & PIC_ISR_PCIX_ARB_ERR) &&
-		(err_status & PIC_ISR_PCIX_ARB_ERR) &&
 		PCIBR_WAR_ENABLED(PV856155, pcibr_soft)) {
 	bridge->b_arb |= (0xf << 20);
    }
@@ -1081,14 +956,9 @@ pcibr_error_cleanup(pcibr_soft_t pcibr_soft, int error_code)
    ASSERT(error_code & IOECODE_PIO);
    error_code = error_code;
-    if (IS_PIC_SOFT(pcibr_soft)) {
+    bridge->p_int_rst_stat_64 = BRIDGE_IRR_PCI_GRP_CLR |
-        bridge->p_int_rst_stat_64 = BRIDGE_IRR_PCI_GRP_CLR |
 				    PIC_PCIX_GRP_CLR |
 				    BRIDGE_IRR_MULTI_CLR;
-    } else {
-        bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR;
-    }
    (void) bridge->b_wid_tflush;	/* flushbus */
 }
@@ -1522,13 +1392,8 @@ pcibr_pioerror(
 	     */
 	    BEM_ADD_STR("Raw info from Bridge/PCI layer:\n");
-	    if (IS_PIC_SOFT(pcibr_soft)) {
+	    if (bridge->p_int_status_64 & (picreg_t)BRIDGE_ISR_PCIBUS_PIOERR)
-		if (bridge->p_int_status_64 & (picreg_t)BRIDGE_ISR_PCIBUS_PIOERR)
+		pcibr_error_dump(pcibr_soft);
-		    pcibr_error_dump(pcibr_soft);
-	    } else {
-		if (bridge->b_int_status & (bridgereg_t)BRIDGE_ISR_PCIBUS_PIOERR)
-		    pcibr_error_dump(pcibr_soft);
-	    }
 	    BEM_ADD_SPC(raw_space);
 	    BEM_ADD_VAR(raw_paddr);
 	    if (IOERROR_FIELDVALID(ioe, widgetdev)) {

--- a/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c
@@ -281,9 +281,7 @@ pcibr_force_interrupt(pcibr_intr_t intr)
 			PCIBR_DEBUG((PCIBR_DEBUG_INTR, pcibr_soft->bs_vhdl,
 		    		"pcibr_force_interrupt: bit=0x%x\n", bit));
-			if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) {
+    			bridge->b_force_pin[bit].intr = 1;
-	    			bridge->b_force_pin[bit].intr = 1;
-			}
 		}
 	}
 }
@@ -651,10 +649,7 @@ pcibr_intr_connect(pcibr_intr_t pcibr_intr, intr_func_t intr_func, intr_arg_t in
 	     * Use the pcibr wrapper function to handle all Bridge interrupts
 	     * regardless of whether the interrupt line is shared or not.
 	     */
-	    if (IS_PIC_SOFT(pcibr_soft)) 
+	    int_addr = (void *)&(bridge->p_int_addr_64[pcibr_int_bit]);
-		int_addr = (void *)&(bridge->p_int_addr_64[pcibr_int_bit]);
-	    else
-		int_addr = (void *)&(bridge->b_int_addr[pcibr_int_bit].addr);
 	    xtalk_intr_connect(xtalk_intr, pcibr_intr_func, (intr_arg_t) intr_wrap,
 					(xtalk_intr_setfunc_t) pcibr_setpciint,
@@ -673,8 +668,7 @@ pcibr_intr_connect(pcibr_intr_t pcibr_intr, intr_func_t intr_func, intr_arg_t in
 	 * On PIC we must write 64-bit MMRs with 64-bit stores
 	 */
 	s = pcibr_lock(pcibr_soft);
-	if (IS_PIC_SOFT(pcibr_soft) &&
+	if (PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
-			PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
 	    int_enable = bridge->p_int_enable_64;
 	    int_enable |= pcibr_int_bits;
 	    bridge->p_int_enable_64 = int_enable;
@@ -728,7 +722,7 @@ pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
     * On PIC we must write 64-bit MMRs with 64-bit stores
     */
    s = pcibr_lock(pcibr_soft);
-    if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
+    if (PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
 	int_enable = bridge->p_int_enable_64;
 	int_enable &= ~pcibr_int_bits;
 	bridge->p_int_enable_64 = int_enable;
@@ -773,10 +767,7 @@ pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
            if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
                continue;
-            if (IS_PIC_SOFT(pcibr_soft))
+            int_addr = (void *)&(bridge->p_int_addr_64[pcibr_int_bit]);
-                int_addr = (void *)&(bridge->p_int_addr_64[pcibr_int_bit]);
-            else
-                int_addr = (void *)&(bridge->b_int_addr[pcibr_int_bit].addr);
 	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
 				pcibr_intr_func, (intr_arg_t) intr_wrap,
@@ -948,8 +939,7 @@ pcibr_intr_func(intr_arg_t arg)
 	 * interrupt problem.   Briefly disable the enable bit for
 	 * this device.
 	 */
-	if (IS_PIC_SOFT(pcibr_soft) &&
+	if (PCIBR_WAR_ENABLED(PV855272, pcibr_soft)) {
-			PCIBR_WAR_ENABLED(PV855272, pcibr_soft)) {
 		unsigned s;
 		/* disable-enable interrupts for this bridge pin */
@@ -1059,8 +1049,7 @@ pcibr_intr_func(intr_arg_t arg)
 	     * On PIC we must write 64-bit MMRs with 64-bit stores
 	     */
 	    s = pcibr_lock(pcibr_soft);
-	    if (IS_PIC_SOFT(pcibr_soft) &&
+	    if (PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
-				PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
 		int_enable = bridge->p_int_enable_64;
 		int_enable &= ~mask;
 		bridge->p_int_enable_64 = int_enable;

--- a/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c
@@ -401,18 +401,8 @@ pcibr_wrb_flush(vertex_hdl_t pconn_vhdl)
    volatile bridgereg_t   *wrb_flush;
    wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
-    if ( IS_PIC_SOFT(pcibr_soft) ) {
+    while (*wrb_flush)
-	while (*wrb_flush)
+	;
-		;
-    }
-    else {
-	if (io_get_sh_swapper(NASID_GET(bridge))) {
-		while (BRIDGE_REG_GET32((wrb_flush)));
-	} else {
-		while (*wrb_flush)
-			;
-	}
-    }
    return(0);
 }
@@ -710,24 +700,17 @@ pcibr_slot_initial_rrb_alloc(vertex_hdl_t pcibr_vhdl,
    for (vchan = 0; vchan < vchan_total; vchan++) 
        chan[vchan] = do_pcibr_rrb_count_valid(bridge, slot, vchan);
-    if (IS_PIC_SOFT(pcibr_soft)) {
+    PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_vhdl,
- 	PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_vhdl,
 	    "pcibr_slot_initial_rrb_alloc: slot %d started with %d+%d+%d+%d\n",
 	    PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), 
 	    chan[VCHAN0], chan[VCHAN1], chan[VCHAN2], chan[VCHAN3]));
-    } else {
-	PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_vhdl,
-	    "pcibr_slot_initial_rrb_alloc: slot %d started with %d+%d\n",
-	    PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), 
-	    chan[VCHAN0], chan[VCHAN1]));
-    }
    /* Do we really need any?
     */
    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
    pcibr_info = pcibr_infoh[0];
-    if (PCIBR_WAR_ENABLED(PV856866, pcibr_soft) && IS_PIC_SOFT(pcibr_soft) &&
+    if (PCIBR_WAR_ENABLED(PV856866, pcibr_soft) &&
                        (slot == 2 || slot == 3) &&
                        (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
                        !pcibr_soft->bs_slot[slot].has_host) {
@@ -867,13 +850,8 @@ pcibr_rrb_debug(char *calling_func, pcibr_soft_t pcibr_soft)
                    "%s: rrbs available, even=%d, odd=%d\n", calling_func,
                    pcibr_soft->bs_rrb_avail[0], pcibr_soft->bs_rrb_avail[1]));
-        if (IS_PIC_SOFT(pcibr_soft)) {
+        PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
-            PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
                        "\tslot\tvchan0\tvchan1\tvchan2\tvchan3\treserved\n"));
-        } else {
-	    PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
-		        "\tslot\tvchan0\tvchan1\treserved\n"));
-        }
        for (slot=0; slot < PCIBR_NUM_SLOTS(pcibr_soft); slot++) {
 	    /*
@@ -881,22 +859,13 @@ pcibr_rrb_debug(char *calling_func, pcibr_soft_t pcibr_soft)
             * attempting to call PCIBR_DEBUG_ALWAYS() with more than 5 printf
             * arguments fails so sprintf() it into a temporary string.
             */
-	    if (IS_PIC_SOFT(pcibr_soft)) {
+            sprintf(tmp_str, "\t %d\t  %d\t  %d\t  %d\t  %d\t  %d\n", 
-                sprintf(tmp_str, "\t %d\t  %d\t  %d\t  %d\t  %d\t  %d\n", 
 		        PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
                        0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN0],
                        0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN1],
                        0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN2],
                        0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN3],
                        pcibr_soft->bs_rrb_res[slot]);
-	    } else {
-	        sprintf(tmp_str, "\t %d\t  %d\t  %d\t  %d\n", 
-		        PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
-		        0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN0],
-		        0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN1],
-		        pcibr_soft->bs_rrb_res[slot]);
-	    }
            PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
                        "%s", tmp_str));
        }

--- a/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c
@@ -380,13 +380,8 @@ pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
    slotp->resp_b_int_device = bridge->b_int_device;
-    if (IS_PIC_SOFT(pcibr_soft)) {
+    slotp->resp_p_int_enable = bridge->p_int_enable_64;
-	slotp->resp_p_int_enable = bridge->p_int_enable_64;
+    slotp->resp_p_int_host = bridge->p_int_addr_64[slot];
-	slotp->resp_p_int_host = bridge->p_int_addr_64[slot];
-    } else {
-	slotp->resp_b_int_enable = bridge->b_int_enable;
-	slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
-    }
    if (COPYOUT(slotp, respp, sizeof(*respp))) {
        return(EFAULT);
@@ -1364,7 +1359,7 @@ pcibr_slot_device_init(vertex_hdl_t pcibr_vhdl,
     * for 64-bit devices).  We set the bit in pcibr_try_set_device()
     * if we're 64-bit and requesting virtual channels.
     */
-    if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV855271, pcibr_soft))
+    if (PCIBR_WAR_ENABLED(PV855271, pcibr_soft))
 	devreg |= BRIDGE_DEV_COH;
    else
 	devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;

--- a/arch/ia64/sn/io/sn2/shub.c
+++ b/arch/ia64/sn/io/sn2/shub.c
@@ -6,8 +6,6 @@
 * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc.  All Rights Reserved.
 */
-#ident  "$Revision: 1.167 $"
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>
@@ -35,43 +33,6 @@
 #include <asm/sn/sn2/shubio.h>
 #include <asm/sn/sn2/shub_mmr.h>
-/*
- * Shub WAR for Xbridge Little Endian problem:
- *	Xbridge has to run in BIG ENDIAN even with Shub.
- */
-/*
- * io_sh_swapper: Turn on Shub byte swapping.
- *	All data destined to and from Shub to XIO are byte-swapped.
- */
-void
-io_sh_swapper(nasid_t nasid, int onoff)
-{
-    ii_iwc_u_t      ii_iwc;
-    ii_iwc.ii_iwc_regval = REMOTE_HUB_L(nasid, IIO_IWC);
-    ii_iwc.ii_iwc_fld_s.i_dma_byte_swap = onoff;
-    REMOTE_HUB_S(nasid, IIO_IWC, ii_iwc.ii_iwc_regval);
-    ii_iwc.ii_iwc_regval = REMOTE_HUB_L(nasid, IIO_IWC);
-}
-/*
- * io_get_sh_swapper: Return current Swap mode.
- *	1 = Swap on, 0 = Swap off.
- */
-int
-io_get_sh_swapper(nasid_t nasid)
-{
-    ii_iwc_u_t      ii_iwc;
-    ii_iwc.ii_iwc_regval = REMOTE_HUB_L(nasid, IIO_IWC);
-    return(ii_iwc.ii_iwc_fld_s.i_dma_byte_swap);
-}
 #define SHUB_NUM_ECF_REGISTERS 8
 static uint32_t	shub_perf_counts[SHUB_NUM_ECF_REGISTERS];

--- a/arch/ia64/sn/kernel/setup.c
+++ b/arch/ia64/sn/kernel/setup.c
@@ -216,7 +216,6 @@ sn_setup(char **cmdline_p)
 	long status, ticks_per_sec, drift;
 	int pxm;
 	int major = sn_sal_rev_major(), minor = sn_sal_rev_minor();
-	extern void io_sh_swapper(int, int);
 	extern nasid_t get_master_baseio_nasid(void);
 	extern void sn_cpu_init(void);
@@ -239,8 +238,6 @@ sn_setup(char **cmdline_p)
 		panic("PROM version too old\n");
 	}
-	io_sh_swapper(get_nasid(), 0);
 	master_nasid = get_nasid();
 	(void)get_console_nasid();
 	(void)get_master_baseio_nasid();

--- a/include/asm-ia64/sn/iograph.h
+++ b/include/asm-ia64/sn/iograph.h
@@ -18,13 +18,10 @@
 /* edges names */
 #define EDGE_LBL_BUS			"bus"
 #define EDGE_LBL_CONN			".connection"
-#define EDGE_LBL_ECP			"ecp"		/* EPP/ECP plp */
-#define EDGE_LBL_ECPP			"ecpp"
 #define EDGE_LBL_GUEST			".guest"	/* For IOC3 */
 #define EDGE_LBL_HOST			".host"		/* For IOC3 */
 #define EDGE_LBL_PERFMON		"mon"
 #define EDGE_LBL_USRPCI			"usrpci"
-#define EDGE_LBL_VME			"vmebus"
 #define EDGE_LBL_BLOCK			"block"
 #define EDGE_LBL_BOARD			"board"
 #define EDGE_LBL_CHAR			"char"
@@ -34,50 +31,13 @@
 #define EDGE_LBL_DIRECT			"direct"
 #define EDGE_LBL_DISABLED		"disabled"
 #define EDGE_LBL_DISK			"disk"
-#define EDGE_LBL_DMA_ENGINE             "dma_engine"    /* Only available on
-							   VMEbus now        */
-#define EDGE_LBL_NET			"net"		/* all nw. devs */
-#define EDGE_LBL_EF			"ef"		/* For if_ef ethernet */
-#define EDGE_LBL_ET			"et"		/* For if_ee ethernet */
-#define EDGE_LBL_EC			"ec"		/* For if_ec2 ether */
-#define EDGE_LBL_ECF			"ec"		/* For if_ecf enet */
-#define EDGE_LBL_EM			"ec"		/* For O2 ether */
-#define EDGE_LBL_IPG			"ipg"		/* For IPG FDDI */
-#define EDGE_LBL_XPI			"xpi"		/* For IPG FDDI */
-#define EDGE_LBL_HIP			"hip"		/* For HIPPI */
-#define EDGE_LBL_GSN                    "gsn"           /* For GSN */
-#define EDGE_LBL_ATM			"atm"		/* For ATM */
-#define EDGE_LBL_FXP			"fxp"		/* For FXP ether */
-#define EDGE_LBL_EP			"ep"		/* For eplex ether */
-#define EDGE_LBL_VFE			"vfe"		/* For VFE ether */
-#define EDGE_LBL_GFE			"gfe"		/* For GFE ether */
-#define EDGE_LBL_RNS			"rns"		/* RNS PCI FDDI card */
-#define EDGE_LBL_MTR			"mtr"		/* MTR PCI 802.5 card */
-#define EDGE_LBL_FV			"fv"		/* FV VME 802.5 card */
-#define EDGE_LBL_GTR			"gtr"		/* GTR GIO 802.5 card */
-#define EDGE_LBL_ISDN                   "isdn"		/* Digi PCI ISDN-BRI card */
-#define EDGE_LBL_EISA			"eisa"
-#define EDGE_LBL_ENET			"ethernet"
-#define EDGE_LBL_FLOPPY			"floppy"
-#define EDGE_LBL_PFD			"pfd"		/* For O2 pfd floppy */
-#define EDGE_LBL_FOP                    "fop"           /* Fetchop pseudo device */
-#define EDGE_LBL_GIO			"gio"
-#define EDGE_LBL_HEART			"heart"		/* For RACER */
-#define EDGE_LBL_HPC			"hpc"
-#define EDGE_LBL_GFX			"gfx"
 #define EDGE_LBL_HUB			"hub"		/* For SN0 */
 #define EDGE_LBL_HW			"hw"
-#define EDGE_LBL_SYNERGY		"synergy"	/* For SNIA only */
-#define EDGE_LBL_IBUS			"ibus"		/* For EVEREST */
 #define EDGE_LBL_INTERCONNECT		"link"
 #define EDGE_LBL_IO			"io"
-#define EDGE_LBL_IO4			"io4"		/* For EVEREST */
-#define EDGE_LBL_IOC3			"ioc3"
 #define EDGE_LBL_LUN                    "lun"
 #define EDGE_LBL_LINUX                  "linux"
 #define EDGE_LBL_LINUX_BUS              EDGE_LBL_LINUX "/bus/pci-x"
-#define EDGE_LBL_MACE                   "mace" 		/* O2 mace */
 #define EDGE_LBL_MACHDEP                "machdep"       /* Platform depedent devices */
 #define EDGE_LBL_MASTER			".master"
 #define EDGE_LBL_MEMORY			"memory"
@@ -102,11 +62,8 @@
 #define EDGE_LBL_SCSI			"scsi"
 #define EDGE_LBL_SCSI_CTLR		"scsi_ctlr"
 #define EDGE_LBL_SLOT			"slot"
-#define EDGE_LBL_TAPE			"tape"
 #define EDGE_LBL_TARGET                 "target"
 #define EDGE_LBL_UNKNOWN		"unknown"
-#define EDGE_LBL_VOLUME			"volume"
-#define EDGE_LBL_VOLUME_HEADER		"volume_header"
 #define EDGE_LBL_XBOW			"xbow"
 #define	EDGE_LBL_XIO			"xio"
 #define EDGE_LBL_XSWITCH		".xswitch"
@@ -114,23 +71,15 @@
 #define EDGE_LBL_XWIDGET		"xwidget"
 #define EDGE_LBL_ELSC			"elsc"
 #define EDGE_LBL_L1			"L1"
-#define EDGE_LBL_MADGE_TR               "Madge-tokenring"
 #define EDGE_LBL_XPLINK			"xplink" 	/* Cross partition */
 #define	EDGE_LBL_XPLINK_NET		"net" 		/* XP network devs */
 #define	EDGE_LBL_XPLINK_RAW		"raw"		/* XP Raw devs */
 #define EDGE_LBL_SLAB			"slab"		/* Slab of a module */
 #define	EDGE_LBL_XPLINK_KERNEL		"kernel"	/* XP kernel devs */
 #define	EDGE_LBL_XPLINK_ADMIN		"admin"	   	/* Partition admin */
-#define	EDGE_LBL_KAIO			"kaio"	   	/* Kernel async i/o poll */
-#define EDGE_LBL_RPS                    "rps"           /* redundant power supply */ 
-#define EDGE_LBL_XBOX_RPS               "xbox_rps"      /* redundant power supply for xbox unit */ 
 #define EDGE_LBL_IOBRICK		"iobrick"
-#define EDGE_LBL_PBRICK			"Pbrick"
-#define EDGE_LBL_PEBRICK		"PEbrick"
 #define EDGE_LBL_PXBRICK		"PXbrick"
 #define EDGE_LBL_IXBRICK		"IXbrick"
-#define EDGE_LBL_IBRICK			"Ibrick"
-#define EDGE_LBL_XBRICK			"Xbrick"
 #define EDGE_LBL_CGBRICK		"CGbrick"
 #define EDGE_LBL_CPUBUS			"cpubus"	/* CPU Interfaces (SysAd) */
@@ -147,19 +96,11 @@
 #define INFO_LBL_DRIVER			"_driver"	/* points to attached device_driver_t */
 #define INFO_LBL_ELSC			"_elsc"
 #define	INFO_LBL_SUBCH			"_subch"	/* system controller subchannel */
-#define INFO_LBL_L1SCP			"_l1scp"	/* points to l1sc_t */
-#define INFO_LBL_FC_PORTNAME		"_fc_portname"
-#define INFO_LBL_GIOIO			"_gioio"
-#define INFO_LBL_GFUNCS			"_gioio_ops"	/* ops vector for gio providers */
 #define INFO_LBL_HUB_INFO		"_hubinfo"
 #define INFO_LBL_HWGFSLIST		"_hwgfs_list"
 #define INFO_LBL_TRAVERSE		"_hwg_traverse" /* hwgraph traverse function */
-#define INFO_LBL_INVENT 		"_invent"	/* inventory data */
-#define INFO_LBL_MLRESET		"_mlreset"	/* present if device preinitialized */
 #define INFO_LBL_MODULE_INFO		"_module"	/* module data ptr */
-#define INFO_LBL_MONDATA		"_mon"		/* monitor data ptr */
 #define INFO_LBL_MDPERF_DATA		"_mdperf"	/* mdperf monitoring*/
-#define INFO_LBL_NIC			"_nic"
 #define INFO_LBL_NODE_INFO		"_node"
 #define	INFO_LBL_PCIBR_HINTS		"_pcibr_hints"
 #define INFO_LBL_PCIIO			"_pciio"
@@ -167,15 +108,11 @@
 #define INFO_LBL_PERMISSIONS		"_permissions"	/* owner, uid, gid */
 #define INFO_LBL_ROUTER_INFO		"_router"
 #define INFO_LBL_SUBDEVS		"_subdevs"	/* subdevice enable bits */
-#define INFO_LBL_VME_FUNCS		"_vmeio_ops"	/* ops vector for VME providers */
 #define INFO_LBL_XSWITCH		"_xswitch"
 #define INFO_LBL_XSWITCH_ID		"_xswitch_id"
 #define INFO_LBL_XSWITCH_VOL		"_xswitch_volunteer"
 #define INFO_LBL_XFUNCS			"_xtalk_ops"	/* ops vector for gio providers */
 #define INFO_LBL_XWIDGET		"_xwidget"
-#define INFO_LBL_GRIO_DSK		"_grio_disk"	/* guaranteed rate I/O */
-#define INFO_LBL_ASYNC_ATTACH           "_async_attach"	/* parallel attachment */
-#define INFO_LBL_GFXID			"_gfxid"	/* gfx pipe ID #s */
 /* Device/Driver  Admin directive labels  */
 #define ADMIN_LBL_INTR_TARGET		"INTR_TARGET"	/* Target cpu for device interrupts*/
 #define ADMIN_LBL_INTR_SWLEVEL		"INTR_SWLEVEL"	/* Priority level of the ithread */

--- a/include/asm-ia64/sn/klconfig.h
+++ b/include/asm-ia64/sn/klconfig.h
@@ -72,10 +72,8 @@ typedef s32 klconf_off_t;
 #define DUPLICATE_BOARD 	0x04    /* Boards like midplanes/routers which
                                   	   are discovered twice. Use one of them */
 #define VISITED_BOARD		0x08	/* Used for compact hub numbering. */
-#define LOCAL_MASTER_IO6	0x10 	/* master io6 for that node */
+#define LOCAL_MASTER_IO6	0x10    /* master io6 for that node */
-#define GLOBAL_MASTER_IO6	0x20
+#define KLTYPE_IOBRICK_XBOW	(KLCLASS_MIDPLANE | 0x2)
-#define GLOBAL_MASTER_EXT 	0x40  	/* extend master io6 to other bus on ibrick */
-#define SECOND_NIC_PRESENT 	0x80 	/* addons like MIO are present */
 /* klinfo->flags fields */
@@ -347,47 +345,18 @@ typedef struct kl_config_hdr {
 #define KLTYPE_WEIRDIO	(KLCLASS_IOBRICK  | 0x0)
 #define KLTYPE_BASEIO	(KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
-#define KLTYPE_IO6	KLTYPE_BASEIO       /* Additional name */
-#define KLTYPE_4CHSCSI	(KLCLASS_IO  | 0x2)
-#define KLTYPE_MSCSI	KLTYPE_4CHSCSI      /* Additional name */
 #define KLTYPE_ETHERNET	(KLCLASS_IO  | 0x3)
-#define KLTYPE_MENET	KLTYPE_ETHERNET     /* Additional name */
 #define KLTYPE_FDDI  	(KLCLASS_IO  | 0x4)
-#define KLTYPE_UNUSED	(KLCLASS_IO  | 0x5) /* XXX UNUSED */
-#define KLTYPE_HAROLD   (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */
-#define KLTYPE_PCI	KLTYPE_HAROLD
-#define KLTYPE_VME      (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
-#define KLTYPE_MIO   	(KLCLASS_IO  | 0x8)
 #define KLTYPE_FC    	(KLCLASS_IO  | 0x9)
-#define KLTYPE_LINC    	(KLCLASS_IO  | 0xA)
-#define KLTYPE_TPU    	(KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
 #define KLTYPE_GSN_A   	(KLCLASS_IO  | 0xC) /* Main GSN board */
 #define KLTYPE_GSN_B   	(KLCLASS_IO  | 0xD) /* Auxiliary GSN board */
-#define KLTYPE_SHOEHORN (KLCLASS_IO  | 0xE)
-#define KLTYPE_SERIAL_HIPPI (KLCLASS_IO  | 0xF)
-#define KLTYPE_GFX	(KLCLASS_GFX | 0x0) /* unknown graphics type */
-#define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
-#define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
-#define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
 #define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
-#define KLTYPE_ROUTER2    KLTYPE_ROUTER		/* Obsolete! */
-#define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
 #define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
 #define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4)
-#define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
-#define KLTYPE_MIDPLANE8  (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
-#define KLTYPE_MIDPLANE    KLTYPE_MIDPLANE8
-#define KLTYPE_IOBRICK_XBOW	(KLCLASS_MIDPLANE | 0x2)
 #define KLTYPE_IOBRICK		(KLCLASS_IOBRICK | 0x0)
-#define KLTYPE_IBRICK		(KLCLASS_IOBRICK | 0x1)
-#define KLTYPE_PBRICK		(KLCLASS_IOBRICK | 0x2)
-#define KLTYPE_XBRICK		(KLCLASS_IOBRICK | 0x3)
 #define KLTYPE_NBRICK		(KLCLASS_IOBRICK | 0x4)
-#define KLTYPE_PEBRICK		(KLCLASS_IOBRICK | 0x5)
 #define KLTYPE_PXBRICK		(KLCLASS_IOBRICK | 0x6)
 #define KLTYPE_IXBRICK		(KLCLASS_IOBRICK | 0x7)
 #define KLTYPE_CGBRICK		(KLCLASS_IOBRICK | 0x8)
@@ -406,9 +375,6 @@ typedef struct kl_config_hdr {
 #define KLTYPE_UNKNOWN	(KLCLASS_UNKNOWN | 0xf)
 #define KLTYPE(_x) 	((_x) & KLTYPE_MASK)
-#define IS_MIO_PRESENT(l)	((l->brd_type == KLTYPE_BASEIO) && \
-				 (l->brd_flags & SECOND_NIC_PRESENT))
-#define IS_MIO_IOC3(l,n)	(IS_MIO_PRESENT(l) && (n > 2))
 /* 
 * board structures

--- a/include/asm-ia64/sn/ksys/l1.h
+++ b/include/asm-ia64/sn/ksys/l1.h
@@ -89,13 +89,8 @@
 /* brick type response codes */
 #define L1_BRICKTYPE_IP45       0x34            /* 4 */
 #define L1_BRICKTYPE_C          0x43            /* C */
-#define L1_BRICKTYPE_I          0x49            /* I */
-#define L1_BRICKTYPE_P          0x50            /* P */
 #define L1_BRICKTYPE_R          0x52            /* R */
-#define L1_BRICKTYPE_X          0x58            /* X */
-#define L1_BRICKTYPE_X2         0x59            /* Y */
 #define L1_BRICKTYPE_N          0x4e            /* N */
-#define L1_BRICKTYPE_PE		0x25		/* % */
 #define L1_BRICKTYPE_PX		0x23		/* # */
 #define L1_BRICKTYPE_IX		0x3d		/* = */

--- a/include/asm-ia64/sn/pci/pci_bus_cvlink.h
+++ b/include/asm-ia64/sn/pci/pci_bus_cvlink.h
@@ -38,8 +38,6 @@
 #define IS_PCI32G(dev)	((dev)->dma_mask >= 0xffffffff)
 #define IS_PCI32L(dev)	((dev)->dma_mask < 0xffffffff)
-#define IS_PIC_DEVICE(dev) ((struct sn_device_sysdata *)dev->sysdata)->isPIC
 #define PCIDEV_VERTEX(pci_dev) \
 	(((struct sn_device_sysdata *)((pci_dev)->sysdata))->vhdl)
@@ -53,7 +51,6 @@ struct sn_widget_sysdata {
 struct sn_device_sysdata {
        vertex_hdl_t  vhdl;
 	int		isa64;
-	int		isPIC;
 	volatile unsigned int *dma_buf_sync;
 	volatile unsigned int *xbow_buf_sync;
 };

--- a/include/asm-ia64/sn/pci/pcibr_private.h
+++ b/include/asm-ia64/sn/pci/pcibr_private.h
@@ -199,14 +199,10 @@ struct pcibr_intr_s {
 #define PCIBR_INFO_SLOT_GET_INT(info)	    (((pcibr_info_t)info)->f_dev)
 #define PCIBR_DEVICE_TO_SLOT(pcibr_soft, dev_num) \
-	(((dev_num) != PCIIO_SLOT_NONE) ? \
+	(((dev_num) != PCIIO_SLOT_NONE) ? ((dev_num) + 1) : PCIIO_SLOT_NONE)
-	    (IS_PIC_SOFT((pcibr_soft)) ? ((dev_num) + 1) : (dev_num)) : \
-	    PCIIO_SLOT_NONE)
 #define PCIBR_SLOT_TO_DEVICE(pcibr_soft, slot) \
-        (((slot) != PCIIO_SLOT_NONE) ? \
+        (((slot) != PCIIO_SLOT_NONE) ? ((slot) - 1) : PCIIO_SLOT_NONE)
-            (IS_PIC_SOFT((pcibr_soft)) ? ((slot) - 1) : (slot)) : \
-            PCIIO_SLOT_NONE)
 /*
 * per-connect point pcibr data, including standard pciio data in-line:
@@ -287,12 +283,7 @@ struct pcibr_intr_wrap_s {
 #define PCIBR_BRIDGETYPE_BRIDGE		0
 #define PCIBR_BRIDGETYPE_XBRIDGE	1
 #define PCIBR_BRIDGETYPE_PIC		2
-#define IS_XBRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_XBRIDGE)
+#define IS_PIC_BUSNUM_SOFT(ps, bus)	((ps)->bs_busnum == (bus))
-#define IS_PIC_SOFT(ps)     (ps->bs_bridge_type == PCIBR_BRIDGETYPE_PIC)
-#define IS_PIC_BUSNUM_SOFT(ps, bus)	\
-		(IS_PIC_SOFT(ps) && ((ps)->bs_busnum == (bus)))
-#define IS_BRIDGE_SOFT(ps)  (ps->bs_bridge_type == PCIBR_BRIDGETYPE_BRIDGE)
-#define IS_XBRIDGE_OR_PIC_SOFT(ps) (IS_XBRIDGE_SOFT(ps) || IS_PIC_SOFT(ps))
 /*
 * Runtime checks for workarounds.