Commit 84ed7412 authored by Marc Zyngier's avatar Marc Zyngier Committed by Christoffer Dall

arm64: KVM: Fix outdated comment about VTCR_EL2.PS

Commit 87366d8c ("arm64: Add boot time configuration of
Intermediate Physical Address size") removed the hardcoded setting
of VTCR_EL2.PS to use ID_AA64MMFR0_EL1.PARange instead, but didn't
remove the (now rather misleading) comment.

Fix the comments to match reality (at least for the next few minutes).
Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
parent 04b8dc85
...@@ -129,6 +129,9 @@ ...@@ -129,6 +129,9 @@
* 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
* not known to exist and will break with this configuration. * not known to exist and will break with this configuration.
* *
* VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time
* (see hyp-init.S).
*
* Note that when using 4K pages, we concatenate two first level page tables * Note that when using 4K pages, we concatenate two first level page tables
* together. * together.
* *
...@@ -138,7 +141,6 @@ ...@@ -138,7 +141,6 @@
#ifdef CONFIG_ARM64_64K_PAGES #ifdef CONFIG_ARM64_64K_PAGES
/* /*
* Stage2 translation configuration: * Stage2 translation configuration:
* 40bits output (PS = 2)
* 40bits input (T0SZ = 24) * 40bits input (T0SZ = 24)
* 64kB pages (TG0 = 1) * 64kB pages (TG0 = 1)
* 2 level page tables (SL = 1) * 2 level page tables (SL = 1)
...@@ -150,7 +152,6 @@ ...@@ -150,7 +152,6 @@
#else #else
/* /*
* Stage2 translation configuration: * Stage2 translation configuration:
* 40bits output (PS = 2)
* 40bits input (T0SZ = 24) * 40bits input (T0SZ = 24)
* 4kB pages (TG0 = 0) * 4kB pages (TG0 = 0)
* 3 level page tables (SL = 1) * 3 level page tables (SL = 1)
......
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