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Commit 89d22544 authored by Russell King's avatar Russell King
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[ARM] Add prefix to driver constants to prevent namespace clashes.

parent 5d016022
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Showing with 130 additions and 130 deletions
drivers/scsi/arm/acornscsi.c
View file @ 89d22544
......@@ -216,7 +216,7 @@ sbic_arm_write(unsigned int io_port, int reg, int value)
static inline
int sbic_arm_read(unsigned int io_port, int reg)
{
if(reg == ASR)
if(reg == SBIC_ASR)
return __raw_readl(io_port) & 255;
__raw_writeb(reg, io_port);
return __raw_readl(io_port + 4) & 255;
......@@ -238,9 +238,9 @@ int sbic_arm_read(unsigned int io_port, int reg)
static inline
unsigned int dmac_address(unsigned int io_port)
{
return dmac_read(io_port, TXADRHI) << 16 |
dmac_read(io_port, TXADRMD) << 8 |
dmac_read(io_port, TXADRLO);
return dmac_read(io_port, DMAC_TXADRHI) << 16 |
dmac_read(io_port, DMAC_TXADRMD) << 8 |
dmac_read(io_port, DMAC_TXADRLO);
}
static
......@@ -248,15 +248,15 @@ void acornscsi_dumpdma(AS_Host *host, char *where)
{
unsigned int mode, addr, len;
mode = dmac_read(host->dma.io_port, MODECON);
mode = dmac_read(host->dma.io_port, DMAC_MODECON);
addr = dmac_address(host->dma.io_port);
len = dmac_read(host->dma.io_port, TXCNTHI) << 8 |
dmac_read(host->dma.io_port, TXCNTLO);
len = dmac_read(host->dma.io_port, DMAC_TXCNTHI) << 8 |
dmac_read(host->dma.io_port, DMAC_TXCNTLO);
printk("scsi%d: %s: DMAC %02x @%06x+%04x msk %02x, ",
host->host->host_no, where,
mode, addr, (len + 1) & 0xffff,
dmac_read(host->dma.io_port, MASKREG));
dmac_read(host->dma.io_port, DMAC_MASKREG));
printk("DMA @%06x, ", host->dma.start_addr);
printk("BH @%p +%04x, ", host->scsi.SCp.ptr,
......@@ -272,7 +272,7 @@ unsigned long acornscsi_sbic_xfcount(AS_Host *host)
{
unsigned long length;
length = sbic_arm_read(host->scsi.io_port, TRANSCNTH) << 16;
length = sbic_arm_read(host->scsi.io_port, SBIC_TRANSCNTH) << 16;
length |= sbic_arm_readnext(host->scsi.io_port) << 8;
length |= sbic_arm_readnext(host->scsi.io_port);
......@@ -285,7 +285,7 @@ acornscsi_sbic_wait(AS_Host *host, int stat_mask, int stat, int timeout, char *m
int asr;
do {
asr = sbic_arm_read(host->scsi.io_port, ASR);
asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
if ((asr & stat_mask) == stat)
return 0;
......@@ -304,7 +304,7 @@ int acornscsi_sbic_issuecmd(AS_Host *host, int command)
if (acornscsi_sbic_wait(host, ASR_CIP, 0, 1000, "issuing command"))
return -1;
sbic_arm_write(host->scsi.io_port, CMND, command);
sbic_arm_write(host->scsi.io_port, SBIC_CMND, command);
return 0;
}
......@@ -353,12 +353,12 @@ void acornscsi_resetcard(AS_Host *host)
printk("scsi%d: timeout while resetting card\n",
host->host->host_no);
sbic_arm_read(host->scsi.io_port, ASR);
sbic_arm_read(host->scsi.io_port, SSR);
sbic_arm_read(host->scsi.io_port, SBIC_ASR);
sbic_arm_read(host->scsi.io_port, SBIC_SSR);
/* setup sbic - WD33C93A */
sbic_arm_write(host->scsi.io_port, OWNID, OWNID_EAF | host->host->this_id);
sbic_arm_write(host->scsi.io_port, CMND, CMND_RESET);
sbic_arm_write(host->scsi.io_port, SBIC_OWNID, OWNID_EAF | host->host->this_id);
sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_RESET);
/*
* Command should cause a reset interrupt
......@@ -374,26 +374,26 @@ void acornscsi_resetcard(AS_Host *host)
printk("scsi%d: timeout while resetting card\n",
host->host->host_no);
sbic_arm_read(host->scsi.io_port, ASR);
if (sbic_arm_read(host->scsi.io_port, SSR) != 0x01)
sbic_arm_read(host->scsi.io_port, SBIC_ASR);
if (sbic_arm_read(host->scsi.io_port, SBIC_SSR) != 0x01)
printk(KERN_CRIT "scsi%d: WD33C93A didn't give enhanced reset interrupt\n",
host->host->host_no);
sbic_arm_write(host->scsi.io_port, CTRL, INIT_SBICDMA | CTRL_IDI);
sbic_arm_write(host->scsi.io_port, TIMEOUT, TIMEOUT_TIME);
sbic_arm_write(host->scsi.io_port, SYNCHTRANSFER, SYNCHTRANSFER_2DBA);
sbic_arm_write(host->scsi.io_port, SOURCEID, SOURCEID_ER | SOURCEID_DSP);
sbic_arm_write(host->scsi.io_port, SBIC_CTRL, INIT_SBICDMA | CTRL_IDI);
sbic_arm_write(host->scsi.io_port, SBIC_TIMEOUT, TIMEOUT_TIME);
sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, SYNCHTRANSFER_2DBA);
sbic_arm_write(host->scsi.io_port, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP);
host->card.page_reg = 0x40;
outb(host->card.page_reg, host->card.io_page);
/* setup dmac - uPC71071 */
dmac_write(host->dma.io_port, INIT, 0);
dmac_write(host->dma.io_port, DMAC_INIT, 0);
#ifdef USE_DMAC
dmac_write(host->dma.io_port, INIT, INIT_8BIT);
dmac_write(host->dma.io_port, CHANNEL, CHANNEL_0);
dmac_write(host->dma.io_port, DEVCON0, INIT_DEVCON0);
dmac_write(host->dma.io_port, DEVCON1, INIT_DEVCON1);
dmac_write(host->dma.io_port, DMAC_INIT, INIT_8BIT);
dmac_write(host->dma.io_port, DMAC_CHANNEL, CHANNEL_0);
dmac_write(host->dma.io_port, DMAC_DEVCON0, INIT_DEVCON0);
dmac_write(host->dma.io_port, DMAC_DEVCON1, INIT_DEVCON1);
#endif
host->SCpnt = NULL;
......@@ -741,9 +741,9 @@ intr_ret_t acornscsi_kick(AS_Host *host)
* If we have an interrupt pending, then we may have been reselected.
* In this case, we don't want to write to the registers
*/
if (!(sbic_arm_read(host->scsi.io_port, ASR) & (ASR_INT|ASR_BSY|ASR_CIP))) {
sbic_arm_write(host->scsi.io_port, DESTID, SCpnt->device->id);
sbic_arm_write(host->scsi.io_port, CMND, CMND_SELWITHATN);
if (!(sbic_arm_read(host->scsi.io_port, SBIC_ASR) & (ASR_INT|ASR_BSY|ASR_CIP))) {
sbic_arm_write(host->scsi.io_port, SBIC_DESTID, SCpnt->device->id);
sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_SELWITHATN);
}
/*
......@@ -807,7 +807,7 @@ void acornscsi_done(AS_Host *host, Scsi_Cmnd **SCpntp, unsigned int result)
Scsi_Cmnd *SCpnt = *SCpntp;
/* clean up */
sbic_arm_write(host->scsi.io_port, SOURCEID, SOURCEID_ER | SOURCEID_DSP);
sbic_arm_write(host->scsi.io_port, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP);
host->stats.fins += 1;
......@@ -1008,7 +1008,7 @@ void acornscsi_data_write(AS_Host *host, char *ptr,
static inline
void acornscsi_dma_stop(AS_Host *host)
{
dmac_write(host->dma.io_port, MASKREG, MASK_ON);
dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON);
dmac_clearintr(host->dma.io_intr_clear);
#if (DEBUG & DEBUG_DMA)
......@@ -1031,7 +1031,7 @@ void acornscsi_dma_setup(AS_Host *host, dmadir_t direction)
host->dma.direction = direction;
dmac_write(host->dma.io_port, MASKREG, MASK_ON);
dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON);
if (direction == DMA_OUT) {
#if (DEBUG & DEBUG_NO_WRITE)
......@@ -1062,13 +1062,13 @@ void acornscsi_dma_setup(AS_Host *host, dmadir_t direction)
length);
length -= 1;
dmac_write(host->dma.io_port, TXCNTLO, length);
dmac_write(host->dma.io_port, TXCNTHI, length >> 8);
dmac_write(host->dma.io_port, TXADRLO, address);
dmac_write(host->dma.io_port, TXADRMD, address >> 8);
dmac_write(host->dma.io_port, TXADRHI, 0);
dmac_write(host->dma.io_port, MODECON, mode);
dmac_write(host->dma.io_port, MASKREG, MASK_OFF);
dmac_write(host->dma.io_port, DMAC_TXCNTLO, length);
dmac_write(host->dma.io_port, DMAC_TXCNTHI, length >> 8);
dmac_write(host->dma.io_port, DMAC_TXADRLO, address);
dmac_write(host->dma.io_port, DMAC_TXADRMD, address >> 8);
dmac_write(host->dma.io_port, DMAC_TXADRHI, 0);
dmac_write(host->dma.io_port, DMAC_MODECON, mode);
dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_OFF);
#if (DEBUG & DEBUG_DMA)
DBG(host->SCpnt, acornscsi_dumpdma(host, "strt"));
......@@ -1088,7 +1088,7 @@ void acornscsi_dma_setup(AS_Host *host, dmadir_t direction)
static
void acornscsi_dma_cleanup(AS_Host *host)
{
dmac_write(host->dma.io_port, MASKREG, MASK_ON);
dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON);
dmac_clearintr(host->dma.io_intr_clear);
/*
......@@ -1152,7 +1152,7 @@ void acornscsi_dma_intr(AS_Host *host)
DBG(host->SCpnt, acornscsi_dumpdma(host, "inti"));
#endif
dmac_write(host->dma.io_port, MASKREG, MASK_ON);
dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON);
dmac_clearintr(host->dma.io_intr_clear);
/*
......@@ -1190,12 +1190,12 @@ void acornscsi_dma_intr(AS_Host *host)
length);
length -= 1;
dmac_write(host->dma.io_port, TXCNTLO, length);
dmac_write(host->dma.io_port, TXCNTHI, length >> 8);
dmac_write(host->dma.io_port, TXADRLO, address);
dmac_write(host->dma.io_port, TXADRMD, address >> 8);
dmac_write(host->dma.io_port, TXADRHI, 0);
dmac_write(host->dma.io_port, MASKREG, MASK_OFF);
dmac_write(host->dma.io_port, DMAC_TXCNTLO, length);
dmac_write(host->dma.io_port, DMAC_TXCNTHI, length >> 8);
dmac_write(host->dma.io_port, DMAC_TXADRLO, address);
dmac_write(host->dma.io_port, DMAC_TXADRMD, address >> 8);
dmac_write(host->dma.io_port, DMAC_TXADRHI, 0);
dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_OFF);
#if (DEBUG & DEBUG_DMA)
DBG(host->SCpnt, acornscsi_dumpdma(host, "into"));
......@@ -1209,15 +1209,15 @@ void acornscsi_dma_intr(AS_Host *host)
* attention condition. We continue giving one byte until
* the device recognises the attention.
*/
if (dmac_read(host->dma.io_port, STATUS) & STATUS_RQ0) {
if (dmac_read(host->dma.io_port, DMAC_STATUS) & STATUS_RQ0) {
acornscsi_abortcmd(host, host->SCpnt->tag);
dmac_write(host->dma.io_port, TXCNTLO, 0);
dmac_write(host->dma.io_port, TXCNTHI, 0);
dmac_write(host->dma.io_port, TXADRLO, 0);
dmac_write(host->dma.io_port, TXADRMD, 0);
dmac_write(host->dma.io_port, TXADRHI, 0);
dmac_write(host->dma.io_port, MASKREG, MASK_OFF);
dmac_write(host->dma.io_port, DMAC_TXCNTLO, 0);
dmac_write(host->dma.io_port, DMAC_TXCNTHI, 0);
dmac_write(host->dma.io_port, DMAC_TXADRLO, 0);
dmac_write(host->dma.io_port, DMAC_TXADRMD, 0);
dmac_write(host->dma.io_port, DMAC_TXADRHI, 0);
dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_OFF);
}
#endif
}
......@@ -1271,9 +1271,9 @@ void acornscsi_dma_adjust(AS_Host *host)
host->dma.xfer_setup = 0;
else {
transferred += host->dma.start_addr;
dmac_write(host->dma.io_port, TXADRLO, transferred);
dmac_write(host->dma.io_port, TXADRMD, transferred >> 8);
dmac_write(host->dma.io_port, TXADRHI, transferred >> 16);
dmac_write(host->dma.io_port, DMAC_TXADRLO, transferred);
dmac_write(host->dma.io_port, DMAC_TXADRMD, transferred >> 8);
dmac_write(host->dma.io_port, DMAC_TXADRHI, transferred >> 16);
#if (DEBUG & (DEBUG_DMA|DEBUG_WRITE))
DBG(host->SCpnt, acornscsi_dumpdma(host, "adjo"));
#endif
......@@ -1292,12 +1292,12 @@ acornscsi_write_pio(AS_Host *host, char *bytes, int *ptr, int len, unsigned int
int my_ptr = *ptr;
while (my_ptr < len) {
asr = sbic_arm_read(host->scsi.io_port, ASR);
asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
if (asr & ASR_DBR) {
timeout = max_timeout;
sbic_arm_write(host->scsi.io_port, DATA, bytes[my_ptr++]);
sbic_arm_write(host->scsi.io_port, SBIC_DATA, bytes[my_ptr++]);
} else if (asr & ASR_INT)
break;
else if (--timeout == 0)
......@@ -1320,7 +1320,7 @@ acornscsi_sendcommand(AS_Host *host)
{
Scsi_Cmnd *SCpnt = host->SCpnt;
sbic_arm_write(host->scsi.io_port, TRANSCNTH, 0);
sbic_arm_write(host->scsi.io_port, SBIC_TRANSCNTH, 0);
sbic_arm_writenext(host->scsi.io_port, 0);
sbic_arm_writenext(host->scsi.io_port, SCpnt->cmd_len - host->scsi.SCp.sent_command);
......@@ -1351,7 +1351,7 @@ void acornscsi_sendmessage(AS_Host *host)
acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "sending message 1");
sbic_arm_write(host->scsi.io_port, DATA, NOP);
sbic_arm_write(host->scsi.io_port, SBIC_DATA, NOP);
host->scsi.last_message = NOP;
#if (DEBUG & DEBUG_MESSAGES)
......@@ -1365,7 +1365,7 @@ void acornscsi_sendmessage(AS_Host *host)
acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "sending message 2");
sbic_arm_write(host->scsi.io_port, DATA, msg->msg[0]);
sbic_arm_write(host->scsi.io_port, SBIC_DATA, msg->msg[0]);
host->scsi.last_message = msg->msg[0];
#if (DEBUG & DEBUG_MESSAGES)
......@@ -1382,7 +1382,7 @@ void acornscsi_sendmessage(AS_Host *host)
* initiator. This provides an interlock so that the
* initiator can determine which message byte is rejected.
*/
sbic_arm_write(host->scsi.io_port, TRANSCNTH, 0);
sbic_arm_write(host->scsi.io_port, SBIC_TRANSCNTH, 0);
sbic_arm_writenext(host->scsi.io_port, 0);
sbic_arm_writenext(host->scsi.io_port, message_length);
acornscsi_sbic_issuecmd(host, CMND_XFERINFO);
......@@ -1421,7 +1421,7 @@ void acornscsi_readstatusbyte(AS_Host *host)
{
acornscsi_sbic_issuecmd(host, CMND_XFERINFO|CMND_SBT);
acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "reading status byte");
host->scsi.SCp.Status = sbic_arm_read(host->scsi.io_port, DATA);
host->scsi.SCp.Status = sbic_arm_read(host->scsi.io_port, SBIC_DATA);
}
/*
......@@ -1438,12 +1438,12 @@ unsigned char acornscsi_readmessagebyte(AS_Host *host)
acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "for message byte");
message = sbic_arm_read(host->scsi.io_port, DATA);
message = sbic_arm_read(host->scsi.io_port, SBIC_DATA);
/* wait for MSGIN-XFER-PAUSED */
acornscsi_sbic_wait(host, ASR_INT, ASR_INT, 1000, "for interrupt after message byte");
sbic_arm_read(host->scsi.io_port, SSR);
sbic_arm_read(host->scsi.io_port, SBIC_SSR);
return message;
}
......@@ -1480,7 +1480,7 @@ void acornscsi_message(AS_Host *host)
/* wait for next msg-in */
acornscsi_sbic_wait(host, ASR_INT, ASR_INT, 1000, "for interrupt after negate ack");
sbic_arm_read(host->scsi.io_port, SSR);
sbic_arm_read(host->scsi.io_port, SBIC_SSR);
}
} while (msgidx < msglen);
......@@ -1602,7 +1602,7 @@ void acornscsi_message(AS_Host *host)
host->host->host_no, acornscsi_target(host));
host->device[host->SCpnt->device->id].sync_xfer = SYNCHTRANSFER_2DBA;
host->device[host->SCpnt->device->id].sync_state = SYNC_ASYNCHRONOUS;
sbic_arm_write(host->scsi.io_port, SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
break;
default:
......@@ -1652,7 +1652,7 @@ void acornscsi_message(AS_Host *host)
host->device[host->SCpnt->device->id].sync_xfer =
calc_sync_xfer(period * 4, length);
}
sbic_arm_write(host->scsi.io_port, SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
break;
#else
/* We do not accept synchronous transfers. Respond with a
......@@ -1792,7 +1792,7 @@ int acornscsi_starttransfer(AS_Host *host)
residual = host->SCpnt->request_bufflen - host->scsi.SCp.scsi_xferred;
sbic_arm_write(host->scsi.io_port, SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
sbic_arm_writenext(host->scsi.io_port, residual >> 16);
sbic_arm_writenext(host->scsi.io_port, residual >> 8);
sbic_arm_writenext(host->scsi.io_port, residual);
......@@ -1816,7 +1816,7 @@ int acornscsi_reconnect(AS_Host *host)
{
unsigned int target, lun, ok = 0;
target = sbic_arm_read(host->scsi.io_port, SOURCEID);
target = sbic_arm_read(host->scsi.io_port, SBIC_SOURCEID);
if (!(target & 8))
printk(KERN_ERR "scsi%d: invalid source id after reselection "
......@@ -1832,7 +1832,7 @@ int acornscsi_reconnect(AS_Host *host)
host->SCpnt = NULL;
}
lun = sbic_arm_read(host->scsi.io_port, DATA) & 7;
lun = sbic_arm_read(host->scsi.io_port, SBIC_DATA) & 7;
host->scsi.reconnected.target = target;
host->scsi.reconnected.lun = lun;
......@@ -1952,7 +1952,7 @@ static
void acornscsi_abortcmd(AS_Host *host, unsigned char tag)
{
host->scsi.phase = PHASE_ABORTED;
sbic_arm_write(host->scsi.io_port, CMND, CMND_ASSERTATN);
sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_ASSERTATN);
msgqueue_flush(&host->scsi.msgs);
#ifdef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE
......@@ -1979,11 +1979,11 @@ intr_ret_t acornscsi_sbicintr(AS_Host *host, int in_irq)
{
unsigned int asr, ssr;
asr = sbic_arm_read(host->scsi.io_port, ASR);
asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
if (!(asr & ASR_INT))
return INTR_IDLE;
ssr = sbic_arm_read(host->scsi.io_port, SSR);
ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR);
#if (DEBUG & DEBUG_PHASES)
print_sbic_status(asr, ssr, host->scsi.phase);
......@@ -1999,15 +1999,15 @@ intr_ret_t acornscsi_sbicintr(AS_Host *host, int in_irq)
printk(KERN_ERR "scsi%d: reset in standard mode but wanted advanced mode.\n",
host->host->host_no);
/* setup sbic - WD33C93A */
sbic_arm_write(host->scsi.io_port, OWNID, OWNID_EAF | host->host->this_id);
sbic_arm_write(host->scsi.io_port, CMND, CMND_RESET);
sbic_arm_write(host->scsi.io_port, SBIC_OWNID, OWNID_EAF | host->host->this_id);
sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_RESET);
return INTR_IDLE;
case 0x01: /* reset state - advanced */
sbic_arm_write(host->scsi.io_port, CTRL, INIT_SBICDMA | CTRL_IDI);
sbic_arm_write(host->scsi.io_port, TIMEOUT, TIMEOUT_TIME);
sbic_arm_write(host->scsi.io_port, SYNCHTRANSFER, SYNCHTRANSFER_2DBA);
sbic_arm_write(host->scsi.io_port, SOURCEID, SOURCEID_ER | SOURCEID_DSP);
sbic_arm_write(host->scsi.io_port, SBIC_CTRL, INIT_SBICDMA | CTRL_IDI);
sbic_arm_write(host->scsi.io_port, SBIC_TIMEOUT, TIMEOUT_TIME);
sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, SYNCHTRANSFER_2DBA);
sbic_arm_write(host->scsi.io_port, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP);
msgqueue_flush(&host->scsi.msgs);
return INTR_IDLE;
......@@ -2025,10 +2025,10 @@ intr_ret_t acornscsi_sbicintr(AS_Host *host, int in_irq)
msgqueue_flush(&host->scsi.msgs);
host->dma.transferred = host->scsi.SCp.scsi_xferred;
/* 33C93 gives next interrupt indicating bus phase */
asr = sbic_arm_read(host->scsi.io_port, ASR);
asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
if (!(asr & ASR_INT))
break;
ssr = sbic_arm_read(host->scsi.io_port, SSR);
ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR);
ADD_STATUS(8, ssr, host->scsi.phase, 1);
ADD_STATUS(host->SCpnt->device->id, ssr, host->scsi.phase, 1);
goto connected;
......@@ -2655,7 +2655,7 @@ acornscsi_do_abort(AS_Host *host, Scsi_Cmnd *SCpnt)
* busylun bit.
*/
case PHASE_CONNECTED:
sbic_arm_write(host->scsi.io_port, CMND, CMND_DISCONNECT);
sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_DISCONNECT);
host->SCpnt = NULL;
res = res_success_clear;
break;
......@@ -2699,8 +2699,8 @@ int acornscsi_abort(Scsi_Cmnd *SCpnt)
#if (DEBUG & DEBUG_ABORT)
{
int asr, ssr;
asr = sbic_arm_read(host->scsi.io_port, ASR);
ssr = sbic_arm_read(host->scsi.io_port, SSR);
asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR);
printk(KERN_WARNING "acornscsi_abort: ");
print_sbic_status(asr, ssr, host->scsi.phase);
......@@ -2787,8 +2787,8 @@ int acornscsi_reset(Scsi_Cmnd *SCpnt, unsigned int reset_flags)
{
int asr, ssr;
asr = sbic_arm_read(host->scsi.io_port, ASR);
ssr = sbic_arm_read(host->scsi.io_port, SSR);
asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR);
printk(KERN_WARNING "acornscsi_reset: ");
print_sbic_status(asr, ssr, host->scsi.phase);
......
drivers/scsi/arm/acornscsi.h
View file @ 89d22544
......@@ -13,13 +13,13 @@
#define ACORNSCSI_H
/* SBIC registers */
#define OWNID 0
#define SBIC_OWNID 0
#define OWNID_FS1 (1<<7)
#define OWNID_FS2 (1<<6)
#define OWNID_EHP (1<<4)
#define OWNID_EAF (1<<3)
#define CTRL 1
#define SBIC_CTRL 1
#define CTRL_DMAMODE (1<<7)
#define CTRL_DMADBAMODE (1<<6)
#define CTRL_DMABURST (1<<5)
......@@ -30,25 +30,25 @@
#define CTRL_HA (1<<1)
#define CTRL_HSP (1<<0)
#define TIMEOUT 2
#define TOTSECTS 3
#define TOTHEADS 4
#define TOTCYLH 5
#define TOTCYLL 6
#define LOGADDRH 7
#define LOGADDRM2 8
#define LOGADDRM1 9
#define LOGADDRL 10
#define SECTORNUM 11
#define HEADNUM 12
#define CYLH 13
#define CYLL 14
#define TARGETLUN 15
#define SBIC_TIMEOUT 2
#define SBIC_TOTSECTS 3
#define SBIC_TOTHEADS 4
#define SBIC_TOTCYLH 5
#define SBIC_TOTCYLL 6
#define SBIC_LOGADDRH 7
#define SBIC_LOGADDRM2 8
#define SBIC_LOGADDRM1 9
#define SBIC_LOGADDRL 10
#define SBIC_SECTORNUM 11
#define SBIC_HEADNUM 12
#define SBIC_CYLH 13
#define SBIC_CYLL 14
#define SBIC_TARGETLUN 15
#define TARGETLUN_TLV (1<<7)
#define TARGETLUN_DOK (1<<6)
#define CMNDPHASE 16
#define SYNCHTRANSFER 17
#define SBIC_CMNDPHASE 16
#define SBIC_SYNCHTRANSFER 17
#define SYNCHTRANSFER_OF0 0x00
#define SYNCHTRANSFER_OF1 0x01
#define SYNCHTRANSFER_OF2 0x02
......@@ -70,21 +70,21 @@
#define SYNCHTRANSFER_6DBA 0x60
#define SYNCHTRANSFER_7DBA 0x70
#define TRANSCNTH 18
#define TRANSCNTM 19
#define TRANSCNTL 20
#define DESTID 21
#define SBIC_TRANSCNTH 18
#define SBIC_TRANSCNTM 19
#define SBIC_TRANSCNTL 20
#define SBIC_DESTID 21
#define DESTID_SCC (1<<7)
#define DESTID_DPD (1<<6)
#define SOURCEID 22
#define SBIC_SOURCEID 22
#define SOURCEID_ER (1<<7)
#define SOURCEID_ES (1<<6)
#define SOURCEID_DSP (1<<5)
#define SOURCEID_SIV (1<<4)
#define SSR 23
#define CMND 24
#define SBIC_SSR 23
#define SBIC_CMND 24
#define CMND_RESET 0x00
#define CMND_ABORT 0x01
#define CMND_ASSERTATN 0x02
......@@ -113,8 +113,8 @@
#define CMND_XFERINFO 0x20
#define CMND_SBT (1<<7)
#define DATA 25
#define ASR 26
#define SBIC_DATA 25
#define SBIC_ASR 26
#define ASR_INT (1<<7)
#define ASR_LCI (1<<6)
#define ASR_BSY (1<<5)
......@@ -123,22 +123,22 @@
#define ASR_DBR (1<<0)
/* DMAC registers */
#define INIT 0x00
#define DMAC_INIT 0x00
#define INIT_8BIT (1)
#define CHANNEL 0x80
#define DMAC_CHANNEL 0x80
#define CHANNEL_0 0x00
#define CHANNEL_1 0x01
#define CHANNEL_2 0x02
#define CHANNEL_3 0x03
#define TXCNTLO 0x01
#define TXCNTHI 0x81
#define TXADRLO 0x02
#define TXADRMD 0x82
#define TXADRHI 0x03
#define DMAC_TXCNTLO 0x01
#define DMAC_TXCNTHI 0x81
#define DMAC_TXADRLO 0x02
#define DMAC_TXADRMD 0x82
#define DMAC_TXADRHI 0x03
#define DEVCON0 0x04
#define DMAC_DEVCON0 0x04
#define DEVCON0_AKL (1<<7)
#define DEVCON0_RQL (1<<6)
#define DEVCON0_EXW (1<<5)
......@@ -148,11 +148,11 @@
#define DEVCON0_AHLD (1<<1)
#define DEVCON0_MTM (1<<0)
#define DEVCON1 0x84
#define DMAC_DEVCON1 0x84
#define DEVCON1_WEV (1<<1)
#define DEVCON1_BHLD (1<<0)
#define MODECON 0x05
#define DMAC_MODECON 0x05
#define MODECON_WOED 0x01
#define MODECON_VERIFY 0x00
#define MODECON_READ 0x04
......@@ -164,14 +164,14 @@
#define MODECON_BLOCK 0x80
#define MODECON_CASCADE 0xC0
#define STATUS 0x85
#define DMAC_STATUS 0x85
#define STATUS_TC0 (1<<0)
#define STATUS_RQ0 (1<<4)
#define TEMPLO 0x06
#define TEMPHI 0x86
#define REQREG 0x07
#define MASKREG 0x87
#define DMAC_TEMPLO 0x06
#define DMAC_TEMPHI 0x86
#define DMAC_REQREG 0x07
#define DMAC_MASKREG 0x87
#define MASKREG_M0 0x01
#define MASKREG_M1 0x02
#define MASKREG_M2 0x04
......
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