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Commit 8bc1e4ec authored by Heiko Carstens's avatar Heiko Carstens
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s390/disassembler: generate opcode tables from text file 

The current way of adding new instructions to the opcode tables is
painful and error prone. Therefore add, similar to binutils, a text
file which contains all opcodes and the corresponding mnemonics and
instruction formats.

A small gen_opcode_table tool then generates a header file with the
required enums and opcode table initializers at the prepare step of
the kernel build.

This way only a simple text file has to be maintained, which can be
rather easily extended.

Unlike before where there were plenty of opcode tables and a large
switch statement to find the correct opcode table, there is now only
one opcode table left which contains all instructions. A second opcode
offset table now contains offsets within the opcode table to find
instructions which have the same opcode prefix. In order to save space
all 1-byte opcode instructions are grouped together at the end of the
opcode table. This is also quite similar to like it was before.

In addition also move and change code and definitions within the
disassembler. As a side effect this reduces the size required for the
code and opcode tables by ~1.5k.
Signed-off-by: default avatarHeiko Carstens <heiko.carstens@de.ibm.com>
parent dac6dc26
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Showing with 1813 additions and 1856 deletions
arch/s390/Makefile
View file @ 8bc1e4ec
......@@ -133,6 +133,7 @@ archclean:
archprepare:
$(Q)$(MAKE) $(build)=$(tools) include/generated/facilities.h
$(Q)$(MAKE) $(build)=$(tools) include/generated/dis.h
# Don't use tabs in echo arguments
define archhelp
......
arch/s390/include/asm/dis.h
View file @ 8bc1e4ec
......@@ -8,32 +8,7 @@
#ifndef __ASM_S390_DIS_H__
#define __ASM_S390_DIS_H__
/* Type of operand */
#define OPERAND_GPR 0x1 /* Operand printed as %rx */
#define OPERAND_FPR 0x2 /* Operand printed as %fx */
#define OPERAND_AR 0x4 /* Operand printed as %ax */
#define OPERAND_CR 0x8 /* Operand printed as %cx */
#define OPERAND_VR 0x10 /* Operand printed as %vx */
#define OPERAND_DISP 0x20 /* Operand printed as displacement */
#define OPERAND_BASE 0x40 /* Operand printed as base register */
#define OPERAND_INDEX 0x80 /* Operand printed as index register */
#define OPERAND_PCREL 0x100 /* Operand printed as pc-relative symbol */
#define OPERAND_SIGNED 0x200 /* Operand printed as signed value */
#define OPERAND_LENGTH 0x400 /* Operand printed as length (+1) */
struct s390_operand {
int bits; /* The number of bits in the operand. */
int shift; /* The number of bits to shift. */
int flags; /* One bit syntax flags. */
};
struct s390_insn {
const char name[5];
unsigned char opfrag;
unsigned char format;
};
#include <generated/dis.h>
static inline int insn_length(unsigned char code)
{
......
arch/s390/kernel/dis.c
View file @ 8bc1e4ec
......@@ -21,52 +21,91 @@
#include <linux/reboot.h>
#include <linux/kprobes.h>
#include <linux/kdebug.h>
#include <linux/uaccess.h>
#include <linux/atomic.h>
#include <asm/dis.h>
#include <asm/io.h>
#include <linux/atomic.h>
#include <asm/cpcmd.h>
#include <asm/lowcore.h>
#include <asm/debug.h>
#include <asm/irq.h>
/* Type of operand */
#define OPERAND_GPR 0x1 /* Operand printed as %rx */
#define OPERAND_FPR 0x2 /* Operand printed as %fx */
#define OPERAND_AR 0x4 /* Operand printed as %ax */
#define OPERAND_CR 0x8 /* Operand printed as %cx */
#define OPERAND_VR 0x10 /* Operand printed as %vx */
#define OPERAND_DISP 0x20 /* Operand printed as displacement */
#define OPERAND_BASE 0x40 /* Operand printed as base register */
#define OPERAND_INDEX 0x80 /* Operand printed as index register */
#define OPERAND_PCREL 0x100 /* Operand printed as pc-relative symbol */
#define OPERAND_SIGNED 0x200 /* Operand printed as signed value */
#define OPERAND_LENGTH 0x400 /* Operand printed as length (+1) */
struct s390_operand {
unsigned char bits; /* The number of bits in the operand. */
unsigned char shift; /* The number of bits to shift. */
unsigned short flags; /* One bit syntax flags. */
};
struct s390_insn {
union {
const char name[5];
struct {
unsigned char zero;
unsigned int offset;
} __packed;
};
unsigned char opfrag;
unsigned char format;
};
struct s390_opcode_offset {
unsigned char opcode;
unsigned char mask;
unsigned char byte;
unsigned short offset;
unsigned short count;
} __packed;
enum {
UNUSED, /* Indicates the end of the operand list */
R_8, /* GPR starting at position 8 */
R_12, /* GPR starting at position 12 */
R_16, /* GPR starting at position 16 */
R_20, /* GPR starting at position 20 */
R_24, /* GPR starting at position 24 */
R_28, /* GPR starting at position 28 */
R_32, /* GPR starting at position 32 */
F_8, /* FPR starting at position 8 */
F_12, /* FPR starting at position 12 */
F_16, /* FPR starting at position 16 */
F_20, /* FPR starting at position 16 */
F_24, /* FPR starting at position 24 */
F_28, /* FPR starting at position 28 */
F_32, /* FPR starting at position 32 */
UNUSED,
A_8, /* Access reg. starting at position 8 */
A_12, /* Access reg. starting at position 12 */
A_24, /* Access reg. starting at position 24 */
A_28, /* Access reg. starting at position 28 */
C_8, /* Control reg. starting at position 8 */
C_12, /* Control reg. starting at position 12 */
V_8, /* Vector reg. starting at position 8, extension bit at 36 */
V_12, /* Vector reg. starting at position 12, extension bit at 37 */
V_16, /* Vector reg. starting at position 16, extension bit at 38 */
V_32, /* Vector reg. starting at position 32, extension bit at 39 */
W_12, /* Vector reg. at bit 12, extension at bit 37, used as index */
B_16, /* Base register starting at position 16 */
B_32, /* Base register starting at position 32 */
X_12, /* Index register starting at position 12 */
C_8, /* Control reg. starting at position 8 */
C_12, /* Control reg. starting at position 12 */
D20_20, /* 20 bit displacement starting at 20 */
D_20, /* Displacement starting at position 20 */
D_36, /* Displacement starting at position 36 */
D20_20, /* 20 bit displacement starting at 20 */
F_8, /* FPR starting at position 8 */
F_12, /* FPR starting at position 12 */
F_16, /* FPR starting at position 16 */
F_24, /* FPR starting at position 24 */
F_28, /* FPR starting at position 28 */
F_32, /* FPR starting at position 32 */
I8_8, /* 8 bit signed value starting at 8 */
I8_32, /* 8 bit signed value starting at 32 */
I16_16, /* 16 bit signed value starting at 16 */
I16_32, /* 16 bit signed value starting at 32 */
I32_16, /* 32 bit signed value starting at 16 */
J12_12, /* 12 bit PC relative offset at 12 */
J16_16, /* 16 bit PC relative offset at 16 */
J16_32, /* 16 bit PC relative offset at 32 */
J24_24, /* 24 bit PC relative offset at 24 */
J32_16, /* 32 bit PC relative offset at 16 */
L4_8, /* 4 bit length starting at position 8 */
L4_12, /* 4 bit length starting at position 12 */
L8_8, /* 8 bit length starting at position 8 */
R_8, /* GPR starting at position 8 */
R_12, /* GPR starting at position 12 */
R_16, /* GPR starting at position 16 */
R_24, /* GPR starting at position 24 */
R_28, /* GPR starting at position 28 */
U4_8, /* 4 bit unsigned value starting at 8 */
U4_12, /* 4 bit unsigned value starting at 12 */
U4_16, /* 4 bit unsigned value starting at 16 */
......@@ -80,127 +119,55 @@ enum {
U8_24, /* 8 bit unsigned value starting at 24 */
U8_28, /* 8 bit unsigned value starting at 28 */
U8_32, /* 8 bit unsigned value starting at 32 */
I8_8, /* 8 bit signed value starting at 8 */
I8_16, /* 8 bit signed value starting at 16 */
I8_24, /* 8 bit signed value starting at 24 */
I8_32, /* 8 bit signed value starting at 32 */
J12_12, /* PC relative offset at 12 */
I16_16, /* 16 bit signed value starting at 16 */
I16_32, /* 32 bit signed value starting at 16 */
U12_16, /* 12 bit unsigned value starting at 16 */
U16_16, /* 16 bit unsigned value starting at 16 */
U16_32, /* 32 bit unsigned value starting at 16 */
J16_16, /* PC relative jump offset at 16 */
J16_32, /* PC relative offset at 16 */
I24_24, /* 24 bit signed value starting at 24 */
J32_16, /* PC relative long offset at 16 */
I32_16, /* 32 bit signed value starting at 16 */
U16_32, /* 16 bit unsigned value starting at 32 */
U32_16, /* 32 bit unsigned value starting at 16 */
M_16, /* 4 bit optional mask starting at 16 */
M_20, /* 4 bit optional mask starting at 20 */
M_24, /* 4 bit optional mask starting at 24 */
M_28, /* 4 bit optional mask starting at 28 */
M_32, /* 4 bit optional mask starting at 32 */
RO_28, /* optional GPR starting at position 28 */
};
/*
* Enumeration of the different instruction formats.
* For details consult the principles of operation.
*/
enum {
INSTR_INVALID,
INSTR_E,
INSTR_IE_UU,
INSTR_MII_UPI,
INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU,
INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, INSTR_RIE_RRI0,
INSTR_RIE_RUI0, INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP,
INSTR_RIS_R0RDU, INSTR_RIS_R0UU, INSTR_RIS_RURDI, INSTR_RIS_RURDU,
INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP,
INSTR_RRE_00, INSTR_RRE_0R, INSTR_RRE_AA, INSTR_RRE_AR, INSTR_RRE_F0,
INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF,
INSTR_RRE_RR, INSTR_RRE_RR_OPT,
INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_FUFF2, INSTR_RRF_M0RR,
INSTR_RRF_R0RR, INSTR_RRF_R0RR2, INSTR_RRF_RMRR, INSTR_RRF_RURR,
INSTR_RRF_U0FF, INSTR_RRF_U0RF, INSTR_RRF_U0RR, INSTR_RRF_UUFF,
INSTR_RRF_UUFR, INSTR_RRF_UURF,
INSTR_RRR_F0FF, INSTR_RRS_RRRDU,
INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR,
INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD,
INSTR_RSI_RRP,
INSTR_RSL_LRDFU, INSTR_RSL_R0RD,
INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD,
INSTR_RSY_RURD2, INSTR_RSY_RDRM, INSTR_RSY_RMRD,
INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD,
INSTR_RS_RURD,
INSTR_RXE_FRRD, INSTR_RXE_RRRD, INSTR_RXE_RRRDM,
INSTR_RXF_FRRDF,
INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RXY_URRD,
INSTR_RX_FRRD, INSTR_RX_RRRD, INSTR_RX_URRD,
INSTR_SIL_RDI, INSTR_SIL_RDU,
INSTR_SIY_IRD, INSTR_SIY_URD,
INSTR_SI_URD,
INSTR_SMI_U0RDP,
INSTR_SSE_RDRD,
INSTR_SSF_RRDRD, INSTR_SSF_RRDRD2,
INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD,
INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3,
INSTR_S_00, INSTR_S_RD,
INSTR_VRI_V0IM, INSTR_VRI_V0I0, INSTR_VRI_V0IIM, INSTR_VRI_VVIM,
INSTR_VRI_VVV0IM, INSTR_VRI_VVV0I0, INSTR_VRI_VVIMM,
INSTR_VRR_VV00MMM, INSTR_VRR_VV000MM, INSTR_VRR_VV0000M,
INSTR_VRR_VV00000, INSTR_VRR_VVV0M0M, INSTR_VRR_VV00M0M,
INSTR_VRR_VVV000M, INSTR_VRR_VVV000V, INSTR_VRR_VVV0000,
INSTR_VRR_VVV0MMM, INSTR_VRR_VVV00MM, INSTR_VRR_VVVMM0V,
INSTR_VRR_VVVM0MV, INSTR_VRR_VVVM00V, INSTR_VRR_VRR0000,
INSTR_VRS_VVRDM, INSTR_VRS_VVRD0, INSTR_VRS_VRRDM, INSTR_VRS_VRRD0,
INSTR_VRS_RVRDM,
INSTR_VRV_VVRDM, INSTR_VRV_VWRDM,
INSTR_VRX_VRRDM, INSTR_VRX_VRRD0,
INSTR_VSI_URDV, INSTR_VRS_RRDV, INSTR_VRI_V0UU2, INSTR_VRR_RV0U,
INSTR_VRI_VR0UU, INSTR_VRI_VVUUU2, INSTR_VRR_0V, INSTR_VRI_VVV0UU2,
INSTR_VRR_0VV0U, INSTR_VRR_VVV, INSTR_VRR_VVVU0UV,
INSTR_VRR_VVVUU0V, INSTR_VRR_VVV0UUU,
VX_12, /* Vector index register starting at position 12 */
V_8, /* Vector reg. starting at position 8 */
V_12, /* Vector reg. starting at position 12 */
V_16, /* Vector reg. starting at position 16 */
V_32, /* Vector reg. starting at position 32 */
X_12, /* Index register starting at position 12 */
};
static const struct s390_operand operands[] =
{
static const struct s390_operand operands[] = {
[UNUSED] = { 0, 0, 0 },
[R_8] = { 4, 8, OPERAND_GPR },
[R_12] = { 4, 12, OPERAND_GPR },
[R_16] = { 4, 16, OPERAND_GPR },
[R_20] = { 4, 20, OPERAND_GPR },
[R_24] = { 4, 24, OPERAND_GPR },
[R_28] = { 4, 28, OPERAND_GPR },
[R_32] = { 4, 32, OPERAND_GPR },
[F_8] = { 4, 8, OPERAND_FPR },
[F_12] = { 4, 12, OPERAND_FPR },
[F_16] = { 4, 16, OPERAND_FPR },
[F_20] = { 4, 16, OPERAND_FPR },
[F_24] = { 4, 24, OPERAND_FPR },
[F_28] = { 4, 28, OPERAND_FPR },
[F_32] = { 4, 32, OPERAND_FPR },
[A_8] = { 4, 8, OPERAND_AR },
[A_12] = { 4, 12, OPERAND_AR },
[A_24] = { 4, 24, OPERAND_AR },
[A_28] = { 4, 28, OPERAND_AR },
[C_8] = { 4, 8, OPERAND_CR },
[C_12] = { 4, 12, OPERAND_CR },
[V_8] = { 4, 8, OPERAND_VR },
[V_12] = { 4, 12, OPERAND_VR },
[V_16] = { 4, 16, OPERAND_VR },
[V_32] = { 4, 32, OPERAND_VR },
[W_12] = { 4, 12, OPERAND_INDEX | OPERAND_VR },
[B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR },
[B_32] = { 4, 32, OPERAND_BASE | OPERAND_GPR },
[X_12] = { 4, 12, OPERAND_INDEX | OPERAND_GPR },
[C_8] = { 4, 8, OPERAND_CR },
[C_12] = { 4, 12, OPERAND_CR },
[D20_20] = { 20, 20, OPERAND_DISP | OPERAND_SIGNED },
[D_20] = { 12, 20, OPERAND_DISP },
[D_36] = { 12, 36, OPERAND_DISP },
[D20_20] = { 20, 20, OPERAND_DISP | OPERAND_SIGNED },
[F_8] = { 4, 8, OPERAND_FPR },
[F_12] = { 4, 12, OPERAND_FPR },
[F_16] = { 4, 16, OPERAND_FPR },
[F_24] = { 4, 24, OPERAND_FPR },
[F_28] = { 4, 28, OPERAND_FPR },
[F_32] = { 4, 32, OPERAND_FPR },
[I8_8] = { 8, 8, OPERAND_SIGNED },
[I8_32] = { 8, 32, OPERAND_SIGNED },
[I16_16] = { 16, 16, OPERAND_SIGNED },
[I16_32] = { 16, 32, OPERAND_SIGNED },
[I32_16] = { 32, 16, OPERAND_SIGNED },
[J12_12] = { 12, 12, OPERAND_PCREL },
[J16_16] = { 16, 16, OPERAND_PCREL },
[J16_32] = { 16, 32, OPERAND_PCREL },
[J24_24] = { 24, 24, OPERAND_PCREL },
[J32_16] = { 32, 16, OPERAND_PCREL },
[L4_8] = { 4, 8, OPERAND_LENGTH },
[L4_12] = { 4, 12, OPERAND_LENGTH },
[L8_8] = { 8, 8, OPERAND_LENGTH },
[R_8] = { 4, 8, OPERAND_GPR },
[R_12] = { 4, 12, OPERAND_GPR },
[R_16] = { 4, 16, OPERAND_GPR },
[R_24] = { 4, 24, OPERAND_GPR },
[R_28] = { 4, 28, OPERAND_GPR },
[U4_8] = { 4, 8, 0 },
[U4_12] = { 4, 12, 0 },
[U4_16] = { 4, 16, 0 },
......@@ -214,1614 +181,162 @@ static const struct s390_operand operands[] =
[U8_24] = { 8, 24, 0 },
[U8_28] = { 8, 28, 0 },
[U8_32] = { 8, 32, 0 },
[J12_12] = { 12, 12, OPERAND_PCREL },
[I8_8] = { 8, 8, OPERAND_SIGNED },
[I8_16] = { 8, 16, OPERAND_SIGNED },
[I8_24] = { 8, 24, OPERAND_SIGNED },
[I8_32] = { 8, 32, OPERAND_SIGNED },
[I16_32] = { 16, 32, OPERAND_SIGNED },
[I16_16] = { 16, 16, OPERAND_SIGNED },
[U12_16] = { 12, 16, 0 },
[U16_16] = { 16, 16, 0 },
[U16_32] = { 16, 32, 0 },
[J16_16] = { 16, 16, OPERAND_PCREL },
[J16_32] = { 16, 32, OPERAND_PCREL },
[I24_24] = { 24, 24, OPERAND_SIGNED },
[J32_16] = { 32, 16, OPERAND_PCREL },
[I32_16] = { 32, 16, OPERAND_SIGNED },
[U32_16] = { 32, 16, 0 },
[M_16] = { 4, 16, 0 },
[M_20] = { 4, 20, 0 },
[M_24] = { 4, 24, 0 },
[M_28] = { 4, 28, 0 },
[M_32] = { 4, 32, 0 },
[RO_28] = { 4, 28, OPERAND_GPR }
};
static const unsigned char formats[][7] = {
[INSTR_E] = { 0xff, 0,0,0,0,0,0 },
[INSTR_IE_UU] = { 0xff, U4_24,U4_28,0,0,0,0 },
[INSTR_MII_UPI] = { 0xff, U4_8,J12_12,I24_24 },
[INSTR_RIE_R0IU] = { 0xff, R_8,I16_16,U4_32,0,0,0 },
[INSTR_RIE_R0UU] = { 0xff, R_8,U16_16,U4_32,0,0,0 },
[INSTR_RIE_RRI0] = { 0xff, R_8,R_12,I16_16,0,0,0 },
[INSTR_RIE_RRPU] = { 0xff, R_8,R_12,U4_32,J16_16,0,0 },
[INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 },
[INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 },
[INSTR_RIE_RUI0] = { 0xff, R_8,I16_16,U4_12,0,0,0 },
[INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 },
[INSTR_RIE_RUPU] = { 0xff, R_8,U8_32,U4_12,J16_16,0,0 },
[INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 },
[INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 },
[INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 },
[INSTR_RIL_UP] = { 0x0f, U4_8,J32_16,0,0,0,0 },
[INSTR_RIS_R0RDU] = { 0xff, R_8,U8_32,D_20,B_16,0,0 },
[INSTR_RIS_RURDI] = { 0xff, R_8,I8_32,U4_12,D_20,B_16,0 },
[INSTR_RIS_RURDU] = { 0xff, R_8,U8_32,U4_12,D_20,B_16,0 },
[INSTR_RI_RI] = { 0x0f, R_8,I16_16,0,0,0,0 },
[INSTR_RI_RP] = { 0x0f, R_8,J16_16,0,0,0,0 },
[INSTR_RI_RU] = { 0x0f, R_8,U16_16,0,0,0,0 },
[INSTR_RI_UP] = { 0x0f, U4_8,J16_16,0,0,0,0 },
[INSTR_RRE_00] = { 0xff, 0,0,0,0,0,0 },
[INSTR_RRE_0R] = { 0xff, R_28,0,0,0,0,0 },
[INSTR_RRE_AA] = { 0xff, A_24,A_28,0,0,0,0 },
[INSTR_RRE_AR] = { 0xff, A_24,R_28,0,0,0,0 },
[INSTR_RRE_F0] = { 0xff, F_24,0,0,0,0,0 },
[INSTR_RRE_FF] = { 0xff, F_24,F_28,0,0,0,0 },
[INSTR_RRE_FR] = { 0xff, F_24,R_28,0,0,0,0 },
[INSTR_RRE_R0] = { 0xff, R_24,0,0,0,0,0 },
[INSTR_RRE_RA] = { 0xff, R_24,A_28,0,0,0,0 },
[INSTR_RRE_RF] = { 0xff, R_24,F_28,0,0,0,0 },
[INSTR_RRE_RR] = { 0xff, R_24,R_28,0,0,0,0 },
[INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 },
[INSTR_RRF_0UFF] = { 0xff, F_24,F_28,U4_20,0,0,0 },
[INSTR_RRF_F0FF2] = { 0xff, F_24,F_16,F_28,0,0,0 },
[INSTR_RRF_F0FF] = { 0xff, F_16,F_24,F_28,0,0,0 },
[INSTR_RRF_F0FR] = { 0xff, F_24,F_16,R_28,0,0,0 },
[INSTR_RRF_FFRU] = { 0xff, F_24,F_16,R_28,U4_20,0,0 },
[INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 },
[INSTR_RRF_FUFF2] = { 0xff, F_24,F_28,F_16,U4_20,0,0 },
[INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 },
[INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 },
[INSTR_RRF_R0RR2] = { 0xff, R_24,R_28,R_16,0,0,0 },
[INSTR_RRF_RMRR] = { 0xff, R_24,R_16,R_28,M_20,0,0 },
[INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 },
[INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 },
[INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 },
[INSTR_RRF_U0RR] = { 0xff, R_24,R_28,U4_16,0,0,0 },
[INSTR_RRF_UUFF] = { 0xff, F_24,U4_16,F_28,U4_20,0,0 },
[INSTR_RRF_UUFR] = { 0xff, F_24,U4_16,R_28,U4_20,0,0 },
[INSTR_RRF_UURF] = { 0xff, R_24,U4_16,F_28,U4_20,0,0 },
[INSTR_RRR_F0FF] = { 0xff, F_24,F_28,F_16,0,0,0 },
[INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 },
[INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 },
[INSTR_RR_R0] = { 0xff, R_8, 0,0,0,0,0 },
[INSTR_RR_RR] = { 0xff, R_8,R_12,0,0,0,0 },
[INSTR_RR_U0] = { 0xff, U8_8, 0,0,0,0,0 },
[INSTR_RR_UR] = { 0xff, U4_8,R_12,0,0,0,0 },
[INSTR_RSE_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 },
[INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 },
[INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 },
[INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 },
[INSTR_RSL_LRDFU] = { 0xff, F_32,D_20,L8_8,B_16,U4_36,0 },
[INSTR_RSL_R0RD] = { 0xff, D_20,L4_8,B_16,0,0,0 },
[INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 },
[INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 },
[INSTR_RSY_RDRM] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 },
[INSTR_RSY_RMRD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 },
[INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 },
[INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 },
[INSTR_RSY_RURD2] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 },
[INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 },
[INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 },
[INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 },
[INSTR_RS_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 },
[INSTR_RS_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 },
[INSTR_RXE_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 },
[INSTR_RXE_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 },
[INSTR_RXE_RRRDM] = { 0xff, R_8,D_20,X_12,B_16,M_32,0 },
[INSTR_RXF_FRRDF] = { 0xff, F_32,F_8,D_20,X_12,B_16,0 },
[INSTR_RXY_FRRD] = { 0xff, F_8,D20_20,X_12,B_16,0,0 },
[INSTR_RXY_RRRD] = { 0xff, R_8,D20_20,X_12,B_16,0,0 },
[INSTR_RXY_URRD] = { 0xff, U4_8,D20_20,X_12,B_16,0,0 },
[INSTR_RX_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 },
[INSTR_RX_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 },
[INSTR_RX_URRD] = { 0xff, U4_8,D_20,X_12,B_16,0,0 },
[INSTR_SIL_RDI] = { 0xff, D_20,B_16,I16_32,0,0,0 },
[INSTR_SIL_RDU] = { 0xff, D_20,B_16,U16_32,0,0,0 },
[INSTR_SIY_IRD] = { 0xff, D20_20,B_16,I8_8,0,0,0 },
[INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 },
[INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 },
[INSTR_SMI_U0RDP] = { 0xff, U4_8,J16_32,D_20,B_16,0,0 },
[INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 },
[INSTR_SSF_RRDRD] = { 0x0f, D_20,B_16,D_36,B_32,R_8,0 },
[INSTR_SSF_RRDRD2]= { 0x0f, R_8,D_20,B_16,D_36,B_32,0 },
[INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 },
[INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 },
[INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 },
[INSTR_SS_RRRDRD2]= { 0xff, R_8,D_20,B_16,R_12,D_36,B_32 },
[INSTR_SS_RRRDRD3]= { 0xff, R_8,R_12,D_20,B_16,D_36,B_32 },
[INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 },
[INSTR_S_00] = { 0xff, 0,0,0,0,0,0 },
[INSTR_S_RD] = { 0xff, D_20,B_16,0,0,0,0 },
[INSTR_VRI_V0IM] = { 0xff, V_8,I16_16,M_32,0,0,0 },
[INSTR_VRI_V0I0] = { 0xff, V_8,I16_16,0,0,0,0 },
[INSTR_VRI_V0IIM] = { 0xff, V_8,I8_16,I8_24,M_32,0,0 },
[INSTR_VRI_VVIM] = { 0xff, V_8,I16_16,V_12,M_32,0,0 },
[INSTR_VRI_VVV0IM]= { 0xff, V_8,V_12,V_16,I8_24,M_32,0 },
[INSTR_VRI_VVV0I0]= { 0xff, V_8,V_12,V_16,I8_24,0,0 },
[INSTR_VRI_VVIMM] = { 0xff, V_8,V_12,I16_16,M_32,M_28,0 },
[INSTR_VRR_VV00MMM]={ 0xff, V_8,V_12,M_32,M_28,M_24,0 },
[INSTR_VRR_VV000MM]={ 0xff, V_8,V_12,M_32,M_28,0,0 },
[INSTR_VRR_VV0000M]={ 0xff, V_8,V_12,M_32,0,0,0 },
[INSTR_VRR_VV00000]={ 0xff, V_8,V_12,0,0,0,0 },
[INSTR_VRR_VVV0M0M]={ 0xff, V_8,V_12,V_16,M_32,M_24,0 },
[INSTR_VRR_VV00M0M]={ 0xff, V_8,V_12,M_32,M_24,0,0 },
[INSTR_VRR_VVV000M]={ 0xff, V_8,V_12,V_16,M_32,0,0 },
[INSTR_VRR_VVV000V]={ 0xff, V_8,V_12,V_16,V_32,0,0 },
[INSTR_VRR_VVV0000]={ 0xff, V_8,V_12,V_16,0,0,0 },
[INSTR_VRR_VVV0MMM]={ 0xff, V_8,V_12,V_16,M_32,M_28,M_24 },
[INSTR_VRR_VVV00MM]={ 0xff, V_8,V_12,V_16,M_32,M_28,0 },
[INSTR_VRR_VVVMM0V]={ 0xff, V_8,V_12,V_16,V_32,M_20,M_24 },
[INSTR_VRR_VVVM0MV]={ 0xff, V_8,V_12,V_16,V_32,M_28,M_20 },
[INSTR_VRR_VVVM00V]={ 0xff, V_8,V_12,V_16,V_32,M_20,0 },
[INSTR_VRR_VRR0000]={ 0xff, V_8,R_12,R_16,0,0,0 },
[INSTR_VRS_VVRDM] = { 0xff, V_8,V_12,D_20,B_16,M_32,0 },
[INSTR_VRS_VVRD0] = { 0xff, V_8,V_12,D_20,B_16,0,0 },
[INSTR_VRS_VRRDM] = { 0xff, V_8,R_12,D_20,B_16,M_32,0 },
[INSTR_VRS_VRRD0] = { 0xff, V_8,R_12,D_20,B_16,0,0 },
[INSTR_VRS_RVRDM] = { 0xff, R_8,V_12,D_20,B_16,M_32,0 },
[INSTR_VRV_VVRDM] = { 0xff, V_8,V_12,D_20,B_16,M_32,0 },
[INSTR_VRV_VWRDM] = { 0xff, V_8,D_20,W_12,B_16,M_32,0 },
[INSTR_VRX_VRRDM] = { 0xff, V_8,D_20,X_12,B_16,M_32,0 },
[INSTR_VRX_VRRD0] = { 0xff, V_8,D_20,X_12,B_16,0,0 },
[INSTR_VRI_V0UU2] = {0xff, V_8,U16_16,U4_32,0,0,0 },
[INSTR_VRI_VR0UU] = {0xff, V_8,V_12,U8_28,U8_16,U4_24,0 },
[INSTR_VRI_VVUUU2]= {0xff, V_8,V_12,U8_28,U8_16,U4_24,0 },
[INSTR_VRI_VVV0UU2]= {0xff, V_8,V_12,V_16,U8_28,U4_24,0 },
[INSTR_VRR_0VV0U] = {0xff, V_12,V_16,U4_24,0,0,0 },
[INSTR_VRR_0V] = {0xff, V_12,0,0,0,0,0 },
[INSTR_VRR_RV0U] = {0xff, R_8,V_12,U4_24,0,0,0 },
[INSTR_VRR_VVV0UUU]= {0xff, V_8,V_12,V_16,U4_32,U4_28,U4_24 },
[INSTR_VRR_VVVU0UV]= {0xff, V_8,V_12,V_16,V_32,U4_28,U4_20 },
[INSTR_VRR_VVVUU0V]= {0xff, V_8,V_12,V_16,V_32,U4_20,U4_24 },
[INSTR_VRR_VVV] = {0xff, V_8,V_12,V_16,0,0,0 },
[INSTR_VRS_RRDV] = {0xff, V_32,R_12,D_20,B_16,0,0 },
[INSTR_VSI_URDV] = {0xff, V_32,D_20,B_16,U8_8,0,0 },
};
enum {
LONG_INSN_ALGHSIK,
LONG_INSN_ALHHHR,
LONG_INSN_ALHHLR,
LONG_INSN_ALHSIK,
LONG_INSN_ALSIHN,
LONG_INSN_CDFBRA,
LONG_INSN_CDGBRA,
LONG_INSN_CDGTRA,
LONG_INSN_CDLFBR,
LONG_INSN_CDLFTR,
LONG_INSN_CDLGBR,
LONG_INSN_CDLGTR,
LONG_INSN_CEFBRA,
LONG_INSN_CEGBRA,
LONG_INSN_CELFBR,
LONG_INSN_CELGBR,
LONG_INSN_CFDBRA,
LONG_INSN_CFEBRA,
LONG_INSN_CFXBRA,
LONG_INSN_CGDBRA,
LONG_INSN_CGDTRA,
LONG_INSN_CGEBRA,
LONG_INSN_CGXBRA,
LONG_INSN_CGXTRA,
LONG_INSN_CLFDBR,
LONG_INSN_CLFDTR,
LONG_INSN_CLFEBR,
LONG_INSN_CLFHSI,
LONG_INSN_CLFXBR,
LONG_INSN_CLFXTR,
LONG_INSN_CLGDBR,
LONG_INSN_CLGDTR,
LONG_INSN_CLGEBR,
LONG_INSN_CLGFRL,
LONG_INSN_CLGHRL,
LONG_INSN_CLGHSI,
LONG_INSN_CLGXBR,
LONG_INSN_CLGXTR,
LONG_INSN_CLHHSI,
LONG_INSN_CXFBRA,
LONG_INSN_CXGBRA,
LONG_INSN_CXGTRA,
LONG_INSN_CXLFBR,
LONG_INSN_CXLFTR,
LONG_INSN_CXLGBR,
LONG_INSN_CXLGTR,
LONG_INSN_FIDBRA,
LONG_INSN_FIEBRA,
LONG_INSN_FIXBRA,
LONG_INSN_LDXBRA,
LONG_INSN_LEDBRA,
LONG_INSN_LEXBRA,
LONG_INSN_LLGFAT,
LONG_INSN_LLGFRL,
LONG_INSN_LLGHRL,
LONG_INSN_LLGTAT,
LONG_INSN_LLZRGF,
LONG_INSN_LOCFHR,
LONG_INSN_LOCGHI,
LONG_INSN_LOCHHI,
LONG_INSN_POPCNT,
LONG_INSN_RIEMIT,
LONG_INSN_RINEXT,
LONG_INSN_RISBGN,
LONG_INSN_RISBHG,
LONG_INSN_RISBLG,
LONG_INSN_SLHHHR,
LONG_INSN_SLHHLR,
LONG_INSN_STOCFH,
LONG_INSN_TABORT,
LONG_INSN_TBEGIN,
LONG_INSN_TBEGINC,
LONG_INSN_PCISTG,
LONG_INSN_MPCIFC,
LONG_INSN_STPCIFC,
LONG_INSN_PCISTB,
LONG_INSN_VPOPCT,
LONG_INSN_VERLLV,
LONG_INSN_VESRAV,
LONG_INSN_VESRLV,
LONG_INSN_VSBCBI,
LONG_INSN_STCCTM,
LONG_INSN_MSGRKC,
LONG_INSN_LLGFSG,
LONG_INSN_VSTRLR,
LONG_INSN_VBPERM,
};
static char *long_insn_name[] = {
[LONG_INSN_ALGHSIK] = "alghsik",
[LONG_INSN_ALHHHR] = "alhhhr",
[LONG_INSN_ALHHLR] = "alhhlr",
[LONG_INSN_ALHSIK] = "alhsik",
[LONG_INSN_ALSIHN] = "alsihn",
[LONG_INSN_CDFBRA] = "cdfbra",
[LONG_INSN_CDGBRA] = "cdgbra",
[LONG_INSN_CDGTRA] = "cdgtra",
[LONG_INSN_CDLFBR] = "cdlfbr",
[LONG_INSN_CDLFTR] = "cdlftr",
[LONG_INSN_CDLGBR] = "cdlgbr",
[LONG_INSN_CDLGTR] = "cdlgtr",
[LONG_INSN_CEFBRA] = "cefbra",
[LONG_INSN_CEGBRA] = "cegbra",
[LONG_INSN_CELFBR] = "celfbr",
[LONG_INSN_CELGBR] = "celgbr",
[LONG_INSN_CFDBRA] = "cfdbra",
[LONG_INSN_CFEBRA] = "cfebra",
[LONG_INSN_CFXBRA] = "cfxbra",
[LONG_INSN_CGDBRA] = "cgdbra",
[LONG_INSN_CGDTRA] = "cgdtra",
[LONG_INSN_CGEBRA] = "cgebra",
[LONG_INSN_CGXBRA] = "cgxbra",
[LONG_INSN_CGXTRA] = "cgxtra",
[LONG_INSN_CLFDBR] = "clfdbr",
[LONG_INSN_CLFDTR] = "clfdtr",
[LONG_INSN_CLFEBR] = "clfebr",
[LONG_INSN_CLFHSI] = "clfhsi",
[LONG_INSN_CLFXBR] = "clfxbr",
[LONG_INSN_CLFXTR] = "clfxtr",
[LONG_INSN_CLGDBR] = "clgdbr",
[LONG_INSN_CLGDTR] = "clgdtr",
[LONG_INSN_CLGEBR] = "clgebr",
[LONG_INSN_CLGFRL] = "clgfrl",
[LONG_INSN_CLGHRL] = "clghrl",
[LONG_INSN_CLGHSI] = "clghsi",
[LONG_INSN_CLGXBR] = "clgxbr",
[LONG_INSN_CLGXTR] = "clgxtr",
[LONG_INSN_CLHHSI] = "clhhsi",
[LONG_INSN_CXFBRA] = "cxfbra",
[LONG_INSN_CXGBRA] = "cxgbra",
[LONG_INSN_CXGTRA] = "cxgtra",
[LONG_INSN_CXLFBR] = "cxlfbr",
[LONG_INSN_CXLFTR] = "cxlftr",
[LONG_INSN_CXLGBR] = "cxlgbr",
[LONG_INSN_CXLGTR] = "cxlgtr",
[LONG_INSN_FIDBRA] = "fidbra",
[LONG_INSN_FIEBRA] = "fiebra",
[LONG_INSN_FIXBRA] = "fixbra",
[LONG_INSN_LDXBRA] = "ldxbra",
[LONG_INSN_LEDBRA] = "ledbra",
[LONG_INSN_LEXBRA] = "lexbra",
[LONG_INSN_LLGFAT] = "llgfat",
[LONG_INSN_LLGFRL] = "llgfrl",
[LONG_INSN_LLGHRL] = "llghrl",
[LONG_INSN_LLGTAT] = "llgtat",
[LONG_INSN_LLZRGF] = "llzrgf",
[LONG_INSN_POPCNT] = "popcnt",
[LONG_INSN_RIEMIT] = "riemit",
[LONG_INSN_RINEXT] = "rinext",
[LONG_INSN_RISBGN] = "risbgn",
[LONG_INSN_RISBHG] = "risbhg",
[LONG_INSN_RISBLG] = "risblg",
[LONG_INSN_SLHHHR] = "slhhhr",
[LONG_INSN_SLHHLR] = "slhhlr",
[LONG_INSN_TABORT] = "tabort",
[LONG_INSN_TBEGIN] = "tbegin",
[LONG_INSN_TBEGINC] = "tbeginc",
[LONG_INSN_PCISTG] = "pcistg",
[LONG_INSN_MPCIFC] = "mpcifc",
[LONG_INSN_STPCIFC] = "stpcifc",
[LONG_INSN_PCISTB] = "pcistb",
[LONG_INSN_VPOPCT] = "vpopct",
[LONG_INSN_VERLLV] = "verllv",
[LONG_INSN_VESRAV] = "vesrav",
[LONG_INSN_VESRLV] = "vesrlv",
[LONG_INSN_VSBCBI] = "vsbcbi",
[LONG_INSN_STCCTM] = "stcctm",
[LONG_INSN_LOCFHR] = "locfhr",
[LONG_INSN_LOCGHI] = "locghi",
[LONG_INSN_LOCHHI] = "lochhi",
[LONG_INSN_STOCFH] = "stocfh",
[LONG_INSN_MSGRKC] = "msgrkc",
[LONG_INSN_LLGFSG] = "llgfsg",
[LONG_INSN_VSTRLR] = "vstrlr",
[LONG_INSN_VBPERM] = "vbperm",
};
static struct s390_insn opcode[] = {
{ "bprp", 0xc5, INSTR_MII_UPI },
{ "bpp", 0xc7, INSTR_SMI_U0RDP },
{ "trtr", 0xd0, INSTR_SS_L0RDRD },
{ "lmd", 0xef, INSTR_SS_RRRDRD3 },
{ "spm", 0x04, INSTR_RR_R0 },
{ "balr", 0x05, INSTR_RR_RR },
{ "bctr", 0x06, INSTR_RR_RR },
{ "bcr", 0x07, INSTR_RR_UR },
{ "svc", 0x0a, INSTR_RR_U0 },
{ "bsm", 0x0b, INSTR_RR_RR },
{ "bassm", 0x0c, INSTR_RR_RR },
{ "basr", 0x0d, INSTR_RR_RR },
{ "mvcl", 0x0e, INSTR_RR_RR },
{ "clcl", 0x0f, INSTR_RR_RR },
{ "lpr", 0x10, INSTR_RR_RR },
{ "lnr", 0x11, INSTR_RR_RR },
{ "ltr", 0x12, INSTR_RR_RR },
{ "lcr", 0x13, INSTR_RR_RR },
{ "nr", 0x14, INSTR_RR_RR },
{ "clr", 0x15, INSTR_RR_RR },
{ "or", 0x16, INSTR_RR_RR },
{ "xr", 0x17, INSTR_RR_RR },
{ "lr", 0x18, INSTR_RR_RR },
{ "cr", 0x19, INSTR_RR_RR },
{ "ar", 0x1a, INSTR_RR_RR },
{ "sr", 0x1b, INSTR_RR_RR },
{ "mr", 0x1c, INSTR_RR_RR },
{ "dr", 0x1d, INSTR_RR_RR },
{ "alr", 0x1e, INSTR_RR_RR },
{ "slr", 0x1f, INSTR_RR_RR },
{ "lpdr", 0x20, INSTR_RR_FF },
{ "lndr", 0x21, INSTR_RR_FF },
{ "ltdr", 0x22, INSTR_RR_FF },
{ "lcdr", 0x23, INSTR_RR_FF },
{ "hdr", 0x24, INSTR_RR_FF },
{ "ldxr", 0x25, INSTR_RR_FF },
{ "mxr", 0x26, INSTR_RR_FF },
{ "mxdr", 0x27, INSTR_RR_FF },
{ "ldr", 0x28, INSTR_RR_FF },
{ "cdr", 0x29, INSTR_RR_FF },
{ "adr", 0x2a, INSTR_RR_FF },
{ "sdr", 0x2b, INSTR_RR_FF },
{ "mdr", 0x2c, INSTR_RR_FF },
{ "ddr", 0x2d, INSTR_RR_FF },
{ "awr", 0x2e, INSTR_RR_FF },
{ "swr", 0x2f, INSTR_RR_FF },
{ "lper", 0x30, INSTR_RR_FF },
{ "lner", 0x31, INSTR_RR_FF },
{ "lter", 0x32, INSTR_RR_FF },
{ "lcer", 0x33, INSTR_RR_FF },
{ "her", 0x34, INSTR_RR_FF },
{ "ledr", 0x35, INSTR_RR_FF },
{ "axr", 0x36, INSTR_RR_FF },
{ "sxr", 0x37, INSTR_RR_FF },
{ "ler", 0x38, INSTR_RR_FF },
{ "cer", 0x39, INSTR_RR_FF },
{ "aer", 0x3a, INSTR_RR_FF },
{ "ser", 0x3b, INSTR_RR_FF },
{ "mder", 0x3c, INSTR_RR_FF },
{ "der", 0x3d, INSTR_RR_FF },
{ "aur", 0x3e, INSTR_RR_FF },
{ "sur", 0x3f, INSTR_RR_FF },
{ "sth", 0x40, INSTR_RX_RRRD },
{ "la", 0x41, INSTR_RX_RRRD },
{ "stc", 0x42, INSTR_RX_RRRD },
{ "ic", 0x43, INSTR_RX_RRRD },
{ "ex", 0x44, INSTR_RX_RRRD },
{ "bal", 0x45, INSTR_RX_RRRD },
{ "bct", 0x46, INSTR_RX_RRRD },
{ "bc", 0x47, INSTR_RX_URRD },
{ "lh", 0x48, INSTR_RX_RRRD },
{ "ch", 0x49, INSTR_RX_RRRD },
{ "ah", 0x4a, INSTR_RX_RRRD },
{ "sh", 0x4b, INSTR_RX_RRRD },
{ "mh", 0x4c, INSTR_RX_RRRD },
{ "bas", 0x4d, INSTR_RX_RRRD },
{ "cvd", 0x4e, INSTR_RX_RRRD },
{ "cvb", 0x4f, INSTR_RX_RRRD },
{ "st", 0x50, INSTR_RX_RRRD },
{ "lae", 0x51, INSTR_RX_RRRD },
{ "n", 0x54, INSTR_RX_RRRD },
{ "cl", 0x55, INSTR_RX_RRRD },
{ "o", 0x56, INSTR_RX_RRRD },
{ "x", 0x57, INSTR_RX_RRRD },
{ "l", 0x58, INSTR_RX_RRRD },
{ "c", 0x59, INSTR_RX_RRRD },
{ "a", 0x5a, INSTR_RX_RRRD },
{ "s", 0x5b, INSTR_RX_RRRD },
{ "m", 0x5c, INSTR_RX_RRRD },
{ "d", 0x5d, INSTR_RX_RRRD },
{ "al", 0x5e, INSTR_RX_RRRD },
{ "sl", 0x5f, INSTR_RX_RRRD },
{ "std", 0x60, INSTR_RX_FRRD },
{ "mxd", 0x67, INSTR_RX_FRRD },
{ "ld", 0x68, INSTR_RX_FRRD },
{ "cd", 0x69, INSTR_RX_FRRD },
{ "ad", 0x6a, INSTR_RX_FRRD },
{ "sd", 0x6b, INSTR_RX_FRRD },
{ "md", 0x6c, INSTR_RX_FRRD },
{ "dd", 0x6d, INSTR_RX_FRRD },
{ "aw", 0x6e, INSTR_RX_FRRD },
{ "sw", 0x6f, INSTR_RX_FRRD },
{ "ste", 0x70, INSTR_RX_FRRD },
{ "ms", 0x71, INSTR_RX_RRRD },
{ "le", 0x78, INSTR_RX_FRRD },
{ "ce", 0x79, INSTR_RX_FRRD },
{ "ae", 0x7a, INSTR_RX_FRRD },
{ "se", 0x7b, INSTR_RX_FRRD },
{ "mde", 0x7c, INSTR_RX_FRRD },
{ "de", 0x7d, INSTR_RX_FRRD },
{ "au", 0x7e, INSTR_RX_FRRD },
{ "su", 0x7f, INSTR_RX_FRRD },
{ "ssm", 0x80, INSTR_S_RD },
{ "lpsw", 0x82, INSTR_S_RD },
{ "diag", 0x83, INSTR_RS_RRRD },
{ "brxh", 0x84, INSTR_RSI_RRP },
{ "brxle", 0x85, INSTR_RSI_RRP },
{ "bxh", 0x86, INSTR_RS_RRRD },
{ "bxle", 0x87, INSTR_RS_RRRD },
{ "srl", 0x88, INSTR_RS_R0RD },
{ "sll", 0x89, INSTR_RS_R0RD },
{ "sra", 0x8a, INSTR_RS_R0RD },
{ "sla", 0x8b, INSTR_RS_R0RD },
{ "srdl", 0x8c, INSTR_RS_R0RD },
{ "sldl", 0x8d, INSTR_RS_R0RD },
{ "srda", 0x8e, INSTR_RS_R0RD },
{ "slda", 0x8f, INSTR_RS_R0RD },
{ "stm", 0x90, INSTR_RS_RRRD },
{ "tm", 0x91, INSTR_SI_URD },
{ "mvi", 0x92, INSTR_SI_URD },
{ "ts", 0x93, INSTR_S_RD },
{ "ni", 0x94, INSTR_SI_URD },
{ "cli", 0x95, INSTR_SI_URD },
{ "oi", 0x96, INSTR_SI_URD },
{ "xi", 0x97, INSTR_SI_URD },
{ "lm", 0x98, INSTR_RS_RRRD },
{ "trace", 0x99, INSTR_RS_RRRD },
{ "lam", 0x9a, INSTR_RS_AARD },
{ "stam", 0x9b, INSTR_RS_AARD },
{ "mvcle", 0xa8, INSTR_RS_RRRD },
{ "clcle", 0xa9, INSTR_RS_RRRD },
{ "stnsm", 0xac, INSTR_SI_URD },
{ "stosm", 0xad, INSTR_SI_URD },
{ "sigp", 0xae, INSTR_RS_RRRD },
{ "mc", 0xaf, INSTR_SI_URD },
{ "lra", 0xb1, INSTR_RX_RRRD },
{ "stctl", 0xb6, INSTR_RS_CCRD },
{ "lctl", 0xb7, INSTR_RS_CCRD },
{ "cs", 0xba, INSTR_RS_RRRD },
{ "cds", 0xbb, INSTR_RS_RRRD },
{ "clm", 0xbd, INSTR_RS_RURD },
{ "stcm", 0xbe, INSTR_RS_RURD },
{ "icm", 0xbf, INSTR_RS_RURD },
{ "mvn", 0xd1, INSTR_SS_L0RDRD },
{ "mvc", 0xd2, INSTR_SS_L0RDRD },
{ "mvz", 0xd3, INSTR_SS_L0RDRD },
{ "nc", 0xd4, INSTR_SS_L0RDRD },
{ "clc", 0xd5, INSTR_SS_L0RDRD },
{ "oc", 0xd6, INSTR_SS_L0RDRD },
{ "xc", 0xd7, INSTR_SS_L0RDRD },
{ "mvck", 0xd9, INSTR_SS_RRRDRD },
{ "mvcp", 0xda, INSTR_SS_RRRDRD },
{ "mvcs", 0xdb, INSTR_SS_RRRDRD },
{ "tr", 0xdc, INSTR_SS_L0RDRD },
{ "trt", 0xdd, INSTR_SS_L0RDRD },
{ "ed", 0xde, INSTR_SS_L0RDRD },
{ "edmk", 0xdf, INSTR_SS_L0RDRD },
{ "pku", 0xe1, INSTR_SS_L0RDRD },
{ "unpku", 0xe2, INSTR_SS_L0RDRD },
{ "mvcin", 0xe8, INSTR_SS_L0RDRD },
{ "pka", 0xe9, INSTR_SS_L0RDRD },
{ "unpka", 0xea, INSTR_SS_L0RDRD },
{ "plo", 0xee, INSTR_SS_RRRDRD2 },
{ "srp", 0xf0, INSTR_SS_LIRDRD },
{ "mvo", 0xf1, INSTR_SS_LLRDRD },
{ "pack", 0xf2, INSTR_SS_LLRDRD },
{ "unpk", 0xf3, INSTR_SS_LLRDRD },
{ "zap", 0xf8, INSTR_SS_LLRDRD },
{ "cp", 0xf9, INSTR_SS_LLRDRD },
{ "ap", 0xfa, INSTR_SS_LLRDRD },
{ "sp", 0xfb, INSTR_SS_LLRDRD },
{ "mp", 0xfc, INSTR_SS_LLRDRD },
{ "dp", 0xfd, INSTR_SS_LLRDRD },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_01[] = {
{ "ptff", 0x04, INSTR_E },
{ "pfpo", 0x0a, INSTR_E },
{ "sam64", 0x0e, INSTR_E },
{ "pr", 0x01, INSTR_E },
{ "upt", 0x02, INSTR_E },
{ "sckpf", 0x07, INSTR_E },
{ "tam", 0x0b, INSTR_E },
{ "sam24", 0x0c, INSTR_E },
{ "sam31", 0x0d, INSTR_E },
{ "trap2", 0xff, INSTR_E },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_a5[] = {
{ "iihh", 0x00, INSTR_RI_RU },
{ "iihl", 0x01, INSTR_RI_RU },
{ "iilh", 0x02, INSTR_RI_RU },
{ "iill", 0x03, INSTR_RI_RU },
{ "nihh", 0x04, INSTR_RI_RU },
{ "nihl", 0x05, INSTR_RI_RU },
{ "nilh", 0x06, INSTR_RI_RU },
{ "nill", 0x07, INSTR_RI_RU },
{ "oihh", 0x08, INSTR_RI_RU },
{ "oihl", 0x09, INSTR_RI_RU },
{ "oilh", 0x0a, INSTR_RI_RU },
{ "oill", 0x0b, INSTR_RI_RU },
{ "llihh", 0x0c, INSTR_RI_RU },
{ "llihl", 0x0d, INSTR_RI_RU },
{ "llilh", 0x0e, INSTR_RI_RU },
{ "llill", 0x0f, INSTR_RI_RU },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_a7[] = {
{ "tmhh", 0x02, INSTR_RI_RU },
{ "tmhl", 0x03, INSTR_RI_RU },
{ "brctg", 0x07, INSTR_RI_RP },
{ "lghi", 0x09, INSTR_RI_RI },
{ "aghi", 0x0b, INSTR_RI_RI },
{ "mghi", 0x0d, INSTR_RI_RI },
{ "cghi", 0x0f, INSTR_RI_RI },
{ "tmlh", 0x00, INSTR_RI_RU },
{ "tmll", 0x01, INSTR_RI_RU },
{ "brc", 0x04, INSTR_RI_UP },
{ "bras", 0x05, INSTR_RI_RP },
{ "brct", 0x06, INSTR_RI_RP },
{ "lhi", 0x08, INSTR_RI_RI },
{ "ahi", 0x0a, INSTR_RI_RI },
{ "mhi", 0x0c, INSTR_RI_RI },
{ "chi", 0x0e, INSTR_RI_RI },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_aa[] = {
{ { 0, LONG_INSN_RINEXT }, 0x00, INSTR_RI_RI },
{ "rion", 0x01, INSTR_RI_RI },
{ "tric", 0x02, INSTR_RI_RI },
{ "rioff", 0x03, INSTR_RI_RI },
{ { 0, LONG_INSN_RIEMIT }, 0x04, INSTR_RI_RI },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_b2[] = {
{ "stckf", 0x7c, INSTR_S_RD },
{ "lpp", 0x80, INSTR_S_RD },
{ "lcctl", 0x84, INSTR_S_RD },
{ "lpctl", 0x85, INSTR_S_RD },
{ "qsi", 0x86, INSTR_S_RD },
{ "lsctl", 0x87, INSTR_S_RD },
{ "qctri", 0x8e, INSTR_S_RD },
{ "stfle", 0xb0, INSTR_S_RD },
{ "lpswe", 0xb2, INSTR_S_RD },
{ "srnmb", 0xb8, INSTR_S_RD },
{ "srnmt", 0xb9, INSTR_S_RD },
{ "lfas", 0xbd, INSTR_S_RD },
{ "scctr", 0xe0, INSTR_RRE_RR },
{ "spctr", 0xe1, INSTR_RRE_RR },
{ "ecctr", 0xe4, INSTR_RRE_RR },
{ "epctr", 0xe5, INSTR_RRE_RR },
{ "ppa", 0xe8, INSTR_RRF_U0RR },
{ "etnd", 0xec, INSTR_RRE_R0 },
{ "ecpga", 0xed, INSTR_RRE_RR },
{ "tend", 0xf8, INSTR_S_00 },
{ "niai", 0xfa, INSTR_IE_UU },
{ { 0, LONG_INSN_TABORT }, 0xfc, INSTR_S_RD },
{ "stidp", 0x02, INSTR_S_RD },
{ "sck", 0x04, INSTR_S_RD },
{ "stck", 0x05, INSTR_S_RD },
{ "sckc", 0x06, INSTR_S_RD },
{ "stckc", 0x07, INSTR_S_RD },
{ "spt", 0x08, INSTR_S_RD },
{ "stpt", 0x09, INSTR_S_RD },
{ "spka", 0x0a, INSTR_S_RD },
{ "ipk", 0x0b, INSTR_S_00 },
{ "ptlb", 0x0d, INSTR_S_00 },
{ "spx", 0x10, INSTR_S_RD },
{ "stpx", 0x11, INSTR_S_RD },
{ "stap", 0x12, INSTR_S_RD },
{ "sie", 0x14, INSTR_S_RD },
{ "pc", 0x18, INSTR_S_RD },
{ "sac", 0x19, INSTR_S_RD },
{ "cfc", 0x1a, INSTR_S_RD },
{ "servc", 0x20, INSTR_RRE_RR },
{ "ipte", 0x21, INSTR_RRE_RR },
{ "ipm", 0x22, INSTR_RRE_R0 },
{ "ivsk", 0x23, INSTR_RRE_RR },
{ "iac", 0x24, INSTR_RRE_R0 },
{ "ssar", 0x25, INSTR_RRE_R0 },
{ "epar", 0x26, INSTR_RRE_R0 },
{ "esar", 0x27, INSTR_RRE_R0 },
{ "pt", 0x28, INSTR_RRE_RR },
{ "iske", 0x29, INSTR_RRE_RR },
{ "rrbe", 0x2a, INSTR_RRE_RR },
{ "sske", 0x2b, INSTR_RRF_M0RR },
{ "tb", 0x2c, INSTR_RRE_0R },
{ "dxr", 0x2d, INSTR_RRE_FF },
{ "pgin", 0x2e, INSTR_RRE_RR },
{ "pgout", 0x2f, INSTR_RRE_RR },
{ "csch", 0x30, INSTR_S_00 },
{ "hsch", 0x31, INSTR_S_00 },
{ "msch", 0x32, INSTR_S_RD },
{ "ssch", 0x33, INSTR_S_RD },
{ "stsch", 0x34, INSTR_S_RD },
{ "tsch", 0x35, INSTR_S_RD },
{ "tpi", 0x36, INSTR_S_RD },
{ "sal", 0x37, INSTR_S_00 },
{ "rsch", 0x38, INSTR_S_00 },
{ "stcrw", 0x39, INSTR_S_RD },
{ "stcps", 0x3a, INSTR_S_RD },
{ "rchp", 0x3b, INSTR_S_00 },
{ "schm", 0x3c, INSTR_S_00 },
{ "bakr", 0x40, INSTR_RRE_RR },
{ "cksm", 0x41, INSTR_RRE_RR },
{ "sqdr", 0x44, INSTR_RRE_FF },
{ "sqer", 0x45, INSTR_RRE_FF },
{ "stura", 0x46, INSTR_RRE_RR },
{ "msta", 0x47, INSTR_RRE_R0 },
{ "palb", 0x48, INSTR_RRE_00 },
{ "ereg", 0x49, INSTR_RRE_RR },
{ "esta", 0x4a, INSTR_RRE_RR },
{ "lura", 0x4b, INSTR_RRE_RR },
{ "tar", 0x4c, INSTR_RRE_AR },
{ "cpya", 0x4d, INSTR_RRE_AA },
{ "sar", 0x4e, INSTR_RRE_AR },
{ "ear", 0x4f, INSTR_RRE_RA },
{ "csp", 0x50, INSTR_RRE_RR },
{ "msr", 0x52, INSTR_RRE_RR },
{ "mvpg", 0x54, INSTR_RRE_RR },
{ "mvst", 0x55, INSTR_RRE_RR },
{ "sthyi", 0x56, INSTR_RRE_RR },
{ "cuse", 0x57, INSTR_RRE_RR },
{ "bsg", 0x58, INSTR_RRE_RR },
{ "bsa", 0x5a, INSTR_RRE_RR },
{ "clst", 0x5d, INSTR_RRE_RR },
{ "srst", 0x5e, INSTR_RRE_RR },
{ "cmpsc", 0x63, INSTR_RRE_RR },
{ "siga", 0x74, INSTR_S_RD },
{ "xsch", 0x76, INSTR_S_00 },
{ "rp", 0x77, INSTR_S_RD },
{ "stcke", 0x78, INSTR_S_RD },
{ "sacf", 0x79, INSTR_S_RD },
{ "stsi", 0x7d, INSTR_S_RD },
{ "srnm", 0x99, INSTR_S_RD },
{ "stfpc", 0x9c, INSTR_S_RD },
{ "lfpc", 0x9d, INSTR_S_RD },
{ "tre", 0xa5, INSTR_RRE_RR },
{ "cuutf", 0xa6, INSTR_RRF_M0RR },
{ "cutfu", 0xa7, INSTR_RRF_M0RR },
{ "stfl", 0xb1, INSTR_S_RD },
{ "trap4", 0xff, INSTR_S_RD },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_b3[] = {
{ "maylr", 0x38, INSTR_RRF_F0FF },
{ "mylr", 0x39, INSTR_RRF_F0FF },
{ "mayr", 0x3a, INSTR_RRF_F0FF },
{ "myr", 0x3b, INSTR_RRF_F0FF },
{ "mayhr", 0x3c, INSTR_RRF_F0FF },
{ "myhr", 0x3d, INSTR_RRF_F0FF },
{ "lpdfr", 0x70, INSTR_RRE_FF },
{ "lndfr", 0x71, INSTR_RRE_FF },
{ "cpsdr", 0x72, INSTR_RRF_F0FF2 },
{ "lcdfr", 0x73, INSTR_RRE_FF },
{ "sfasr", 0x85, INSTR_RRE_R0 },
{ { 0, LONG_INSN_CELFBR }, 0x90, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDLFBR }, 0x91, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CXLFBR }, 0x92, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CEFBRA }, 0x94, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDFBRA }, 0x95, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CXFBRA }, 0x96, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CFEBRA }, 0x98, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CFDBRA }, 0x99, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CFXBRA }, 0x9a, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CLFEBR }, 0x9c, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLFDBR }, 0x9d, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLFXBR }, 0x9e, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CELGBR }, 0xa0, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDLGBR }, 0xa1, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CXLGBR }, 0xa2, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CEGBRA }, 0xa4, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDGBRA }, 0xa5, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CXGBRA }, 0xa6, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CGEBRA }, 0xa8, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CGDBRA }, 0xa9, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CGXBRA }, 0xaa, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CLGEBR }, 0xac, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLGDBR }, 0xad, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLGXBR }, 0xae, INSTR_RRF_UUFR },
{ "ldgr", 0xc1, INSTR_RRE_FR },
{ "cegr", 0xc4, INSTR_RRE_FR },
{ "cdgr", 0xc5, INSTR_RRE_FR },
{ "cxgr", 0xc6, INSTR_RRE_FR },
{ "cger", 0xc8, INSTR_RRF_U0RF },
{ "cgdr", 0xc9, INSTR_RRF_U0RF },
{ "cgxr", 0xca, INSTR_RRF_U0RF },
{ "lgdr", 0xcd, INSTR_RRE_RF },
{ "mdtra", 0xd0, INSTR_RRF_FUFF2 },
{ "ddtra", 0xd1, INSTR_RRF_FUFF2 },
{ "adtra", 0xd2, INSTR_RRF_FUFF2 },
{ "sdtra", 0xd3, INSTR_RRF_FUFF2 },
{ "ldetr", 0xd4, INSTR_RRF_0UFF },
{ "ledtr", 0xd5, INSTR_RRF_UUFF },
{ "ltdtr", 0xd6, INSTR_RRE_FF },
{ "fidtr", 0xd7, INSTR_RRF_UUFF },
{ "mxtra", 0xd8, INSTR_RRF_FUFF2 },
{ "dxtra", 0xd9, INSTR_RRF_FUFF2 },
{ "axtra", 0xda, INSTR_RRF_FUFF2 },
{ "sxtra", 0xdb, INSTR_RRF_FUFF2 },
{ "lxdtr", 0xdc, INSTR_RRF_0UFF },
{ "ldxtr", 0xdd, INSTR_RRF_UUFF },
{ "ltxtr", 0xde, INSTR_RRE_FF },
{ "fixtr", 0xdf, INSTR_RRF_UUFF },
{ "kdtr", 0xe0, INSTR_RRE_FF },
{ { 0, LONG_INSN_CGDTRA }, 0xe1, INSTR_RRF_UURF },
{ "cudtr", 0xe2, INSTR_RRE_RF },
{ "csdtr", 0xe3, INSTR_RRE_RF },
{ "cdtr", 0xe4, INSTR_RRE_FF },
{ "eedtr", 0xe5, INSTR_RRE_RF },
{ "esdtr", 0xe7, INSTR_RRE_RF },
{ "kxtr", 0xe8, INSTR_RRE_FF },
{ { 0, LONG_INSN_CGXTRA }, 0xe9, INSTR_RRF_UUFR },
{ "cuxtr", 0xea, INSTR_RRE_RF },
{ "csxtr", 0xeb, INSTR_RRE_RF },
{ "cxtr", 0xec, INSTR_RRE_FF },
{ "eextr", 0xed, INSTR_RRE_RF },
{ "esxtr", 0xef, INSTR_RRE_RF },
{ { 0, LONG_INSN_CDGTRA }, 0xf1, INSTR_RRF_UUFR },
{ "cdutr", 0xf2, INSTR_RRE_FR },
{ "cdstr", 0xf3, INSTR_RRE_FR },
{ "cedtr", 0xf4, INSTR_RRE_FF },
{ "qadtr", 0xf5, INSTR_RRF_FUFF },
{ "iedtr", 0xf6, INSTR_RRF_F0FR },
{ "rrdtr", 0xf7, INSTR_RRF_FFRU },
{ { 0, LONG_INSN_CXGTRA }, 0xf9, INSTR_RRF_UURF },
{ "cxutr", 0xfa, INSTR_RRE_FR },
{ "cxstr", 0xfb, INSTR_RRE_FR },
{ "cextr", 0xfc, INSTR_RRE_FF },
{ "qaxtr", 0xfd, INSTR_RRF_FUFF },
{ "iextr", 0xfe, INSTR_RRF_F0FR },
{ "rrxtr", 0xff, INSTR_RRF_FFRU },
{ "lpebr", 0x00, INSTR_RRE_FF },
{ "lnebr", 0x01, INSTR_RRE_FF },
{ "ltebr", 0x02, INSTR_RRE_FF },
{ "lcebr", 0x03, INSTR_RRE_FF },
{ "ldebr", 0x04, INSTR_RRE_FF },
{ "lxdbr", 0x05, INSTR_RRE_FF },
{ "lxebr", 0x06, INSTR_RRE_FF },
{ "mxdbr", 0x07, INSTR_RRE_FF },
{ "kebr", 0x08, INSTR_RRE_FF },
{ "cebr", 0x09, INSTR_RRE_FF },
{ "aebr", 0x0a, INSTR_RRE_FF },
{ "sebr", 0x0b, INSTR_RRE_FF },
{ "mdebr", 0x0c, INSTR_RRE_FF },
{ "debr", 0x0d, INSTR_RRE_FF },
{ "maebr", 0x0e, INSTR_RRF_F0FF },
{ "msebr", 0x0f, INSTR_RRF_F0FF },
{ "lpdbr", 0x10, INSTR_RRE_FF },
{ "lndbr", 0x11, INSTR_RRE_FF },
{ "ltdbr", 0x12, INSTR_RRE_FF },
{ "lcdbr", 0x13, INSTR_RRE_FF },
{ "sqebr", 0x14, INSTR_RRE_FF },
{ "sqdbr", 0x15, INSTR_RRE_FF },
{ "sqxbr", 0x16, INSTR_RRE_FF },
{ "meebr", 0x17, INSTR_RRE_FF },
{ "kdbr", 0x18, INSTR_RRE_FF },
{ "cdbr", 0x19, INSTR_RRE_FF },
{ "adbr", 0x1a, INSTR_RRE_FF },
{ "sdbr", 0x1b, INSTR_RRE_FF },
{ "mdbr", 0x1c, INSTR_RRE_FF },
{ "ddbr", 0x1d, INSTR_RRE_FF },
{ "madbr", 0x1e, INSTR_RRF_F0FF },
{ "msdbr", 0x1f, INSTR_RRF_F0FF },
{ "lder", 0x24, INSTR_RRE_FF },
{ "lxdr", 0x25, INSTR_RRE_FF },
{ "lxer", 0x26, INSTR_RRE_FF },
{ "maer", 0x2e, INSTR_RRF_F0FF },
{ "mser", 0x2f, INSTR_RRF_F0FF },
{ "sqxr", 0x36, INSTR_RRE_FF },
{ "meer", 0x37, INSTR_RRE_FF },
{ "madr", 0x3e, INSTR_RRF_F0FF },
{ "msdr", 0x3f, INSTR_RRF_F0FF },
{ "lpxbr", 0x40, INSTR_RRE_FF },
{ "lnxbr", 0x41, INSTR_RRE_FF },
{ "ltxbr", 0x42, INSTR_RRE_FF },
{ "lcxbr", 0x43, INSTR_RRE_FF },
{ { 0, LONG_INSN_LEDBRA }, 0x44, INSTR_RRF_UUFF },
{ { 0, LONG_INSN_LDXBRA }, 0x45, INSTR_RRF_UUFF },
{ { 0, LONG_INSN_LEXBRA }, 0x46, INSTR_RRF_UUFF },
{ { 0, LONG_INSN_FIXBRA }, 0x47, INSTR_RRF_UUFF },
{ "kxbr", 0x48, INSTR_RRE_FF },
{ "cxbr", 0x49, INSTR_RRE_FF },
{ "axbr", 0x4a, INSTR_RRE_FF },
{ "sxbr", 0x4b, INSTR_RRE_FF },
{ "mxbr", 0x4c, INSTR_RRE_FF },
{ "dxbr", 0x4d, INSTR_RRE_FF },
{ "tbedr", 0x50, INSTR_RRF_U0FF },
{ "tbdr", 0x51, INSTR_RRF_U0FF },
{ "diebr", 0x53, INSTR_RRF_FUFF },
{ { 0, LONG_INSN_FIEBRA }, 0x57, INSTR_RRF_UUFF },
{ "thder", 0x58, INSTR_RRE_FF },
{ "thdr", 0x59, INSTR_RRE_FF },
{ "didbr", 0x5b, INSTR_RRF_FUFF },
{ { 0, LONG_INSN_FIDBRA }, 0x5f, INSTR_RRF_UUFF },
{ "lpxr", 0x60, INSTR_RRE_FF },
{ "lnxr", 0x61, INSTR_RRE_FF },
{ "ltxr", 0x62, INSTR_RRE_FF },
{ "lcxr", 0x63, INSTR_RRE_FF },
{ "lxr", 0x65, INSTR_RRE_FF },
{ "lexr", 0x66, INSTR_RRE_FF },
{ "fixr", 0x67, INSTR_RRE_FF },
{ "cxr", 0x69, INSTR_RRE_FF },
{ "lzer", 0x74, INSTR_RRE_F0 },
{ "lzdr", 0x75, INSTR_RRE_F0 },
{ "lzxr", 0x76, INSTR_RRE_F0 },
{ "fier", 0x77, INSTR_RRE_FF },
{ "fidr", 0x7f, INSTR_RRE_FF },
{ "sfpc", 0x84, INSTR_RRE_RR_OPT },
{ "efpc", 0x8c, INSTR_RRE_RR_OPT },
{ "cefr", 0xb4, INSTR_RRE_FR },
{ "cdfr", 0xb5, INSTR_RRE_FR },
{ "cxfr", 0xb6, INSTR_RRE_FR },
{ "cfer", 0xb8, INSTR_RRF_U0RF },
{ "cfdr", 0xb9, INSTR_RRF_U0RF },
{ "cfxr", 0xba, INSTR_RRF_U0RF },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_b9[] = {
{ "lpgr", 0x00, INSTR_RRE_RR },
{ "lngr", 0x01, INSTR_RRE_RR },
{ "ltgr", 0x02, INSTR_RRE_RR },
{ "lcgr", 0x03, INSTR_RRE_RR },
{ "lgr", 0x04, INSTR_RRE_RR },
{ "lurag", 0x05, INSTR_RRE_RR },
{ "lgbr", 0x06, INSTR_RRE_RR },
{ "lghr", 0x07, INSTR_RRE_RR },
{ "agr", 0x08, INSTR_RRE_RR },
{ "sgr", 0x09, INSTR_RRE_RR },
{ "algr", 0x0a, INSTR_RRE_RR },
{ "slgr", 0x0b, INSTR_RRE_RR },
{ "msgr", 0x0c, INSTR_RRE_RR },
{ "dsgr", 0x0d, INSTR_RRE_RR },
{ "eregg", 0x0e, INSTR_RRE_RR },
{ "lrvgr", 0x0f, INSTR_RRE_RR },
{ "lpgfr", 0x10, INSTR_RRE_RR },
{ "lngfr", 0x11, INSTR_RRE_RR },
{ "ltgfr", 0x12, INSTR_RRE_RR },
{ "lcgfr", 0x13, INSTR_RRE_RR },
{ "lgfr", 0x14, INSTR_RRE_RR },
{ "llgfr", 0x16, INSTR_RRE_RR },
{ "llgtr", 0x17, INSTR_RRE_RR },
{ "agfr", 0x18, INSTR_RRE_RR },
{ "sgfr", 0x19, INSTR_RRE_RR },
{ "algfr", 0x1a, INSTR_RRE_RR },
{ "slgfr", 0x1b, INSTR_RRE_RR },
{ "msgfr", 0x1c, INSTR_RRE_RR },
{ "dsgfr", 0x1d, INSTR_RRE_RR },
{ "cgr", 0x20, INSTR_RRE_RR },
{ "clgr", 0x21, INSTR_RRE_RR },
{ "sturg", 0x25, INSTR_RRE_RR },
{ "lbr", 0x26, INSTR_RRE_RR },
{ "lhr", 0x27, INSTR_RRE_RR },
{ "kma", 0x29, INSTR_RRF_R0RR },
{ "cgfr", 0x30, INSTR_RRE_RR },
{ "clgfr", 0x31, INSTR_RRE_RR },
{ "ppno", 0x3c, INSTR_RRE_RR },
{ "cfdtr", 0x41, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLGDTR }, 0x42, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLFDTR }, 0x43, INSTR_RRF_UURF },
{ "bctgr", 0x46, INSTR_RRE_RR },
{ "cfxtr", 0x49, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CLGXTR }, 0x4a, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CLFXTR }, 0x4b, INSTR_RRF_UUFR },
{ "cdftr", 0x51, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDLGTR }, 0x52, INSTR_RRF_UUFR },
{ { 0, LONG_INSN_CDLFTR }, 0x53, INSTR_RRF_UUFR },
{ "cxftr", 0x59, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CXLGTR }, 0x5a, INSTR_RRF_UURF },
{ { 0, LONG_INSN_CXLFTR }, 0x5b, INSTR_RRF_UUFR },
{ "cgrt", 0x60, INSTR_RRF_U0RR },
{ "clgrt", 0x61, INSTR_RRF_U0RR },
{ "crt", 0x72, INSTR_RRF_U0RR },
{ "clrt", 0x73, INSTR_RRF_U0RR },
{ "ngr", 0x80, INSTR_RRE_RR },
{ "ogr", 0x81, INSTR_RRE_RR },
{ "xgr", 0x82, INSTR_RRE_RR },
{ "flogr", 0x83, INSTR_RRE_RR },
{ "llgcr", 0x84, INSTR_RRE_RR },
{ "llghr", 0x85, INSTR_RRE_RR },
{ "mlgr", 0x86, INSTR_RRE_RR },
{ "dlgr", 0x87, INSTR_RRE_RR },
{ "alcgr", 0x88, INSTR_RRE_RR },
{ "slbgr", 0x89, INSTR_RRE_RR },
{ "cspg", 0x8a, INSTR_RRE_RR },
{ "idte", 0x8e, INSTR_RRF_R0RR },
{ "crdte", 0x8f, INSTR_RRF_RMRR },
{ "llcr", 0x94, INSTR_RRE_RR },
{ "llhr", 0x95, INSTR_RRE_RR },
{ "esea", 0x9d, INSTR_RRE_R0 },
{ "ptf", 0xa2, INSTR_RRE_R0 },
{ "lptea", 0xaa, INSTR_RRF_RURR },
{ "rrbm", 0xae, INSTR_RRE_RR },
{ "pfmf", 0xaf, INSTR_RRE_RR },
{ "cu14", 0xb0, INSTR_RRF_M0RR },
{ "cu24", 0xb1, INSTR_RRF_M0RR },
{ "cu41", 0xb2, INSTR_RRE_RR },
{ "cu42", 0xb3, INSTR_RRE_RR },
{ "trtre", 0xbd, INSTR_RRF_M0RR },
{ "srstu", 0xbe, INSTR_RRE_RR },
{ "trte", 0xbf, INSTR_RRF_M0RR },
{ "ahhhr", 0xc8, INSTR_RRF_R0RR2 },
{ "shhhr", 0xc9, INSTR_RRF_R0RR2 },
{ { 0, LONG_INSN_ALHHHR }, 0xca, INSTR_RRF_R0RR2 },
{ { 0, LONG_INSN_SLHHHR }, 0xcb, INSTR_RRF_R0RR2 },
{ "chhr", 0xcd, INSTR_RRE_RR },
{ "clhhr", 0xcf, INSTR_RRE_RR },
{ { 0, LONG_INSN_PCISTG }, 0xd0, INSTR_RRE_RR },
{ "pcilg", 0xd2, INSTR_RRE_RR },
{ "rpcit", 0xd3, INSTR_RRE_RR },
{ "ahhlr", 0xd8, INSTR_RRF_R0RR2 },
{ "shhlr", 0xd9, INSTR_RRF_R0RR2 },
{ { 0, LONG_INSN_ALHHLR }, 0xda, INSTR_RRF_R0RR2 },
{ { 0, LONG_INSN_SLHHLR }, 0xdb, INSTR_RRF_R0RR2 },
{ "chlr", 0xdd, INSTR_RRE_RR },
{ "clhlr", 0xdf, INSTR_RRE_RR },
{ { 0, LONG_INSN_LOCFHR }, 0xe0, INSTR_RRF_U0RR },
{ { 0, LONG_INSN_POPCNT }, 0xe1, INSTR_RRE_RR },
{ "locgr", 0xe2, INSTR_RRF_M0RR },
{ "ngrk", 0xe4, INSTR_RRF_R0RR2 },
{ "ogrk", 0xe6, INSTR_RRF_R0RR2 },
{ "xgrk", 0xe7, INSTR_RRF_R0RR2 },
{ "agrk", 0xe8, INSTR_RRF_R0RR2 },
{ "sgrk", 0xe9, INSTR_RRF_R0RR2 },
{ "algrk", 0xea, INSTR_RRF_R0RR2 },
{ "slgrk", 0xeb, INSTR_RRF_R0RR2 },
{ "mgrk", 0xec, INSTR_RRF_R0RR2 },
{ { 0, LONG_INSN_MSGRKC }, 0xed, INSTR_RRF_R0RR2 },
{ "locr", 0xf2, INSTR_RRF_M0RR },
{ "nrk", 0xf4, INSTR_RRF_R0RR2 },
{ "ork", 0xf6, INSTR_RRF_R0RR2 },
{ "xrk", 0xf7, INSTR_RRF_R0RR2 },
{ "ark", 0xf8, INSTR_RRF_R0RR2 },
{ "srk", 0xf9, INSTR_RRF_R0RR2 },
{ "alrk", 0xfa, INSTR_RRF_R0RR2 },
{ "slrk", 0xfb, INSTR_RRF_R0RR2 },
{ "msrkc", 0xfd, INSTR_RRF_R0RR2 },
{ "kmac", 0x1e, INSTR_RRE_RR },
{ "lrvr", 0x1f, INSTR_RRE_RR },
{ "km", 0x2e, INSTR_RRE_RR },
{ "kmc", 0x2f, INSTR_RRE_RR },
{ "kimd", 0x3e, INSTR_RRE_RR },
{ "klmd", 0x3f, INSTR_RRE_RR },
{ "epsw", 0x8d, INSTR_RRE_RR },
{ "trtt", 0x90, INSTR_RRF_M0RR },
{ "trto", 0x91, INSTR_RRF_M0RR },
{ "trot", 0x92, INSTR_RRF_M0RR },
{ "troo", 0x93, INSTR_RRF_M0RR },
{ "mlr", 0x96, INSTR_RRE_RR },
{ "dlr", 0x97, INSTR_RRE_RR },
{ "alcr", 0x98, INSTR_RRE_RR },
{ "slbr", 0x99, INSTR_RRE_RR },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_c0[] = {
{ "lgfi", 0x01, INSTR_RIL_RI },
{ "xihf", 0x06, INSTR_RIL_RU },
{ "xilf", 0x07, INSTR_RIL_RU },
{ "iihf", 0x08, INSTR_RIL_RU },
{ "iilf", 0x09, INSTR_RIL_RU },
{ "nihf", 0x0a, INSTR_RIL_RU },
{ "nilf", 0x0b, INSTR_RIL_RU },
{ "oihf", 0x0c, INSTR_RIL_RU },
{ "oilf", 0x0d, INSTR_RIL_RU },
{ "llihf", 0x0e, INSTR_RIL_RU },
{ "llilf", 0x0f, INSTR_RIL_RU },
{ "larl", 0x00, INSTR_RIL_RP },
{ "brcl", 0x04, INSTR_RIL_UP },
{ "brasl", 0x05, INSTR_RIL_RP },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_c2[] = {
{ "msgfi", 0x00, INSTR_RIL_RI },
{ "msfi", 0x01, INSTR_RIL_RI },
{ "slgfi", 0x04, INSTR_RIL_RU },
{ "slfi", 0x05, INSTR_RIL_RU },
{ "agfi", 0x08, INSTR_RIL_RI },
{ "afi", 0x09, INSTR_RIL_RI },
{ "algfi", 0x0a, INSTR_RIL_RU },
{ "alfi", 0x0b, INSTR_RIL_RU },
{ "cgfi", 0x0c, INSTR_RIL_RI },
{ "cfi", 0x0d, INSTR_RIL_RI },
{ "clgfi", 0x0e, INSTR_RIL_RU },
{ "clfi", 0x0f, INSTR_RIL_RU },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_c4[] = {
{ "llhrl", 0x02, INSTR_RIL_RP },
{ "lghrl", 0x04, INSTR_RIL_RP },
{ "lhrl", 0x05, INSTR_RIL_RP },
{ { 0, LONG_INSN_LLGHRL }, 0x06, INSTR_RIL_RP },
{ "sthrl", 0x07, INSTR_RIL_RP },
{ "lgrl", 0x08, INSTR_RIL_RP },
{ "stgrl", 0x0b, INSTR_RIL_RP },
{ "lgfrl", 0x0c, INSTR_RIL_RP },
{ "lrl", 0x0d, INSTR_RIL_RP },
{ { 0, LONG_INSN_LLGFRL }, 0x0e, INSTR_RIL_RP },
{ "strl", 0x0f, INSTR_RIL_RP },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_c6[] = {
{ "exrl", 0x00, INSTR_RIL_RP },
{ "pfdrl", 0x02, INSTR_RIL_UP },
{ "cghrl", 0x04, INSTR_RIL_RP },
{ "chrl", 0x05, INSTR_RIL_RP },
{ { 0, LONG_INSN_CLGHRL }, 0x06, INSTR_RIL_RP },
{ "clhrl", 0x07, INSTR_RIL_RP },
{ "cgrl", 0x08, INSTR_RIL_RP },
{ "clgrl", 0x0a, INSTR_RIL_RP },
{ "cgfrl", 0x0c, INSTR_RIL_RP },
{ "crl", 0x0d, INSTR_RIL_RP },
{ { 0, LONG_INSN_CLGFRL }, 0x0e, INSTR_RIL_RP },
{ "clrl", 0x0f, INSTR_RIL_RP },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_c8[] = {
{ "mvcos", 0x00, INSTR_SSF_RRDRD },
{ "ectg", 0x01, INSTR_SSF_RRDRD },
{ "csst", 0x02, INSTR_SSF_RRDRD },
{ "lpd", 0x04, INSTR_SSF_RRDRD2 },
{ "lpdg", 0x05, INSTR_SSF_RRDRD2 },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_cc[] = {
{ "brcth", 0x06, INSTR_RIL_RP },
{ "aih", 0x08, INSTR_RIL_RI },
{ "alsih", 0x0a, INSTR_RIL_RI },
{ { 0, LONG_INSN_ALSIHN }, 0x0b, INSTR_RIL_RI },
{ "cih", 0x0d, INSTR_RIL_RI },
{ "clih", 0x0f, INSTR_RIL_RI },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_e3[] = {
{ "ltg", 0x02, INSTR_RXY_RRRD },
{ "lrag", 0x03, INSTR_RXY_RRRD },
{ "lg", 0x04, INSTR_RXY_RRRD },
{ "cvby", 0x06, INSTR_RXY_RRRD },
{ "ag", 0x08, INSTR_RXY_RRRD },
{ "sg", 0x09, INSTR_RXY_RRRD },
{ "alg", 0x0a, INSTR_RXY_RRRD },
{ "slg", 0x0b, INSTR_RXY_RRRD },
{ "msg", 0x0c, INSTR_RXY_RRRD },
{ "dsg", 0x0d, INSTR_RXY_RRRD },
{ "cvbg", 0x0e, INSTR_RXY_RRRD },
{ "lrvg", 0x0f, INSTR_RXY_RRRD },
{ "lt", 0x12, INSTR_RXY_RRRD },
{ "lray", 0x13, INSTR_RXY_RRRD },
{ "lgf", 0x14, INSTR_RXY_RRRD },
{ "lgh", 0x15, INSTR_RXY_RRRD },
{ "llgf", 0x16, INSTR_RXY_RRRD },
{ "llgt", 0x17, INSTR_RXY_RRRD },
{ "agf", 0x18, INSTR_RXY_RRRD },
{ "sgf", 0x19, INSTR_RXY_RRRD },
{ "algf", 0x1a, INSTR_RXY_RRRD },
{ "slgf", 0x1b, INSTR_RXY_RRRD },
{ "msgf", 0x1c, INSTR_RXY_RRRD },
{ "dsgf", 0x1d, INSTR_RXY_RRRD },
{ "cg", 0x20, INSTR_RXY_RRRD },
{ "clg", 0x21, INSTR_RXY_RRRD },
{ "stg", 0x24, INSTR_RXY_RRRD },
{ "ntstg", 0x25, INSTR_RXY_RRRD },
{ "cvdy", 0x26, INSTR_RXY_RRRD },
{ "lzrg", 0x2a, INSTR_RXY_RRRD },
{ "cvdg", 0x2e, INSTR_RXY_RRRD },
{ "strvg", 0x2f, INSTR_RXY_RRRD },
{ "cgf", 0x30, INSTR_RXY_RRRD },
{ "clgf", 0x31, INSTR_RXY_RRRD },
{ "ltgf", 0x32, INSTR_RXY_RRRD },
{ "cgh", 0x34, INSTR_RXY_RRRD },
{ "pfd", 0x36, INSTR_RXY_URRD },
{ "agh", 0x38, INSTR_RXY_RRRD },
{ "sgh", 0x39, INSTR_RXY_RRRD },
{ { 0, LONG_INSN_LLZRGF }, 0x3a, INSTR_RXY_RRRD },
{ "lzrf", 0x3b, INSTR_RXY_RRRD },
{ "mgh", 0x3c, INSTR_RXY_RRRD },
{ "strvh", 0x3f, INSTR_RXY_RRRD },
{ "bctg", 0x46, INSTR_RXY_RRRD },
{ "bic", 0x47, INSTR_RXY_URRD },
{ { 0, LONG_INSN_LLGFSG }, 0x48, INSTR_RXY_RRRD },
{ "stgsc", 0x49, INSTR_RXY_RRRD },
{ "lgg", 0x4c, INSTR_RXY_RRRD },
{ "lgsc", 0x4d, INSTR_RXY_RRRD },
{ "sty", 0x50, INSTR_RXY_RRRD },
{ "msy", 0x51, INSTR_RXY_RRRD },
{ "msc", 0x53, INSTR_RXY_RRRD },
{ "ny", 0x54, INSTR_RXY_RRRD },
{ "cly", 0x55, INSTR_RXY_RRRD },
{ "oy", 0x56, INSTR_RXY_RRRD },
{ "xy", 0x57, INSTR_RXY_RRRD },
{ "ly", 0x58, INSTR_RXY_RRRD },
{ "cy", 0x59, INSTR_RXY_RRRD },
{ "ay", 0x5a, INSTR_RXY_RRRD },
{ "sy", 0x5b, INSTR_RXY_RRRD },
{ "mfy", 0x5c, INSTR_RXY_RRRD },
{ "aly", 0x5e, INSTR_RXY_RRRD },
{ "sly", 0x5f, INSTR_RXY_RRRD },
{ "sthy", 0x70, INSTR_RXY_RRRD },
{ "lay", 0x71, INSTR_RXY_RRRD },
{ "stcy", 0x72, INSTR_RXY_RRRD },
{ "icy", 0x73, INSTR_RXY_RRRD },
{ "laey", 0x75, INSTR_RXY_RRRD },
{ "lb", 0x76, INSTR_RXY_RRRD },
{ "lgb", 0x77, INSTR_RXY_RRRD },
{ "lhy", 0x78, INSTR_RXY_RRRD },
{ "chy", 0x79, INSTR_RXY_RRRD },
{ "ahy", 0x7a, INSTR_RXY_RRRD },
{ "shy", 0x7b, INSTR_RXY_RRRD },
{ "mhy", 0x7c, INSTR_RXY_RRRD },
{ "ng", 0x80, INSTR_RXY_RRRD },
{ "og", 0x81, INSTR_RXY_RRRD },
{ "xg", 0x82, INSTR_RXY_RRRD },
{ "msgc", 0x83, INSTR_RXY_RRRD },
{ "mg", 0x84, INSTR_RXY_RRRD },
{ "lgat", 0x85, INSTR_RXY_RRRD },
{ "mlg", 0x86, INSTR_RXY_RRRD },
{ "dlg", 0x87, INSTR_RXY_RRRD },
{ "alcg", 0x88, INSTR_RXY_RRRD },
{ "slbg", 0x89, INSTR_RXY_RRRD },
{ "stpq", 0x8e, INSTR_RXY_RRRD },
{ "lpq", 0x8f, INSTR_RXY_RRRD },
{ "llgc", 0x90, INSTR_RXY_RRRD },
{ "llgh", 0x91, INSTR_RXY_RRRD },
{ "llc", 0x94, INSTR_RXY_RRRD },
{ "llh", 0x95, INSTR_RXY_RRRD },
{ { 0, LONG_INSN_LLGTAT }, 0x9c, INSTR_RXY_RRRD },
{ { 0, LONG_INSN_LLGFAT }, 0x9d, INSTR_RXY_RRRD },
{ "lat", 0x9f, INSTR_RXY_RRRD },
{ "lbh", 0xc0, INSTR_RXY_RRRD },
{ "llch", 0xc2, INSTR_RXY_RRRD },
{ "stch", 0xc3, INSTR_RXY_RRRD },
{ "lhh", 0xc4, INSTR_RXY_RRRD },
{ "llhh", 0xc6, INSTR_RXY_RRRD },
{ "sthh", 0xc7, INSTR_RXY_RRRD },
{ "lfhat", 0xc8, INSTR_RXY_RRRD },
{ "lfh", 0xca, INSTR_RXY_RRRD },
{ "stfh", 0xcb, INSTR_RXY_RRRD },
{ "chf", 0xcd, INSTR_RXY_RRRD },
{ "clhf", 0xcf, INSTR_RXY_RRRD },
{ { 0, LONG_INSN_MPCIFC }, 0xd0, INSTR_RXY_RRRD },
{ { 0, LONG_INSN_STPCIFC }, 0xd4, INSTR_RXY_RRRD },
{ "lrv", 0x1e, INSTR_RXY_RRRD },
{ "lrvh", 0x1f, INSTR_RXY_RRRD },
{ "strv", 0x3e, INSTR_RXY_RRRD },
{ "ml", 0x96, INSTR_RXY_RRRD },
{ "dl", 0x97, INSTR_RXY_RRRD },
{ "alc", 0x98, INSTR_RXY_RRRD },
{ "slb", 0x99, INSTR_RXY_RRRD },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_e5[] = {
{ "strag", 0x02, INSTR_SSE_RDRD },
{ "mvhhi", 0x44, INSTR_SIL_RDI },
{ "mvghi", 0x48, INSTR_SIL_RDI },
{ "mvhi", 0x4c, INSTR_SIL_RDI },
{ "chhsi", 0x54, INSTR_SIL_RDI },
{ { 0, LONG_INSN_CLHHSI }, 0x55, INSTR_SIL_RDU },
{ "cghsi", 0x58, INSTR_SIL_RDI },
{ { 0, LONG_INSN_CLGHSI }, 0x59, INSTR_SIL_RDU },
{ "chsi", 0x5c, INSTR_SIL_RDI },
{ { 0, LONG_INSN_CLFHSI }, 0x5d, INSTR_SIL_RDU },
{ { 0, LONG_INSN_TBEGIN }, 0x60, INSTR_SIL_RDU },
{ { 0, LONG_INSN_TBEGINC }, 0x61, INSTR_SIL_RDU },
{ "lasp", 0x00, INSTR_SSE_RDRD },
{ "tprot", 0x01, INSTR_SSE_RDRD },
{ "mvcsk", 0x0e, INSTR_SSE_RDRD },
{ "mvcdk", 0x0f, INSTR_SSE_RDRD },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_e6[] = {
{ "vpkz", 0x34, INSTR_VSI_URDV },
{ "vlrl", 0x35, INSTR_VSI_URDV },
{ "vlrlr", 0x37, INSTR_VRS_RRDV },
{ "vupkz", 0x3c, INSTR_VSI_URDV },
{ "vstrl", 0x3d, INSTR_VSI_URDV },
{ {0 , LONG_INSN_VSTRLR }, 0x3f, INSTR_VRS_RRDV },
{ "vlip", 0x49, INSTR_VRI_V0UU2 },
{ "vcvb", 0x50, INSTR_VRR_RV0U },
{ "vcvbg", 0x52, INSTR_VRR_RV0U },
{ "vcvd", 0x58, INSTR_VRI_VR0UU },
{ "vsrp", 0x59, INSTR_VRI_VVUUU2 },
{ "vcvdg", 0x5a, INSTR_VRI_VR0UU },
{ "vpsop", 0x5b, INSTR_VRI_VVUUU2 },
{ "vtp", 0x5f, INSTR_VRR_0V },
{ "vap", 0x71, INSTR_VRI_VVV0UU2 },
{ "vsp", 0x73, INSTR_VRI_VVV0UU2 },
{ "vcp", 0x77, INSTR_VRR_0VV0U },
{ "vmp", 0x78, INSTR_VRI_VVV0UU2 },
{ "vmsp", 0x79, INSTR_VRI_VVV0UU2 },
{ "vdp", 0x7a, INSTR_VRI_VVV0UU2 },
{ "vrp", 0x7b, INSTR_VRI_VVV0UU2 },
{ "vsdp", 0x7e, INSTR_VRI_VVV0UU2 },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_e7[] = {
{ "lcbb", 0x27, INSTR_RXE_RRRDM },
{ "vgef", 0x13, INSTR_VRV_VVRDM },
{ "vgeg", 0x12, INSTR_VRV_VVRDM },
{ "vgbm", 0x44, INSTR_VRI_V0I0 },
{ "vgm", 0x46, INSTR_VRI_V0IIM },
{ "vl", 0x06, INSTR_VRX_VRRD0 },
{ "vlr", 0x56, INSTR_VRR_VV00000 },
{ "vlrp", 0x05, INSTR_VRX_VRRDM },
{ "vleb", 0x00, INSTR_VRX_VRRDM },
{ "vleh", 0x01, INSTR_VRX_VRRDM },
{ "vlef", 0x03, INSTR_VRX_VRRDM },
{ "vleg", 0x02, INSTR_VRX_VRRDM },
{ "vleib", 0x40, INSTR_VRI_V0IM },
{ "vleih", 0x41, INSTR_VRI_V0IM },
{ "vleif", 0x43, INSTR_VRI_V0IM },
{ "vleig", 0x42, INSTR_VRI_V0IM },
{ "vlgv", 0x21, INSTR_VRS_RVRDM },
{ "vllez", 0x04, INSTR_VRX_VRRDM },
{ "vlm", 0x36, INSTR_VRS_VVRD0 },
{ "vlbb", 0x07, INSTR_VRX_VRRDM },
{ "vlvg", 0x22, INSTR_VRS_VRRDM },
{ "vlvgp", 0x62, INSTR_VRR_VRR0000 },
{ "vll", 0x37, INSTR_VRS_VRRD0 },
{ "vmrh", 0x61, INSTR_VRR_VVV000M },
{ "vmrl", 0x60, INSTR_VRR_VVV000M },
{ "vpk", 0x94, INSTR_VRR_VVV000M },
{ "vpks", 0x97, INSTR_VRR_VVV0M0M },
{ "vpkls", 0x95, INSTR_VRR_VVV0M0M },
{ "vperm", 0x8c, INSTR_VRR_VVV000V },
{ "vpdi", 0x84, INSTR_VRR_VVV000M },
{ "vrep", 0x4d, INSTR_VRI_VVIM },
{ "vrepi", 0x45, INSTR_VRI_V0IM },
{ "vscef", 0x1b, INSTR_VRV_VWRDM },
{ "vsceg", 0x1a, INSTR_VRV_VWRDM },
{ "vsel", 0x8d, INSTR_VRR_VVV000V },
{ "vseg", 0x5f, INSTR_VRR_VV0000M },
{ "vst", 0x0e, INSTR_VRX_VRRD0 },
{ "vsteb", 0x08, INSTR_VRX_VRRDM },
{ "vsteh", 0x09, INSTR_VRX_VRRDM },
{ "vstef", 0x0b, INSTR_VRX_VRRDM },
{ "vsteg", 0x0a, INSTR_VRX_VRRDM },
{ "vstm", 0x3e, INSTR_VRS_VVRD0 },
{ "vstl", 0x3f, INSTR_VRS_VRRD0 },
{ "vuph", 0xd7, INSTR_VRR_VV0000M },
{ "vuplh", 0xd5, INSTR_VRR_VV0000M },
{ "vupl", 0xd6, INSTR_VRR_VV0000M },
{ "vupll", 0xd4, INSTR_VRR_VV0000M },
{ "va", 0xf3, INSTR_VRR_VVV000M },
{ "vacc", 0xf1, INSTR_VRR_VVV000M },
{ "vac", 0xbb, INSTR_VRR_VVVM00V },
{ "vaccc", 0xb9, INSTR_VRR_VVVM00V },
{ "vn", 0x68, INSTR_VRR_VVV0000 },
{ "vnc", 0x69, INSTR_VRR_VVV0000 },
{ "vavg", 0xf2, INSTR_VRR_VVV000M },
{ "vavgl", 0xf0, INSTR_VRR_VVV000M },
{ "vcksm", 0x66, INSTR_VRR_VVV0000 },
{ "vec", 0xdb, INSTR_VRR_VV0000M },
{ "vecl", 0xd9, INSTR_VRR_VV0000M },
{ "vceq", 0xf8, INSTR_VRR_VVV0M0M },
{ "vch", 0xfb, INSTR_VRR_VVV0M0M },
{ "vchl", 0xf9, INSTR_VRR_VVV0M0M },
{ "vclz", 0x53, INSTR_VRR_VV0000M },
{ "vctz", 0x52, INSTR_VRR_VV0000M },
{ "vx", 0x6d, INSTR_VRR_VVV0000 },
{ "vgfm", 0xb4, INSTR_VRR_VVV000M },
{ "vgfma", 0xbc, INSTR_VRR_VVVM00V },
{ "vlc", 0xde, INSTR_VRR_VV0000M },
{ "vlp", 0xdf, INSTR_VRR_VV0000M },
{ "vmx", 0xff, INSTR_VRR_VVV000M },
{ "vmxl", 0xfd, INSTR_VRR_VVV000M },
{ "vmn", 0xfe, INSTR_VRR_VVV000M },
{ "vmnl", 0xfc, INSTR_VRR_VVV000M },
{ "vmal", 0xaa, INSTR_VRR_VVVM00V },
{ "vmae", 0xae, INSTR_VRR_VVVM00V },
{ "vmale", 0xac, INSTR_VRR_VVVM00V },
{ "vmah", 0xab, INSTR_VRR_VVVM00V },
{ "vmalh", 0xa9, INSTR_VRR_VVVM00V },
{ "vmao", 0xaf, INSTR_VRR_VVVM00V },
{ "vmalo", 0xad, INSTR_VRR_VVVM00V },
{ "vmh", 0xa3, INSTR_VRR_VVV000M },
{ "vmlh", 0xa1, INSTR_VRR_VVV000M },
{ "vml", 0xa2, INSTR_VRR_VVV000M },
{ "vme", 0xa6, INSTR_VRR_VVV000M },
{ "vmle", 0xa4, INSTR_VRR_VVV000M },
{ "vmo", 0xa7, INSTR_VRR_VVV000M },
{ "vmlo", 0xa5, INSTR_VRR_VVV000M },
{ "vno", 0x6b, INSTR_VRR_VVV0000 },
{ "vo", 0x6a, INSTR_VRR_VVV0000 },
{ { 0, LONG_INSN_VPOPCT }, 0x50, INSTR_VRR_VV0000M },
{ { 0, LONG_INSN_VERLLV }, 0x73, INSTR_VRR_VVV000M },
{ "verll", 0x33, INSTR_VRS_VVRDM },
{ "verim", 0x72, INSTR_VRI_VVV0IM },
{ "veslv", 0x70, INSTR_VRR_VVV000M },
{ "vesl", 0x30, INSTR_VRS_VVRDM },
{ { 0, LONG_INSN_VESRAV }, 0x7a, INSTR_VRR_VVV000M },
{ "vesra", 0x3a, INSTR_VRS_VVRDM },
{ { 0, LONG_INSN_VESRLV }, 0x78, INSTR_VRR_VVV000M },
{ "vesrl", 0x38, INSTR_VRS_VVRDM },
{ "vsl", 0x74, INSTR_VRR_VVV0000 },
{ "vslb", 0x75, INSTR_VRR_VVV0000 },
{ "vsldb", 0x77, INSTR_VRI_VVV0I0 },
{ "vsra", 0x7e, INSTR_VRR_VVV0000 },
{ "vsrab", 0x7f, INSTR_VRR_VVV0000 },
{ "vsrl", 0x7c, INSTR_VRR_VVV0000 },
{ "vsrlb", 0x7d, INSTR_VRR_VVV0000 },
{ "vs", 0xf7, INSTR_VRR_VVV000M },
{ "vscb", 0xf5, INSTR_VRR_VVV000M },
{ "vsb", 0xbf, INSTR_VRR_VVVM00V },
{ { 0, LONG_INSN_VSBCBI }, 0xbd, INSTR_VRR_VVVM00V },
{ "vsumg", 0x65, INSTR_VRR_VVV000M },
{ "vsumq", 0x67, INSTR_VRR_VVV000M },
{ "vsum", 0x64, INSTR_VRR_VVV000M },
{ "vtm", 0xd8, INSTR_VRR_VV00000 },
{ "vfae", 0x82, INSTR_VRR_VVV0M0M },
{ "vfee", 0x80, INSTR_VRR_VVV0M0M },
{ "vfene", 0x81, INSTR_VRR_VVV0M0M },
{ "vistr", 0x5c, INSTR_VRR_VV00M0M },
{ "vstrc", 0x8a, INSTR_VRR_VVVMM0V },
{ "vfa", 0xe3, INSTR_VRR_VVV00MM },
{ "wfc", 0xcb, INSTR_VRR_VV000MM },
{ "wfk", 0xca, INSTR_VRR_VV000MM },
{ "vfce", 0xe8, INSTR_VRR_VVV0MMM },
{ "vfch", 0xeb, INSTR_VRR_VVV0MMM },
{ "vfche", 0xea, INSTR_VRR_VVV0MMM },
{ "vcdg", 0xc3, INSTR_VRR_VV00MMM },
{ "vcdlg", 0xc1, INSTR_VRR_VV00MMM },
{ "vcgd", 0xc2, INSTR_VRR_VV00MMM },
{ "vclgd", 0xc0, INSTR_VRR_VV00MMM },
{ "vfd", 0xe5, INSTR_VRR_VVV00MM },
{ "vfi", 0xc7, INSTR_VRR_VV00MMM },
{ "vlde", 0xc4, INSTR_VRR_VV000MM },
{ "vled", 0xc5, INSTR_VRR_VV00MMM },
{ "vfm", 0xe7, INSTR_VRR_VVV00MM },
{ "vfma", 0x8f, INSTR_VRR_VVVM0MV },
{ "vfms", 0x8e, INSTR_VRR_VVVM0MV },
{ "vfpso", 0xcc, INSTR_VRR_VV00MMM },
{ "vfsq", 0xce, INSTR_VRR_VV000MM },
{ "vfs", 0xe2, INSTR_VRR_VVV00MM },
{ "vftci", 0x4a, INSTR_VRI_VVIMM },
{ "vnx", 0x6c, INSTR_VRR_VVV },
{ "vnn", 0x6e, INSTR_VRR_VVV },
{ "voc", 0x6f, INSTR_VRR_VVV },
{ { 0, LONG_INSN_VBPERM }, 0x85, INSTR_VRR_VVV },
{ "vfnms", 0x9e, INSTR_VRR_VVVU0UV },
{ "vfnma", 0x9f, INSTR_VRR_VVVU0UV },
{ "vmsl", 0xb8, INSTR_VRR_VVVUU0V },
{ "vfmin", 0xee, INSTR_VRR_VVV0UUU },
{ "vfmax", 0xef, INSTR_VRR_VVV0UUU },
{ "", 0, INSTR_INVALID }
};
static struct s390_insn opcode_eb[] = {
{ "lmg", 0x04, INSTR_RSY_RRRD },
{ "srag", 0x0a, INSTR_RSY_RRRD },
{ "slag", 0x0b, INSTR_RSY_RRRD },
{ "srlg", 0x0c, INSTR_RSY_RRRD },
{ "sllg", 0x0d, INSTR_RSY_RRRD },
{ "tracg", 0x0f, INSTR_RSY_RRRD },
{ "csy", 0x14, INSTR_RSY_RRRD },
{ "rllg", 0x1c, INSTR_RSY_RRRD },
{ "clmh", 0x20, INSTR_RSY_RURD },
{ "clmy", 0x21, INSTR_RSY_RURD },
{ "clt", 0x23, INSTR_RSY_RURD },
{ "stmg", 0x24, INSTR_RSY_RRRD },
{ "stctg", 0x25, INSTR_RSY_CCRD },
{ "stmh", 0x26, INSTR_RSY_RRRD },
{ "clgt", 0x2b, INSTR_RSY_RURD },
{ "stcmh", 0x2c, INSTR_RSY_RURD },
{ "stcmy", 0x2d, INSTR_RSY_RURD },
{ "lctlg", 0x2f, INSTR_RSY_CCRD },
{ "csg", 0x30, INSTR_RSY_RRRD },
{ "cdsy", 0x31, INSTR_RSY_RRRD },
{ "cdsg", 0x3e, INSTR_RSY_RRRD },
{ "bxhg", 0x44, INSTR_RSY_RRRD },
{ "bxleg", 0x45, INSTR_RSY_RRRD },
{ "ecag", 0x4c, INSTR_RSY_RRRD },
{ "tmy", 0x51, INSTR_SIY_URD },
{ "mviy", 0x52, INSTR_SIY_URD },
{ "niy", 0x54, INSTR_SIY_URD },
{ "cliy", 0x55, INSTR_SIY_URD },
{ "oiy", 0x56, INSTR_SIY_URD },
{ "xiy", 0x57, INSTR_SIY_URD },
{ "asi", 0x6a, INSTR_SIY_IRD },
{ "alsi", 0x6e, INSTR_SIY_IRD },
{ "agsi", 0x7a, INSTR_SIY_IRD },
{ "algsi", 0x7e, INSTR_SIY_IRD },
{ "icmh", 0x80, INSTR_RSY_RURD },
{ "icmy", 0x81, INSTR_RSY_RURD },
{ "clclu", 0x8f, INSTR_RSY_RRRD },
{ "stmy", 0x90, INSTR_RSY_RRRD },
{ "lmh", 0x96, INSTR_RSY_RRRD },
{ "lmy", 0x98, INSTR_RSY_RRRD },
{ "lamy", 0x9a, INSTR_RSY_AARD },
{ "stamy", 0x9b, INSTR_RSY_AARD },
{ { 0, LONG_INSN_PCISTB }, 0xd0, INSTR_RSY_RRRD },
{ "sic", 0xd1, INSTR_RSY_RRRD },
{ "srak", 0xdc, INSTR_RSY_RRRD },
{ "slak", 0xdd, INSTR_RSY_RRRD },
{ "srlk", 0xde, INSTR_RSY_RRRD },
{ "sllk", 0xdf, INSTR_RSY_RRRD },
{ "locfh", 0xe0, INSTR_RSY_RURD2 },
{ { 0, LONG_INSN_STOCFH }, 0xe1, INSTR_RSY_RURD2 },
{ "locg", 0xe2, INSTR_RSY_RDRM },
{ "stocg", 0xe3, INSTR_RSY_RDRM },
{ "lang", 0xe4, INSTR_RSY_RRRD },
{ "laog", 0xe6, INSTR_RSY_RRRD },
{ "laxg", 0xe7, INSTR_RSY_RRRD },
{ "laag", 0xe8, INSTR_RSY_RRRD },
{ "laalg", 0xea, INSTR_RSY_RRRD },
{ "loc", 0xf2, INSTR_RSY_RDRM },
{ "stoc", 0xf3, INSTR_RSY_RDRM },
{ "lan", 0xf4, INSTR_RSY_RRRD },
{ "lao", 0xf6, INSTR_RSY_RRRD },
{ "lax", 0xf7, INSTR_RSY_RRRD },
{ "laa", 0xf8, INSTR_RSY_RRRD },
{ "laal", 0xfa, INSTR_RSY_RRRD },
{ "lric", 0x60, INSTR_RSY_RDRM },
{ "stric", 0x61, INSTR_RSY_RDRM },
{ "mric", 0x62, INSTR_RSY_RDRM },
{ { 0, LONG_INSN_STCCTM }, 0x17, INSTR_RSY_RMRD },
{ "rll", 0x1d, INSTR_RSY_RRRD },
{ "mvclu", 0x8e, INSTR_RSY_RRRD },
{ "tp", 0xc0, INSTR_RSL_R0RD },
{ "", 0, INSTR_INVALID }
[VX_12] = { 4, 12, OPERAND_INDEX | OPERAND_VR },
[V_8] = { 4, 8, OPERAND_VR },
[V_12] = { 4, 12, OPERAND_VR },
[V_16] = { 4, 16, OPERAND_VR },
[V_32] = { 4, 32, OPERAND_VR },
[X_12] = { 4, 12, OPERAND_INDEX | OPERAND_GPR },
};
static struct s390_insn opcode_ec[] = {
{ "lochi", 0x42, INSTR_RIE_RUI0 },
{ "brxhg", 0x44, INSTR_RIE_RRP },
{ "brxlg", 0x45, INSTR_RIE_RRP },
{ { 0, LONG_INSN_LOCGHI }, 0x46, INSTR_RIE_RUI0 },
{ { 0, LONG_INSN_LOCHHI }, 0x4e, INSTR_RIE_RUI0 },
{ { 0, LONG_INSN_RISBLG }, 0x51, INSTR_RIE_RRUUU },
{ "rnsbg", 0x54, INSTR_RIE_RRUUU },
{ "risbg", 0x55, INSTR_RIE_RRUUU },
{ "rosbg", 0x56, INSTR_RIE_RRUUU },
{ "rxsbg", 0x57, INSTR_RIE_RRUUU },
{ { 0, LONG_INSN_RISBGN }, 0x59, INSTR_RIE_RRUUU },
{ { 0, LONG_INSN_RISBHG }, 0x5D, INSTR_RIE_RRUUU },
{ "cgrj", 0x64, INSTR_RIE_RRPU },
{ "clgrj", 0x65, INSTR_RIE_RRPU },
{ "cgit", 0x70, INSTR_RIE_R0IU },
{ "clgit", 0x71, INSTR_RIE_R0UU },
{ "cit", 0x72, INSTR_RIE_R0IU },
{ "clfit", 0x73, INSTR_RIE_R0UU },
{ "crj", 0x76, INSTR_RIE_RRPU },
{ "clrj", 0x77, INSTR_RIE_RRPU },
{ "cgij", 0x7c, INSTR_RIE_RUPI },
{ "clgij", 0x7d, INSTR_RIE_RUPU },
{ "cij", 0x7e, INSTR_RIE_RUPI },
{ "clij", 0x7f, INSTR_RIE_RUPU },
{ "ahik", 0xd8, INSTR_RIE_RRI0 },
{ "aghik", 0xd9, INSTR_RIE_RRI0 },
{ { 0, LONG_INSN_ALHSIK }, 0xda, INSTR_RIE_RRI0 },
{ { 0, LONG_INSN_ALGHSIK }, 0xdb, INSTR_RIE_RRI0 },
{ "cgrb", 0xe4, INSTR_RRS_RRRDU },
{ "clgrb", 0xe5, INSTR_RRS_RRRDU },
{ "crb", 0xf6, INSTR_RRS_RRRDU },
{ "clrb", 0xf7, INSTR_RRS_RRRDU },
{ "cgib", 0xfc, INSTR_RIS_RURDI },
{ "clgib", 0xfd, INSTR_RIS_RURDU },
{ "cib", 0xfe, INSTR_RIS_RURDI },
{ "clib", 0xff, INSTR_RIS_RURDU },
{ "", 0, INSTR_INVALID }
static const unsigned char formats[][6] = {
[INSTR_E] = { 0, 0, 0, 0, 0, 0 },
[INSTR_IE_UU] = { U4_24, U4_28, 0, 0, 0, 0 },
[INSTR_MII_UPP] = { U4_8, J12_12, J24_24 },
[INSTR_RIE_R0IU] = { R_8, I16_16, U4_32, 0, 0, 0 },
[INSTR_RIE_R0UU] = { R_8, U16_16, U4_32, 0, 0, 0 },
[INSTR_RIE_RRI0] = { R_8, R_12, I16_16, 0, 0, 0 },
[INSTR_RIE_RRP] = { R_8, R_12, J16_16, 0, 0, 0 },
[INSTR_RIE_RRPU] = { R_8, R_12, U4_32, J16_16, 0, 0 },
[INSTR_RIE_RRUUU] = { R_8, R_12, U8_16, U8_24, U8_32, 0 },
[INSTR_RIE_RUI0] = { R_8, I16_16, U4_12, 0, 0, 0 },
[INSTR_RIE_RUPI] = { R_8, I8_32, U4_12, J16_16, 0, 0 },
[INSTR_RIE_RUPU] = { R_8, U8_32, U4_12, J16_16, 0, 0 },
[INSTR_RIL_RI] = { R_8, I32_16, 0, 0, 0, 0 },
[INSTR_RIL_RP] = { R_8, J32_16, 0, 0, 0, 0 },
[INSTR_RIL_RU] = { R_8, U32_16, 0, 0, 0, 0 },
[INSTR_RIL_UP] = { U4_8, J32_16, 0, 0, 0, 0 },
[INSTR_RIS_RURDI] = { R_8, I8_32, U4_12, D_20, B_16, 0 },
[INSTR_RIS_RURDU] = { R_8, U8_32, U4_12, D_20, B_16, 0 },
[INSTR_RI_RI] = { R_8, I16_16, 0, 0, 0, 0 },
[INSTR_RI_RP] = { R_8, J16_16, 0, 0, 0, 0 },
[INSTR_RI_RU] = { R_8, U16_16, 0, 0, 0, 0 },
[INSTR_RI_UP] = { U4_8, J16_16, 0, 0, 0, 0 },
[INSTR_RRE_00] = { 0, 0, 0, 0, 0, 0 },
[INSTR_RRE_AA] = { A_24, A_28, 0, 0, 0, 0 },
[INSTR_RRE_AR] = { A_24, R_28, 0, 0, 0, 0 },
[INSTR_RRE_F0] = { F_24, 0, 0, 0, 0, 0 },
[INSTR_RRE_FF] = { F_24, F_28, 0, 0, 0, 0 },
[INSTR_RRE_FR] = { F_24, R_28, 0, 0, 0, 0 },
[INSTR_RRE_R0] = { R_24, 0, 0, 0, 0, 0 },
[INSTR_RRE_RA] = { R_24, A_28, 0, 0, 0, 0 },
[INSTR_RRE_RF] = { R_24, F_28, 0, 0, 0, 0 },
[INSTR_RRE_RR] = { R_24, R_28, 0, 0, 0, 0 },
[INSTR_RRF_0UFF] = { F_24, F_28, U4_20, 0, 0, 0 },
[INSTR_RRF_0URF] = { R_24, F_28, U4_20, 0, 0, 0 },
[INSTR_RRF_F0FF] = { F_16, F_24, F_28, 0, 0, 0 },
[INSTR_RRF_F0FF2] = { F_24, F_16, F_28, 0, 0, 0 },
[INSTR_RRF_F0FR] = { F_24, F_16, R_28, 0, 0, 0 },
[INSTR_RRF_FFRU] = { F_24, F_16, R_28, U4_20, 0, 0 },
[INSTR_RRF_FUFF] = { F_24, F_16, F_28, U4_20, 0, 0 },
[INSTR_RRF_FUFF2] = { F_24, F_28, F_16, U4_20, 0, 0 },
[INSTR_RRF_R0RR] = { R_24, R_16, R_28, 0, 0, 0 },
[INSTR_RRF_R0RR2] = { R_24, R_28, R_16, 0, 0, 0 },
[INSTR_RRF_RURR] = { R_24, R_28, R_16, U4_20, 0, 0 },
[INSTR_RRF_RURR2] = { R_24, R_16, R_28, U4_20, 0, 0 },
[INSTR_RRF_U0FF] = { F_24, U4_16, F_28, 0, 0, 0 },
[INSTR_RRF_U0RF] = { R_24, U4_16, F_28, 0, 0, 0 },
[INSTR_RRF_U0RR] = { R_24, R_28, U4_16, 0, 0, 0 },
[INSTR_RRF_UUFF] = { F_24, U4_16, F_28, U4_20, 0, 0 },
[INSTR_RRF_UUFR] = { F_24, U4_16, R_28, U4_20, 0, 0 },
[INSTR_RRF_UURF] = { R_24, U4_16, F_28, U4_20, 0, 0 },
[INSTR_RRS_RRRDU] = { R_8, R_12, U4_32, D_20, B_16 },
[INSTR_RR_FF] = { F_8, F_12, 0, 0, 0, 0 },
[INSTR_RR_R0] = { R_8, 0, 0, 0, 0, 0 },
[INSTR_RR_RR] = { R_8, R_12, 0, 0, 0, 0 },
[INSTR_RR_U0] = { U8_8, 0, 0, 0, 0, 0 },
[INSTR_RR_UR] = { U4_8, R_12, 0, 0, 0, 0 },
[INSTR_RSI_RRP] = { R_8, R_12, J16_16, 0, 0, 0 },
[INSTR_RSL_LRDFU] = { F_32, D_20, L8_8, B_16, U4_36, 0 },
[INSTR_RSL_R0RD] = { D_20, L4_8, B_16, 0, 0, 0 },
[INSTR_RSY_AARD] = { A_8, A_12, D20_20, B_16, 0, 0 },
[INSTR_RSY_CCRD] = { C_8, C_12, D20_20, B_16, 0, 0 },
[INSTR_RSY_RDRU] = { R_8, D20_20, B_16, U4_12, 0, 0 },
[INSTR_RSY_RRRD] = { R_8, R_12, D20_20, B_16, 0, 0 },
[INSTR_RSY_RURD] = { R_8, U4_12, D20_20, B_16, 0, 0 },
[INSTR_RSY_RURD2] = { R_8, D20_20, B_16, U4_12, 0, 0 },
[INSTR_RS_AARD] = { A_8, A_12, D_20, B_16, 0, 0 },
[INSTR_RS_CCRD] = { C_8, C_12, D_20, B_16, 0, 0 },
[INSTR_RS_R0RD] = { R_8, D_20, B_16, 0, 0, 0 },
[INSTR_RS_RRRD] = { R_8, R_12, D_20, B_16, 0, 0 },
[INSTR_RS_RURD] = { R_8, U4_12, D_20, B_16, 0, 0 },
[INSTR_RXE_FRRD] = { F_8, D_20, X_12, B_16, 0, 0 },
[INSTR_RXE_RRRDU] = { R_8, D_20, X_12, B_16, U4_32, 0 },
[INSTR_RXF_FRRDF] = { F_32, F_8, D_20, X_12, B_16, 0 },
[INSTR_RXY_FRRD] = { F_8, D20_20, X_12, B_16, 0, 0 },
[INSTR_RXY_RRRD] = { R_8, D20_20, X_12, B_16, 0, 0 },
[INSTR_RXY_URRD] = { U4_8, D20_20, X_12, B_16, 0, 0 },
[INSTR_RX_FRRD] = { F_8, D_20, X_12, B_16, 0, 0 },
[INSTR_RX_RRRD] = { R_8, D_20, X_12, B_16, 0, 0 },
[INSTR_RX_URRD] = { U4_8, D_20, X_12, B_16, 0, 0 },
[INSTR_SIL_RDI] = { D_20, B_16, I16_32, 0, 0, 0 },
[INSTR_SIL_RDU] = { D_20, B_16, U16_32, 0, 0, 0 },
[INSTR_SIY_IRD] = { D20_20, B_16, I8_8, 0, 0, 0 },
[INSTR_SIY_URD] = { D20_20, B_16, U8_8, 0, 0, 0 },
[INSTR_SI_RD] = { D_20, B_16, 0, 0, 0, 0 },
[INSTR_SI_URD] = { D_20, B_16, U8_8, 0, 0, 0 },
[INSTR_SMI_U0RDP] = { U4_8, J16_32, D_20, B_16, 0, 0 },
[INSTR_SSE_RDRD] = { D_20, B_16, D_36, B_32, 0, 0 },
[INSTR_SSF_RRDRD] = { D_20, B_16, D_36, B_32, R_8, 0 },
[INSTR_SSF_RRDRD2] = { R_8, D_20, B_16, D_36, B_32, 0 },
[INSTR_SS_L0RDRD] = { D_20, L8_8, B_16, D_36, B_32, 0 },
[INSTR_SS_L2RDRD] = { D_20, B_16, D_36, L8_8, B_32, 0 },
[INSTR_SS_LIRDRD] = { D_20, L4_8, B_16, D_36, B_32, U4_12 },
[INSTR_SS_LLRDRD] = { D_20, L4_8, B_16, D_36, L4_12, B_32 },
[INSTR_SS_RRRDRD] = { D_20, R_8, B_16, D_36, B_32, R_12 },
[INSTR_SS_RRRDRD2] = { R_8, D_20, B_16, R_12, D_36, B_32 },
[INSTR_SS_RRRDRD3] = { R_8, R_12, D_20, B_16, D_36, B_32 },
[INSTR_S_00] = { 0, 0, 0, 0, 0, 0 },
[INSTR_S_RD] = { D_20, B_16, 0, 0, 0, 0 },
[INSTR_VRI_V0IU] = { V_8, I16_16, U4_32, 0, 0, 0 },
[INSTR_VRI_V0U] = { V_8, U16_16, 0, 0, 0, 0 },
[INSTR_VRI_V0UU2] = { V_8, U16_16, U4_32, 0, 0, 0 },
[INSTR_VRI_V0UUU] = { V_8, U8_16, U8_24, U4_32, 0, 0 },
[INSTR_VRI_VR0UU] = { V_8, R_12, U8_28, U4_24, 0, 0 },
[INSTR_VRI_VVUU] = { V_8, V_12, U16_16, U4_32, 0, 0 },
[INSTR_VRI_VVUUU] = { V_8, V_12, U12_16, U4_32, U4_28, 0 },
[INSTR_VRI_VVUUU2] = { V_8, V_12, U8_28, U8_16, U4_24, 0 },
[INSTR_VRI_VVV0U] = { V_8, V_12, V_16, U8_24, 0, 0 },
[INSTR_VRI_VVV0UU] = { V_8, V_12, V_16, U8_24, U4_32, 0 },
[INSTR_VRI_VVV0UU2] = { V_8, V_12, V_16, U8_28, U4_24, 0 },
[INSTR_VRR_0V] = { V_12, 0, 0, 0, 0, 0 },
[INSTR_VRR_0VV0U] = { V_12, V_16, U4_24, 0, 0, 0 },
[INSTR_VRR_RV0U] = { R_8, V_12, U4_24, 0, 0, 0 },
[INSTR_VRR_VRR] = { V_8, R_12, R_16, 0, 0, 0 },
[INSTR_VRR_VV] = { V_8, V_12, 0, 0, 0, 0 },
[INSTR_VRR_VV0U] = { V_8, V_12, U4_32, 0, 0, 0 },
[INSTR_VRR_VV0U0U] = { V_8, V_12, U4_32, U4_24, 0, 0 },
[INSTR_VRR_VV0UU2] = { V_8, V_12, U4_32, U4_28, 0, 0 },
[INSTR_VRR_VV0UUU] = { V_8, V_12, U4_32, U4_28, U4_24, 0 },
[INSTR_VRR_VVV] = { V_8, V_12, V_16, 0, 0, 0 },
[INSTR_VRR_VVV0U] = { V_8, V_12, V_16, U4_32, 0, 0 },
[INSTR_VRR_VVV0U0U] = { V_8, V_12, V_16, U4_32, U4_24, 0 },
[INSTR_VRR_VVV0UU] = { V_8, V_12, V_16, U4_32, U4_28, 0 },
[INSTR_VRR_VVV0UUU] = { V_8, V_12, V_16, U4_32, U4_28, U4_24 },
[INSTR_VRR_VVV0V] = { V_8, V_12, V_16, V_32, 0, 0 },
[INSTR_VRR_VVVU0UV] = { V_8, V_12, V_16, V_32, U4_28, U4_20 },
[INSTR_VRR_VVVU0V] = { V_8, V_12, V_16, V_32, U4_20, 0 },
[INSTR_VRR_VVVUU0V] = { V_8, V_12, V_16, V_32, U4_20, U4_24 },
[INSTR_VRS_RRDV] = { V_32, R_12, D_20, B_16, 0, 0 },
[INSTR_VRS_RVRDU] = { R_8, V_12, D_20, B_16, U4_32, 0 },
[INSTR_VRS_VRRD] = { V_8, R_12, D_20, B_16, 0, 0 },
[INSTR_VRS_VRRDU] = { V_8, R_12, D_20, B_16, U4_32, 0 },
[INSTR_VRS_VVRD] = { V_8, V_12, D_20, B_16, 0, 0 },
[INSTR_VRS_VVRDU] = { V_8, V_12, D_20, B_16, U4_32, 0 },
[INSTR_VRV_VVXRDU] = { V_8, D_20, VX_12, B_16, U4_32, 0 },
[INSTR_VRX_VRRD] = { V_8, D_20, X_12, B_16, 0, 0 },
[INSTR_VRX_VRRDU] = { V_8, D_20, X_12, B_16, U4_32, 0 },
[INSTR_VRX_VV] = { V_8, V_12, 0, 0, 0, 0 },
[INSTR_VSI_URDV] = { V_32, D_20, B_16, U8_8, 0, 0 },
};
static struct s390_insn opcode_ed[] = {
{ "mayl", 0x38, INSTR_RXF_FRRDF },
{ "myl", 0x39, INSTR_RXF_FRRDF },
{ "may", 0x3a, INSTR_RXF_FRRDF },
{ "my", 0x3b, INSTR_RXF_FRRDF },
{ "mayh", 0x3c, INSTR_RXF_FRRDF },
{ "myh", 0x3d, INSTR_RXF_FRRDF },
{ "sldt", 0x40, INSTR_RXF_FRRDF },
{ "srdt", 0x41, INSTR_RXF_FRRDF },
{ "slxt", 0x48, INSTR_RXF_FRRDF },
{ "srxt", 0x49, INSTR_RXF_FRRDF },
{ "tdcet", 0x50, INSTR_RXE_FRRD },
{ "tdget", 0x51, INSTR_RXE_FRRD },
{ "tdcdt", 0x54, INSTR_RXE_FRRD },
{ "tdgdt", 0x55, INSTR_RXE_FRRD },
{ "tdcxt", 0x58, INSTR_RXE_FRRD },
{ "tdgxt", 0x59, INSTR_RXE_FRRD },
{ "ley", 0x64, INSTR_RXY_FRRD },
{ "ldy", 0x65, INSTR_RXY_FRRD },
{ "stey", 0x66, INSTR_RXY_FRRD },
{ "stdy", 0x67, INSTR_RXY_FRRD },
{ "czdt", 0xa8, INSTR_RSL_LRDFU },
{ "czxt", 0xa9, INSTR_RSL_LRDFU },
{ "cdzt", 0xaa, INSTR_RSL_LRDFU },
{ "cxzt", 0xab, INSTR_RSL_LRDFU },
{ "ldeb", 0x04, INSTR_RXE_FRRD },
{ "lxdb", 0x05, INSTR_RXE_FRRD },
{ "lxeb", 0x06, INSTR_RXE_FRRD },
{ "mxdb", 0x07, INSTR_RXE_FRRD },
{ "keb", 0x08, INSTR_RXE_FRRD },
{ "ceb", 0x09, INSTR_RXE_FRRD },
{ "aeb", 0x0a, INSTR_RXE_FRRD },
{ "seb", 0x0b, INSTR_RXE_FRRD },
{ "mdeb", 0x0c, INSTR_RXE_FRRD },
{ "deb", 0x0d, INSTR_RXE_FRRD },
{ "maeb", 0x0e, INSTR_RXF_FRRDF },
{ "mseb", 0x0f, INSTR_RXF_FRRDF },
{ "tceb", 0x10, INSTR_RXE_FRRD },
{ "tcdb", 0x11, INSTR_RXE_FRRD },
{ "tcxb", 0x12, INSTR_RXE_FRRD },
{ "sqeb", 0x14, INSTR_RXE_FRRD },
{ "sqdb", 0x15, INSTR_RXE_FRRD },
{ "meeb", 0x17, INSTR_RXE_FRRD },
{ "kdb", 0x18, INSTR_RXE_FRRD },
{ "cdb", 0x19, INSTR_RXE_FRRD },
{ "adb", 0x1a, INSTR_RXE_FRRD },
{ "sdb", 0x1b, INSTR_RXE_FRRD },
{ "mdb", 0x1c, INSTR_RXE_FRRD },
{ "ddb", 0x1d, INSTR_RXE_FRRD },
{ "madb", 0x1e, INSTR_RXF_FRRDF },
{ "msdb", 0x1f, INSTR_RXF_FRRDF },
{ "lde", 0x24, INSTR_RXE_FRRD },
{ "lxd", 0x25, INSTR_RXE_FRRD },
{ "lxe", 0x26, INSTR_RXE_FRRD },
{ "mae", 0x2e, INSTR_RXF_FRRDF },
{ "mse", 0x2f, INSTR_RXF_FRRDF },
{ "sqe", 0x34, INSTR_RXE_FRRD },
{ "sqd", 0x35, INSTR_RXE_FRRD },
{ "mee", 0x37, INSTR_RXE_FRRD },
{ "mad", 0x3e, INSTR_RXF_FRRDF },
{ "msd", 0x3f, INSTR_RXF_FRRDF },
{ "cdpt", 0xae, INSTR_RSL_LRDFU },
{ "cxpt", 0xaf, INSTR_RSL_LRDFU },
{ "cpdt", 0xac, INSTR_RSL_LRDFU },
{ "cpxt", 0xad, INSTR_RSL_LRDFU },
{ "", 0, INSTR_INVALID }
};
static char long_insn_name[][7] = LONG_INSN_INITIALIZER;
static struct s390_insn opcode[] = OPCODE_TABLE_INITIALIZER;
static struct s390_opcode_offset opcode_offset[] = OPCODE_OFFSET_INITIALIZER;
/* Extracts an operand value from an instruction. */
static unsigned int extract_operand(unsigned char *code,
......@@ -1876,87 +391,24 @@ static unsigned int extract_operand(unsigned char *code,
struct s390_insn *find_insn(unsigned char *code)
{
unsigned char opfrag = code[1];
unsigned char opmask;
struct s390_insn *table;
struct s390_opcode_offset *entry;
struct s390_insn *insn;
unsigned char opfrag;
int i;
switch (code[0]) {
case 0x01:
table = opcode_01;
break;
case 0xa5:
table = opcode_a5;
break;
case 0xa7:
table = opcode_a7;
break;
case 0xaa:
table = opcode_aa;
break;
case 0xb2:
table = opcode_b2;
break;
case 0xb3:
table = opcode_b3;
break;
case 0xb9:
table = opcode_b9;
break;
case 0xc0:
table = opcode_c0;
break;
case 0xc2:
table = opcode_c2;
break;
case 0xc4:
table = opcode_c4;
break;
case 0xc6:
table = opcode_c6;
break;
case 0xc8:
table = opcode_c8;
break;
case 0xcc:
table = opcode_cc;
break;
case 0xe3:
table = opcode_e3;
opfrag = code[5];
break;
case 0xe5:
table = opcode_e5;
break;
case 0xe6:
table = opcode_e6;
opfrag = code[5];
break;
case 0xe7:
table = opcode_e7;
opfrag = code[5];
break;
case 0xeb:
table = opcode_eb;
opfrag = code[5];
break;
case 0xec:
table = opcode_ec;
opfrag = code[5];
break;
case 0xed:
table = opcode_ed;
opfrag = code[5];
break;
default:
table = opcode;
opfrag = code[0];
for (i = 0; i < ARRAY_SIZE(opcode_offset); i++) {
entry = &opcode_offset[i];
if (entry->opcode == code[0] || entry->opcode == 0)
break;
}
while (table->format != INSTR_INVALID) {
opmask = formats[table->format][0];
if (table->opfrag == (opfrag & opmask))
return table;
table++;
opfrag = *(code + entry->byte) & entry->mask;
insn = &opcode[entry->offset];
for (i = 0; i < entry->count; i++) {
if (insn->opfrag == opfrag)
return insn;
insn++;
}
return NULL;
}
......@@ -1974,14 +426,14 @@ static int print_insn(char *buffer, unsigned char *code, unsigned long addr)
ptr = buffer;
insn = find_insn(code);
if (insn) {
if (insn->name[0] == '\0')
ptr += sprintf(ptr, "%s\t",
long_insn_name[(int) insn->name[1]]);
if (insn->zero == 0)
ptr += sprintf(ptr, "%.7s\t",
long_insn_name[insn->offset]);
else
ptr += sprintf(ptr, "%.5s\t", insn->name);
/* Extract the operands. */
separator = 0;
for (ops = formats[insn->format] + 1, i = 0;
for (ops = formats[insn->format], i = 0;
*ops != 0 && i < 6; ops++, i++) {
operand = operands + *ops;
value = extract_operand(code, operand);
......
arch/s390/tools/Makefile
View file @ 8bc1e4ec
......@@ -3,11 +3,21 @@
#
hostprogs-y += gen_facilities
hostprogs-y += gen_opcode_table
HOSTCFLAGS_gen_facilities.o += -Wall $(LINUXINCLUDE)
HOSTCFLAGS_gen_opcode_table.o += -Wall $(LINUXINCLUDE)
define filechk_facilities.h
$(obj)/gen_facilities
endef
define filechk_dis.h
( $(obj)/gen_opcode_table < $(srctree)/arch/$(ARCH)/tools/opcodes.txt )
endef
include/generated/facilities.h: $(obj)/gen_facilities FORCE
$(call filechk,facilities.h)
include/generated/dis.h: $(obj)/gen_opcode_table FORCE
$(call filechk,dis.h,__FUN)
arch/s390/tools/gen_opcode_table.c 0 → 100644
View file @ 8bc1e4ec
/*
* Generate opcode table initializers for the in-kernel disassembler.
*
* Copyright IBM Corp. 2017
*
*/
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#include <stdio.h>
#define STRING_SIZE_MAX 20
struct insn_type {
unsigned char byte;
unsigned char mask;
char **format;
};
struct insn {
struct insn_type *type;
char opcode[STRING_SIZE_MAX];
char name[STRING_SIZE_MAX];
char upper[STRING_SIZE_MAX];
char format[STRING_SIZE_MAX];
unsigned int name_len;
};
struct insn_group {
struct insn_type *type;
int offset;
int count;
char opcode[2];
};
struct insn_format {
char *format;
int type;
};
struct gen_opcode {
struct insn *insn;
int nr;
struct insn_group *group;
int nr_groups;
};
/*
* Table of instruction format types. Each opcode is defined with at
* least one byte (two nibbles), three nibbles, or two bytes (four
* nibbles).
* The byte member of each instruction format type entry defines
* within which byte of an instruction the third (and fourth) nibble
* of an opcode can be found. The mask member is the and-mask that
* needs to be applied on this byte in order to get the third (and
* fourth) nibble of the opcode.
* The format array defines all instruction formats (as defined in the
* Principles of Operation) which have the same position of the opcode
* nibbles.
* A special case are instruction formats with 1-byte opcodes. In this
* case the byte member always is zero, so that the mask is applied on
* the (only) byte that contains the opcode.
*/
static struct insn_type insn_type_table[] = {
{
.byte = 0,
.mask = 0xff,
.format = (char *[]) {
"MII",
"RR",
"RS",
"RSI",
"RX",
"SI",
"SMI",
"SS",
NULL,
},
},
{
.byte = 1,
.mask = 0x0f,
.format = (char *[]) {
"RI",
"RIL",
"SSF",
NULL,
},
},
{
.byte = 1,
.mask = 0xff,
.format = (char *[]) {
"E",
"IE",
"RRE",
"RRF",
"RRR",
"S",
"SIL",
"SSE",
NULL,
},
},
{
.byte = 5,
.mask = 0xff,
.format = (char *[]) {
"RIE",
"RIS",
"RRS",
"RSE",
"RSL",
"RSY",
"RXE",
"RXF",
"RXY",
"SIY",
"VRI",
"VRR",
"VRS",
"VRV",
"VRX",
"VSI",
NULL,
},
},
};
static struct insn_type *insn_format_to_type(char *format)
{
char tmp[STRING_SIZE_MAX];
char *base_format, **ptr;
int i;
strcpy(tmp, format);
base_format = tmp;
base_format = strsep(&base_format, "_");
for (i = 0; i < sizeof(insn_type_table) / sizeof(insn_type_table[0]); i++) {
ptr = insn_type_table[i].format;
while (*ptr) {
if (!strcmp(base_format, *ptr))
return &insn_type_table[i];
ptr++;
}
}
exit(EXIT_FAILURE);
}
static void read_instructions(struct gen_opcode *desc)
{
struct insn insn;
int rc, i;
while (1) {
rc = scanf("%s %s %s", insn.opcode, insn.name, insn.format);
if (rc == EOF)
break;
if (rc != 3)
exit(EXIT_FAILURE);
insn.type = insn_format_to_type(insn.format);
insn.name_len = strlen(insn.name);
for (i = 0; i <= insn.name_len; i++)
insn.upper[i] = toupper((unsigned char)insn.name[i]);
desc->nr++;
desc->insn = realloc(desc->insn, desc->nr * sizeof(*desc->insn));
if (!desc->insn)
exit(EXIT_FAILURE);
desc->insn[desc->nr - 1] = insn;
}
}
static int cmpformat(const void *a, const void *b)
{
return strcmp(((struct insn *)a)->format, ((struct insn *)b)->format);
}
static void print_formats(struct gen_opcode *desc)
{
char *format;
int i, count;
qsort(desc->insn, desc->nr, sizeof(*desc->insn), cmpformat);
format = "";
count = 0;
printf("enum {\n");
for (i = 0; i < desc->nr; i++) {
if (!strcmp(format, desc->insn[i].format))
continue;
count++;
format = desc->insn[i].format;
printf("\tINSTR_%s,\n", format);
}
printf("}; /* %d */\n\n", count);
}
static int cmp_long_insn(const void *a, const void *b)
{
return strcmp(((struct insn *)a)->name, ((struct insn *)b)->name);
}
static void print_long_insn(struct gen_opcode *desc)
{
struct insn *insn;
int i, count;
qsort(desc->insn, desc->nr, sizeof(*desc->insn), cmp_long_insn);
count = 0;
printf("enum {\n");
for (i = 0; i < desc->nr; i++) {
insn = &desc->insn[i];
if (insn->name_len < 6)
continue;
printf("\tLONG_INSN_%s,\n", insn->upper);
count++;
}
printf("}; /* %d */\n\n", count);
printf("#define LONG_INSN_INITIALIZER { \\\n");
for (i = 0; i < desc->nr; i++) {
insn = &desc->insn[i];
if (insn->name_len < 6)
continue;
printf("\t[LONG_INSN_%s] = \"%s\", \\\n", insn->upper, insn->name);
}
printf("}\n\n");
}
static void print_opcode(struct insn *insn, int nr)
{
char *opcode;
opcode = insn->opcode;
if (insn->type->byte != 0)
opcode += 2;
printf("\t[%4d] = { .opfrag = 0x%s, .format = INSTR_%s, ", nr, opcode, insn->format);
if (insn->name_len < 6)
printf(".name = \"%s\" ", insn->name);
else
printf(".offset = LONG_INSN_%s ", insn->upper);
printf("}, \\\n");
}
static void add_to_group(struct gen_opcode *desc, struct insn *insn, int offset)
{
struct insn_group *group;
group = desc->group ? &desc->group[desc->nr_groups - 1] : NULL;
if (group && (!strncmp(group->opcode, insn->opcode, 2) || group->type->byte == 0)) {
group->count++;
return;
}
desc->nr_groups++;
desc->group = realloc(desc->group, desc->nr_groups * sizeof(*desc->group));
if (!desc->group)
exit(EXIT_FAILURE);
group = &desc->group[desc->nr_groups - 1];
strncpy(group->opcode, insn->opcode, 2);
group->type = insn->type;
group->offset = offset;
group->count = 1;
}
static int cmpopcode(const void *a, const void *b)
{
return strcmp(((struct insn *)a)->opcode, ((struct insn *)b)->opcode);
}
static void print_opcode_table(struct gen_opcode *desc)
{
char opcode[2] = "";
struct insn *insn;
int i, offset;
qsort(desc->insn, desc->nr, sizeof(*desc->insn), cmpopcode);
printf("#define OPCODE_TABLE_INITIALIZER { \\\n");
offset = 0;
for (i = 0; i < desc->nr; i++) {
insn = &desc->insn[i];
if (insn->type->byte == 0)
continue;
add_to_group(desc, insn, offset);
if (strncmp(opcode, insn->opcode, 2)) {
strncpy(opcode, insn->opcode, 2);
printf("\t/* %.2s */ \\\n", opcode);
}
print_opcode(insn, offset);
offset++;
}
printf("\t/* 1-byte opcode instructions */ \\\n");
for (i = 0; i < desc->nr; i++) {
insn = &desc->insn[i];
if (insn->type->byte != 0)
continue;
add_to_group(desc, insn, offset);
print_opcode(insn, offset);
offset++;
}
printf("}\n\n");
}
static void print_opcode_table_offsets(struct gen_opcode *desc)
{
struct insn_group *group;
int i;
printf("#define OPCODE_OFFSET_INITIALIZER { \\\n");
for (i = 0; i < desc->nr_groups; i++) {
group = &desc->group[i];
printf("\t{ .opcode = 0x%.2s, .mask = 0x%02x, .byte = %d, .offset = %d, .count = %d }, \\\n",
group->opcode, group->type->mask, group->type->byte, group->offset, group->count);
}
printf("}\n\n");
}
int main(int argc, char **argv)
{
struct gen_opcode _desc = { 0 };
struct gen_opcode *desc = &_desc;
read_instructions(desc);
printf("#ifndef __S390_GENERATED_DIS_H__\n");
printf("#define __S390_GENERATED_DIS_H__\n");
printf("/*\n");
printf(" * DO NOT MODIFY.\n");
printf(" *\n");
printf(" * This file was generated by %s\n", __FILE__);
printf(" */\n\n");
print_formats(desc);
print_long_insn(desc);
print_opcode_table(desc);
print_opcode_table_offsets(desc);
printf("#endif\n");
exit(EXIT_SUCCESS);
}
arch/s390/tools/opcodes.txt 0 → 100644
View file @ 8bc1e4ec
0101 pr E
0102 upt E
0104 ptff E
0107 sckpf E
010a pfpo E
010b tam E
010c sam24 E
010d sam31 E
010e sam64 E
01ff trap2 E
04 spm RR_R0
05 balr RR_RR
06 bctr RR_RR
07 bcr RR_UR
0a svc RR_U0
0b bsm RR_RR
0c bassm RR_RR
0d basr RR_RR
0e mvcl RR_RR
0f clcl RR_RR
10 lpr RR_RR
11 lnr RR_RR
12 ltr RR_RR
13 lcr RR_RR
14 nr RR_RR
15 clr RR_RR
16 or RR_RR
17 xr RR_RR
18 lr RR_RR
19 cr RR_RR
1a ar RR_RR
1b sr RR_RR
1c mr RR_RR
1d dr RR_RR
1e alr RR_RR
1f slr RR_RR
20 lpdr RR_FF
21 lndr RR_FF
22 ltdr RR_FF
23 lcdr RR_FF
24 hdr RR_FF
25 ldxr RR_FF
26 mxr RR_FF
27 mxdr RR_FF
28 ldr RR_FF
29 cdr RR_FF
2a adr RR_FF
2b sdr RR_FF
2c mdr RR_FF
2d ddr RR_FF
2e awr RR_FF
2f swr RR_FF
30 lper RR_FF
31 lner RR_FF
32 lter RR_FF
33 lcer RR_FF
34 her RR_FF
35 ledr RR_FF
36 axr RR_FF
37 sxr RR_FF
38 ler RR_FF
39 cer RR_FF
3a aer RR_FF
3b ser RR_FF
3c mder RR_FF
3d der RR_FF
3e aur RR_FF
3f sur RR_FF
40 sth RX_RRRD
41 la RX_RRRD
42 stc RX_RRRD
43 ic RX_RRRD
44 ex RX_RRRD
45 bal RX_RRRD
46 bct RX_RRRD
47 bc RX_URRD
48 lh RX_RRRD
49 ch RX_RRRD
4a ah RX_RRRD
4b sh RX_RRRD
4c mh RX_RRRD
4d bas RX_RRRD
4e cvd RX_RRRD
4f cvb RX_RRRD
50 st RX_RRRD
51 lae RX_RRRD
54 n RX_RRRD
55 cl RX_RRRD
56 o RX_RRRD
57 x RX_RRRD
58 l RX_RRRD
59 c RX_RRRD
5a a RX_RRRD
5b s RX_RRRD
5c m RX_RRRD
5d d RX_RRRD
5e al RX_RRRD
5f sl RX_RRRD
60 std RX_FRRD
67 mxd RX_FRRD
68 ld RX_FRRD
69 cd RX_FRRD
6a ad RX_FRRD
6b sd RX_FRRD
6c md RX_FRRD
6d dd RX_FRRD
6e aw RX_FRRD
6f sw RX_FRRD
70 ste RX_FRRD
71 ms RX_RRRD
78 le RX_FRRD
79 ce RX_FRRD
7a ae RX_FRRD
7b se RX_FRRD
7c mde RX_FRRD
7d de RX_FRRD
7e au RX_FRRD
7f su RX_FRRD
80 ssm SI_RD
82 lpsw SI_RD
83 diag RS_RRRD
84 brxh RSI_RRP
85 brxle RSI_RRP
86 bxh RS_RRRD
87 bxle RS_RRRD
88 srl RS_R0RD
89 sll RS_R0RD
8a sra RS_R0RD
8b sla RS_R0RD
8c srdl RS_R0RD
8d sldl RS_R0RD
8e srda RS_R0RD
8f slda RS_R0RD
90 stm RS_RRRD
91 tm SI_URD
92 mvi SI_URD
93 ts SI_RD
94 ni SI_URD
95 cli SI_URD
96 oi SI_URD
97 xi SI_URD
98 lm RS_RRRD
99 trace RS_RRRD
9a lam RS_AARD
9b stam RS_AARD
a50 iihh RI_RU
a51 iihl RI_RU
a52 iilh RI_RU
a53 iill RI_RU
a54 nihh RI_RU
a55 nihl RI_RU
a56 nilh RI_RU
a57 nill RI_RU
a58 oihh RI_RU
a59 oihl RI_RU
a5a oilh RI_RU
a5b oill RI_RU
a5c llihh RI_RU
a5d llihl RI_RU
a5e llilh RI_RU
a5f llill RI_RU
a70 tmlh RI_RU
a71 tmll RI_RU
a72 tmhh RI_RU
a73 tmhl RI_RU
a74 brc RI_UP
a75 bras RI_RP
a76 brct RI_RP
a77 brctg RI_RP
a78 lhi RI_RI
a79 lghi RI_RI
a7a ahi RI_RI
a7b aghi RI_RI
a7c mhi RI_RI
a7d mghi RI_RI
a7e chi RI_RI
a7f cghi RI_RI
a8 mvcle RS_RRRD
a9 clcle RS_RRRD
aa0 rinext RI_RI
aa1 rion RI_RI
aa2 tric RI_RI
aa3 rioff RI_RI
aa4 riemit RI_RI
ac stnsm SI_URD
ad stosm SI_URD
ae sigp RS_RRRD
af mc SI_URD
b1 lra RX_RRRD
b202 stidp S_RD
b204 sck S_RD
b205 stck S_RD
b206 sckc S_RD
b207 stckc S_RD
b208 spt S_RD
b209 stpt S_RD
b20a spka S_RD
b20b ipk S_00
b20d ptlb S_00
b210 spx S_RD
b211 stpx S_RD
b212 stap S_RD
b214 sie S_RD
b218 pc S_RD
b219 sac S_RD
b21a cfc S_RD
b220 servc RRE_RR
b221 ipte RRF_RURR
b222 ipm RRE_R0
b223 ivsk RRE_RR
b224 iac RRE_R0
b225 ssar RRE_R0
b226 epar RRE_R0
b227 esar RRE_R0
b228 pt RRE_RR
b229 iske RRE_RR
b22a rrbe RRE_RR
b22b sske RRF_U0RR
b22c tb RRE_RR
b22d dxr RRE_FF
b22e pgin RRE_RR
b22f pgout RRE_RR
b230 csch S_00
b231 hsch S_00
b232 msch S_RD
b233 ssch S_RD
b234 stsch S_RD
b235 tsch S_RD
b236 tpi S_RD
b237 sal S_00
b238 rsch S_00
b239 stcrw S_RD
b23a stcps S_RD
b23b rchp S_00
b23c schm S_00
b240 bakr RRE_RR
b241 cksm RRE_RR
b244 sqdr RRE_FF
b245 sqer RRE_FF
b246 stura RRE_RR
b247 msta RRE_R0
b248 palb RRE_00
b249 ereg RRE_RR
b24a esta RRE_RR
b24b lura RRE_RR
b24c tar RRE_AR
b24d cpya RRE_AA
b24e sar RRE_AR
b24f ear RRE_RA
b250 csp RRE_RR
b252 msr RRE_RR
b254 mvpg RRE_RR
b255 mvst RRE_RR
b256 sthyi RRE_RR
b257 cuse RRE_RR
b258 bsg RRE_RR
b25a bsa RRE_RR
b25d clst RRE_RR
b25e srst RRE_RR
b263 cmpsc RRE_RR
b274 siga S_RD
b276 xsch S_00
b277 rp S_RD
b278 stcke S_RD
b279 sacf S_RD
b27c stckf S_RD
b27d stsi S_RD
b280 lpp S_RD
b284 lcctl S_RD
b285 lpctl S_RD
b286 qsi S_RD
b287 lsctl S_RD
b28e qctri S_RD
b299 srnm S_RD
b29c stfpc S_RD
b29d lfpc S_RD
b2a5 tre RRE_RR
b2a6 cu21 RRF_U0RR
b2a7 cu12 RRF_U0RR
b2b0 stfle S_RD
b2b1 stfl S_RD
b2b2 lpswe S_RD
b2b8 srnmb S_RD
b2b9 srnmt S_RD
b2bd lfas S_RD
b2e0 scctr RRE_RR
b2e1 spctr RRE_RR
b2e4 ecctr RRE_RR
b2e5 epctr RRE_RR
b2e8 ppa RRF_U0RR
b2ec etnd RRE_R0
b2ed ecpga RRE_RR
b2f8 tend S_00
b2fa niai IE_UU
b2fc tabort S_RD
b2ff trap4 S_RD
b300 lpebr RRE_FF
b301 lnebr RRE_FF
b302 ltebr RRE_FF
b303 lcebr RRE_FF
b304 ldebr RRE_FF
b305 lxdbr RRE_FF
b306 lxebr RRE_FF
b307 mxdbr RRE_FF
b308 kebr RRE_FF
b309 cebr RRE_FF
b30a aebr RRE_FF
b30b sebr RRE_FF
b30c mdebr RRE_FF
b30d debr RRE_FF
b30e maebr RRF_F0FF
b30f msebr RRF_F0FF
b310 lpdbr RRE_FF
b311 lndbr RRE_FF
b312 ltdbr RRE_FF
b313 lcdbr RRE_FF
b314 sqebr RRE_FF
b315 sqdbr RRE_FF
b316 sqxbr RRE_FF
b317 meebr RRE_FF
b318 kdbr RRE_FF
b319 cdbr RRE_FF
b31a adbr RRE_FF
b31b sdbr RRE_FF
b31c mdbr RRE_FF
b31d ddbr RRE_FF
b31e madbr RRF_F0FF
b31f msdbr RRF_F0FF
b324 lder RRE_FF
b325 lxdr RRE_FF
b326 lxer RRE_FF
b32e maer RRF_F0FF
b32f mser RRF_F0FF
b336 sqxr RRE_FF
b337 meer RRE_FF
b338 maylr RRF_F0FF
b339 mylr RRF_F0FF
b33a mayr RRF_F0FF
b33b myr RRF_F0FF
b33c mayhr RRF_F0FF
b33d myhr RRF_F0FF
b33e madr RRF_F0FF
b33f msdr RRF_F0FF
b340 lpxbr RRE_FF
b341 lnxbr RRE_FF
b342 ltxbr RRE_FF
b343 lcxbr RRE_FF
b344 ledbra RRF_UUFF
b345 ldxbra RRF_UUFF
b346 lexbra RRF_UUFF
b347 fixbra RRF_UUFF
b348 kxbr RRE_FF
b349 cxbr RRE_FF
b34a axbr RRE_FF
b34b sxbr RRE_FF
b34c mxbr RRE_FF
b34d dxbr RRE_FF
b350 tbedr RRF_U0FF
b351 tbdr RRF_U0FF
b353 diebr RRF_FUFF
b357 fiebra RRF_UUFF
b358 thder RRE_FF
b359 thdr RRE_FF
b35b didbr RRF_FUFF
b35f fidbra RRF_UUFF
b360 lpxr RRE_FF
b361 lnxr RRE_FF
b362 ltxr RRE_FF
b363 lcxr RRE_FF
b365 lxr RRE_FF
b366 lexr RRE_FF
b367 fixr RRE_FF
b369 cxr RRE_FF
b370 lpdfr RRE_FF
b371 lndfr RRE_FF
b372 cpsdr RRF_F0FF2
b373 lcdfr RRE_FF
b374 lzer RRE_F0
b375 lzdr RRE_F0
b376 lzxr RRE_F0
b377 fier RRE_FF
b37f fidr RRE_FF
b384 sfpc RRE_RR
b385 sfasr RRE_R0
b38c efpc RRE_RR
b390 celfbr RRF_UUFR
b391 cdlfbr RRF_UUFR
b392 cxlfbr RRF_UUFR
b394 cefbra RRF_UUFR
b395 cdfbra RRF_UUFR
b396 cxfbra RRF_UUFR
b398 cfebra RRF_UURF
b399 cfdbra RRF_UURF
b39a cfxbra RRF_UURF
b39c clfebr RRF_UURF
b39d clfdbr RRF_UURF
b39e clfxbr RRF_UURF
b3a0 celgbr RRF_UUFR
b3a1 cdlgbr RRF_UUFR
b3a2 cxlgbr RRF_UUFR
b3a4 cegbra RRF_UUFR
b3a5 cdgbra RRF_UUFR
b3a6 cxgbra RRF_UUFR
b3a8 cgebra RRF_UURF
b3a9 cgdbra RRF_UURF
b3aa cgxbra RRF_UURF
b3ac clgebr RRF_UURF
b3ad clgdbr RRF_UURF
b3ae clgxbr RRF_UURF
b3b4 cefr RRE_FR
b3b5 cdfr RRE_FR
b3b6 cxfr RRE_FR
b3b8 cfer RRF_U0RF
b3b9 cfdr RRF_U0RF
b3ba cfxr RRF_U0RF
b3c1 ldgr RRE_FR
b3c4 cegr RRE_FR
b3c5 cdgr RRE_FR
b3c6 cxgr RRE_FR
b3c8 cger RRF_U0RF
b3c9 cgdr RRF_U0RF
b3ca cgxr RRF_U0RF
b3cd lgdr RRE_RF
b3d0 mdtra RRF_FUFF2
b3d1 ddtra RRF_FUFF2
b3d2 adtra RRF_FUFF2
b3d3 sdtra RRF_FUFF2
b3d4 ldetr RRF_0UFF
b3d5 ledtr RRF_UUFF
b3d6 ltdtr RRE_FF
b3d7 fidtr RRF_UUFF
b3d8 mxtra RRF_FUFF2
b3d9 dxtra RRF_FUFF2
b3da axtra RRF_FUFF2
b3db sxtra RRF_FUFF2
b3dc lxdtr RRF_0UFF
b3dd ldxtr RRF_UUFF
b3de ltxtr RRE_FF
b3df fixtr RRF_UUFF
b3e0 kdtr RRE_FF
b3e1 cgdtra RRF_UURF
b3e2 cudtr RRE_RF
b3e3 csdtr RRF_0URF
b3e4 cdtr RRE_FF
b3e5 eedtr RRE_RF
b3e7 esdtr RRE_RF
b3e8 kxtr RRE_FF
b3e9 cgxtra RRF_UURF
b3ea cuxtr RRE_RF
b3eb csxtr RRF_0URF
b3ec cxtr RRE_FF
b3ed eextr RRE_RF
b3ef esxtr RRE_RF
b3f1 cdgtra RRF_UUFR
b3f2 cdutr RRE_FR
b3f3 cdstr RRE_FR
b3f4 cedtr RRE_FF
b3f5 qadtr RRF_FUFF
b3f6 iedtr RRF_F0FR
b3f7 rrdtr RRF_FFRU
b3f9 cxgtra RRF_UUFR
b3fa cxutr RRE_FR
b3fb cxstr RRE_FR
b3fc cextr RRE_FF
b3fd qaxtr RRF_FUFF
b3fe iextr RRF_F0FR
b3ff rrxtr RRF_FFRU
b6 stctl RS_CCRD
b7 lctl RS_CCRD
b900 lpgr RRE_RR
b901 lngr RRE_RR
b902 ltgr RRE_RR
b903 lcgr RRE_RR
b904 lgr RRE_RR
b905 lurag RRE_RR
b906 lgbr RRE_RR
b907 lghr RRE_RR
b908 agr RRE_RR
b909 sgr RRE_RR
b90a algr RRE_RR
b90b slgr RRE_RR
b90c msgr RRE_RR
b90d dsgr RRE_RR
b90e eregg RRE_RR
b90f lrvgr RRE_RR
b910 lpgfr RRE_RR
b911 lngfr RRE_RR
b912 ltgfr RRE_RR
b913 lcgfr RRE_RR
b914 lgfr RRE_RR
b916 llgfr RRE_RR
b917 llgtr RRE_RR
b918 agfr RRE_RR
b919 sgfr RRE_RR
b91a algfr RRE_RR
b91b slgfr RRE_RR
b91c msgfr RRE_RR
b91d dsgfr RRE_RR
b91e kmac RRE_RR
b91f lrvr RRE_RR
b920 cgr RRE_RR
b921 clgr RRE_RR
b925 sturg RRE_RR
b926 lbr RRE_RR
b927 lhr RRE_RR
b928 pckmo RRE_00
b929 kma RRF_R0RR
b92a kmf RRE_RR
b92b kmo RRE_RR
b92c pcc RRE_00
b92d kmctr RRF_R0RR
b92e km RRE_RR
b92f kmc RRE_RR
b930 cgfr RRE_RR
b931 clgfr RRE_RR
b93c ppno RRE_RR
b93e kimd RRE_RR
b93f klmd RRE_RR
b941 cfdtr RRF_UURF
b942 clgdtr RRF_UURF
b943 clfdtr RRF_UURF
b946 bctgr RRE_RR
b949 cfxtr RRF_UURF
b94a clgxtr RRF_UURF
b94b clfxtr RRF_UURF
b951 cdftr RRF_UUFR
b952 cdlgtr RRF_UUFR
b953 cdlftr RRF_UUFR
b959 cxftr RRF_UUFR
b95a cxlgtr RRF_UUFR
b95b cxlftr RRF_UUFR
b960 cgrt RRF_U0RR
b961 clgrt RRF_U0RR
b972 crt RRF_U0RR
b973 clrt RRF_U0RR
b980 ngr RRE_RR
b981 ogr RRE_RR
b982 xgr RRE_RR
b983 flogr RRE_RR
b984 llgcr RRE_RR
b985 llghr RRE_RR
b986 mlgr RRE_RR
b987 dlgr RRE_RR
b988 alcgr RRE_RR
b989 slbgr RRE_RR
b98a cspg RRE_RR
b98d epsw RRE_RR
b98e idte RRF_RURR2
b98f crdte RRF_RURR2
b990 trtt RRF_U0RR
b991 trto RRF_U0RR
b992 trot RRF_U0RR
b993 troo RRF_U0RR
b994 llcr RRE_RR
b995 llhr RRE_RR
b996 mlr RRE_RR
b997 dlr RRE_RR
b998 alcr RRE_RR
b999 slbr RRE_RR
b99a epair RRE_R0
b99b esair RRE_R0
b99d esea RRE_R0
b99e pti RRE_RR
b99f ssair RRE_R0
b9a1 tpei RRE_RR
b9a2 ptf RRE_R0
b9aa lptea RRF_RURR2
b9ac irbm RRE_RR
b9ae rrbm RRE_RR
b9af pfmf RRE_RR
b9b0 cu14 RRF_U0RR
b9b1 cu24 RRF_U0RR
b9b2 cu41 RRE_RR
b9b3 cu42 RRE_RR
b9bd trtre RRF_U0RR
b9be srstu RRE_RR
b9bf trte RRF_U0RR
b9c8 ahhhr RRF_R0RR2
b9c9 shhhr RRF_R0RR2
b9ca alhhhr RRF_R0RR2
b9cb slhhhr RRF_R0RR2
b9cd chhr RRE_RR
b9cf clhhr RRE_RR
b9d0 pcistg RRE_RR
b9d2 pcilg RRE_RR
b9d3 rpcit RRE_RR
b9d8 ahhlr RRF_R0RR2
b9d9 shhlr RRF_R0RR2
b9da alhhlr RRF_R0RR2
b9db slhhlr RRF_R0RR2
b9dd chlr RRE_RR
b9df clhlr RRE_RR
b9e0 locfhr RRF_U0RR
b9e1 popcnt RRE_RR
b9e2 locgr RRF_U0RR
b9e4 ngrk RRF_R0RR2
b9e6 ogrk RRF_R0RR2
b9e7 xgrk RRF_R0RR2
b9e8 agrk RRF_R0RR2
b9e9 sgrk RRF_R0RR2
b9ea algrk RRF_R0RR2
b9eb slgrk RRF_R0RR2
b9ec mgrk RRF_R0RR2
b9ed msgrkc RRF_R0RR2
b9f2 locr RRF_U0RR
b9f4 nrk RRF_R0RR2
b9f6 ork RRF_R0RR2
b9f7 xrk RRF_R0RR2
b9f8 ark RRF_R0RR2
b9f9 srk RRF_R0RR2
b9fa alrk RRF_R0RR2
b9fb slrk RRF_R0RR2
b9fd msrkc RRF_R0RR2
ba cs RS_RRRD
bb cds RS_RRRD
bd clm RS_RURD
be stcm RS_RURD
bf icm RS_RURD
c00 larl RIL_RP
c01 lgfi RIL_RI
c04 brcl RIL_UP
c05 brasl RIL_RP
c06 xihf RIL_RU
c07 xilf RIL_RU
c08 iihf RIL_RU
c09 iilf RIL_RU
c0a nihf RIL_RU
c0b nilf RIL_RU
c0c oihf RIL_RU
c0d oilf RIL_RU
c0e llihf RIL_RU
c0f llilf RIL_RU
c20 msgfi RIL_RI
c21 msfi RIL_RI
c24 slgfi RIL_RU
c25 slfi RIL_RU
c28 agfi RIL_RI
c29 afi RIL_RI
c2a algfi RIL_RU
c2b alfi RIL_RU
c2c cgfi RIL_RI
c2d cfi RIL_RI
c2e clgfi RIL_RU
c2f clfi RIL_RU
c42 llhrl RIL_RP
c44 lghrl RIL_RP
c45 lhrl RIL_RP
c46 llghrl RIL_RP
c47 sthrl RIL_RP
c48 lgrl RIL_RP
c4b stgrl RIL_RP
c4c lgfrl RIL_RP
c4d lrl RIL_RP
c4e llgfrl RIL_RP
c4f strl RIL_RP
c5 bprp MII_UPP
c60 exrl RIL_RP
c62 pfdrl RIL_UP
c64 cghrl RIL_RP
c65 chrl RIL_RP
c66 clghrl RIL_RP
c67 clhrl RIL_RP
c68 cgrl RIL_RP
c6a clgrl RIL_RP
c6c cgfrl RIL_RP
c6d crl RIL_RP
c6e clgfrl RIL_RP
c6f clrl RIL_RP
c7 bpp SMI_U0RDP
c80 mvcos SSF_RRDRD
c81 ectg SSF_RRDRD
c82 csst SSF_RRDRD
c84 lpd SSF_RRDRD2
c85 lpdg SSF_RRDRD2
cc6 brcth RIL_RP
cc8 aih RIL_RI
cca alsih RIL_RI
ccb alsihn RIL_RI
ccd cih RIL_RI
ccf clih RIL_RU
d0 trtr SS_L0RDRD
d1 mvn SS_L0RDRD
d2 mvc SS_L0RDRD
d3 mvz SS_L0RDRD
d4 nc SS_L0RDRD
d5 clc SS_L0RDRD
d6 oc SS_L0RDRD
d7 xc SS_L0RDRD
d9 mvck SS_RRRDRD
da mvcp SS_RRRDRD
db mvcs SS_RRRDRD
dc tr SS_L0RDRD
dd trt SS_L0RDRD
de ed SS_L0RDRD
df edmk SS_L0RDRD
e1 pku SS_L2RDRD
e2 unpku SS_L0RDRD
e302 ltg RXY_RRRD
e303 lrag RXY_RRRD
e304 lg RXY_RRRD
e306 cvby RXY_RRRD
e308 ag RXY_RRRD
e309 sg RXY_RRRD
e30a alg RXY_RRRD
e30b slg RXY_RRRD
e30c msg RXY_RRRD
e30d dsg RXY_RRRD
e30e cvbg RXY_RRRD
e30f lrvg RXY_RRRD
e312 lt RXY_RRRD
e313 lray RXY_RRRD
e314 lgf RXY_RRRD
e315 lgh RXY_RRRD
e316 llgf RXY_RRRD
e317 llgt RXY_RRRD
e318 agf RXY_RRRD
e319 sgf RXY_RRRD
e31a algf RXY_RRRD
e31b slgf RXY_RRRD
e31c msgf RXY_RRRD
e31d dsgf RXY_RRRD
e31e lrv RXY_RRRD
e31f lrvh RXY_RRRD
e320 cg RXY_RRRD
e321 clg RXY_RRRD
e324 stg RXY_RRRD
e325 ntstg RXY_RRRD
e326 cvdy RXY_RRRD
e32a lzrg RXY_RRRD
e32e cvdg RXY_RRRD
e32f strvg RXY_RRRD
e330 cgf RXY_RRRD
e331 clgf RXY_RRRD
e332 ltgf RXY_RRRD
e334 cgh RXY_RRRD
e336 pfd RXY_URRD
e338 agh RXY_RRRD
e339 sgh RXY_RRRD
e33a llzrgf RXY_RRRD
e33b lzrf RXY_RRRD
e33c mgh RXY_RRRD
e33e strv RXY_RRRD
e33f strvh RXY_RRRD
e346 bctg RXY_RRRD
e347 bic RXY_URRD
e348 llgfsg RXY_RRRD
e349 stgsc RXY_RRRD
e34c lgg RXY_RRRD
e34d lgsc RXY_RRRD
e350 sty RXY_RRRD
e351 msy RXY_RRRD
e353 msc RXY_RRRD
e354 ny RXY_RRRD
e355 cly RXY_RRRD
e356 oy RXY_RRRD
e357 xy RXY_RRRD
e358 ly RXY_RRRD
e359 cy RXY_RRRD
e35a ay RXY_RRRD
e35b sy RXY_RRRD
e35c mfy RXY_RRRD
e35e aly RXY_RRRD
e35f sly RXY_RRRD
e370 sthy RXY_RRRD
e371 lay RXY_RRRD
e372 stcy RXY_RRRD
e373 icy RXY_RRRD
e375 laey RXY_RRRD
e376 lb RXY_RRRD
e377 lgb RXY_RRRD
e378 lhy RXY_RRRD
e379 chy RXY_RRRD
e37a ahy RXY_RRRD
e37b shy RXY_RRRD
e37c mhy RXY_RRRD
e380 ng RXY_RRRD
e381 og RXY_RRRD
e382 xg RXY_RRRD
e383 msgc RXY_RRRD
e384 mg RXY_RRRD
e385 lgat RXY_RRRD
e386 mlg RXY_RRRD
e387 dlg RXY_RRRD
e388 alcg RXY_RRRD
e389 slbg RXY_RRRD
e38e stpq RXY_RRRD
e38f lpq RXY_RRRD
e390 llgc RXY_RRRD
e391 llgh RXY_RRRD
e394 llc RXY_RRRD
e395 llh RXY_RRRD
e396 ml RXY_RRRD
e397 dl RXY_RRRD
e398 alc RXY_RRRD
e399 slb RXY_RRRD
e39c llgtat RXY_RRRD
e39d llgfat RXY_RRRD
e39f lat RXY_RRRD
e3c0 lbh RXY_RRRD
e3c2 llch RXY_RRRD
e3c3 stch RXY_RRRD
e3c4 lhh RXY_RRRD
e3c6 llhh RXY_RRRD
e3c7 sthh RXY_RRRD
e3c8 lfhat RXY_RRRD
e3ca lfh RXY_RRRD
e3cb stfh RXY_RRRD
e3cd chf RXY_RRRD
e3cf clhf RXY_RRRD
e3d0 mpcifc RXY_RRRD
e3d4 stpcifc RXY_RRRD
e500 lasp SSE_RDRD
e501 tprot SSE_RDRD
e502 strag SSE_RDRD
e50e mvcsk SSE_RDRD
e50f mvcdk SSE_RDRD
e544 mvhhi SIL_RDI
e548 mvghi SIL_RDI
e54c mvhi SIL_RDI
e554 chhsi SIL_RDI
e555 clhhsi SIL_RDU
e558 cghsi SIL_RDI
e559 clghsi SIL_RDU
e55c chsi SIL_RDI
e55d clfhsi SIL_RDU
e560 tbegin SIL_RDU
e561 tbeginc SIL_RDU
e634 vpkz VSI_URDV
e635 vlrl VSI_URDV
e637 vlrlr VRS_RRDV
e63c vupkz VSI_URDV
e63d vstrl VSI_URDV
e63f vstrlr VRS_RRDV
e649 vlip VRI_V0UU2
e650 vcvb VRR_RV0U
e652 vcvbg VRR_RV0U
e658 vcvd VRI_VR0UU
e659 vsrp VRI_VVUUU2
e65a vcvdg VRI_VR0UU
e65b vpsop VRI_VVUUU2
e65f vtp VRR_0V
e671 vap VRI_VVV0UU2
e673 vsp VRI_VVV0UU2
e677 vcp VRR_0VV0U
e678 vmp VRI_VVV0UU2
e679 vmsp VRI_VVV0UU2
e67a vdp VRI_VVV0UU2
e67b vrp VRI_VVV0UU2
e67e vsdp VRI_VVV0UU2
e700 vleb VRX_VRRDU
e701 vleh VRX_VRRDU
e702 vleg VRX_VRRDU
e703 vlef VRX_VRRDU
e704 vllez VRX_VRRDU
e705 vlrep VRX_VRRDU
e706 vl VRX_VRRD
e707 vlbb VRX_VRRDU
e708 vsteb VRX_VRRDU
e709 vsteh VRX_VRRDU
e70a vsteg VRX_VRRDU
e70b vstef VRX_VRRDU
e70e vst VRX_VRRD
e712 vgeg VRV_VVXRDU
e713 vgef VRV_VVXRDU
e71a vsceg VRV_VVXRDU
e71b vscef VRV_VVXRDU
e721 vlgv VRS_RVRDU
e722 vlvg VRS_VRRDU
e727 lcbb RXE_RRRDU
e730 vesl VRS_VVRDU
e733 verll VRS_VVRDU
e736 vlm VRS_VVRD
e737 vll VRS_VRRD
e738 vesrl VRS_VVRDU
e73a vesra VRS_VVRDU
e73e vstm VRS_VVRD
e73f vstl VRS_VRRD
e740 vleib VRI_V0IU
e741 vleih VRI_V0IU
e742 vleig VRI_V0IU
e743 vleif VRI_V0IU
e744 vgbm VRI_V0U
e745 vrepi VRI_V0IU
e746 vgm VRI_V0UUU
e74a vftci VRI_VVUUU
e74d vrep VRI_VVUU
e750 vpopct VRR_VV0U
e752 vctz VRR_VV0U
e753 vclz VRR_VV0U
e756 vlr VRX_VV
e75c vistr VRR_VV0U0U
e75f vseg VRR_VV0U
e760 vmrl VRR_VVV0U
e761 vmrh VRR_VVV0U
e762 vlvgp VRR_VRR
e764 vsum VRR_VVV0U
e765 vsumg VRR_VVV0U
e766 vcksm VRR_VVV
e767 vsumq VRR_VVV0U
e768 vn VRR_VVV
e769 vnc VRR_VVV
e76a vo VRR_VVV
e76b vno VRR_VVV
e76c vnx VRR_VVV
e76d vx VRR_VVV
e76e vnn VRR_VVV
e76f voc VRR_VVV
e770 veslv VRR_VVV0U
e772 verim VRI_VVV0UU
e773 verllv VRR_VVV0U
e774 vsl VRR_VVV
e775 vslb VRR_VVV
e777 vsldb VRI_VVV0U
e778 vesrlv VRR_VVV0U
e77a vesrav VRR_VVV0U
e77c vsrl VRR_VVV
e77d vsrlb VRR_VVV
e77e vsra VRR_VVV
e77f vsrab VRR_VVV
e780 vfee VRR_VVV0U0U
e781 vfene VRR_VVV0U0U
e782 vfae VRR_VVV0U0U
e784 vpdi VRR_VVV0U
e785 vbperm VRR_VVV
e78a vstrc VRR_VVVUU0V
e78c vperm VRR_VVV0V
e78d vsel VRR_VVV0V
e78e vfms VRR_VVVU0UV
e78f vfma VRR_VVVU0UV
e794 vpk VRR_VVV0U
e795 vpkls VRR_VVV0U0U
e797 vpks VRR_VVV0U0U
e79e vfnms VRR_VVVU0UV
e79f vfnma VRR_VVVU0UV
e7a1 vmlh VRR_VVV0U
e7a2 vml VRR_VVV0U
e7a3 vmh VRR_VVV0U
e7a4 vmle VRR_VVV0U
e7a5 vmlo VRR_VVV0U
e7a6 vme VRR_VVV0U
e7a7 vmo VRR_VVV0U
e7a9 vmalh VRR_VVVU0V
e7aa vmal VRR_VVVU0V
e7ab vmah VRR_VVVU0V
e7ac vmale VRR_VVVU0V
e7ad vmalo VRR_VVVU0V
e7ae vmae VRR_VVVU0V
e7af vmao VRR_VVVU0V
e7b4 vgfm VRR_VVV0U
e7b8 vmsl VRR_VVVUU0V
e7b9 vaccc VRR_VVVU0V
e7bb vac VRR_VVVU0V
e7bc vgfma VRR_VVVU0V
e7bd vsbcbi VRR_VVVU0V
e7bf vsbi VRR_VVVU0V
e7c0 vclgd VRR_VV0UUU
e7c1 vcdlg VRR_VV0UUU
e7c2 vcgd VRR_VV0UUU
e7c3 vcdg VRR_VV0UUU
e7c4 vlde VRR_VV0UU2
e7c5 vled VRR_VV0UUU
e7c7 vfi VRR_VV0UUU
e7ca wfk VRR_VV0UU2
e7cb wfc VRR_VV0UU2
e7cc vfpso VRR_VV0UUU
e7ce vfsq VRR_VV0UU2
e7d4 vupll VRR_VV0U
e7d5 vuplh VRR_VV0U
e7d6 vupl VRR_VV0U
e7d7 vuph VRR_VV0U
e7d8 vtm VRR_VV
e7d9 vecl VRR_VV0U
e7db vec VRR_VV0U
e7de vlc VRR_VV0U
e7df vlp VRR_VV0U
e7e2 vfs VRR_VVV0UU
e7e3 vfa VRR_VVV0UU
e7e5 vfd VRR_VVV0UU
e7e7 vfm VRR_VVV0UU
e7e8 vfce VRR_VVV0UUU
e7ea vfche VRR_VVV0UUU
e7eb vfch VRR_VVV0UUU
e7ee vfmin VRR_VVV0UUU
e7ef vfmax VRR_VVV0UUU
e7f0 vavgl VRR_VVV0U
e7f1 vacc VRR_VVV0U
e7f2 vavg VRR_VVV0U
e7f3 va VRR_VVV0U
e7f5 vscbi VRR_VVV0U
e7f7 vs VRR_VVV0U
e7f8 vceq VRR_VVV0U0U
e7f9 vchl VRR_VVV0U0U
e7fb vch VRR_VVV0U0U
e7fc vmnl VRR_VVV0U
e7fd vmxl VRR_VVV0U
e7fe vmn VRR_VVV0U
e7ff vmx VRR_VVV0U
e8 mvcin SS_L0RDRD
e9 pka SS_L2RDRD
ea unpka SS_L0RDRD
eb04 lmg RSY_RRRD
eb0a srag RSY_RRRD
eb0b slag RSY_RRRD
eb0c srlg RSY_RRRD
eb0d sllg RSY_RRRD
eb0f tracg RSY_RRRD
eb14 csy RSY_RRRD
eb17 stcctm RSY_RURD
eb1c rllg RSY_RRRD
eb1d rll RSY_RRRD
eb20 clmh RSY_RURD
eb21 clmy RSY_RURD
eb23 clt RSY_RURD
eb24 stmg RSY_RRRD
eb25 stctg RSY_CCRD
eb26 stmh RSY_RRRD
eb2b clgt RSY_RURD
eb2c stcmh RSY_RURD
eb2d stcmy RSY_RURD
eb2f lctlg RSY_CCRD
eb30 csg RSY_RRRD
eb31 cdsy RSY_RRRD
eb3e cdsg RSY_RRRD
eb44 bxhg RSY_RRRD
eb45 bxleg RSY_RRRD
eb4c ecag RSY_RRRD
eb51 tmy SIY_URD
eb52 mviy SIY_URD
eb54 niy SIY_URD
eb55 cliy SIY_URD
eb56 oiy SIY_URD
eb57 xiy SIY_URD
eb60 lric RSY_RDRU
eb61 stric RSY_RDRU
eb62 mric RSY_RDRU
eb6a asi SIY_IRD
eb6e alsi SIY_IRD
eb7a agsi SIY_IRD
eb7e algsi SIY_IRD
eb80 icmh RSY_RURD
eb81 icmy RSY_RURD
eb8e mvclu RSY_RRRD
eb8f clclu RSY_RRRD
eb90 stmy RSY_RRRD
eb96 lmh RSY_RRRD
eb98 lmy RSY_RRRD
eb9a lamy RSY_AARD
eb9b stamy RSY_AARD
ebc0 tp RSL_R0RD
ebd0 pcistb RSY_RRRD
ebd1 sic RSY_RRRD
ebdc srak RSY_RRRD
ebdd slak RSY_RRRD
ebde srlk RSY_RRRD
ebdf sllk RSY_RRRD
ebe0 locfh RSY_RURD2
ebe1 stocfh RSY_RURD2
ebe2 locg RSY_RURD2
ebe3 stocg RSY_RURD2
ebe4 lang RSY_RRRD
ebe6 laog RSY_RRRD
ebe7 laxg RSY_RRRD
ebe8 laag RSY_RRRD
ebea laalg RSY_RRRD
ebf2 loc RSY_RURD2
ebf3 stoc RSY_RURD2
ebf4 lan RSY_RRRD
ebf6 lao RSY_RRRD
ebf7 lax RSY_RRRD
ebf8 laa RSY_RRRD
ebfa laal RSY_RRRD
ec42 lochi RIE_RUI0
ec44 brxhg RIE_RRP
ec45 brxlg RIE_RRP
ec46 locghi RIE_RUI0
ec4e lochhi RIE_RUI0
ec51 risblg RIE_RRUUU
ec54 rnsbg RIE_RRUUU
ec55 risbg RIE_RRUUU
ec56 rosbg RIE_RRUUU
ec57 rxsbg RIE_RRUUU
ec59 risbgn RIE_RRUUU
ec5d risbhg RIE_RRUUU
ec64 cgrj RIE_RRPU
ec65 clgrj RIE_RRPU
ec70 cgit RIE_R0IU
ec71 clgit RIE_R0UU
ec72 cit RIE_R0IU
ec73 clfit RIE_R0UU
ec76 crj RIE_RRPU
ec77 clrj RIE_RRPU
ec7c cgij RIE_RUPI
ec7d clgij RIE_RUPU
ec7e cij RIE_RUPI
ec7f clij RIE_RUPU
ecd8 ahik RIE_RRI0
ecd9 aghik RIE_RRI0
ecda alhsik RIE_RRI0
ecdb alghsik RIE_RRI0
ece4 cgrb RRS_RRRDU
ece5 clgrb RRS_RRRDU
ecf6 crb RRS_RRRDU
ecf7 clrb RRS_RRRDU
ecfc cgib RIS_RURDI
ecfd clgib RIS_RURDU
ecfe cib RIS_RURDI
ecff clib RIS_RURDU
ed04 ldeb RXE_FRRD
ed05 lxdb RXE_FRRD
ed06 lxeb RXE_FRRD
ed07 mxdb RXE_FRRD
ed08 keb RXE_FRRD
ed09 ceb RXE_FRRD
ed0a aeb RXE_FRRD
ed0b seb RXE_FRRD
ed0c mdeb RXE_FRRD
ed0d deb RXE_FRRD
ed0e maeb RXF_FRRDF
ed0f mseb RXF_FRRDF
ed10 tceb RXE_FRRD
ed11 tcdb RXE_FRRD
ed12 tcxb RXE_FRRD
ed14 sqeb RXE_FRRD
ed15 sqdb RXE_FRRD
ed17 meeb RXE_FRRD
ed18 kdb RXE_FRRD
ed19 cdb RXE_FRRD
ed1a adb RXE_FRRD
ed1b sdb RXE_FRRD
ed1c mdb RXE_FRRD
ed1d ddb RXE_FRRD
ed1e madb RXF_FRRDF
ed1f msdb RXF_FRRDF
ed24 lde RXE_FRRD
ed25 lxd RXE_FRRD
ed26 lxe RXE_FRRD
ed2e mae RXF_FRRDF
ed2f mse RXF_FRRDF
ed34 sqe RXE_FRRD
ed35 sqd RXE_FRRD
ed37 mee RXE_FRRD
ed38 mayl RXF_FRRDF
ed39 myl RXF_FRRDF
ed3a may RXF_FRRDF
ed3b my RXF_FRRDF
ed3c mayh RXF_FRRDF
ed3d myh RXF_FRRDF
ed3e mad RXF_FRRDF
ed3f msd RXF_FRRDF
ed40 sldt RXF_FRRDF
ed41 srdt RXF_FRRDF
ed48 slxt RXF_FRRDF
ed49 srxt RXF_FRRDF
ed50 tdcet RXE_FRRD
ed51 tdget RXE_FRRD
ed54 tdcdt RXE_FRRD
ed55 tdgdt RXE_FRRD
ed58 tdcxt RXE_FRRD
ed59 tdgxt RXE_FRRD
ed64 ley RXY_FRRD
ed65 ldy RXY_FRRD
ed66 stey RXY_FRRD
ed67 stdy RXY_FRRD
eda8 czdt RSL_LRDFU
eda9 czxt RSL_LRDFU
edaa cdzt RSL_LRDFU
edab cxzt RSL_LRDFU
edac cpdt RSL_LRDFU
edad cpxt RSL_LRDFU
edae cdpt RSL_LRDFU
edaf cxpt RSL_LRDFU
ee plo SS_RRRDRD2
ef lmd SS_RRRDRD3
f0 srp SS_LIRDRD
f1 mvo SS_LLRDRD
f2 pack SS_LLRDRD
f3 unpk SS_LLRDRD
f8 zap SS_LLRDRD
f9 cp SS_LLRDRD
fa ap SS_LLRDRD
fb sp SS_LLRDRD
fc mp SS_LLRDRD
fd dp SS_LLRDRD
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