Skip to content

L
linux
Commit 8bdbf169 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files
Options

Merge branch 'arm/late' into arm/dt 

Include originally "late" updates for OMAP and Qualcomm,
now that it's not late any more.

* arm/late: (122 commits)
  ARM: OMAP2+: Drop legacy platform data for ti81xx edma
  ARM: dts: Configure interconnect target module for ti816x edma
  ARM: dts: Configure interconnect target module for dm814x tptc3
  ARM: dts: Configure interconnect target module for dm814x tptc2
  ARM: dts: Configure interconnect target module for dm814x tptc1
  ARM: dts: Configure interconnect target module for dm814x tptc0
  ARM: dts: Configure interconnect target module for dm814x tpcc
  ARM: OMAP2+: Drop legacy platform data for dm814x cpsw
  ARM: dts: Configure interconnect target module for dm814x cpsw
  clk: ti: Fix dm814x clkctrl for ethernet
  arm64: dts: qcom: sdm845-mtp: Relocate remoteproc firmware
  arm64: dts: sdm845: add IPA information
  arm64: dts: qcom: db845c: add analog audio support
  arm64: dts: qcom: sdm845: add pinctrl nodes for quat i2s
  arm64: dts: qcom: c630: Enable audio support
  arm64: dts: qcom: sdm845: add apr nodes
  arm64: dts: qcom: sdm845: add slimbus nodes
  arm64: dts: qcom: sc7180: Update reg names for SDHC
  arm64: dts: qcom: qcs404: Enable CQE support for eMMC
  arm64: dts: msm8916: Add fastrpc node
  ...
parents fdd41fac 56effbdd
Hide whitespace changes
Inline Side-by-side
Showing with 4655 additions and 2195 deletions
Documentation/devicetree/bindings/arm/qcom.yaml
View file @ 8bdbf169
...@@ -28,6 +28,7 @@ description: | ...@@ -28,6 +28,7 @@ description: |
apq8074 apq8074
apq8084 apq8084
apq8096 apq8096
ipq6018
ipq8074 ipq8074
mdm9615 mdm9615
msm8916 msm8916
...@@ -41,6 +42,7 @@ description: | ...@@ -41,6 +42,7 @@ description: |
The 'board' element must be one of the following strings: The 'board' element must be one of the following strings:
cdp cdp
cp01-c1
dragonboard dragonboard
hk01 hk01
idp idp
...@@ -150,4 +152,10 @@ properties: ...@@ -150,4 +152,10 @@ properties:
- enum: - enum:
- qcom,sc7180-idp - qcom,sc7180-idp
- const: qcom,sc7180 - const: qcom,sc7180
- items:
- enum:
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
... ...
Documentation/devicetree/bindings/bus/ti-sysc.txt
View file @ 8bdbf169
...@@ -38,6 +38,7 @@ Required standard properties: ...@@ -38,6 +38,7 @@ Required standard properties:
"ti,sysc-dra7-mcasp" "ti,sysc-dra7-mcasp"
"ti,sysc-usb-host-fs" "ti,sysc-usb-host-fs"
"ti,sysc-dra7-mcan" "ti,sysc-dra7-mcan"
"ti,sysc-pruss"
- reg shall have register areas implemented for the interconnect - reg shall have register areas implemented for the interconnect
target module in question such as revision, sysc and syss target module in question such as revision, sysc and syss
......
arch/arm/boot/dts/am33xx-l4.dtsi
View file @ 8bdbf169
...@@ -759,12 +759,27 @@ target-module@200000 { /* 0x4a200000, ap 7 02.0 */ ...@@ -759,12 +759,27 @@ target-module@200000 { /* 0x4a200000, ap 7 02.0 */
ranges = <0x0 0x200000 0x80000>; ranges = <0x0 0x200000 0x80000>;
}; };
target-module@300000 { /* 0x4a300000, ap 9 04.0 */ pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
compatible = "ti,sysc"; compatible = "ti,sysc-pruss", "ti,sysc";
status = "disabled"; reg = <0x326000 0x4>,
<0x326004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
SYSC_PRUSS_SUB_MWAIT)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_per 1>;
reset-names = "rstctrl";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x300000 0x80000>; ranges = <0x0 0x300000 0x80000>;
status = "disabled";
}; };
}; };
}; };
......
arch/arm/boot/dts/am33xx.dtsi
View file @ 8bdbf169
...@@ -205,45 +205,100 @@ intc: interrupt-controller@48200000 { ...@@ -205,45 +205,100 @@ intc: interrupt-controller@48200000 {
reg = <0x48200000 0x1000>; reg = <0x48200000 0x1000>;
}; };
edma: edma@49000000 { target-module@49000000 {
compatible = "ti,edma3-tpcc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tpcc"; reg = <0x49000000 0x4>;
reg = <0x49000000 0x10000>; reg-names = "rev";
reg-names = "edma3_cc"; clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
interrupts = <12 13 14>; clock-names = "fck";
interrupt-names = "edma3_ccint", "edma3_mperr", #address-cells = <1>;
"edma3_ccerrint"; #size-cells = <1>;
dma-requests = <64>; ranges = <0x0 0x49000000 0x10000>;
#dma-cells = <2>;
edma: dma@0 {
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, compatible = "ti,edma3-tpcc";
<&edma_tptc2 0>; reg = <0 0x10000>;
reg-names = "edma3_cc";
ti,edma-memcpy-channels = <20 21>; interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
ti,edma-memcpy-channels = <20 21>;
};
}; };
edma_tptc0: tptc@49800000 { target-module@49800000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc0"; reg = <0x49800000 0x4>,
reg = <0x49800000 0x100000>; <0x49800010 0x4>;
interrupts = <112>; reg-names = "rev", "sysc";
interrupt-names = "edma3_tcerrint"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49800000 0x100000>;
edma_tptc0: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
};
}; };
edma_tptc1: tptc@49900000 { target-module@49900000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc1"; reg = <0x49900000 0x4>,
reg = <0x49900000 0x100000>; <0x49900010 0x4>;
interrupts = <113>; reg-names = "rev", "sysc";
interrupt-names = "edma3_tcerrint"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49900000 0x100000>;
edma_tptc1: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
};
}; };
edma_tptc2: tptc@49a00000 { target-module@49a00000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc2"; reg = <0x49a00000 0x4>,
reg = <0x49a00000 0x100000>; <0x49a00010 0x4>;
interrupts = <114>; reg-names = "rev", "sysc";
interrupt-names = "edma3_tcerrint"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49a00000 0x100000>;
edma_tptc2: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
};
}; };
target-module@47810000 { target-module@47810000 {
......
arch/arm/boot/dts/am4372.dtsi
View file @ 8bdbf169
...@@ -197,47 +197,102 @@ emif: emif@4c000000 { ...@@ -197,47 +197,102 @@ emif: emif@4c000000 {
&pm_sram_data>; &pm_sram_data>;
}; };
edma: edma@49000000 { target-module@49000000 {
compatible = "ti,edma3-tpcc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tpcc"; reg = <0x49000000 0x4>;
reg = <0x49000000 0x10000>; reg-names = "rev";
reg-names = "edma3_cc"; clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, clock-names = "fck";
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, #address-cells = <1>;
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #size-cells = <1>;
interrupt-names = "edma3_ccint", "edma3_mperr", ranges = <0x0 0x49000000 0x10000>;
"edma3_ccerrint";
dma-requests = <64>; edma: dma@0 {
#dma-cells = <2>; compatible = "ti,edma3-tpcc";
reg = <0 0x10000>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, reg-names = "edma3_cc";
<&edma_tptc2 0>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
ti,edma-memcpy-channels = <58 59>; <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
ti,edma-memcpy-channels = <58 59>;
};
}; };
edma_tptc0: tptc@49800000 { target-module@49800000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc0"; reg = <0x49800000 0x4>,
reg = <0x49800000 0x100000>; <0x49800010 0x4>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; reg-names = "rev", "sysc";
interrupt-names = "edma3_tcerrint"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49800000 0x100000>;
edma_tptc0: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
}; };
edma_tptc1: tptc@49900000 { target-module@49900000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc1"; reg = <0x49900000 0x4>,
reg = <0x49900000 0x100000>; <0x49900010 0x4>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; reg-names = "rev", "sysc";
interrupt-names = "edma3_tcerrint"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49900000 0x100000>;
edma_tptc1: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
}; };
edma_tptc2: tptc@49a00000 { target-module@49a00000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc2"; reg = <0x49a00000 0x4>,
reg = <0x49a00000 0x100000>; <0x49a00010 0x4>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; reg-names = "rev", "sysc";
interrupt-names = "edma3_tcerrint"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49a00000 0x100000>;
edma_tptc2: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
}; };
target-module@47810000 { target-module@47810000 {
...@@ -356,6 +411,28 @@ des: des@0 { ...@@ -356,6 +411,28 @@ des: des@0 {
}; };
}; };
pruss_tm: target-module@54400000 {
compatible = "ti,sysc-pruss", "ti,sysc";
reg = <0x54426000 0x4>,
<0x54426004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
SYSC_PRUSS_SUB_MWAIT)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_per 1>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x54400000 0x80000>;
};
gpmc: gpmc@50000000 { gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc"; compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc"; ti,hwmods = "gpmc";
...@@ -406,38 +483,6 @@ qspi: spi@0 { ...@@ -406,38 +483,6 @@ qspi: spi@0 {
}; };
}; };
dss: dss@4832a000 {
compatible = "ti,omap3-dss";
reg = <0x4832a000 0x200>;
status = "disabled";
ti,hwmods = "dss_core";
clocks = <&disp_clk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dispc: dispc@4832a400 {
compatible = "ti,omap3-dispc";
reg = <0x4832a400 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&disp_clk>;
clock-names = "fck";
max-memory-bandwidth = <230000000>;
};
rfbi: rfbi@4832a800 {
compatible = "ti,omap3-rfbi";
reg = <0x4832a800 0x100>;
ti,hwmods = "dss_rfbi";
clocks = <&disp_clk>;
clock-names = "fck";
status = "disabled";
};
};
ocmcram: sram@40300000 { ocmcram: sram@40300000 {
compatible = "mmio-sram"; compatible = "mmio-sram";
reg = <0x40300000 0x40000>; /* 256k */ reg = <0x40300000 0x40000>; /* 256k */
......
arch/arm/boot/dts/am437x-l4.dtsi
View file @ 8bdbf169
...@@ -2117,7 +2117,6 @@ vpfe1: vpfe@0 { ...@@ -2117,7 +2117,6 @@ vpfe1: vpfe@0 {
target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dss_core";
reg = <0x2a000 0x4>, reg = <0x2a000 0x4>,
<0x2a010 0x4>, <0x2a010 0x4>,
<0x2a014 0x4>; <0x2a014 0x4>;
...@@ -2135,6 +2134,82 @@ target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ ...@@ -2135,6 +2134,82 @@ target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
<0x00000800 0x0002a800 0x00000400>, <0x00000800 0x0002a800 0x00000400>,
<0x00000c00 0x0002ac00 0x00000400>, <0x00000c00 0x0002ac00 0x00000400>,
<0x00001000 0x0002b000 0x00001000>; <0x00001000 0x0002b000 0x00001000>;
dss: dss@0 {
compatible = "ti,omap3-dss";
reg = <0 0x200>;
status = "disabled";
clocks = <&disp_clk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x00000400>,
<0x00000400 0x00000400 0x00000400>,
<0x00000800 0x00000800 0x00000400>,
<0x00000c00 0x00000c00 0x00000400>,
<0x00001000 0x00001000 0x00001000>;
target-module@400 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x400 0x4>,
<0x410 0x4>,
<0x414 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x400>;
dispc: dispc@0 {
compatible = "ti,omap3-dispc";
reg = <0 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&disp_clk>;
clock-names = "fck";
max-memory-bandwidth = <230000000>;
};
};
target-module@800 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x800 0x4>,
<0x810 0x4>,
<0x814 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x400>;
rfbi: rfbi@0 {
compatible = "ti,omap3-rfbi";
reg = <0 0x100>;
clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
clock-names = "fck";
status = "disabled";
};
};
};
}; };
target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */ target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
......
arch/arm/boot/dts/am57-pruss.dtsi 0 → 100644
View file @ 8bdbf169
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
*
* Common PRUSS data for TI AM57xx platforms
*/
&ocp {
pruss1_tm: target-module@4b226000 {
compatible = "ti,sysc-pruss", "ti,sysc";
reg = <0x4b226000 0x4>,
<0x4b226004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
SYSC_PRUSS_SUB_MWAIT)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x4b200000 0x80000>;
};
pruss2_tm: target-module@4b2a6000 {
compatible = "ti,sysc-pruss", "ti,sysc";
reg = <0x4b2a6000 0x4>,
<0x4b2a6004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
SYSC_PRUSS_SUB_MWAIT)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x4b280000 0x80000>;
};
};
arch/arm/boot/dts/am5718.dtsi
View file @ 8bdbf169
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
*/ */
#include "dra72x.dtsi" #include "dra72x.dtsi"
#include "am57-pruss.dtsi"
/ { / {
compatible = "ti,am5718", "ti,dra7"; compatible = "ti,am5718", "ti,dra7";
......
arch/arm/boot/dts/am5728.dtsi
View file @ 8bdbf169
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
*/ */
#include "dra74x.dtsi" #include "dra74x.dtsi"
#include "am57-pruss.dtsi"
/ { / {
compatible = "ti,am5728", "ti,dra7"; compatible = "ti,am5728", "ti,dra7";
......
arch/arm/boot/dts/am5748.dtsi
View file @ 8bdbf169
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
*/ */
#include "dra76x.dtsi" #include "dra76x.dtsi"
#include "am57-pruss.dtsi"
/ { / {
compatible = "ti,am5748", "ti,dra762", "ti,dra7"; compatible = "ti,am5748", "ti,dra762", "ti,dra7";
......
arch/arm/boot/dts/dm814x-clocks.dtsi
View file @ 8bdbf169
...@@ -362,4 +362,18 @@ alwon_clkctrl: clk@0 { ...@@ -362,4 +362,18 @@ alwon_clkctrl: clk@0 {
#clock-cells = <2>; #clock-cells = <2>;
}; };
}; };
alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
compatible = "ti,omap4-cm";
reg = <0x15d4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x15d4 0x4>;
alwon_ethernet_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0 0x4>;
#clock-cells = <2>;
};
};
}; };
arch/arm/boot/dts/dm814x.dtsi
View file @ 8bdbf169
...@@ -4,6 +4,8 @@ ...@@ -4,6 +4,8 @@
* kind, whether express or implied. * kind, whether express or implied.
*/ */
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/dm814.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/dm814x.h> #include <dt-bindings/pinctrl/dm814x.h>
...@@ -519,53 +521,123 @@ mmc3: mmc@47810000 { ...@@ -519,53 +521,123 @@ mmc3: mmc@47810000 {
reg = <0x47810000 0x1000>; reg = <0x47810000 0x1000>;
}; };
edma: edma@49000000 { target-module@49000000 {
compatible = "ti,edma3-tpcc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tpcc"; reg = <0x49000000 0x4>;
reg = <0x49000000 0x10000>; reg-names = "rev";
reg-names = "edma3_cc"; clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;
interrupts = <12 13 14>; clock-names = "fck";
interrupt-names = "edma3_ccint", "edma3_mperr", #address-cells = <1>;
"edma3_ccerrint"; #size-cells = <1>;
dma-requests = <64>; ranges = <0x0 0x49000000 0x10000>;
#dma-cells = <2>;
edma: dma@0 {
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, compatible = "ti,edma3-tpcc";
<&edma_tptc2 3>, <&edma_tptc3 0>; reg = <0 0x10000>;
reg-names = "edma3_cc";
ti,edma-memcpy-channels = <20 21>; interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 3>, <&edma_tptc3 0>;
ti,edma-memcpy-channels = <20 21>;
};
}; };
edma_tptc0: tptc@49800000 { target-module@49800000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc0"; reg = <0x49800000 0x4>,
reg = <0x49800000 0x100000>; <0x49800010 0x4>;
interrupts = <112>; reg-names = "rev", "sysc";
interrupt-names = "edma3_tcerrint"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49800000 0x100000>;
edma_tptc0: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
};
}; };
edma_tptc1: tptc@49900000 { target-module@49900000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc1"; reg = <0x49900000 0x4>,
reg = <0x49900000 0x100000>; <0x49900010 0x4>;
interrupts = <113>; reg-names = "rev", "sysc";
interrupt-names = "edma3_tcerrint"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49900000 0x100000>;
edma_tptc1: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
};
}; };
edma_tptc2: tptc@49a00000 { target-module@49a00000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc2"; reg = <0x49a00000 0x4>,
reg = <0x49a00000 0x100000>; <0x49a00010 0x4>;
interrupts = <114>; reg-names = "rev", "sysc";
interrupt-names = "edma3_tcerrint"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49a00000 0x100000>;
edma_tptc2: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
};
}; };
edma_tptc3: tptc@49b00000 { target-module@49b00000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc3"; reg = <0x49b00000 0x4>,
reg = <0x49b00000 0x100000>; <0x49b00010 0x4>;
interrupts = <115>; reg-names = "rev", "sysc";
interrupt-names = "edma3_tcerrint"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49b00000 0x100000>;
edma_tptc3: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <115>;
interrupt-names = "edma3_tcerrint";
};
}; };
/* See TRM "Table 1-318. L4HS Instance Summary" */ /* See TRM "Table 1-318. L4HS Instance Summary" */
...@@ -574,57 +646,73 @@ l4hs: l4hs@4a000000 { ...@@ -574,57 +646,73 @@ l4hs: l4hs@4a000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0x4a000000 0x1b4040>; ranges = <0 0x4a000000 0x1b4040>;
};
/* REVISIT: Move to live under l4hs once driver is fixed */ target-module@100000 {
mac: ethernet@4a100000 { compatible = "ti,sysc-omap4-simple", "ti,sysc";
compatible = "ti,cpsw"; reg = <0x100900 0x4>,
ti,hwmods = "cpgmac0"; <0x100908 0x4>,
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; <0x100904 0x4>;
clock-names = "fck", "cpts"; reg-names = "rev", "sysc", "syss";
cpdma_channels = <8>; ti,sysc-mask = <0>;
ale_entries = <1024>; ti,sysc-midle = <SYSC_IDLE_FORCE>,
bd_ram_size = <0x2000>; <SYSC_IDLE_NO>;
mac_control = <0x20>; ti,sysc-sidle = <SYSC_IDLE_FORCE>,
slaves = <2>; <SYSC_IDLE_NO>;
active_slave = <0>; ti,syss-mask = <1>;
cpts_clock_mult = <0x80000000>; clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
cpts_clock_shift = <29>; clock-names = "fck";
reg = <0x4a100000 0x800
0x4a100900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
* c0_tx_pend
* c0_misc_pend
*/
interrupts = <40 41 42 43>;
ranges;
syscon = <&scm_conf>;
davinci_mdio: mdio@4a100800 {
compatible = "ti,davinci_mdio";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <1>;
ti,hwmods = "davinci_mdio"; ranges = <0 0x100000 0x8000>;
bus_freq = <1000000>;
reg = <0x4a100800 0x100>; mac: ethernet@0 {
}; compatible = "ti,cpsw";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
cpsw_emac0: slave@4a100200 { clock-names = "fck", "cpts";
/* Filled in by U-Boot */ cpdma_channels = <8>;
mac-address = [ 00 00 00 00 00 00 ]; ale_entries = <1024>;
phys = <&phy_gmii_sel 1>; bd_ram_size = <0x2000>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0 0x800>,
<0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
* c0_tx_pend
* c0_misc_pend
*/
interrupts = <40 41 42 43>;
ranges = <0 0 0x8000>;
syscon = <&scm_conf>;
davinci_mdio: mdio@800 {
compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
reg = <0x800 0x100>;
};
}; cpsw_emac0: slave@200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 1>;
};
cpsw_emac1: slave@4a100300 { cpsw_emac1: slave@300 {
/* Filled in by U-Boot */ /* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ]; mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 2>; phys = <&phy_gmii_sel 2>;
};
};
}; };
}; };
......
arch/arm/boot/dts/dm816x.dtsi
View file @ 8bdbf169
...@@ -4,6 +4,8 @@ ...@@ -4,6 +4,8 @@
* kind, whether express or implied. * kind, whether express or implied.
*/ */
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/dm816.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/omap.h> #include <dt-bindings/pinctrl/omap.h>
...@@ -138,13 +140,123 @@ scrm_clockdomains: clockdomains { ...@@ -138,13 +140,123 @@ scrm_clockdomains: clockdomains {
}; };
}; };
edma: edma@49000000 { target-module@49000000 {
compatible = "ti,edma3"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3"; reg = <0x49000000 0x4>;
reg = <0x49000000 0x10000>, reg-names = "rev";
<0x44e10f90 0x40>; clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
interrupts = <12 13 14>; clock-names = "fck";
#dma-cells = <1>; #address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49000000 0x10000>;
edma: dma@0 {
compatible = "ti,edma3-tpcc";
reg = <0 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 3>, <&edma_tptc3 0>;
ti,edma-memcpy-channels = <20 21>;
};
};
target-module@49800000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49800000 0x4>,
<0x49800010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49800000 0x100000>;
edma_tptc0: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
};
};
target-module@49900000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49900000 0x4>,
<0x49900010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49900000 0x100000>;
edma_tptc1: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
};
};
target-module@49a00000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49a00000 0x4>,
<0x49a00010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49a00000 0x100000>;
edma_tptc2: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
};
};
target-module@49b00000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49b00000 0x4>,
<0x49b00010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49b00000 0x100000>;
edma_tptc3: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <115>;
interrupt-names = "edma3_tcerrint";
};
}; };
elm: elm@48080000 { elm: elm@48080000 {
...@@ -185,7 +297,7 @@ gpmc: gpmc@50000000 { ...@@ -185,7 +297,7 @@ gpmc: gpmc@50000000 {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
interrupts = <100>; interrupts = <100>;
dmas = <&edma 52>; dmas = <&edma 52 0>;
dma-names = "rxtx"; dma-names = "rxtx";
gpmc,num-cs = <6>; gpmc,num-cs = <6>;
gpmc,num-waitpins = <2>; gpmc,num-waitpins = <2>;
...@@ -202,7 +314,7 @@ i2c1: i2c@48028000 { ...@@ -202,7 +314,7 @@ i2c1: i2c@48028000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <70>; interrupts = <70>;
dmas = <&edma 58 &edma 59>; dmas = <&edma 58 0 &edma 59 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
...@@ -213,7 +325,7 @@ i2c2: i2c@4802a000 { ...@@ -213,7 +325,7 @@ i2c2: i2c@4802a000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <71>; interrupts = <71>;
dmas = <&edma 60 &edma 61>; dmas = <&edma 60 0 &edma 61 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
...@@ -311,10 +423,10 @@ mcspi1: spi@48030000 { ...@@ -311,10 +423,10 @@ mcspi1: spi@48030000 {
interrupts = <65>; interrupts = <65>;
ti,spi-num-cs = <4>; ti,spi-num-cs = <4>;
ti,hwmods = "mcspi1"; ti,hwmods = "mcspi1";
dmas = <&edma 16 &edma 17 dmas = <&edma 16 0 &edma 17 0
&edma 18 &edma 19 &edma 18 0 &edma 19 0
&edma 20 &edma 21 &edma 20 0 &edma 21 0
&edma 22 &edma 23>; &edma 22 0 &edma 23 0>;
dma-names = "tx0", "rx0", "tx1", "rx1", dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3"; "tx2", "rx2", "tx3", "rx3";
}; };
...@@ -324,7 +436,7 @@ mmc1: mmc@48060000 { ...@@ -324,7 +436,7 @@ mmc1: mmc@48060000 {
reg = <0x48060000 0x11000>; reg = <0x48060000 0x11000>;
ti,hwmods = "mmc1"; ti,hwmods = "mmc1";
interrupts = <64>; interrupts = <64>;
dmas = <&edma 24 &edma 25>; dmas = <&edma 24 0 &edma 25 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
...@@ -392,7 +504,7 @@ uart1: uart@48020000 { ...@@ -392,7 +504,7 @@ uart1: uart@48020000 {
reg = <0x48020000 0x2000>; reg = <0x48020000 0x2000>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
interrupts = <72>; interrupts = <72>;
dmas = <&edma 26 &edma 27>; dmas = <&edma 26 0 &edma 27 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
...@@ -402,7 +514,7 @@ uart2: uart@48022000 { ...@@ -402,7 +514,7 @@ uart2: uart@48022000 {
reg = <0x48022000 0x2000>; reg = <0x48022000 0x2000>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
interrupts = <73>; interrupts = <73>;
dmas = <&edma 28 &edma 29>; dmas = <&edma 28 0 &edma 29 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
...@@ -412,7 +524,7 @@ uart3: uart@48024000 { ...@@ -412,7 +524,7 @@ uart3: uart@48024000 {
reg = <0x48024000 0x2000>; reg = <0x48024000 0x2000>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
interrupts = <74>; interrupts = <74>;
dmas = <&edma 30 &edma 31>; dmas = <&edma 30 0 &edma 31 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
......
arch/arm/boot/dts/dra62x.dtsi
View file @ 8bdbf169
...@@ -12,12 +12,12 @@ / { ...@@ -12,12 +12,12 @@ / {
/* Compared to dm814x, dra62x has different offsets for Ethernet */ /* Compared to dm814x, dra62x has different offsets for Ethernet */
&mac { &mac {
reg = <0x4a100000 0x800 reg = <0 0x800>,
0x4a101200 0x100>; <0x1200 0x100>;
}; };
&davinci_mdio { &davinci_mdio {
reg = <0x4a101000 0x100>; reg = <0x1000 0x100>;
}; };
#include "dra62x-clocks.dtsi" #include "dra62x-clocks.dtsi"
arch/arm/boot/dts/dra7.dtsi
View file @ 8bdbf169
...@@ -143,7 +143,7 @@ mpu { ...@@ -143,7 +143,7 @@ mpu {
* the moment, just use a fake OCP bus entry to represent the whole bus * the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy. * hierarchy.
*/ */
ocp { ocp: ocp {
compatible = "ti,dra7-l3-noc", "simple-bus"; compatible = "ti,dra7-l3-noc", "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -331,43 +331,73 @@ dra7_iodelay_core: padconf@4844a000 { ...@@ -331,43 +331,73 @@ dra7_iodelay_core: padconf@4844a000 {
#pinctrl-cells = <2>; #pinctrl-cells = <2>;
}; };
edma: edma@43300000 { target-module@43300000 {
compatible = "ti,edma3-tpcc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tpcc"; reg = <0x43300000 0x4>;
reg = <0x43300000 0x100000>; reg-names = "rev";
reg-names = "edma3_cc"; clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, clock-names = "fck";
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, #address-cells = <1>;
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; #size-cells = <1>;
interrupt-names = "edma3_ccint", "edma3_mperr", ranges = <0x0 0x43300000 0x100000>;
"edma3_ccerrint";
dma-requests = <64>; edma: dma@0 {
#dma-cells = <2>; compatible = "ti,edma3-tpcc";
reg = <0 0x100000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
/*
* memcpy is disabled, can be enabled with:
* ti,edma-memcpy-channels = <20 21>;
* for example. Note that these channels need to be
* masked in the xbar as well.
*/
};
};
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; target-module@43400000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x43400000 0x4>;
reg-names = "rev";
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x43400000 0x100000>;
/* edma_tptc0: dma@0 {
* memcpy is disabled, can be enabled with: compatible = "ti,edma3-tptc";
* ti,edma-memcpy-channels = <20 21>; reg = <0 0x100000>;
* for example. Note that these channels need to be interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
* masked in the xbar as well. interrupt-names = "edma3_tcerrint";
*/ };
}; };
edma_tptc0: tptc@43400000 { target-module@43500000 {
compatible = "ti,edma3-tptc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "tptc0"; reg = <0x43500000 0x4>;
reg = <0x43400000 0x100000>; reg-names = "rev";
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
interrupt-names = "edma3_tcerrint"; clock-names = "fck";
}; #address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x43500000 0x100000>;
edma_tptc1: tptc@43500000 { edma_tptc1: dma@0 {
compatible = "ti,edma3-tptc"; compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1"; reg = <0 0x100000>;
reg = <0x43500000 0x100000>; interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "edma3_tcerrint";
interrupt-names = "edma3_tcerrint"; };
}; };
dmm@4e000000 { dmm@4e000000 {
...@@ -705,44 +735,99 @@ crossbar_mpu: crossbar@4a002a48 { ...@@ -705,44 +735,99 @@ crossbar_mpu: crossbar@4a002a48 {
ti,irqs-safe-map = <0>; ti,irqs-safe-map = <0>;
}; };
dss: dss@58000000 { target-module@58000000 {
compatible = "ti,dra7-dss"; compatible = "ti,sysc-omap2", "ti,sysc";
/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ reg = <0x58000000 4>,
/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ <0x58000014 4>;
status = "disabled"; reg-names = "rev", "syss";
ti,hwmods = "dss_core"; ti,syss-mask = <1>;
/* CTRL_CORE_DSS_PLL_CONTROL */ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
syscon-pll-ctrl = <&scm_conf 0x538>; <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>;
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges; ranges = <0 0x58000000 0x800000>;
dispc@58001000 {
compatible = "ti,dra7-dispc";
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
/* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>;
};
hdmi: encoder@58060000 { dss: dss@0 {
compatible = "ti,dra7-hdmi"; compatible = "ti,dra7-dss";
reg = <0x58040000 0x200>, /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
<0x58040200 0x80>, /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
<0x58040300 0x80>,
<0x58060000 0x19000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
ti,hwmods = "dss_hdmi"; /* CTRL_CORE_DSS_PLL_CONTROL */
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, syscon-pll-ctrl = <&scm_conf 0x538>;
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; #address-cells = <1>;
clock-names = "fck", "sys_clk"; #size-cells = <1>;
dmas = <&sdma_xbar 76>; ranges = <0 0 0x800000>;
dma-names = "audio_tx";
target-module@1000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x1000 0x4>,
<0x1010 0x4>,
<0x1014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x1000>;
dispc@0 {
compatible = "ti,dra7-dispc";
reg = <0 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
/* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>;
};
};
target-module@40000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x40000 0x4>,
<0x40010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clock-names = "fck", "dss_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40000 0x40000>;
hdmi: encoder@0 {
compatible = "ti,dra7-hdmi";
reg = <0 0x200>,
<0x200 0x80>,
<0x300 0x80>,
<0x20000 0x19000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma_xbar 76>;
dma-names = "audio_tx";
};
};
}; };
}; };
......
arch/arm/boot/dts/dra72x.dtsi
View file @ 8bdbf169
...@@ -60,9 +60,9 @@ csi2_1: port@1 { ...@@ -60,9 +60,9 @@ csi2_1: port@1 {
}; };
&dss { &dss {
reg = <0x58000000 0x80>, reg = <0 0x80>,
<0x58004054 0x4>, <0x4054 0x4>,
<0x58004300 0x20>; <0x4300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1"; reg-names = "dss", "pll1_clkctrl", "pll1";
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
......
arch/arm/boot/dts/dra74x.dtsi
View file @ 8bdbf169
...@@ -132,11 +132,11 @@ &cpu0_opp_table { ...@@ -132,11 +132,11 @@ &cpu0_opp_table {
}; };
&dss { &dss {
reg = <0x58000000 0x80>, reg = <0 0x80>,
<0x58004054 0x4>, <0x4054 0x4>,
<0x58004300 0x20>, <0x4300 0x20>,
<0x58009054 0x4>, <0x9054 0x4>,
<0x58009300 0x20>; <0x9300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1", reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2"; "pll2_clkctrl", "pll2";
......
arch/arm/boot/dts/omap4-l4.dtsi
View file @ 8bdbf169
...@@ -1529,6 +1529,7 @@ timer9: timer@0 { ...@@ -1529,6 +1529,7 @@ timer9: timer@0 {
}; };
}; };
/* Unused DSS L4 access, see L3 instead */
target-module@40000 { /* 0x48040000, ap 13 0a.0 */ target-module@40000 { /* 0x48040000, ap 13 0a.0 */
compatible = "ti,sysc"; compatible = "ti,sysc";
status = "disabled"; status = "disabled";
......
arch/arm/boot/dts/omap4.dtsi
View file @ 8bdbf169
...@@ -108,7 +108,6 @@ mpu { ...@@ -108,7 +108,6 @@ mpu {
dsp { dsp {
compatible = "ti,omap3-c64"; compatible = "ti,omap3-c64";
ti,hwmods = "dsp";
}; };
iva { iva {
...@@ -415,87 +414,213 @@ target-module@56000000 { ...@@ -415,87 +414,213 @@ target-module@56000000 {
*/ */
}; };
dss: dss@58000000 { /*
compatible = "ti,omap4-dss"; * DSS is only using l3 mapping without l4 as noted in the TRM
reg = <0x58000000 0x80>; * "10.1.3 DSS Register Manual" for omap4460.
status = "disabled"; */
ti,hwmods = "dss_core"; target-module@58000000 {
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; compatible = "ti,sysc-omap2", "ti,sysc";
clock-names = "fck"; reg = <0x58000000 4>,
<0x58000014 4>;
reg-names = "rev", "syss";
ti,syss-mask = <1>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges; ranges = <0 0x58000000 0x1000000>;
dispc@58001000 {
compatible = "ti,omap4-dispc";
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
rfbi: encoder@58002000 {
compatible = "ti,omap4-rfbi";
reg = <0x58002000 0x1000>;
status = "disabled";
ti,hwmods = "dss_rfbi";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
clock-names = "fck", "ick";
};
venc: encoder@58003000 { dss: dss@0 {
compatible = "ti,omap4-venc"; compatible = "ti,omap4-dss";
reg = <0x58003000 0x1000>; reg = <0 0x80>;
status = "disabled"; status = "disabled";
ti,hwmods = "dss_venc"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck"; clock-names = "fck";
}; #address-cells = <1>;
#size-cells = <1>;
dsi1: encoder@58004000 { ranges = <0 0 0x1000000>;
compatible = "ti,omap4-dsi";
reg = <0x58004000 0x200>, target-module@1000 {
<0x58004200 0x40>, compatible = "ti,sysc-omap2", "ti,sysc";
<0x58004300 0x20>; reg = <0x1000 0x4>,
reg-names = "proto", "phy", "pll"; <0x1010 0x4>,
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; <0x1014 0x4>;
status = "disabled"; reg-names = "rev", "sysc", "syss";
ti,hwmods = "dss_dsi1"; ti,sysc-sidle = <SYSC_IDLE_FORCE>,
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <SYSC_IDLE_NO>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; <SYSC_IDLE_SMART>;
clock-names = "fck", "sys_clk"; ti,sysc-midle = <SYSC_IDLE_FORCE>,
}; <SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
dsi2: encoder@58005000 { ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
compatible = "ti,omap4-dsi"; SYSC_OMAP2_ENAWAKEUP |
reg = <0x58005000 0x200>, SYSC_OMAP2_SOFTRESET |
<0x58005200 0x40>, SYSC_OMAP2_AUTOIDLE)>;
<0x58005300 0x20>; ti,syss-mask = <1>;
reg-names = "proto", "phy", "pll"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
status = "disabled"; clock-names = "fck", "sys_clk";
ti,hwmods = "dss_dsi2"; #address-cells = <1>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, #size-cells = <1>;
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; ranges = <0 0x1000 0x1000>;
clock-names = "fck", "sys_clk";
}; dispc@0 {
compatible = "ti,omap4-dispc";
hdmi: encoder@58006000 { reg = <0 0x1000>;
compatible = "ti,omap4-hdmi"; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x58006000 0x200>, clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
<0x58006200 0x100>, clock-names = "fck";
<0x58006300 0x100>, };
<0x58006400 0x1000>; };
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; target-module@2000 {
status = "disabled"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dss_hdmi"; reg = <0x2000 0x4>,
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, <0x2010 0x4>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; <0x2014 0x4>;
clock-names = "fck", "sys_clk"; reg-names = "rev", "sysc", "syss";
dmas = <&sdma 76>; ti,sysc-sidle = <SYSC_IDLE_FORCE>,
dma-names = "audio_tx"; <SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x1000>;
rfbi: encoder@0 {
reg = <0 0x1000>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
clock-names = "fck", "ick";
};
};
target-module@3000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x3000 0x4>;
reg-names = "rev";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "sys_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x3000 0x1000>;
venc: encoder@0 {
compatible = "ti,omap4-venc";
reg = <0 0x1000>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck";
};
};
target-module@4000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4000 0x4>,
<0x4010 0x4>,
<0x4014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4000 0x1000>;
dsi1: encoder@0 {
compatible = "ti,omap4-dsi";
reg = <0 0x200>,
<0x200 0x40>,
<0x300 0x20>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
};
target-module@5000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x5000 0x4>,
<0x5010 0x4>,
<0x5014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5000 0x1000>;
dsi2: encoder@0 {
compatible = "ti,omap4-dsi";
reg = <0 0x200>,
<0x200 0x40>,
<0x300 0x20>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
};
target-module@6000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x6000 0x4>,
<0x6010 0x4>;
reg-names = "rev", "sysc";
/*
* Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
* but HDMI audio will fail with them.
*/
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck", "dss_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x6000 0x2000>;
hdmi: encoder@0 {
compatible = "ti,omap4-hdmi";
reg = <0 0x200>,
<0x200 0x100>,
<0x300 0x100>,
<0x400 0x1000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
};
};
}; };
}; };
}; };
......
arch/arm/boot/dts/omap5.dtsi
View file @ 8bdbf169
...@@ -292,78 +292,185 @@ target-module@56000000 { ...@@ -292,78 +292,185 @@ target-module@56000000 {
*/ */
}; };
dss: dss@58000000 { target-module@58000000 {
compatible = "ti,omap5-dss"; compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x58000000 0x80>; reg = <0x58000000 4>,
status = "disabled"; <0x58000014 4>;
ti,hwmods = "dss_core"; reg-names = "rev", "syss";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; ti,syss-mask = <1>;
clock-names = "fck"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges; ranges = <0 0x58000000 0x1000000>;
dispc@58001000 { dss: dss@0 {
compatible = "ti,omap5-dispc"; compatible = "ti,omap5-dss";
reg = <0x58001000 0x1000>; reg = <0 0x80>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; status = "disabled";
ti,hwmods = "dss_dispc";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck"; clock-names = "fck";
}; #address-cells = <1>;
#size-cells = <1>;
rfbi: encoder@58002000 { ranges = <0 0 0x1000000>;
compatible = "ti,omap5-rfbi";
reg = <0x58002000 0x100>; target-module@1000 {
status = "disabled"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dss_rfbi"; reg = <0x1000 0x4>,
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; <0x1010 0x4>,
clock-names = "fck", "ick"; <0x1014 0x4>;
}; reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
dsi1: encoder@58004000 { <SYSC_IDLE_NO>,
compatible = "ti,omap5-dsi"; <SYSC_IDLE_SMART>;
reg = <0x58004000 0x200>, ti,sysc-midle = <SYSC_IDLE_FORCE>,
<0x58004200 0x40>, <SYSC_IDLE_NO>,
<0x58004300 0x40>; <SYSC_IDLE_SMART>;
reg-names = "proto", "phy", "pll"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; SYSC_OMAP2_ENAWAKEUP |
status = "disabled"; SYSC_OMAP2_SOFTRESET |
ti,hwmods = "dss_dsi1"; SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, ti,syss-mask = <1>;
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck", "sys_clk"; clock-names = "fck";
}; #address-cells = <1>;
#size-cells = <1>;
dsi2: encoder@58005000 { ranges = <0 0x1000 0x1000>;
compatible = "ti,omap5-dsi";
reg = <0x58009000 0x200>, dispc@0 {
<0x58009200 0x40>, compatible = "ti,omap5-dispc";
<0x58009300 0x40>; reg = <0 0x1000>;
reg-names = "proto", "phy", "pll"; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
status = "disabled"; clock-names = "fck";
ti,hwmods = "dss_dsi2"; };
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, };
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk"; target-module@2000 {
}; compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2000 0x4>,
hdmi: encoder@58060000 { <0x2010 0x4>,
compatible = "ti,omap5-hdmi"; <0x2014 0x4>;
reg = <0x58040000 0x200>, reg-names = "rev", "sysc", "syss";
<0x58040200 0x80>, ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<0x58040300 0x80>, <SYSC_IDLE_NO>,
<0x58060000 0x19000>; <SYSC_IDLE_SMART>;
reg-names = "wp", "pll", "phy", "core"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; SYSC_OMAP2_AUTOIDLE)>;
status = "disabled"; ti,syss-mask = <1>;
ti,hwmods = "dss_hdmi"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, clock-names = "fck";
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; #address-cells = <1>;
clock-names = "fck", "sys_clk"; #size-cells = <1>;
dmas = <&sdma 76>; ranges = <0 0x2000 0x1000>;
dma-names = "audio_tx";
rfbi: encoder@0 {
compatible = "ti,omap5-rfbi";
reg = <0 0x100>;
status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
clock-names = "fck", "ick";
};
};
target-module@5000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x5000 0x4>,
<0x5010 0x4>,
<0x5014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5000 0x1000>;
dsi1: encoder@0 {
compatible = "ti,omap5-dsi";
reg = <0 0x200>,
<0x200 0x40>,
<0x300 0x40>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
};
target-module@9000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x9000 0x4>,
<0x9010 0x4>,
<0x9014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x9000 0x1000>;
dsi2: encoder@0 {
compatible = "ti,omap5-dsi";
reg = <0 0x200>,
<0x200 0x40>,
<0x300 0x40>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
};
target-module@40000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x40000 0x4>,
<0x40010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck", "dss_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40000 0x40000>;
hdmi: encoder@0 {
compatible = "ti,omap5-hdmi";
reg = <0 0x200>,
<0x200 0x80>,
<0x300 0x80>,
<0x20000 0x19000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
};
};
}; };
}; };
......
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
View file @ 8bdbf169
...@@ -24,16 +24,11 @@ extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup; ...@@ -24,16 +24,11 @@ extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup;
extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr; extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr;
extern struct omap_hwmod_ocp_if am33xx_mpu__prcm; extern struct omap_hwmod_ocp_if am33xx_mpu__prcm;
extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main; extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main;
extern struct omap_hwmod_ocp_if am33xx_pruss__l3_main;
extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main; extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main;
extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx; extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc; extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc; extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2; extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
extern struct omap_hwmod_ocp_if am33xx_l3_main__tpcc;
extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc0;
extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc1;
extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2;
extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc; extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
extern struct omap_hwmod am33xx_l3_main_hwmod; extern struct omap_hwmod am33xx_l3_main_hwmod;
...@@ -42,7 +37,6 @@ extern struct omap_hwmod am33xx_l3_instr_hwmod; ...@@ -42,7 +37,6 @@ extern struct omap_hwmod am33xx_l3_instr_hwmod;
extern struct omap_hwmod am33xx_l4_ls_hwmod; extern struct omap_hwmod am33xx_l4_ls_hwmod;
extern struct omap_hwmod am33xx_l4_wkup_hwmod; extern struct omap_hwmod am33xx_l4_wkup_hwmod;
extern struct omap_hwmod am33xx_mpu_hwmod; extern struct omap_hwmod am33xx_mpu_hwmod;
extern struct omap_hwmod am33xx_pruss_hwmod;
extern struct omap_hwmod am33xx_gfx_hwmod; extern struct omap_hwmod am33xx_gfx_hwmod;
extern struct omap_hwmod am33xx_prcm_hwmod; extern struct omap_hwmod am33xx_prcm_hwmod;
extern struct omap_hwmod am33xx_ocmcram_hwmod; extern struct omap_hwmod am33xx_ocmcram_hwmod;
...@@ -52,10 +46,6 @@ extern struct omap_hwmod am33xx_gpmc_hwmod; ...@@ -52,10 +46,6 @@ extern struct omap_hwmod am33xx_gpmc_hwmod;
extern struct omap_hwmod am33xx_rtc_hwmod; extern struct omap_hwmod am33xx_rtc_hwmod;
extern struct omap_hwmod am33xx_timer1_hwmod; extern struct omap_hwmod am33xx_timer1_hwmod;
extern struct omap_hwmod am33xx_timer2_hwmod; extern struct omap_hwmod am33xx_timer2_hwmod;
extern struct omap_hwmod am33xx_tpcc_hwmod;
extern struct omap_hwmod am33xx_tptc0_hwmod;
extern struct omap_hwmod am33xx_tptc1_hwmod;
extern struct omap_hwmod am33xx_tptc2_hwmod;
extern struct omap_hwmod_class am33xx_emif_hwmod_class; extern struct omap_hwmod_class am33xx_emif_hwmod_class;
extern struct omap_hwmod_class am33xx_l4_hwmod_class; extern struct omap_hwmod_class am33xx_l4_hwmod_class;
......
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View file @ 8bdbf169
...@@ -74,14 +74,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { ...@@ -74,14 +74,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* pru-icss -> l3 main */
struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
.master = &am33xx_pruss_hwmod,
.slave = &am33xx_l3_main_hwmod,
.clk = "l3_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* gfx -> l3 main */ /* gfx -> l3 main */
struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
.master = &am33xx_gfx_hwmod, .master = &am33xx_gfx_hwmod,
...@@ -122,38 +114,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { ...@@ -122,38 +114,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l3 main -> tpcc */
struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_tpcc_hwmod,
.clk = "l3_gclk",
.user = OCP_USER_MPU,
};
/* l3 main -> tpcc0 */
struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_tptc0_hwmod,
.clk = "l3_gclk",
.user = OCP_USER_MPU,
};
/* l3 main -> tpcc1 */
struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_tptc1_hwmod,
.clk = "l3_gclk",
.user = OCP_USER_MPU,
};
/* l3 main -> tpcc2 */
struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_tptc2_hwmod,
.clk = "l3_gclk",
.user = OCP_USER_MPU,
};
/* l3 main -> ocmc */ /* l3 main -> ocmc */
struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
.master = &am33xx_l3_main_hwmod, .master = &am33xx_l3_main_hwmod,
......
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View file @ 8bdbf169
...@@ -133,34 +133,6 @@ struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { ...@@ -133,34 +133,6 @@ struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
.name = "wkup_m3", .name = "wkup_m3",
}; };
/*
* 'pru-icss' class
* Programmable Real-Time Unit and Industrial Communication Subsystem
*/
static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
.name = "pruss",
};
static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
{ .name = "pruss", .rst_shift = 1 },
};
/* pru-icss */
/* Pseudo hwmod for reset control purpose only */
struct omap_hwmod am33xx_pruss_hwmod = {
.name = "pruss",
.class = &am33xx_pruss_hwmod_class,
.clkdm_name = "pruss_ocp_clkdm",
.main_clk = "pruss_ocp_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
.rst_lines = am33xx_pruss_resets,
.rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
};
/* gfx */ /* gfx */
/* Pseudo hwmod for reset control purpose only */ /* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod_class am33xx_gfx_hwmod_class = { static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
...@@ -393,80 +365,6 @@ struct omap_hwmod am33xx_timer2_hwmod = { ...@@ -393,80 +365,6 @@ struct omap_hwmod am33xx_timer2_hwmod = {
}, },
}; };
/* tpcc */
static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
.name = "tpcc",
};
struct omap_hwmod am33xx_tpcc_hwmod = {
.name = "tpcc",
.class = &am33xx_tpcc_hwmod_class,
.clkdm_name = "l3_clkdm",
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x10,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_MIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
.sysc_fields = &omap_hwmod_sysc_type2,
};
/* 'tptc' class */
static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
.name = "tptc",
.sysc = &am33xx_tptc_sysc,
};
/* tptc0 */
struct omap_hwmod am33xx_tptc0_hwmod = {
.name = "tptc0",
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* tptc1 */
struct omap_hwmod am33xx_tptc1_hwmod = {
.name = "tptc1",
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* tptc2 */
struct omap_hwmod am33xx_tptc2_hwmod = {
.name = "tptc2",
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static void omap_hwmod_am33xx_clkctrl(void) static void omap_hwmod_am33xx_clkctrl(void)
{ {
CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET); CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
...@@ -481,12 +379,7 @@ static void omap_hwmod_am33xx_clkctrl(void) ...@@ -481,12 +379,7 @@ static void omap_hwmod_am33xx_clkctrl(void)
CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET); CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET); CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
...@@ -494,7 +387,6 @@ static void omap_hwmod_am33xx_clkctrl(void) ...@@ -494,7 +387,6 @@ static void omap_hwmod_am33xx_clkctrl(void)
static void omap_hwmod_am33xx_rst(void) static void omap_hwmod_am33xx_rst(void)
{ {
RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET); RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET); RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
} }
...@@ -518,12 +410,7 @@ static void omap_hwmod_am43xx_clkctrl(void) ...@@ -518,12 +410,7 @@ static void omap_hwmod_am43xx_clkctrl(void)
CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET); CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET); CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
...@@ -531,9 +418,7 @@ static void omap_hwmod_am43xx_clkctrl(void) ...@@ -531,9 +418,7 @@ static void omap_hwmod_am43xx_clkctrl(void)
static void omap_hwmod_am43xx_rst(void) static void omap_hwmod_am43xx_rst(void)
{ {
RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET); RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET); RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
} }
......
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View file @ 8bdbf169
...@@ -233,14 +233,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { ...@@ -233,14 +233,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 hs -> pru-icss */
static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
.master = &am33xx_l4_hs_hwmod,
.slave = &am33xx_pruss_hwmod,
.clk = "dpll_core_m4_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main -> debugss */ /* l3_main -> debugss */
static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = { static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
.master = &am33xx_l3_main_hwmod, .master = &am33xx_l3_main_hwmod,
...@@ -292,7 +284,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { ...@@ -292,7 +284,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__l3_instr, &am33xx_l3_main__l3_instr,
&am33xx_l3_main__gfx, &am33xx_l3_main__gfx,
&am33xx_l3_s__l3_main, &am33xx_l3_s__l3_main,
&am33xx_pruss__l3_main,
&am33xx_wkup_m3__l4_wkup, &am33xx_wkup_m3__l4_wkup,
&am33xx_gfx__l3_main, &am33xx_gfx__l3_main,
&am33xx_l3_main__debugss, &am33xx_l3_main__debugss,
...@@ -302,13 +293,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { ...@@ -302,13 +293,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__smartreflex1, &am33xx_l4_wkup__smartreflex1,
&am33xx_l4_wkup__timer1, &am33xx_l4_wkup__timer1,
&am33xx_l4_wkup__rtc, &am33xx_l4_wkup__rtc,
&am33xx_l4_hs__pruss,
&am33xx_l4_ls__timer2, &am33xx_l4_ls__timer2,
&am33xx_l3_main__tpcc,
&am33xx_l3_s__gpmc, &am33xx_l3_s__gpmc,
&am33xx_l3_main__tptc0,
&am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc, &am33xx_l3_main__ocmc,
NULL, NULL,
}; };
......
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View file @ 8bdbf169
...@@ -156,75 +156,6 @@ static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = { ...@@ -156,75 +156,6 @@ static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
}, },
}; };
/* dss */
static struct omap_hwmod am43xx_dss_core_hwmod = {
.name = "dss_core",
.class = &omap2_dss_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "disp_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* dispc */
static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
.manager_count = 1,
.has_framedonetv_irq = 0
};
static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
.name = "dispc",
.sysc = &am43xx_dispc_sysc,
};
static struct omap_hwmod am43xx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &am43xx_dispc_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "disp_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
},
},
.dev_attr = &am43xx_dss_dispc_dev_attr,
.parent_hwmod = &am43xx_dss_core_hwmod,
};
/* rfbi */
static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
.name = "dss_rfbi",
.class = &omap2_rfbi_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "disp_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
},
},
.parent_hwmod = &am43xx_dss_core_hwmod,
};
/* Interfaces */ /* Interfaces */
static struct omap_hwmod_ocp_if am43xx_l3_main__emif = { static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
.master = &am33xx_l3_main_hwmod, .master = &am33xx_l3_main_hwmod,
...@@ -254,13 +185,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = { ...@@ -254,13 +185,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_pruss_hwmod,
.clk = "dpll_core_m4_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = { static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex0_hwmod, .slave = &am33xx_smartreflex0_hwmod,
...@@ -310,37 +234,8 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = { ...@@ -310,37 +234,8 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
.master = &am43xx_dss_core_hwmod,
.slave = &am33xx_l3_main_hwmod,
.clk = "l3_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am43xx_dss_core_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am43xx_dss_dispc_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am43xx_dss_rfbi_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__synctimer, &am33xx_l4_wkup__synctimer,
&am43xx_l3_main__pruss,
&am33xx_mpu__l3_main, &am33xx_mpu__l3_main,
&am33xx_mpu__prcm, &am33xx_mpu__prcm,
&am33xx_l3_s__l4_ls, &am33xx_l3_s__l4_ls,
...@@ -351,7 +246,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { ...@@ -351,7 +246,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__gfx, &am33xx_l3_main__gfx,
&am33xx_l3_s__l3_main, &am33xx_l3_s__l3_main,
&am43xx_l3_main__emif, &am43xx_l3_main__emif,
&am33xx_pruss__l3_main,
&am43xx_wkup_m3__l4_wkup, &am43xx_wkup_m3__l4_wkup,
&am33xx_gfx__l3_main, &am33xx_gfx__l3_main,
&am43xx_l4_wkup__wkup_m3, &am43xx_l4_wkup__wkup_m3,
...@@ -360,18 +254,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { ...@@ -360,18 +254,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am43xx_l4_wkup__smartreflex1, &am43xx_l4_wkup__smartreflex1,
&am43xx_l4_wkup__timer1, &am43xx_l4_wkup__timer1,
&am33xx_l4_ls__timer2, &am33xx_l4_ls__timer2,
&am33xx_l3_main__tpcc,
&am33xx_l3_s__gpmc, &am33xx_l3_s__gpmc,
&am33xx_l3_main__tptc0,
&am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc, &am33xx_l3_main__ocmc,
&am43xx_l3_s__usbotgss0, &am43xx_l3_s__usbotgss0,
&am43xx_l3_s__usbotgss1, &am43xx_l3_s__usbotgss1,
&am43xx_dss__l3_main,
&am43xx_l4_ls__dss,
&am43xx_l4_ls__dss_dispc,
&am43xx_l4_ls__dss_rfbi,
NULL, NULL,
}; };
......
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file @ 8bdbf169
...@@ -355,306 +355,6 @@ static struct omap_hwmod omap44xx_debugss_hwmod = { ...@@ -355,306 +355,6 @@ static struct omap_hwmod omap44xx_debugss_hwmod = {
}, },
}; };
/*
* 'dsp' class
* dsp sub-system
*/
static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
.name = "dsp",
};
/* dsp */
static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
{ .name = "dsp", .rst_shift = 0 },
};
static struct omap_hwmod omap44xx_dsp_hwmod = {
.name = "dsp",
.class = &omap44xx_dsp_hwmod_class,
.clkdm_name = "tesla_clkdm",
.rst_lines = omap44xx_dsp_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
.main_clk = "dpll_iva_m4x2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
.rev_offs = 0x0000,
.syss_offs = 0x0014,
.sysc_flags = SYSS_HAS_RESET_STATUS,
};
static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
.name = "dss",
.sysc = &omap44xx_dss_sysc,
.reset = omap_dss_reset,
};
/* dss */
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
{ .role = "tv_clk", .clk = "dss_tv_clk" },
{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
};
static struct omap_hwmod omap44xx_dss_hwmod = {
.name = "dss_core",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.class = &omap44xx_dss_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = dss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
};
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap44xx_dispc_sysc,
};
/* dss_dispc */
static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
.manager_count = 3,
.has_framedonetv_irq = 1
};
static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &omap44xx_dispc_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
.dev_attr = &omap44xx_dss_dispc_dev_attr,
.parent_hwmod = &omap44xx_dss_hwmod,
};
/*
* 'dsi' class
* display serial interface controller
*/
static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
.name = "dsi",
.sysc = &omap44xx_dsi_sysc,
};
/* dss_dsi1 */
static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
.name = "dss_dsi1",
.class = &omap44xx_dsi_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
.opt_clks = dss_dsi1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
.parent_hwmod = &omap44xx_dss_hwmod,
};
/* dss_dsi2 */
static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
.name = "dss_dsi2",
.class = &omap44xx_dsi_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
.opt_clks = dss_dsi2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
.parent_hwmod = &omap44xx_dss_hwmod,
};
/*
* 'hdmi' class
* hdmi controller
*/
static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
.name = "hdmi",
.sysc = &omap44xx_hdmi_sysc,
};
/* dss_hdmi */
static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
};
static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
.name = "dss_hdmi",
.class = &omap44xx_hdmi_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
/*
* HDMI audio requires to use no-idle mode. Hence,
* set idle mode by software.
*/
.flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
.main_clk = "dss_48mhz_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
.opt_clks = dss_hdmi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
.parent_hwmod = &omap44xx_dss_hwmod,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap44xx_rfbi_sysc,
};
/* dss_rfbi */
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
{ .role = "ick", .clk = "l3_div_ck" },
};
static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
.name = "dss_rfbi",
.class = &omap44xx_rfbi_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
.opt_clks = dss_rfbi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
.parent_hwmod = &omap44xx_dss_hwmod,
};
/*
* 'venc' class
* video encoder
*/
static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
.name = "venc",
};
/* dss_venc */
static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
{ .role = "tv_clk", .clk = "dss_tv_clk" },
};
static struct omap_hwmod omap44xx_dss_venc_hwmod = {
.name = "dss_venc",
.class = &omap44xx_venc_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
.main_clk = "dss_tv_clk",
.flags = HWMOD_OPT_CLKS_NEEDED,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
.parent_hwmod = &omap44xx_dss_hwmod,
.opt_clks = dss_venc_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
};
/* /*
* 'emif' class * 'emif' class
* external memory interface no1 * external memory interface no1
...@@ -737,39 +437,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = { ...@@ -737,39 +437,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
}, },
}; };
/*
* 'ipu' class
* imaging processor unit
*/
static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
.name = "ipu",
};
/* ipu */
static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
{ .name = "cpu0", .rst_shift = 0 },
{ .name = "cpu1", .rst_shift = 1 },
};
static struct omap_hwmod omap44xx_ipu_hwmod = {
.name = "ipu",
.class = &omap44xx_ipu_hwmod_class,
.clkdm_name = "ducati_clkdm",
.rst_lines = omap44xx_ipu_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
.main_clk = "ducati_clk_mux_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/* /*
* 'iss' class * 'iss' class
* external images sensor pixel data processor * external images sensor pixel data processor
...@@ -1236,22 +903,6 @@ static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { ...@@ -1236,22 +903,6 @@ static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* dsp -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
.master = &omap44xx_dsp_hwmod,
.slave = &omap44xx_l3_main_1_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
.master = &omap44xx_dss_hwmod,
.slave = &omap44xx_l3_main_1_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> l3_main_1 */ /* l3_main_2 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
.master = &omap44xx_l3_main_2_hwmod, .master = &omap44xx_l3_main_2_hwmod,
...@@ -1284,14 +935,6 @@ static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { ...@@ -1284,14 +935,6 @@ static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* ipu -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
.master = &omap44xx_ipu_hwmod,
.slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* iss -> l3_main_2 */ /* iss -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
.master = &omap44xx_iss_hwmod, .master = &omap44xx_iss_hwmod,
...@@ -1364,14 +1007,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { ...@@ -1364,14 +1007,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* dsp -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
.master = &omap44xx_dsp_hwmod,
.slave = &omap44xx_l4_abe_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l4_abe */ /* l3_main_1 -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
.master = &omap44xx_l3_main_1_hwmod, .master = &omap44xx_l3_main_1_hwmod,
...@@ -1476,142 +1111,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { ...@@ -1476,142 +1111,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* dsp -> iva */
static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
.master = &omap44xx_dsp_hwmod,
.slave = &omap44xx_iva_hwmod,
.clk = "dpll_iva_m5x2_ck",
.user = OCP_USER_DSP,
};
/* dsp -> sl2if */
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
.master = &omap44xx_dsp_hwmod,
.slave = &omap44xx_sl2if_hwmod,
.clk = "dpll_iva_m5x2_ck",
.user = OCP_USER_DSP,
};
/* l4_cfg -> dsp */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_dsp_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> dss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_SDMA,
};
/* l4_per -> dss */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_dss_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU,
};
/* l3_main_2 -> dss_dispc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_dispc_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_SDMA,
};
/* l4_per -> dss_dispc */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_dss_dispc_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU,
};
/* l3_main_2 -> dss_dsi1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_dsi1_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_SDMA,
};
/* l4_per -> dss_dsi1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_dss_dsi1_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU,
};
/* l3_main_2 -> dss_dsi2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_dsi2_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_SDMA,
};
/* l4_per -> dss_dsi2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_dss_dsi2_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU,
};
/* l3_main_2 -> dss_hdmi */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_hdmi_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_SDMA,
};
/* l4_per -> dss_hdmi */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_dss_hdmi_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU,
};
/* l3_main_2 -> dss_rfbi */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_rfbi_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_SDMA,
};
/* l4_per -> dss_rfbi */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_dss_rfbi_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU,
};
/* l3_main_2 -> dss_venc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_venc_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_SDMA,
};
/* l4_per -> dss_venc */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_dss_venc_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU,
};
/* l3_main_2 -> gpmc */ /* l3_main_2 -> gpmc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.master = &omap44xx_l3_main_2_hwmod, .master = &omap44xx_l3_main_2_hwmod,
...@@ -1620,14 +1119,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { ...@@ -1620,14 +1119,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l3_main_2 -> ipu */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_ipu_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> iss */ /* l3_main_2 -> iss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
.master = &omap44xx_l3_main_2_hwmod, .master = &omap44xx_l3_main_2_hwmod,
...@@ -1762,13 +1253,10 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { ...@@ -1762,13 +1253,10 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_iva__l3_instr, &omap44xx_iva__l3_instr,
&omap44xx_l3_main_3__l3_instr, &omap44xx_l3_main_3__l3_instr,
&omap44xx_ocp_wp_noc__l3_instr, &omap44xx_ocp_wp_noc__l3_instr,
&omap44xx_dsp__l3_main_1,
&omap44xx_dss__l3_main_1,
&omap44xx_l3_main_2__l3_main_1, &omap44xx_l3_main_2__l3_main_1,
&omap44xx_l4_cfg__l3_main_1, &omap44xx_l4_cfg__l3_main_1,
&omap44xx_mpu__l3_main_1, &omap44xx_mpu__l3_main_1,
&omap44xx_debugss__l3_main_2, &omap44xx_debugss__l3_main_2,
&omap44xx_ipu__l3_main_2,
&omap44xx_iss__l3_main_2, &omap44xx_iss__l3_main_2,
&omap44xx_iva__l3_main_2, &omap44xx_iva__l3_main_2,
&omap44xx_l3_main_1__l3_main_2, &omap44xx_l3_main_1__l3_main_2,
...@@ -1778,7 +1266,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { ...@@ -1778,7 +1266,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l3_main_1__l3_main_3, &omap44xx_l3_main_1__l3_main_3,
&omap44xx_l3_main_2__l3_main_3, &omap44xx_l3_main_2__l3_main_3,
&omap44xx_l4_cfg__l3_main_3, &omap44xx_l4_cfg__l3_main_3,
&omap44xx_dsp__l4_abe,
&omap44xx_l3_main_1__l4_abe, &omap44xx_l3_main_1__l4_abe,
&omap44xx_mpu__l4_abe, &omap44xx_mpu__l4_abe,
&omap44xx_l3_main_1__l4_cfg, &omap44xx_l3_main_1__l4_cfg,
...@@ -1792,25 +1279,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { ...@@ -1792,25 +1279,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_wkup__ctrl_module_wkup, &omap44xx_l4_wkup__ctrl_module_wkup,
&omap44xx_l4_wkup__ctrl_module_pad_wkup, &omap44xx_l4_wkup__ctrl_module_pad_wkup,
&omap44xx_l3_instr__debugss, &omap44xx_l3_instr__debugss,
&omap44xx_dsp__iva,
/* &omap44xx_dsp__sl2if, */
&omap44xx_l4_cfg__dsp,
&omap44xx_l3_main_2__dss,
&omap44xx_l4_per__dss,
&omap44xx_l3_main_2__dss_dispc,
&omap44xx_l4_per__dss_dispc,
&omap44xx_l3_main_2__dss_dsi1,
&omap44xx_l4_per__dss_dsi1,
&omap44xx_l3_main_2__dss_dsi2,
&omap44xx_l4_per__dss_dsi2,
&omap44xx_l3_main_2__dss_hdmi,
&omap44xx_l4_per__dss_hdmi,
&omap44xx_l3_main_2__dss_rfbi,
&omap44xx_l4_per__dss_rfbi,
&omap44xx_l3_main_2__dss_venc,
&omap44xx_l4_per__dss_venc,
&omap44xx_l3_main_2__gpmc, &omap44xx_l3_main_2__gpmc,
&omap44xx_l3_main_2__ipu,
&omap44xx_l3_main_2__iss, &omap44xx_l3_main_2__iss,
/* &omap44xx_iva__sl2if, */ /* &omap44xx_iva__sl2if, */
&omap44xx_l3_main_2__iva, &omap44xx_l3_main_2__iva,
......
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View file @ 8bdbf169
...@@ -226,240 +226,6 @@ static struct omap_hwmod omap54xx_counter_32k_hwmod = { ...@@ -226,240 +226,6 @@ static struct omap_hwmod omap54xx_counter_32k_hwmod = {
}, },
}; };
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
.rev_offs = 0x0000,
.syss_offs = 0x0014,
.sysc_flags = SYSS_HAS_RESET_STATUS,
};
static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
.name = "dss",
.sysc = &omap54xx_dss_sysc,
.reset = omap_dss_reset,
};
/* dss */
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
{ .role = "32khz_clk", .clk = "dss_32khz_clk" },
{ .role = "sys_clk", .clk = "dss_sys_clk" },
{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
};
static struct omap_hwmod omap54xx_dss_hwmod = {
.name = "dss_core",
.class = &omap54xx_dss_hwmod_class,
.clkdm_name = "dss_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = dss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
};
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap54xx_dispc_sysc,
};
/* dss_dispc */
static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
/* dss_dispc dev_attr */
static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
.has_framedonetv_irq = 1,
.manager_count = 4,
};
static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &omap54xx_dispc_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
.opt_clks = dss_dispc_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
.dev_attr = &dss_dispc_dev_attr,
.parent_hwmod = &omap54xx_dss_hwmod,
};
/*
* 'dsi1' class
* display serial interface controller
*/
static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
.name = "dsi1",
.sysc = &omap54xx_dsi1_sysc,
};
/* dss_dsi1_a */
static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
.name = "dss_dsi1",
.class = &omap54xx_dsi1_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
.opt_clks = dss_dsi1_a_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
.parent_hwmod = &omap54xx_dss_hwmod,
};
/* dss_dsi1_c */
static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
.name = "dss_dsi2",
.class = &omap54xx_dsi1_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
.opt_clks = dss_dsi1_c_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
.parent_hwmod = &omap54xx_dss_hwmod,
};
/*
* 'hdmi' class
* hdmi controller
*/
static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
.name = "hdmi",
.sysc = &omap54xx_hdmi_sysc,
};
static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
.name = "dss_hdmi",
.class = &omap54xx_hdmi_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "dss_48mhz_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
.opt_clks = dss_hdmi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
.parent_hwmod = &omap54xx_dss_hwmod,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap54xx_rfbi_sysc,
};
/* dss_rfbi */
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
{ .role = "ick", .clk = "l3_iclk_div" },
};
static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
.name = "dss_rfbi",
.class = &omap54xx_rfbi_hwmod_class,
.clkdm_name = "dss_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
.opt_clks = dss_rfbi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
.parent_hwmod = &omap54xx_dss_hwmod,
};
/* /*
* 'emif' class * 'emif' class
* external memory interface no1 (wrapper) * external memory interface no1 (wrapper)
...@@ -908,54 +674,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = { ...@@ -908,54 +674,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l3_main_2 -> dss */
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
.master = &omap54xx_l3_main_2_hwmod,
.slave = &omap54xx_dss_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> dss_dispc */
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
.master = &omap54xx_l3_main_2_hwmod,
.slave = &omap54xx_dss_dispc_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> dss_dsi1_a */
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
.master = &omap54xx_l3_main_2_hwmod,
.slave = &omap54xx_dss_dsi1_a_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> dss_dsi1_c */
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
.master = &omap54xx_l3_main_2_hwmod,
.slave = &omap54xx_dss_dsi1_c_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> dss_hdmi */
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
.master = &omap54xx_l3_main_2_hwmod,
.slave = &omap54xx_dss_hdmi_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> dss_rfbi */
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
.master = &omap54xx_l3_main_2_hwmod,
.slave = &omap54xx_dss_rfbi_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> emif1 */ /* mpu -> emif1 */
static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = { static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
.master = &omap54xx_mpu_hwmod, .master = &omap54xx_mpu_hwmod,
...@@ -1030,12 +748,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { ...@@ -1030,12 +748,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l3_main_1__l4_wkup, &omap54xx_l3_main_1__l4_wkup,
&omap54xx_mpu__mpu_private, &omap54xx_mpu__mpu_private,
&omap54xx_l4_wkup__counter_32k, &omap54xx_l4_wkup__counter_32k,
&omap54xx_l3_main_2__dss,
&omap54xx_l3_main_2__dss_dispc,
&omap54xx_l3_main_2__dss_dsi1_a,
&omap54xx_l3_main_2__dss_dsi1_c,
&omap54xx_l3_main_2__dss_hdmi,
&omap54xx_l3_main_2__dss_rfbi,
&omap54xx_mpu__emif1, &omap54xx_mpu__emif1,
&omap54xx_mpu__emif2, &omap54xx_mpu__emif2,
&omap54xx_l4_cfg__mpu, &omap54xx_l4_cfg__mpu,
......
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View file @ 8bdbf169
...@@ -276,203 +276,6 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { ...@@ -276,203 +276,6 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
}, },
}; };
/*
* 'tpcc' class
*
*/
static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
.name = "tpcc",
};
static struct omap_hwmod dra7xx_tpcc_hwmod = {
.name = "tpcc",
.class = &dra7xx_tpcc_hwmod_class,
.clkdm_name = "l3main1_clkdm",
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
},
},
};
/*
* 'tptc' class
*
*/
static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
.name = "tptc",
};
/* tptc0 */
static struct omap_hwmod dra7xx_tptc0_hwmod = {
.name = "tptc0",
.class = &dra7xx_tptc_hwmod_class,
.clkdm_name = "l3main1_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/* tptc1 */
static struct omap_hwmod dra7xx_tptc1_hwmod = {
.name = "tptc1",
.class = &dra7xx_tptc_hwmod_class,
.clkdm_name = "l3main1_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'dss' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
.rev_offs = 0x0000,
.syss_offs = 0x0014,
.sysc_flags = SYSS_HAS_RESET_STATUS,
};
static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
.name = "dss",
.sysc = &dra7xx_dss_sysc,
.reset = omap_dss_reset,
};
/* dss */
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
{ .role = "dss_clk", .clk = "dss_dss_clk" },
{ .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
{ .role = "32khz_clk", .clk = "dss_32khz_clk" },
{ .role = "video2_clk", .clk = "dss_video2_clk" },
{ .role = "video1_clk", .clk = "dss_video1_clk" },
{ .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
{ .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
};
static struct omap_hwmod dra7xx_dss_hwmod = {
.name = "dss_core",
.class = &dra7xx_dss_hwmod_class,
.clkdm_name = "dss_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = dss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
};
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
.name = "dispc",
.sysc = &dra7xx_dispc_sysc,
};
/* dss_dispc */
/* dss_dispc dev_attr */
static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
.has_framedonetv_irq = 1,
.manager_count = 4,
};
static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &dra7xx_dispc_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
.dev_attr = &dss_dispc_dev_attr,
.parent_hwmod = &dra7xx_dss_hwmod,
};
/*
* 'hdmi' class
* hdmi controller
*/
static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
.name = "hdmi",
.sysc = &dra7xx_hdmi_sysc,
};
/* dss_hdmi */
static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_hdmi_clk" },
};
static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
.name = "dss_hdmi",
.class = &dra7xx_hdmi_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "dss_48mhz_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
.opt_clks = dss_hdmi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
.parent_hwmod = &dra7xx_dss_hwmod,
};
/* /*
* 'gpmc' class * 'gpmc' class
* *
...@@ -1077,54 +880,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { ...@@ -1077,54 +880,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l3_main_1 -> tpcc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_tpcc_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU,
};
/* l3_main_1 -> tptc0 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_tptc0_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU,
};
/* l3_main_1 -> tptc1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_tptc1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU,
};
/* l3_main_1 -> dss */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_dss_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> dispc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_dss_dispc_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> dispc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_dss_hdmi_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> gpmc */ /* l3_main_1 -> gpmc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
.master = &dra7xx_l3_main_1_hwmod, .master = &dra7xx_l3_main_1_hwmod,
...@@ -1309,12 +1064,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { ...@@ -1309,12 +1064,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__bb2d, &dra7xx_l3_main_1__bb2d,
&dra7xx_l4_wkup__counter_32k, &dra7xx_l4_wkup__counter_32k,
&dra7xx_l4_wkup__ctrl_module_wkup, &dra7xx_l4_wkup__ctrl_module_wkup,
&dra7xx_l3_main_1__tpcc,
&dra7xx_l3_main_1__tptc0,
&dra7xx_l3_main_1__tptc1,
&dra7xx_l3_main_1__dss,
&dra7xx_l3_main_1__dispc,
&dra7xx_l3_main_1__hdmi,
&dra7xx_l3_main_1__gpmc, &dra7xx_l3_main_1__gpmc,
&dra7xx_l4_cfg__mpu, &dra7xx_l4_cfg__mpu,
&dra7xx_l3_main_1__pciess1, &dra7xx_l3_main_1__pciess1,
......
arch/arm/mach-omap2/omap_hwmod_81xx_data.c
View file @ 8bdbf169
...@@ -129,13 +129,6 @@ static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { ...@@ -129,13 +129,6 @@ static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
.name = "l3_fast",
.clkdm_name = "alwon_l3_fast_clkdm",
.class = &l3_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
/* /*
* L4 standard peripherals, see TRM table 1-12 for devices using this. * L4 standard peripherals, see TRM table 1-12 for devices using this.
* See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
...@@ -867,62 +860,6 @@ static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { ...@@ -867,62 +860,6 @@ static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* CPSW on dm814x */
static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x8,
.syss_offs = 0x4,
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSS_HAS_RESET_STATUS,
.idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
MSTANDBY_NO,
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
.name = "cpgmac0",
.sysc = &dm814x_cpgmac_sysc,
};
static struct omap_hwmod dm814x_cpgmac0_hwmod = {
.name = "cpgmac0",
.class = &dm814x_cpgmac0_hwmod_class,
.clkdm_name = "alwon_ethernet_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "cpsw_125mhz_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
.name = "davinci_mdio",
};
static struct omap_hwmod dm814x_mdio_hwmod = {
.name = "davinci_mdio",
.class = &dm814x_mdio_hwmod_class,
.clkdm_name = "alwon_ethernet_clkdm",
.main_clk = "cpsw_125mhz_gclk",
};
static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
.master = &dm81xx_l4_hs_hwmod,
.slave = &dm814x_cpgmac0_hwmod,
.clk = "cpsw_125mhz_gclk",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
.master = &dm814x_cpgmac0_hwmod,
.slave = &dm814x_mdio_hwmod,
.user = OCP_USER_MPU,
.flags = HWMOD_NO_IDLEST,
};
/* EMAC Ethernet */ /* EMAC Ethernet */
static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
.rev_offs = 0x0, .rev_offs = 0x0,
...@@ -1321,154 +1258,6 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { ...@@ -1321,154 +1258,6 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
.name = "tpcc",
};
static struct omap_hwmod dm81xx_tpcc_hwmod = {
.name = "tpcc",
.class = &dm81xx_tpcc_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
.master = &dm81xx_alwon_l3_fast_hwmod,
.slave = &dm81xx_tpcc_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
.name = "tptc0",
};
static struct omap_hwmod dm81xx_tptc0_hwmod = {
.name = "tptc0",
.class = &dm81xx_tptc0_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
.master = &dm81xx_alwon_l3_fast_hwmod,
.slave = &dm81xx_tptc0_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
.master = &dm81xx_tptc0_hwmod,
.slave = &dm81xx_alwon_l3_fast_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
.name = "tptc1",
};
static struct omap_hwmod dm81xx_tptc1_hwmod = {
.name = "tptc1",
.class = &dm81xx_tptc1_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
.master = &dm81xx_alwon_l3_fast_hwmod,
.slave = &dm81xx_tptc1_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
.master = &dm81xx_tptc1_hwmod,
.slave = &dm81xx_alwon_l3_fast_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
.name = "tptc2",
};
static struct omap_hwmod dm81xx_tptc2_hwmod = {
.name = "tptc2",
.class = &dm81xx_tptc2_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
.master = &dm81xx_alwon_l3_fast_hwmod,
.slave = &dm81xx_tptc2_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
.master = &dm81xx_tptc2_hwmod,
.slave = &dm81xx_alwon_l3_fast_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
.name = "tptc3",
};
static struct omap_hwmod dm81xx_tptc3_hwmod = {
.name = "tptc3",
.class = &dm81xx_tptc3_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
.master = &dm81xx_alwon_l3_fast_hwmod,
.slave = &dm81xx_tptc3_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
.master = &dm81xx_tptc3_hwmod,
.slave = &dm81xx_alwon_l3_fast_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
};
/* /*
* REVISIT: Test and enable the following once clocks work: * REVISIT: Test and enable the following once clocks work:
* dm81xx_l4_ls__mailbox * dm81xx_l4_ls__mailbox
...@@ -1499,19 +1288,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { ...@@ -1499,19 +1288,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
&dm814x_l4_ls__mmc1, &dm814x_l4_ls__mmc1,
&dm814x_l4_ls__mmc2, &dm814x_l4_ls__mmc2,
&ti81xx_l4_ls__rtc, &ti81xx_l4_ls__rtc,
&dm81xx_alwon_l3_fast__tpcc,
&dm81xx_alwon_l3_fast__tptc0,
&dm81xx_alwon_l3_fast__tptc1,
&dm81xx_alwon_l3_fast__tptc2,
&dm81xx_alwon_l3_fast__tptc3,
&dm81xx_tptc0__alwon_l3_fast,
&dm81xx_tptc1__alwon_l3_fast,
&dm81xx_tptc2__alwon_l3_fast,
&dm81xx_tptc3__alwon_l3_fast,
&dm814x_l4_ls__timer1, &dm814x_l4_ls__timer1,
&dm814x_l4_ls__timer2, &dm814x_l4_ls__timer2,
&dm814x_l4_hs__cpgmac0,
&dm814x_cpgmac0__mdio,
&dm81xx_alwon_l3_slow__gpmc, &dm81xx_alwon_l3_slow__gpmc,
&dm814x_default_l3_slow__usbss, &dm814x_default_l3_slow__usbss,
&dm814x_alwon_l3_med__mmc3, &dm814x_alwon_l3_med__mmc3,
...@@ -1554,15 +1332,6 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { ...@@ -1554,15 +1332,6 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_emac0__mdio, &dm81xx_emac0__mdio,
&dm816x_l4_hs__emac1, &dm816x_l4_hs__emac1,
&dm81xx_l4_hs__sata, &dm81xx_l4_hs__sata,
&dm81xx_alwon_l3_fast__tpcc,
&dm81xx_alwon_l3_fast__tptc0,
&dm81xx_alwon_l3_fast__tptc1,
&dm81xx_alwon_l3_fast__tptc2,
&dm81xx_alwon_l3_fast__tptc3,
&dm81xx_tptc0__alwon_l3_fast,
&dm81xx_tptc1__alwon_l3_fast,
&dm81xx_tptc2__alwon_l3_fast,
&dm81xx_tptc3__alwon_l3_fast,
&dm81xx_alwon_l3_slow__gpmc, &dm81xx_alwon_l3_slow__gpmc,
&dm816x_default_l3_slow__usbss, &dm816x_default_l3_slow__usbss,
NULL, NULL,
......
arch/arm/mach-omap2/pdata-quirks.c
View file @ 8bdbf169
...@@ -397,10 +397,16 @@ static int ti_sysc_shutdown_module(struct device *dev, ...@@ -397,10 +397,16 @@ static int ti_sysc_shutdown_module(struct device *dev,
return omap_hwmod_shutdown(cookie->data); return omap_hwmod_shutdown(cookie->data);
} }
static bool ti_sysc_soc_type_gp(void)
{
return omap_type() == OMAP2_DEVICE_TYPE_GP;
}
static struct of_dev_auxdata omap_auxdata_lookup[]; static struct of_dev_auxdata omap_auxdata_lookup[];
static struct ti_sysc_platform_data ti_sysc_pdata = { static struct ti_sysc_platform_data ti_sysc_pdata = {
.auxdata = omap_auxdata_lookup, .auxdata = omap_auxdata_lookup,
.soc_type_gp = ti_sysc_soc_type_gp,
.init_clockdomain = ti_sysc_clkdm_init, .init_clockdomain = ti_sysc_clkdm_init,
.clkdm_deny_idle = ti_sysc_clkdm_deny_idle, .clkdm_deny_idle = ti_sysc_clkdm_deny_idle,
.clkdm_allow_idle = ti_sysc_clkdm_allow_idle, .clkdm_allow_idle = ti_sysc_clkdm_allow_idle,
......
arch/arm64/boot/dts/qcom/Makefile
View file @ 8bdbf169
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
...@@ -22,5 +23,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb ...@@ -22,5 +23,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View file @ 8bdbf169
...@@ -562,7 +562,6 @@ &wcd_codec { ...@@ -562,7 +562,6 @@ &wcd_codec {
&smd_rpm_regulators { &smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l5-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>; vdd_l4_l5_l6-supply = <&pm8916_s4>;
vdd_l7-supply = <&pm8916_s4>; vdd_l7-supply = <&pm8916_s4>;
......
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
View file @ 8bdbf169
...@@ -999,13 +999,7 @@ &ufsphy { ...@@ -999,13 +999,7 @@ &ufsphy {
vdda-phy-supply = <&vreg_l28a_0p925>; vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>; vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
vddp-ref-clk-supply = <&vreg_l25a_1p2>; vddp-ref-clk-supply = <&vreg_l25a_1p2>;
vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
}; };
&ufshc { &ufshc {
......
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts 0 → 100644
View file @ 8bdbf169
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* IPQ6018 CP01 board device tree source
*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include "ipq6018.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
aliases {
serial0 = &blsp1_uart3;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " swiotlb=1";
};
};
&blsp1_uart3 {
pinctrl-0 = <&serial_3_pins>;
pinctrl-names = "default";
status = "ok";
};
&i2c_1 {
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "ok";
};
&spi_0 {
cs-select = <0>;
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "n25q128a11";
spi-max-frequency = <50000000>;
};
};
&tlmm {
i2c_1_pins: i2c-1-pins {
pins = "gpio42", "gpio43";
function = "blsp2_i2c";
drive-strength = <8>;
};
spi_0_pins: spi-0-pins {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
bias-pull-down;
};
};
arch/arm64/boot/dts/qcom/ipq6018.dtsi 0 → 100644
View file @ 8bdbf169
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* IPQ6018 SoC device tree source
*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&intc>;
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
xo: xo {
compatible = "fixed-clock";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
next-level-cache = <&L2_0>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
next-level-cache = <&L2_0>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache {
compatible = "cache";
cache-level = <0x2>;
};
};
firmware {
scm {
compatible = "qcom,scm";
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x80>;
#hwlock-cells = <1>;
};
pmuv8: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tz: tz@48500000 {
reg = <0x0 0x48500000 0x0 0x00200000>;
no-map;
};
smem_region: memory@4aa00000 {
reg = <0x0 0x4aa00000 0x0 0x00100000>;
no-map;
};
q6_region: memory@4ab00000 {
reg = <0x0 0x4ab00000 0x0 0x02800000>;
no-map;
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
hwlocks = <&tcsr_mutex 0>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
dma-ranges;
compatible = "simple-bus";
prng: qrng@e1000 {
compatible = "qcom,prng-ee";
reg = <0xe3000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
cryptobam: dma@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <1>;
qcom,controlled-remotely = <1>;
qcom,config-pipe-trust-reg = <0>;
};
crypto: crypto@73a000 {
compatible = "qcom,crypto-v5.1";
reg = <0x0073a000 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
<&gcc GCC_CRYPTO_CLK>;
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 2>, <&cryptobam 3>;
dma-names = "rx", "tx";
};
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq6018-pinctrl";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 80>;
interrupt-controller;
#interrupt-cells = <2>;
serial_3_pins: serial3-pinmux {
pins = "gpio44", "gpio45";
function = "blsp2_uart";
drive-strength = <8>;
bias-pull-down;
};
};
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq6018";
reg = <0x01800000 0x80000>;
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
tcsr_mutex_regs: syscon@1905000 {
compatible = "syscon";
reg = <0x01905000 0x8000>;
};
tcsr_q6: syscon@1945000 {
compatible = "syscon";
reg = <0x01945000 0xe000>;
};
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x2b000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
blsp1_uart3: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078b1000 0x200>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
spi_0: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 12>, <&blsp_dma 13>;
dma-names = "tx", "rx";
status = "disabled";
};
spi_1: spi@78b6000 {
compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
status = "disabled";
};
i2c_0: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
dmas = <&blsp_dma 15>, <&blsp_dma 14>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
dmas = <&blsp_dma 17>, <&blsp_dma 16>;
dma-names = "rx", "tx";
status = "disabled";
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0b000000 0x1000>, /*GICD*/
<0x0b002000 0x1000>, /*GICC*/
<0x0b001000 0x1000>, /*GICH*/
<0x0b004000 0x1000>; /*GICV*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog@b017000 {
compatible = "qcom,kpss-wdt";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
reg = <0x0b017000 0x40>;
clocks = <&sleep_clk>;
timeout-sec = <10>;
};
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
reg = <0x0b111000 0xc>;
#mbox-cells = <1>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
clock-frequency = <19200000>;
frame@b120000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b121000 0x1000>,
<0x0b122000 0x1000>;
};
frame@b123000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb123000 0x1000>;
status = "disabled";
};
frame@b124000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b124000 0x1000>;
status = "disabled";
};
frame@b125000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b125000 0x1000>;
status = "disabled";
};
frame@b126000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b126000 0x1000>;
status = "disabled";
};
frame@b127000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b127000 0x1000>;
status = "disabled";
};
frame@b128000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b128000 0x1000>;
status = "disabled";
};
};
q6v5_wcss: remoteproc@cd00000 {
compatible = "qcom,ipq8074-wcss-pil";
reg = <0x0cd00000 0x4040>,
<0x004ab000 0x20>;
reg-names = "qdsp6",
"rmb";
interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
<&wcss_smp2p_in 0 0>,
<&wcss_smp2p_in 1 0>,
<&wcss_smp2p_in 2 0>,
<&wcss_smp2p_in 3 0>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
resets = <&gcc GCC_WCSSAON_RESET>,
<&gcc GCC_WCSS_BCR>,
<&gcc GCC_WCSS_Q6_BCR>;
reset-names = "wcss_aon_reset",
"wcss_reset",
"wcss_q6_reset";
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "prng";
qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
qcom,smem-states = <&wcss_smp2p_out 0>,
<&wcss_smp2p_out 1>;
qcom,smem-state-names = "shutdown",
"stop";
memory-region = <&q6_region>;
glink-edge {
interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
qcom,remote-pid = <1>;
mboxes = <&apcs_glb 8>;
qrtr_requests {
qcom,glink-channels = "IPCRTR";
};
};
};
};
wcss: wcss-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 9>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
wcss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
wcss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file @ 8bdbf169
...@@ -21,6 +21,7 @@ tlmm: pinctrl@1000000 { ...@@ -21,6 +21,7 @@ tlmm: pinctrl@1000000 {
reg = <0x1000000 0x300000>; reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&tlmm 0 0 70>;
#gpio-cells = <0x2>; #gpio-cells = <0x2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <0x2>; #interrupt-cells = <0x2>;
......
arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
View file @ 8bdbf169
...@@ -15,6 +15,14 @@ chosen { ...@@ -15,6 +15,14 @@ chosen {
stdout-path = "serial0"; stdout-path = "serial0";
}; };
reserved-memory {
/* Additional memory used by Samsung firmware modifications */
tz-apps@85500000 {
reg = <0x0 0x85500000 0x0 0xb00000>;
no-map;
};
};
soc { soc {
sdhci@7824000 { sdhci@7824000 {
status = "okay"; status = "okay";
......
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ 8bdbf169
...@@ -423,6 +423,7 @@ msmgpio: pinctrl@1000000 { ...@@ -423,6 +423,7 @@ msmgpio: pinctrl@1000000 {
reg = <0x1000000 0x300000>; reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&msmgpio 0 0 122>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -860,7 +861,7 @@ tsens_calsel: calsel@ec { ...@@ -860,7 +861,7 @@ tsens_calsel: calsel@ec {
}; };
tsens: thermal-sensor@4a9000 { tsens: thermal-sensor@4a9000 {
compatible = "qcom,msm8916-tsens"; compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
reg = <0x4a9000 0x1000>, /* TM */ reg = <0x4a9000 0x1000>, /* TM */
<0x4a8000 0x1000>; /* SROT */ <0x4a8000 0x1000>; /* SROT */
nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
...@@ -1129,6 +1130,20 @@ smd-edge { ...@@ -1129,6 +1130,20 @@ smd-edge {
qcom,remote-pid = <1>; qcom,remote-pid = <1>;
label = "hexagon"; label = "hexagon";
fastrpc {
compatible = "qcom,fastrpc";
qcom,smd-channels = "fastrpcsmd-apps-dsp";
label = "adsp";
#address-cells = <1>;
#size-cells = <0>;
cb@1{
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
};
};
}; };
}; };
...@@ -1415,6 +1430,7 @@ etm@85c000 { ...@@ -1415,6 +1430,7 @@ etm@85c000 {
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk"; clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU0>; cpu = <&CPU0>;
...@@ -1433,6 +1449,7 @@ etm@85d000 { ...@@ -1433,6 +1449,7 @@ etm@85d000 {
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk"; clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU1>; cpu = <&CPU1>;
...@@ -1451,6 +1468,7 @@ etm@85e000 { ...@@ -1451,6 +1468,7 @@ etm@85e000 {
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk"; clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU2>; cpu = <&CPU2>;
...@@ -1469,6 +1487,7 @@ etm@85f000 { ...@@ -1469,6 +1487,7 @@ etm@85f000 {
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk"; clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU3>; cpu = <&CPU3>;
......
arch/arm64/boot/dts/qcom/msm8992.dtsi
View file @ 8bdbf169
...@@ -171,6 +171,7 @@ msmgpio: pinctrl@fd510000 { ...@@ -171,6 +171,7 @@ msmgpio: pinctrl@fd510000 {
reg = <0xfd510000 0x4000>; reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&msmgpio 0 0 146>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
......
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file @ 8bdbf169
...@@ -133,6 +133,7 @@ msmgpio: pinctrl@fd510000 { ...@@ -133,6 +133,7 @@ msmgpio: pinctrl@fd510000 {
reg = <0xfd510000 0x4000>; reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&msmgpio 0 0 146>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
......
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file @ 8bdbf169
...@@ -443,10 +443,13 @@ gcc: clock-controller@300000 { ...@@ -443,10 +443,13 @@ gcc: clock-controller@300000 {
#reset-cells = <1>; #reset-cells = <1>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
reg = <0x00300000 0x90000>; reg = <0x00300000 0x90000>;
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
clock-names = "cxo2";
}; };
tsens0: thermal-sensor@4a9000 { tsens0: thermal-sensor@4a9000 {
compatible = "qcom,msm8996-tsens"; compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
reg = <0x004a9000 0x1000>, /* TM */ reg = <0x004a9000 0x1000>, /* TM */
<0x004a8000 0x1000>; /* SROT */ <0x004a8000 0x1000>; /* SROT */
#qcom,sensors = <13>; #qcom,sensors = <13>;
...@@ -457,7 +460,7 @@ tsens0: thermal-sensor@4a9000 { ...@@ -457,7 +460,7 @@ tsens0: thermal-sensor@4a9000 {
}; };
tsens1: thermal-sensor@4ad000 { tsens1: thermal-sensor@4ad000 {
compatible = "qcom,msm8996-tsens"; compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
reg = <0x004ad000 0x1000>, /* TM */ reg = <0x004ad000 0x1000>, /* TM */
<0x004ac000 0x1000>; /* SROT */ <0x004ac000 0x1000>; /* SROT */
#qcom,sensors = <8>; #qcom,sensors = <8>;
...@@ -695,6 +698,7 @@ msmgpio: pinctrl@1010000 { ...@@ -695,6 +698,7 @@ msmgpio: pinctrl@1010000 {
reg = <0x01010000 0x300000>; reg = <0x01010000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&msmgpio 0 0 150>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -882,7 +886,7 @@ ufshc: ufshc@624000 { ...@@ -882,7 +886,7 @@ ufshc: ufshc@624000 {
reg = <0x00624000 0x2500>; reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy>; phys = <&ufsphy_lane>;
phy-names = "ufsphy"; phy-names = "ufsphy";
power-domains = <&gcc UFS_GDSC>; power-domains = <&gcc UFS_GDSC>;
...@@ -934,16 +938,25 @@ ufs_variant { ...@@ -934,16 +938,25 @@ ufs_variant {
}; };
ufsphy: phy@627000 { ufsphy: phy@627000 {
compatible = "qcom,msm8996-ufs-phy-qmp-14nm"; compatible = "qcom,msm8996-qmp-ufs-phy";
reg = <0x00627000 0xda8>; reg = <0x00627000 0x1c4>;
reg-names = "phy_mem"; #address-cells = <1>;
#phy-cells = <0>; #size-cells = <1>;
ranges;
clocks = <&gcc GCC_UFS_CLKREF_CLK>;
clock-names = "ref";
clock-names = "ref_clk_src", "ref_clk";
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_CLKREF_CLK>;
resets = <&ufshc 0>; resets = <&ufshc 0>;
reset-names = "ufsphy";
status = "disabled"; status = "disabled";
ufsphy_lane: lanes@627400 {
reg = <0x627400 0x12c>,
<0x627600 0x200>,
<0x627c00 0x1b4>;
#phy-cells = <0>;
};
}; };
camss: camss@a00000 { camss: camss@a00000 {
......
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
View file @ 8bdbf169
...@@ -95,11 +95,15 @@ &funnel3 { ...@@ -95,11 +95,15 @@ &funnel3 {
}; };
&funnel4 { &funnel4 {
status = "okay"; // FIXME: Figure out why clock late_initcall crashes the board with
// this enabled.
// status = "okay";
}; };
&funnel5 { &funnel5 {
status = "okay"; // FIXME: Figure out why clock late_initcall crashes the board with
// this enabled.
// status = "okay";
}; };
&pm8005_lsid1 { &pm8005_lsid1 {
......
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file @ 8bdbf169
...@@ -130,7 +130,7 @@ cpus { ...@@ -130,7 +130,7 @@ cpus {
CPU0: cpu@0 { CPU0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,armv8"; compatible = "qcom,kryo280";
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
...@@ -149,7 +149,7 @@ L1_D_0: l1-dcache { ...@@ -149,7 +149,7 @@ L1_D_0: l1-dcache {
CPU1: cpu@1 { CPU1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,armv8"; compatible = "qcom,kryo280";
reg = <0x0 0x1>; reg = <0x0 0x1>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
...@@ -164,7 +164,7 @@ L1_D_1: l1-dcache { ...@@ -164,7 +164,7 @@ L1_D_1: l1-dcache {
CPU2: cpu@2 { CPU2: cpu@2 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,armv8"; compatible = "qcom,kryo280";
reg = <0x0 0x2>; reg = <0x0 0x2>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
...@@ -179,7 +179,7 @@ L1_D_2: l1-dcache { ...@@ -179,7 +179,7 @@ L1_D_2: l1-dcache {
CPU3: cpu@3 { CPU3: cpu@3 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,armv8"; compatible = "qcom,kryo280";
reg = <0x0 0x3>; reg = <0x0 0x3>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
...@@ -194,7 +194,7 @@ L1_D_3: l1-dcache { ...@@ -194,7 +194,7 @@ L1_D_3: l1-dcache {
CPU4: cpu@100 { CPU4: cpu@100 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,armv8"; compatible = "qcom,kryo280";
reg = <0x0 0x100>; reg = <0x0 0x100>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
...@@ -213,7 +213,7 @@ L1_D_100: l1-dcache { ...@@ -213,7 +213,7 @@ L1_D_100: l1-dcache {
CPU5: cpu@101 { CPU5: cpu@101 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,armv8"; compatible = "qcom,kryo280";
reg = <0x0 0x101>; reg = <0x0 0x101>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
...@@ -228,7 +228,7 @@ L1_D_101: l1-dcache { ...@@ -228,7 +228,7 @@ L1_D_101: l1-dcache {
CPU6: cpu@102 { CPU6: cpu@102 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,armv8"; compatible = "qcom,kryo280";
reg = <0x0 0x102>; reg = <0x0 0x102>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
...@@ -243,7 +243,7 @@ L1_D_102: l1-dcache { ...@@ -243,7 +243,7 @@ L1_D_102: l1-dcache {
CPU7: cpu@103 { CPU7: cpu@103 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,armv8"; compatible = "qcom,kryo280";
reg = <0x0 0x103>; reg = <0x0 0x103>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
......
arch/arm64/boot/dts/qcom/pm6150.dtsi
View file @ 8bdbf169
...@@ -20,7 +20,7 @@ pm6150_pon: pon@800 { ...@@ -20,7 +20,7 @@ pm6150_pon: pon@800 {
mode-bootloader = <0x2>; mode-bootloader = <0x2>;
mode-recovery = <0x1>; mode-recovery = <0x1>;
pwrkey { pm6150_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey"; compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>; debounce = <15625>;
......
arch/arm64/boot/dts/qcom/pm8998.dtsi
View file @ 8bdbf169
...@@ -45,7 +45,7 @@ pm8998_pon: pon@800 { ...@@ -45,7 +45,7 @@ pm8998_pon: pon@800 {
mode-bootloader = <0x2>; mode-bootloader = <0x2>;
mode-recovery = <0x1>; mode-recovery = <0x1>;
pwrkey { pm8998_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey"; compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>; debounce = <15625>;
......
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
View file @ 8bdbf169
...@@ -200,6 +200,7 @@ vreg_l13_3p3: l13 { ...@@ -200,6 +200,7 @@ vreg_l13_3p3: l13 {
&sdcc1 { &sdcc1 {
status = "ok"; status = "ok";
supports-cqe;
mmc-ddr-1_8v; mmc-ddr-1_8v;
mmc-hs400-1_8v; mmc-hs400-1_8v;
bus-width = <8>; bus-width = <8>;
......
arch/arm64/boot/dts/qcom/qcs404.dtsi
View file @ 8bdbf169
...@@ -685,9 +685,9 @@ pcie_phy: phy@7786000 { ...@@ -685,9 +685,9 @@ pcie_phy: phy@7786000 {
}; };
sdcc1: sdcc@7804000 { sdcc1: sdcc@7804000 {
compatible = "qcom,sdhci-msm-v5"; compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x7805000 0x1000>; reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
reg-names = "hc_mem", "cmdq_mem"; reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm64/boot/dts/qcom/sc7180-idp.dts
View file @ 8bdbf169
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
/dts-v1/; /dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7180.dtsi" #include "sc7180.dtsi"
#include "pm6150.dtsi" #include "pm6150.dtsi"
...@@ -17,6 +18,7 @@ / { ...@@ -17,6 +18,7 @@ / {
compatible = "qcom,sc7180-idp", "qcom,sc7180"; compatible = "qcom,sc7180-idp", "qcom,sc7180";
aliases { aliases {
bluetooth0 = &bluetooth;
hsuart0 = &uart3; hsuart0 = &uart3;
serial0 = &uart8; serial0 = &uart8;
}; };
...@@ -101,9 +103,9 @@ vreg_l11a_1p8: ldo11 { ...@@ -101,9 +103,9 @@ vreg_l11a_1p8: ldo11 {
}; };
vreg_l12a_1p8: ldo12 { vreg_l12a_1p8: ldo12 {
regulator-min-microvolt = <1696000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1952000>; regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
}; };
vreg_l13a_1p8: ldo13 { vreg_l13a_1p8: ldo13 {
...@@ -143,9 +145,9 @@ vreg_l18a_2p8: ldo18 { ...@@ -143,9 +145,9 @@ vreg_l18a_2p8: ldo18 {
}; };
vreg_l19a_2p9: ldo19 { vreg_l19a_2p9: ldo19 {
regulator-min-microvolt = <2696000>; regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <3304000>; regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
}; };
}; };
...@@ -189,9 +191,9 @@ vreg_l5c_1p8: ldo5 { ...@@ -189,9 +191,9 @@ vreg_l5c_1p8: ldo5 {
}; };
vreg_l6c_2p9: ldo6 { vreg_l6c_2p9: ldo6 {
regulator-min-microvolt = <2696000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3304000>; regulator-max-microvolt = <2950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
}; };
vreg_l7c_3p0: ldo7 { vreg_l7c_3p0: ldo7 {
...@@ -207,9 +209,9 @@ vreg_l8c_1p8: ldo8 { ...@@ -207,9 +209,9 @@ vreg_l8c_1p8: ldo8 {
}; };
vreg_l9c_2p9: ldo9 { vreg_l9c_2p9: ldo9 {
regulator-min-microvolt = <2952000>; regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <3304000>; regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
}; };
vreg_l10c_3p3: ldo10 { vreg_l10c_3p3: ldo10 {
...@@ -254,8 +256,40 @@ &qupv3_id_1 { ...@@ -254,8 +256,40 @@ &qupv3_id_1 {
status = "okay"; status = "okay";
}; };
&sdhc_1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
vmmc-supply = <&vreg_l19a_2p9>;
vqmmc-supply = <&vreg_l12a_1p8>;
};
&sdhc_2 {
status = "okay";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
vmmc-supply = <&vreg_l9c_2p9>;
vqmmc-supply = <&vreg_l6c_2p9>;
cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
};
&uart3 { &uart3 {
status = "okay"; status = "okay";
bluetooth: wcn3990-bt {
compatible = "qcom,wcn3990-bt";
vddio-supply = <&vreg_l10a_1p8>;
vddxo-supply = <&vreg_l1c_1p8>;
vddrf-supply = <&vreg_l2c_1p3>;
vddch0-supply = <&vreg_l10c_3p3>;
max-speed = <3200000>;
clocks = <&rpmhcc RPMH_RF_CLK2>;
};
}; };
&uart8 { &uart8 {
...@@ -287,6 +321,12 @@ &usb_1_qmpphy { ...@@ -287,6 +321,12 @@ &usb_1_qmpphy {
vdda-pll-supply = <&vreg_l4a_0p8>; vdda-pll-supply = <&vreg_l4a_0p8>;
}; };
&venus {
video-firmware {
iommus = <&apps_smmu 0x0c42 0x0>;
};
};
/* PINCTRL - additions to nodes defined in sc7180.dtsi */ /* PINCTRL - additions to nodes defined in sc7180.dtsi */
&qspi_clk { &qspi_clk {
......
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file @ 8bdbf169
...@@ -5,8 +5,11 @@ ...@@ -5,8 +5,11 @@
* Copyright (c) 2019, The Linux Foundation. All rights reserved. * Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/ */
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h> #include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h> #include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/power/qcom-aoss-qmp.h>
...@@ -75,6 +78,11 @@ smem_mem: memory@80900000 { ...@@ -75,6 +78,11 @@ smem_mem: memory@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>; reg = <0x0 0x80900000 0x0 0x200000>;
no-map; no-map;
}; };
venus_mem: memory@8f600000 {
reg = <0 0x8f600000 0 0x500000>;
no-map;
};
}; };
cpus { cpus {
...@@ -86,6 +94,8 @@ CPU0: cpu@0 { ...@@ -86,6 +94,8 @@ CPU0: cpu@0 {
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
#cooling-cells = <2>; #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
...@@ -103,6 +113,8 @@ CPU1: cpu@100 { ...@@ -103,6 +113,8 @@ CPU1: cpu@100 {
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x100>; reg = <0x0 0x100>;
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>; next-level-cache = <&L2_100>;
#cooling-cells = <2>; #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
...@@ -117,6 +129,8 @@ CPU2: cpu@200 { ...@@ -117,6 +129,8 @@ CPU2: cpu@200 {
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x200>; reg = <0x0 0x200>;
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>; next-level-cache = <&L2_200>;
#cooling-cells = <2>; #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
...@@ -131,6 +145,8 @@ CPU3: cpu@300 { ...@@ -131,6 +145,8 @@ CPU3: cpu@300 {
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x300>; reg = <0x0 0x300>;
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>; next-level-cache = <&L2_300>;
#cooling-cells = <2>; #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
...@@ -145,6 +161,8 @@ CPU4: cpu@400 { ...@@ -145,6 +161,8 @@ CPU4: cpu@400 {
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x400>; reg = <0x0 0x400>;
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>; next-level-cache = <&L2_400>;
#cooling-cells = <2>; #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
...@@ -159,6 +177,8 @@ CPU5: cpu@500 { ...@@ -159,6 +177,8 @@ CPU5: cpu@500 {
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x500>; reg = <0x0 0x500>;
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>; next-level-cache = <&L2_500>;
#cooling-cells = <2>; #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
...@@ -173,6 +193,8 @@ CPU6: cpu@600 { ...@@ -173,6 +193,8 @@ CPU6: cpu@600 {
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x600>; reg = <0x0 0x600>;
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <405>;
next-level-cache = <&L2_600>; next-level-cache = <&L2_600>;
#cooling-cells = <2>; #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>;
...@@ -187,6 +209,8 @@ CPU7: cpu@700 { ...@@ -187,6 +209,8 @@ CPU7: cpu@700 {
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x700>; reg = <0x0 0x700>;
enable-method = "psci"; enable-method = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <405>;
next-level-cache = <&L2_700>; next-level-cache = <&L2_700>;
#cooling-cells = <2>; #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>;
...@@ -195,6 +219,42 @@ L2_700: l2-cache { ...@@ -195,6 +219,42 @@ L2_700: l2-cache {
next-level-cache = <&L3_0>; next-level-cache = <&L3_0>;
}; };
}; };
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
}; };
memory@80000000 { memory@80000000 {
...@@ -299,7 +359,7 @@ psci { ...@@ -299,7 +359,7 @@ psci {
method = "smc"; method = "smc";
}; };
soc: soc { soc: soc@0 {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
ranges = <0 0 0 0 0x10 0>; ranges = <0 0 0 0 0x10 0>;
...@@ -310,8 +370,9 @@ gcc: clock-controller@100000 { ...@@ -310,8 +370,9 @@ gcc: clock-controller@100000 {
compatible = "qcom,gcc-sc7180"; compatible = "qcom,gcc-sc7180";
reg = <0 0x00100000 0 0x1f0000>; reg = <0 0x00100000 0 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>; <&rpmhcc RPMH_CXO_CLK_A>,
clock-names = "bi_tcxo", "bi_tcxo_ao"; <&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
...@@ -329,6 +390,33 @@ qusb2p_hstx_trim: hstx-trim-primary@25b { ...@@ -329,6 +390,33 @@ qusb2p_hstx_trim: hstx-trim-primary@25b {
}; };
}; };
sdhc_1: sdhci@7c4000 {
compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x7c4000 0 0x1000>,
<0 0x07c5000 0 0x1000>;
reg-names = "hc", "cqhci";
iommus = <&apps_smmu 0x60 0x0>;
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
bus-width = <8>;
non-removable;
supports-cqe;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "disabled";
};
qupv3_id_0: geniqup@8c0000 { qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup"; compatible = "qcom,geni-se-qup";
reg = <0 0x008c0000 0 0x6000>; reg = <0 0x008c0000 0 0x6000>;
...@@ -338,6 +426,7 @@ qupv3_id_0: geniqup@8c0000 { ...@@ -338,6 +426,7 @@ qupv3_id_0: geniqup@8c0000 {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
iommus = <&apps_smmu 0x43 0x0>;
status = "disabled"; status = "disabled";
i2c0: i2c@880000 { i2c0: i2c@880000 {
...@@ -546,6 +635,7 @@ qupv3_id_1: geniqup@ac0000 { ...@@ -546,6 +635,7 @@ qupv3_id_1: geniqup@ac0000 {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
iommus = <&apps_smmu 0x4c3 0x0>;
status = "disabled"; status = "disabled";
i2c6: i2c@a80000 { i2c6: i2c@a80000 {
...@@ -745,6 +835,69 @@ uart11: serial@a94000 { ...@@ -745,6 +835,69 @@ uart11: serial@a94000 {
}; };
}; };
config_noc: interconnect@1500000 {
compatible = "qcom,sc7180-config-noc";
reg = <0 0x01500000 0 0x28000>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1620000 {
compatible = "qcom,sc7180-system-noc";
reg = <0 0x01620000 0 0x17080>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@1638000 {
compatible = "qcom,sc7180-mc-virt";
reg = <0 0x01638000 0 0x1000>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
qup_virt: interconnect@1650000 {
compatible = "qcom,sc7180-qup-virt";
reg = <0 0x01650000 0 0x1000>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sc7180-aggre1-noc";
reg = <0 0x016e0000 0 0x15080>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1705000 {
compatible = "qcom,sc7180-aggre2-noc";
reg = <0 0x01705000 0 0x9000>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
compute_noc: interconnect@170e000 {
compatible = "qcom,sc7180-compute-noc";
reg = <0 0x0170e000 0 0x6000>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,sc7180-mmss-noc";
reg = <0 0x01740000 0 0x1c100>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
ipa_virt: interconnect@1e00000 {
compatible = "qcom,sc7180-ipa-virt";
reg = <0 0x01e00000 0 0x1000>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
tcsr_mutex_regs: syscon@1f40000 { tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon"; compatible = "syscon";
reg = <0 0x01f40000 0 0x40000>; reg = <0 0x01f40000 0 0x40000>;
...@@ -1037,6 +1190,140 @@ pinmux { ...@@ -1037,6 +1190,140 @@ pinmux {
function = "qup15"; function = "qup15";
}; };
}; };
sdc1_on: sdc1-on {
pinconf-clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
pinconf-cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
pinconf-data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
pinconf-rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_off: sdc1-off {
pinconf-clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
pinconf-cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
pinconf-data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
pinconf-rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc2_on: sdc2-on {
pinconf-clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
pinconf-cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
pinconf-data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
pinconf-sd-cd {
pins = "gpio69";
bias-pull-up;
drive-strength = <2>;
};
};
sdc2_off: sdc2-off {
pinconf-clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
pinconf-cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
pinconf-data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
pinconf-sd-cd {
pins = "gpio69";
bias-disable;
drive-strength = <2>;
};
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
iommus = <&apps_smmu 0x80 0>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
bus-width = <4>;
status = "disabled";
};
gpucc: clock-controller@5090000 {
compatible = "qcom,sc7180-gpucc";
reg = <0 0x05090000 0 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
}; };
qspi: spi@88dc000 { qspi: spi@88dc000 {
...@@ -1081,8 +1368,8 @@ usb_1_qmpphy: phy-wrapper@88e9000 { ...@@ -1081,8 +1368,8 @@ usb_1_qmpphy: phy-wrapper@88e9000 {
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux"; clock-names = "aux", "cfg_ahb", "ref", "com_aux";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>; <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common"; reset-names = "phy", "common";
usb_1_ssphy: phy@88e9200 { usb_1_ssphy: phy@88e9200 {
...@@ -1100,6 +1387,13 @@ usb_1_ssphy: phy@88e9200 { ...@@ -1100,6 +1387,13 @@ usb_1_ssphy: phy@88e9200 {
}; };
}; };
dc_noc: interconnect@9160000 {
compatible = "qcom,sc7180-dc-noc";
reg = <0 0x09160000 0 0x03200>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system-cache-controller@9200000 { system-cache-controller@9200000 {
compatible = "qcom,sc7180-llcc"; compatible = "qcom,sc7180-llcc";
reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
...@@ -1107,6 +1401,20 @@ system-cache-controller@9200000 { ...@@ -1107,6 +1401,20 @@ system-cache-controller@9200000 {
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
}; };
gem_noc: interconnect@9680000 {
compatible = "qcom,sc7180-gem-noc";
reg = <0 0x09680000 0 0x3e200>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
npu_noc: interconnect@9990000 {
compatible = "qcom,sc7180-npu-noc";
reg = <0 0x09990000 0 0x1600>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
usb_1: usb@a6f8800 { usb_1: usb@a6f8800 {
compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>; reg = <0 0x0a6f8800 0 0x400>;
...@@ -1151,6 +1459,201 @@ usb_1_dwc3: dwc3@a600000 { ...@@ -1151,6 +1459,201 @@ usb_1_dwc3: dwc3@a600000 {
}; };
}; };
venus: video-codec@aa00000 {
compatible = "qcom,sc7180-venus";
reg = <0 0x0aa00000 0 0xff000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&videocc VENUS_GDSC>,
<&videocc VCODEC0_GDSC>;
power-domain-names = "venus", "vcodec0";
clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
<&videocc VIDEO_CC_VENUS_AHB_CLK>,
<&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
<&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
<&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
clock-names = "core", "iface", "bus",
"vcodec0_core", "vcodec0_bus";
iommus = <&apps_smmu 0x0c00 0x60>;
memory-region = <&venus_mem>;
video-decoder {
compatible = "venus-decoder";
};
video-encoder {
compatible = "venus-encoder";
};
};
videocc: clock-controller@ab00000 {
compatible = "qcom,sc7180-videocc";
reg = <0 0x0ab00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
camnoc_virt: interconnect@ac00000 {
compatible = "qcom,sc7180-camnoc-virt";
reg = <0 0x0ac00000 0 0x1000>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mdss: mdss@ae00000 {
compatible = "qcom,sc7180-mdss";
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "bus", "ahb", "core";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
assigned-clock-rates = <300000000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
iommus = <&apps_smmu 0x800 0x2>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
mdp: mdp@ae01000 {
compatible = "qcom,sc7180-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb0000 0 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "iface", "rot", "lut", "core",
"vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <300000000>,
<19200000>;
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
dsi0: dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
phys = <&dsi_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
};
dsi_phy: dsi-phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
<0 0x0ae94a00 0 0x1e0>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
status = "disabled";
};
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sc7180-dispcc";
reg = <0 0x0af00000 0 0x200000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&dsi_phy 0>,
<&dsi_phy 1>,
<0>,
<0>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dp_phy_pll_link_clk",
"dp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
pdc: interrupt-controller@b220000 { pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7180-pdc", "qcom,pdc"; compatible = "qcom,sc7180-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>; reg = <0 0x0b220000 0 0x30000>;
...@@ -1478,6 +1981,20 @@ rpmhpd_opp_turbo_l1: opp11 { ...@@ -1478,6 +1981,20 @@ rpmhpd_opp_turbo_l1: opp11 {
}; };
}; };
}; };
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
};
osm_l3: interconnect@18321000 {
compatible = "qcom,sc7180-osm-l3";
reg = <0 0x18321000 0 0x1400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#interconnect-cells = <1>;
}; };
cpufreq_hw: cpufreq@18323000 { cpufreq_hw: cpufreq@18323000 {
...@@ -1953,6 +2470,12 @@ aoss0_alert0: trip-point0 { ...@@ -1953,6 +2470,12 @@ aoss0_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
aoss0_crit: aoss0_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2008,6 +2531,12 @@ gpuss0_alert0: trip-point0 { ...@@ -2008,6 +2531,12 @@ gpuss0_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
gpuss0_crit: gpuss0_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2023,6 +2552,12 @@ gpuss1_alert0: trip-point0 { ...@@ -2023,6 +2552,12 @@ gpuss1_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
gpuss1_crit: gpuss1_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2038,6 +2573,12 @@ aoss1_alert0: trip-point0 { ...@@ -2038,6 +2573,12 @@ aoss1_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
aoss1_crit: aoss1_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2053,6 +2594,12 @@ cwlan_alert0: trip-point0 { ...@@ -2053,6 +2594,12 @@ cwlan_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
cwlan_crit: cwlan_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2068,6 +2615,12 @@ audio_alert0: trip-point0 { ...@@ -2068,6 +2615,12 @@ audio_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
audio_crit: audio_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2083,6 +2636,12 @@ ddr_alert0: trip-point0 { ...@@ -2083,6 +2636,12 @@ ddr_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
ddr_crit: ddr_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2098,6 +2657,12 @@ q6_hvx_alert0: trip-point0 { ...@@ -2098,6 +2657,12 @@ q6_hvx_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
q6_hvx_crit: q6_hvx_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2113,6 +2678,12 @@ camera_alert0: trip-point0 { ...@@ -2113,6 +2678,12 @@ camera_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
camera_crit: camera_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2128,6 +2699,12 @@ mdm_alert0: trip-point0 { ...@@ -2128,6 +2699,12 @@ mdm_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
mdm_crit: mdm_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2143,6 +2720,12 @@ mdm_dsp_alert0: trip-point0 { ...@@ -2143,6 +2720,12 @@ mdm_dsp_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
mdm_dsp_crit: mdm_dsp_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2158,6 +2741,12 @@ npu_alert0: trip-point0 { ...@@ -2158,6 +2741,12 @@ npu_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
npu_crit: npu_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
...@@ -2173,6 +2762,12 @@ video_alert0: trip-point0 { ...@@ -2173,6 +2762,12 @@ video_alert0: trip-point0 {
hysteresis = <2000>; hysteresis = <2000>;
type = "hot"; type = "hot";
}; };
video_crit: video_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
}; };
}; };
}; };
......
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View file @ 8bdbf169
...@@ -614,6 +614,11 @@ touchscreen@10 { ...@@ -614,6 +614,11 @@ touchscreen@10 {
}; };
}; };
&ipa {
status = "okay";
modem-init;
};
&lpasscc { &lpasscc {
status = "okay"; status = "okay";
}; };
...@@ -626,6 +631,10 @@ &mdss_mdp { ...@@ -626,6 +631,10 @@ &mdss_mdp {
status = "okay"; status = "okay";
}; };
&pm8998_pwrkey {
status = "disabled";
};
&qupv3_id_0 { &qupv3_id_0 {
status = "okay"; status = "okay";
}; };
...@@ -1292,3 +1301,9 @@ config { ...@@ -1292,3 +1301,9 @@ config {
}; };
}; };
}; };
&venus {
video-firmware {
iommus = <&apps_smmu 0x10b2 0x0>;
};
};
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View file @ 8bdbf169
...@@ -8,6 +8,8 @@ ...@@ -8,6 +8,8 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include "sdm845.dtsi" #include "sdm845.dtsi"
#include "pm8998.dtsi" #include "pm8998.dtsi"
#include "pmi8998.dtsi" #include "pmi8998.dtsi"
...@@ -359,11 +361,56 @@ zap-shader { ...@@ -359,11 +361,56 @@ zap-shader {
}; };
}; };
&i2c11 {
/* On Low speed expansion */
label = "LS-I2C1";
status = "okay";
};
&i2c14 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
&mss_pil { &mss_pil {
status = "okay"; status = "okay";
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
}; };
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
vddpe-3v3-supply = <&pcie0_3p3v_dual>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
};
&pcie0_phy {
status = "okay";
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l26a_1p2>;
};
&pcie1 {
status = "okay";
perst-gpio = <&tlmm 102 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
};
&pcie1_phy {
status = "okay";
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l26a_1p2>;
};
&pm8998_gpio { &pm8998_gpio {
vol_up_pin_a: vol-up-active { vol_up_pin_a: vol-up-active {
pins = "gpio6"; pins = "gpio6";
...@@ -384,6 +431,37 @@ resin { ...@@ -384,6 +431,37 @@ resin {
}; };
}; };
/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */
&q6afedai {
qi2s@22 {
reg = <22>;
qcom,sd-lines = <0 1 2 3>;
};
};
&q6asmdai {
dai@0 {
reg = <0>;
direction = <2>;
};
dai@1 {
reg = <1>;
direction = <2>;
};
dai@2 {
reg = <2>;
direction = <1>;
};
dai@3 {
reg = <3>;
direction = <2>;
is-compress-dai;
};
};
&qupv3_id_0 { &qupv3_id_0 {
status = "okay"; status = "okay";
}; };
...@@ -405,7 +483,121 @@ &sdhc_2 { ...@@ -405,7 +483,121 @@ &sdhc_2 {
cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
}; };
&sound {
compatible = "qcom,db845c-sndcard";
pinctrl-0 = <&quat_mi2s_active
&quat_mi2s_sd0_active
&quat_mi2s_sd1_active
&quat_mi2s_sd2_active
&quat_mi2s_sd3_active>;
pinctrl-names = "default";
model = "DB845c";
audio-routing =
"RX_BIAS", "MCLK",
"AMIC1", "MIC BIAS1",
"AMIC2", "MIC BIAS2",
"DMIC0", "MIC BIAS1",
"DMIC1", "MIC BIAS1",
"DMIC2", "MIC BIAS3",
"DMIC3", "MIC BIAS3",
"SpkrLeft IN", "SPK1 OUT",
"SpkrRight IN", "SPK2 OUT",
"MM_DL1", "MultiMedia1 Playback",
"MM_DL2", "MultiMedia2 Playback",
"MM_DL4", "MultiMedia4 Playback",
"MultiMedia3 Capture", "MM_UL3";
mm1-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
mm2-dai-link {
link-name = "MultiMedia2";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
};
};
mm3-dai-link {
link-name = "MultiMedia3";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
};
};
mm4-dai-link {
link-name = "MultiMedia4";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>;
};
};
slim-dai-link {
link-name = "SLIM Playback";
cpu {
sound-dai = <&q6afedai SLIMBUS_0_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>;
};
};
slimcap-dai-link {
link-name = "SLIM Capture";
cpu {
sound-dai = <&q6afedai SLIMBUS_0_TX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&wcd9340 1>;
};
};
};
&spi2 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
&tlmm { &tlmm {
pcie0_default_state: pcie0-default {
clkreq {
pins = "gpio36";
function = "pci_e0";
bias-pull-up;
};
reset-n {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
output-low;
bias-pull-down;
};
wake-n {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie0_pwren_state: pcie0-pwren { pcie0_pwren_state: pcie0-pwren {
pins = "gpio90"; pins = "gpio90";
function = "gpio"; function = "gpio";
...@@ -414,6 +606,39 @@ pcie0_pwren_state: pcie0-pwren { ...@@ -414,6 +606,39 @@ pcie0_pwren_state: pcie0-pwren {
bias-disable; bias-disable;
}; };
pcie1_default_state: pcie1-default {
perst-n {
pins = "gpio102";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
clkreq {
pins = "gpio103";
function = "pci_e1";
bias-pull-up;
};
wake-n {
pins = "gpio11";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
reset-n {
pins = "gpio75";
function = "gpio";
drive-strength = <16>;
bias-pull-up;
output-high;
};
};
sdc2_default_state: sdc2-default { sdc2_default_state: sdc2-default {
clk { clk {
pins = "sdc2_clk"; pins = "sdc2_clk";
...@@ -444,6 +669,20 @@ sdc2_card_det_n: sd-card-det-n { ...@@ -444,6 +669,20 @@ sdc2_card_det_n: sd-card-det-n {
function = "gpio"; function = "gpio";
bias-pull-up; bias-pull-up;
}; };
wcd_intr_default: wcd_intr_default {
pins = <54>;
function = "gpio";
input-enable;
bias-pull-down;
drive-strength = <2>;
};
};
&uart3 {
label = "LS-UART0";
status = "disabled";
}; };
&uart6 { &uart6 {
...@@ -461,6 +700,7 @@ bluetooth { ...@@ -461,6 +700,7 @@ bluetooth {
}; };
&uart9 { &uart9 {
label = "LS-UART1";
status = "okay"; status = "okay";
}; };
...@@ -534,6 +774,39 @@ &ufs_mem_phy { ...@@ -534,6 +774,39 @@ &ufs_mem_phy {
vdda-pll-supply = <&vreg_l26a_1p2>; vdda-pll-supply = <&vreg_l26a_1p2>;
}; };
&wcd9340{
pinctrl-0 = <&wcd_intr_default>;
pinctrl-names = "default";
clock-names = "extclk";
clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
reset-gpios = <&tlmm 64 0>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>;
swm: swm@c85 {
left_spkr: wsa8810-left{
compatible = "sdw10217201000";
reg = <0 1>;
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrLeft";
#sound-dai-cells = <0>;
};
right_spkr: wsa8810-right{
compatible = "sdw10217201000";
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
reg = <0 2>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrRight";
#sound-dai-cells = <0>;
};
};
};
&wifi { &wifi {
status = "okay"; status = "okay";
...@@ -546,6 +819,16 @@ &wifi { ...@@ -546,6 +819,16 @@ &wifi {
}; };
/* PINCTRL - additions to nodes defined in sdm845.dtsi */ /* PINCTRL - additions to nodes defined in sdm845.dtsi */
&qup_spi2_default {
drive-strength = <16>;
};
&qup_uart3_default{
pinmux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "qup3";
};
};
&qup_uart6_default { &qup_uart6_default {
pinmux { pinmux {
......
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View file @ 8bdbf169
...@@ -50,6 +50,7 @@ vreg_s4a_1p8: pm8998-smps4 { ...@@ -50,6 +50,7 @@ vreg_s4a_1p8: pm8998-smps4 {
&adsp_pas { &adsp_pas {
status = "okay"; status = "okay";
firmware-name = "qcom/sdm845/adsp.mdt";
}; };
&apps_rsc { &apps_rsc {
...@@ -350,6 +351,81 @@ vreg_s3c_0p6: smps3 { ...@@ -350,6 +351,81 @@ vreg_s3c_0p6: smps3 {
&cdsp_pas { &cdsp_pas {
status = "okay"; status = "okay";
firmware-name = "qcom/sdm845/cdsp.mdt";
};
&dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
qcom,dual-dsi-mode;
qcom,master-dsi;
#address-cells = <1>;
#size-cells = <0>;
ports {
port@1 {
endpoint {
remote-endpoint = <&truly_in_0>;
data-lanes = <0 1 2 3>;
};
};
};
panel@0 {
compatible = "truly,nt35597-2K-display";
reg = <0>;
vdda-supply = <&vreg_l14a_1p88>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
truly_in_0: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
truly_in_1: endpoint {
remote-endpoint = <&dsi1_out>;
};
};
};
};
};
&dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
&dsi1 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi1_1p2>;
qcom,dual-dsi-mode;
ports {
port@1 {
endpoint {
remote-endpoint = <&truly_in_1>;
data-lanes = <0 1 2 3>;
};
};
};
};
&dsi1_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi1_pll>;
}; };
&gcc { &gcc {
...@@ -372,6 +448,19 @@ &i2c10 { ...@@ -372,6 +448,19 @@ &i2c10 {
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
&mdss {
status = "okay";
};
&mdss_mdp {
status = "okay";
};
&mss_pil {
status = "okay";
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
};
&qupv3_id_1 { &qupv3_id_1 {
status = "okay"; status = "okay";
}; };
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ 8bdbf169
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h> #include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/thermal.h>
...@@ -491,6 +492,57 @@ glink-edge { ...@@ -491,6 +492,57 @@ glink-edge {
label = "lpass"; label = "lpass";
qcom,remote-pid = <2>; qcom,remote-pid = <2>;
mboxes = <&apss_shared 8>; mboxes = <&apss_shared 8>;
apr {
compatible = "qcom,apr-v2";
qcom,glink-channels = "apr_audio_svc";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
qcom,intents = <512 20>;
apr-service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
q6afe: apr-service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6afedai: dais {
compatible = "qcom,q6afe-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
};
};
q6asm: apr-service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6asmdai: dais {
compatible = "qcom,q6asm-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
iommus = <&apps_smmu 0x1821 0x0>;
};
};
q6adm: apr-service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6routing: routing {
compatible = "qcom,q6adm-routing";
#sound-dai-cells = <0>;
};
};
};
fastrpc { fastrpc {
compatible = "qcom,fastrpc"; compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,glink-channels = "fastrpcglink-apps-dsp";
...@@ -675,6 +727,17 @@ modem_smp2p_in: slave-kernel { ...@@ -675,6 +727,17 @@ modem_smp2p_in: slave-kernel {
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
}; };
ipa_smp2p_out: ipa-ap-to-modem {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
ipa_smp2p_in: ipa-modem-to-ap {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
}; };
smp2p-slpi { smp2p-slpi {
...@@ -1364,6 +1427,267 @@ system-cache-controller@1100000 { ...@@ -1364,6 +1427,267 @@ system-cache-controller@1100000 {
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
}; };
pcie0: pci@1c00000 {
compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
reg = <0 0x01c00000 0 0x2000>,
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
<0 0x60100000 0 0x100000>;
reg-names = "parf", "dbi", "elbi", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"tbu";
iommus = <&apps_smmu 0x1c10 0xf>;
iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
<0x100 &apps_smmu 0x1c11 0x1>,
<0x200 &apps_smmu 0x1c12 0x1>,
<0x300 &apps_smmu 0x1c13 0x1>,
<0x400 &apps_smmu 0x1c14 0x1>,
<0x500 &apps_smmu 0x1c15 0x1>,
<0x600 &apps_smmu 0x1c16 0x1>,
<0x700 &apps_smmu 0x1c17 0x1>,
<0x800 &apps_smmu 0x1c18 0x1>,
<0x900 &apps_smmu 0x1c19 0x1>,
<0xa00 &apps_smmu 0x1c1a 0x1>,
<0xb00 &apps_smmu 0x1c1b 0x1>,
<0xc00 &apps_smmu 0x1c1c 0x1>,
<0xd00 &apps_smmu 0x1c1d 0x1>,
<0xe00 &apps_smmu 0x1c1e 0x1>,
<0xf00 &apps_smmu 0x1c1f 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_0_GDSC>;
phys = <&pcie0_lane>;
phy-names = "pciephy";
status = "disabled";
};
pcie0_phy: phy@1c06000 {
compatible = "qcom,sdm845-qmp-pcie-phy";
reg = <0 0x01c06000 0 0x18c>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
assigned-clock-rates = <100000000>;
status = "disabled";
pcie0_lane: lanes@1c06200 {
reg = <0 0x01c06200 0 0x128>,
<0 0x01c06400 0 0x1fc>,
<0 0x01c06800 0 0x218>,
<0 0x01c06600 0 0x70>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
#phy-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
};
};
pcie1: pci@1c08000 {
compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
reg = <0 0x01c08000 0 0x2000>,
<0 0x40000000 0 0xf1d>,
<0 0x40000f20 0 0xa8>,
<0 0x40100000 0 0x100000>;
reg-names = "parf", "dbi", "elbi", "config";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_1_CLKREF_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"ref",
"tbu";
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommus = <&apps_smmu 0x1c00 0xf>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>,
<0x200 &apps_smmu 0x1c02 0x1>,
<0x300 &apps_smmu 0x1c03 0x1>,
<0x400 &apps_smmu 0x1c04 0x1>,
<0x500 &apps_smmu 0x1c05 0x1>,
<0x600 &apps_smmu 0x1c06 0x1>,
<0x700 &apps_smmu 0x1c07 0x1>,
<0x800 &apps_smmu 0x1c08 0x1>,
<0x900 &apps_smmu 0x1c09 0x1>,
<0xa00 &apps_smmu 0x1c0a 0x1>,
<0xb00 &apps_smmu 0x1c0b 0x1>,
<0xc00 &apps_smmu 0x1c0c 0x1>,
<0xd00 &apps_smmu 0x1c0d 0x1>,
<0xe00 &apps_smmu 0x1c0e 0x1>,
<0xf00 &apps_smmu 0x1c0f 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_1_GDSC>;
phys = <&pcie1_lane>;
phy-names = "pciephy";
status = "disabled";
};
pcie1_phy: phy@1c0a000 {
compatible = "qcom,sdm845-qhp-pcie-phy";
reg = <0 0x01c0a000 0 0x800>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_CLKREF_CLK>,
<&gcc GCC_PCIE_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
assigned-clock-rates = <100000000>;
status = "disabled";
pcie1_lane: lanes@1c06200 {
reg = <0 0x01c0a800 0 0x800>,
<0 0x01c0a800 0 0x800>,
<0 0x01c0b800 0 0x400>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe0";
#phy-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
};
};
mem_noc: interconnect@1380000 {
compatible = "qcom,sdm845-mem-noc";
reg = <0 0x01380000 0 0x27200>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
dc_noc: interconnect@14e0000 {
compatible = "qcom,sdm845-dc-noc";
reg = <0 0x014e0000 0 0x400>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
config_noc: interconnect@1500000 {
compatible = "qcom,sdm845-config-noc";
reg = <0 0x01500000 0 0x5080>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1620000 {
compatible = "qcom,sdm845-system-noc";
reg = <0 0x01620000 0 0x18080>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sdm845-aggre1-noc";
reg = <0 0x016e0000 0 0x15080>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sdm845-aggre2-noc";
reg = <0 0x01700000 0 0x1f300>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,sdm845-mmss-noc";
reg = <0 0x01740000 0 0x1c100>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
ufs_mem_hc: ufshc@1d84000 { ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc", compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0"; "jedec,ufs-2.0";
...@@ -1435,6 +1759,44 @@ ufs_mem_phy_lanes: lanes@1d87400 { ...@@ -1435,6 +1759,44 @@ ufs_mem_phy_lanes: lanes@1d87400 {
}; };
}; };
ipa: ipa@1e40000 {
compatible = "qcom,sdm845-ipa";
reg = <0 0x1e40000 0 0x7000>,
<0 0x1e47000 0 0x2000>,
<0 0x1e04000 0 0x2c000>;
reg-names = "ipa-reg",
"ipa-shared",
"gsi";
interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
<&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ipa",
"gsi",
"ipa-clock-query",
"ipa-setup-ready";
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
interconnects = <&aggre2_noc MASTER_IPA &mem_noc SLAVE_EBI1>,
<&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>,
<&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
interconnect-names = "memory",
"imem",
"config";
qcom,smem-states = <&ipa_smp2p_out 0>,
<&ipa_smp2p_out 1>;
qcom,smem-state-names = "ipa-clock-enabled-valid",
"ipa-clock-enabled";
modem-remoteproc = <&mss_pil>;
status = "disabled";
};
tcsr_mutex_regs: syscon@1f40000 { tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon"; compatible = "syscon";
reg = <0 0x01f40000 0 0x40000>; reg = <0 0x01f40000 0 0x40000>;
...@@ -1837,6 +2199,142 @@ pinmux { ...@@ -1837,6 +2199,142 @@ pinmux {
function = "qup15"; function = "qup15";
}; };
}; };
quat_mi2s_sleep: quat_mi2s_sleep {
mux {
pins = "gpio58", "gpio59";
function = "gpio";
};
config {
pins = "gpio58", "gpio59";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
quat_mi2s_active: quat_mi2s_active {
mux {
pins = "gpio58", "gpio59";
function = "qua_mi2s";
};
config {
pins = "gpio58", "gpio59";
drive-strength = <8>;
bias-disable;
output-high;
};
};
quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
mux {
pins = "gpio60";
function = "gpio";
};
config {
pins = "gpio60";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
quat_mi2s_sd0_active: quat_mi2s_sd0_active {
mux {
pins = "gpio60";
function = "qua_mi2s";
};
config {
pins = "gpio60";
drive-strength = <8>;
bias-disable;
};
};
quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
mux {
pins = "gpio61";
function = "gpio";
};
config {
pins = "gpio61";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
quat_mi2s_sd1_active: quat_mi2s_sd1_active {
mux {
pins = "gpio61";
function = "qua_mi2s";
};
config {
pins = "gpio61";
drive-strength = <8>;
bias-disable;
};
};
quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
mux {
pins = "gpio62";
function = "gpio";
};
config {
pins = "gpio62";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
quat_mi2s_sd2_active: quat_mi2s_sd2_active {
mux {
pins = "gpio62";
function = "qua_mi2s";
};
config {
pins = "gpio62";
drive-strength = <8>;
bias-disable;
};
};
quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
mux {
pins = "gpio63";
function = "gpio";
};
config {
pins = "gpio63";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
quat_mi2s_sd3_active: quat_mi2s_sd3_active {
mux {
pins = "gpio63";
function = "qua_mi2s";
};
config {
pins = "gpio63";
drive-strength = <8>;
bias-disable;
};
};
}; };
mss_pil: remoteproc@4080000 { mss_pil: remoteproc@4080000 {
...@@ -1903,8 +2401,12 @@ gpucc: clock-controller@5090000 { ...@@ -1903,8 +2401,12 @@ gpucc: clock-controller@5090000 {
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
clocks = <&rpmhcc RPMH_CXO_CLK>; clocks = <&rpmhcc RPMH_CXO_CLK>,
clock-names = "xo"; <&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src";
}; };
stm@6002000 { stm@6002000 {
...@@ -2386,6 +2888,87 @@ qspi: spi@88df000 { ...@@ -2386,6 +2888,87 @@ qspi: spi@88df000 {
status = "disabled"; status = "disabled";
}; };
slim: slim@171c0000 {
compatible = "qcom,slim-ngd-v2.1.0";
reg = <0 0x171c0000 0 0x2c000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
qcom,apps-ch-pipes = <0x780000>;
qcom,ea-pc = <0x270>;
status = "okay";
dmas = <&slimbam 3>, <&slimbam 4>,
<&slimbam 5>, <&slimbam 6>;
dma-names = "rx", "tx", "tx2", "rx2";
iommus = <&apps_smmu 0x1806 0x0>;
#address-cells = <1>;
#size-cells = <0>;
ngd@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
wcd9340_ifd: ifd@0{
compatible = "slim217,250";
reg = <0 0>;
};
wcd9340: codec@1{
compatible = "slim217,250";
reg = <1 0>;
slim-ifc-dev = <&wcd9340_ifd>;
#sound-dai-cells = <1>;
interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
#clock-cells = <0>;
clock-frequency = <9600000>;
clock-output-names = "mclk";
qcom,micbias1-millivolt = <1800>;
qcom,micbias2-millivolt = <1800>;
qcom,micbias3-millivolt = <1800>;
qcom,micbias4-millivolt = <1800>;
#address-cells = <1>;
#size-cells = <1>;
wcdgpio: gpio-controller@42 {
compatible = "qcom,wcd9340-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42 0x2>;
};
swm: swm@c85 {
compatible = "qcom,soundwire-v1.3.0";
reg = <0xc85 0x40>;
interrupts-extended = <&wcd9340 20>;
qcom,dout-ports = <6>;
qcom,din-ports = <2>;
qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
#sound-dai-cells = <1>;
clocks = <&wcd9340>;
clock-names = "iface";
#address-cells = <2>;
#size-cells = <0>;
};
};
};
};
sound: sound {
};
usb_1_hsphy: phy@88e2000 { usb_1_hsphy: phy@88e2000 {
compatible = "qcom,sdm845-qusb2-phy"; compatible = "qcom,sdm845-qusb2-phy";
reg = <0 0x088e2000 0 0x400>; reg = <0 0x088e2000 0 0x400>;
...@@ -2570,39 +3153,42 @@ usb_2_dwc3: dwc3@a800000 { ...@@ -2570,39 +3153,42 @@ usb_2_dwc3: dwc3@a800000 {
}; };
}; };
video-codec@aa00000 { venus: video-codec@aa00000 {
compatible = "qcom,sdm845-venus"; compatible = "qcom,sdm845-venus-v2";
reg = <0 0x0aa00000 0 0xff000>; reg = <0 0x0aa00000 0 0xff000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&videocc VENUS_GDSC>; power-domains = <&videocc VENUS_GDSC>,
<&videocc VCODEC0_GDSC>,
<&videocc VCODEC1_GDSC>;
power-domain-names = "venus", "vcodec0", "vcodec1";
clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
<&videocc VIDEO_CC_VENUS_AHB_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>,
<&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
clock-names = "core", "iface", "bus"; <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
<&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
<&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
<&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
clock-names = "core", "iface", "bus",
"vcodec0_core", "vcodec0_bus",
"vcodec1_core", "vcodec1_bus";
iommus = <&apps_smmu 0x10a0 0x8>, iommus = <&apps_smmu 0x10a0 0x8>,
<&apps_smmu 0x10b0 0x0>; <&apps_smmu 0x10b0 0x0>;
memory-region = <&venus_mem>; memory-region = <&venus_mem>;
video-core0 { video-core0 {
compatible = "venus-decoder"; compatible = "venus-decoder";
clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
<&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
clock-names = "core", "bus";
power-domains = <&videocc VCODEC0_GDSC>;
}; };
video-core1 { video-core1 {
compatible = "venus-encoder"; compatible = "venus-encoder";
clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
<&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
clock-names = "core", "bus";
power-domains = <&videocc VCODEC1_GDSC>;
}; };
}; };
videocc: clock-controller@ab00000 { videocc: clock-controller@ab00000 {
compatible = "qcom,sdm845-videocc"; compatible = "qcom,sdm845-videocc";
reg = <0 0x0ab00000 0 0x10000>; reg = <0 0x0ab00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>; #clock-cells = <1>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
...@@ -2933,6 +3519,24 @@ opp-200000000 { ...@@ -2933,6 +3519,24 @@ opp-200000000 {
dispcc: clock-controller@af00000 { dispcc: clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc"; compatible = "qcom,sdm845-dispcc";
reg = <0 0x0af00000 0 0x10000>; reg = <0 0x0af00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<0>,
<0>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"gcc_disp_gpll0_div_clk_src",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_byteclk",
"dsi1_phy_pll_out_dsiclk",
"dp_link_clk_divsel_ten",
"dp_vco_divided_clk_src_mux";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
...@@ -3098,6 +3702,13 @@ lpasscc: clock-controller@17014000 { ...@@ -3098,6 +3702,13 @@ lpasscc: clock-controller@17014000 {
status = "disabled"; status = "disabled";
}; };
gladiator_noc: interconnect@17900000 {
compatible = "qcom,sdm845-gladiator-noc";
reg = <0 0x17900000 0 0xd080>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
watchdog@17980000 { watchdog@17980000 {
compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
reg = <0 0x17980000 0 0x1000>; reg = <0 0x17980000 0 0x1000>;
...@@ -3127,6 +3738,10 @@ apps_rsc: rsc@179c0000 { ...@@ -3127,6 +3738,10 @@ apps_rsc: rsc@179c0000 {
<WAKE_TCS 3>, <WAKE_TCS 3>,
<CONTROL_TCS 1>; <CONTROL_TCS 1>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
rpmhcc: clock-controller { rpmhcc: clock-controller {
compatible = "qcom,sdm845-rpmh-clk"; compatible = "qcom,sdm845-rpmh-clk";
#clock-cells = <1>; #clock-cells = <1>;
...@@ -3183,11 +3798,6 @@ rpmhpd_opp_turbo_l1: opp10 { ...@@ -3183,11 +3798,6 @@ rpmhpd_opp_turbo_l1: opp10 {
}; };
}; };
}; };
rsc_hlos: interconnect {
compatible = "qcom,sdm845-rsc-hlos";
#interconnect-cells = <1>;
};
}; };
intc: interrupt-controller@17a00000 { intc: interrupt-controller@17a00000 {
...@@ -3210,6 +3820,18 @@ msi-controller@17a40000 { ...@@ -3210,6 +3820,18 @@ msi-controller@17a40000 {
}; };
}; };
slimbam: dma@17184000 {
compatible = "qcom,bam-v1.7.0";
qcom,controlled-remotely;
reg = <0 0x17184000 0 0x2a000>;
num-channels = <31>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <1>;
qcom,num-ees = <2>;
iommus = <&apps_smmu 0x1806 0x0>;
};
timer@17c90000 { timer@17c90000 {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
...@@ -3268,6 +3890,16 @@ frame@17d10000 { ...@@ -3268,6 +3890,16 @@ frame@17d10000 {
}; };
}; };
osm_l3: interconnect@17d41000 {
compatible = "qcom,sdm845-osm-l3";
reg = <0 0x17d41000 0 0x1400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#interconnect-cells = <1>;
};
cpufreq_hw: cpufreq@17d43000 { cpufreq_hw: cpufreq@17d43000 {
compatible = "qcom,cpufreq-hw"; compatible = "qcom,cpufreq-hw";
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
......
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View file @ 8bdbf169
...@@ -7,7 +7,10 @@ ...@@ -7,7 +7,10 @@
/dts-v1/; /dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include "sdm845.dtsi" #include "sdm845.dtsi"
#include "pm8998.dtsi" #include "pm8998.dtsi"
...@@ -353,6 +356,75 @@ &qupv3_id_1 { ...@@ -353,6 +356,75 @@ &qupv3_id_1 {
status = "okay"; status = "okay";
}; };
&q6asmdai {
dai@0 {
reg = <0>;
direction = <2>;
};
dai@1 {
reg = <1>;
direction = <1>;
};
};
&sound {
compatible = "qcom,db845c-sndcard";
model = "Lenovo-YOGA-C630-13Q50";
audio-routing =
"RX_BIAS", "MCLK",
"AMIC2", "MIC BIAS2",
"SpkrLeft IN", "SPK1 OUT",
"SpkrRight IN", "SPK2 OUT",
"MM_DL1", "MultiMedia1 Playback",
"MultiMedia2 Capture", "MM_UL2";
mm1-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
mm2-dai-link {
link-name = "MultiMedia2";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
};
};
slim-dai-link {
link-name = "SLIM Playback";
cpu {
sound-dai = <&q6afedai SLIMBUS_0_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>;
};
};
slimcap-dai-link {
link-name = "SLIM Capture";
cpu {
sound-dai = <&q6afedai SLIMBUS_0_TX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&wcd9340 1>;
};
};
};
&tlmm { &tlmm {
gpio-reserved-ranges = <0 4>, <81 4>; gpio-reserved-ranges = <0 4>, <81 4>;
...@@ -382,6 +454,15 @@ i2c12_hid_active: i2c12-hid-active { ...@@ -382,6 +454,15 @@ i2c12_hid_active: i2c12-hid-active {
bias-pull-up; bias-pull-up;
drive-strength = <2>; drive-strength = <2>;
}; };
wcd_intr_default: wcd_intr_default {
pins = <54>;
function = "gpio";
input-enable;
bias-pull-down;
drive-strength = <2>;
};
}; };
&uart6 { &uart6 {
...@@ -465,3 +546,36 @@ &usb_2_qmpphy { ...@@ -465,3 +546,36 @@ &usb_2_qmpphy {
vdda-phy-supply = <&vdda_usb2_ss_1p2>; vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>; vdda-pll-supply = <&vdda_usb2_ss_core>;
}; };
&wcd9340{
pinctrl-0 = <&wcd_intr_default>;
pinctrl-names = "default";
clock-names = "extclk";
clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
reset-gpios = <&tlmm 64 0>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>;
swm: swm@c85 {
left_spkr: wsa8810-left{
compatible = "sdw10217211000";
reg = <0 3>;
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrLeft";
#sound-dai-cells = <0>;
};
right_spkr: wsa8810-right{
compatible = "sdw10217211000";
powerdown-gpios = <&wcdgpio 3 GPIO_ACTIVE_HIGH>;
reg = <0 4>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrRight";
#sound-dai-cells = <0>;
};
};
};
arch/arm64/boot/dts/qcom/sm8250-mtp.dts 0 → 100644
View file @ 8bdbf169
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include "sm8250.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SM8250 MTP";
compatible = "qcom,sm8250-mtp";
aliases {
serial0 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&qupv3_id_1 {
status = "okay";
};
&uart2 {
status = "okay";
};
arch/arm64/boot/dts/qcom/sm8250.dtsi 0 → 100644
View file @ 8bdbf169
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm";
#reset-cells = <1>;
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: memory@80000000 {
reg = <0x0 0x80000000 0x0 0x600000>;
no-map;
};
xbl_aop_mem: memory@80700000 {
reg = <0x0 0x80700000 0x0 0x160000>;
no-map;
};
cmd_db: memory@80860000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x80860000 0x0 0x20000>;
no-map;
};
smem_mem: memory@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
};
removed_mem: memory@80b00000 {
reg = <0x0 0x80b00000 0x0 0x5300000>;
no-map;
};
camera_mem: memory@86200000 {
reg = <0x0 0x86200000 0x0 0x500000>;
no-map;
};
wlan_mem: memory@86700000 {
reg = <0x0 0x86700000 0x0 0x100000>;
no-map;
};
ipa_fw_mem: memory@86800000 {
reg = <0x0 0x86800000 0x0 0x10000>;
no-map;
};
ipa_gsi_mem: memory@86810000 {
reg = <0x0 0x86810000 0x0 0xa000>;
no-map;
};
gpu_mem: memory@8681a000 {
reg = <0x0 0x8681a000 0x0 0x2000>;
no-map;
};
npu_mem: memory@86900000 {
reg = <0x0 0x86900000 0x0 0x500000>;
no-map;
};
video_mem: memory@86e00000 {
reg = <0x0 0x86e00000 0x0 0x500000>;
no-map;
};
cvp_mem: memory@87300000 {
reg = <0x0 0x87300000 0x0 0x500000>;
no-map;
};
cdsp_mem: memory@87800000 {
reg = <0x0 0x87800000 0x0 0x1400000>;
no-map;
};
slpi_mem: memory@88c00000 {
reg = <0x0 0x88c00000 0x0 0x1500000>;
no-map;
};
adsp_mem: memory@8a100000 {
reg = <0x0 0x8a100000 0x0 0x1d00000>;
no-map;
};
spss_mem: memory@8be00000 {
reg = <0x0 0x8be00000 0x0 0x100000>;
no-map;
};
cdsp_secure_heap: memory@8bf00000 {
reg = <0x0 0x8bf00000 0x0 0x4600000>;
no-map;
};
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sm8250";
reg = <0x0 0x00100000 0x0 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "bi_tcxo", "sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc 133>, <&gcc 134>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
uart2: serial@a90000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00a90000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc 113>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8250-pdc";
reg = <0x0b220000 0x30000>, <0x17c000f0 0x60>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
<125 63 1>, <126 716 12>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
spmi: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x0001100>,
<0x0 0x0c600000 0x0 0x2000000>,
<0x0 0x0e600000 0x0 0x0100000>,
<0x0 0x0e700000 0x0 0x00a0000>,
<0x0 0x0c40a000 0x0 0x0026000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x0 0x18200000 0x0 0x10000>,
<0x0 0x18210000 0x0 0x10000>,
<0x0 0x18220000 0x0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
rpmhcc: clock-controller {
compatible = "qcom,sm8250-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x0 0x01f40000 0x0 0x40000>;
};
timer@17c20000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x17c20000 0x0 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c21000 0x0 0x1000>,
<0x0 0x17c22000 0x0 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c23000 0x0 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c25000 0x0 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c27000 0x0 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c29000 0x0 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c2b000 0x0 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c2d000 0x0 0x1000>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
};
drivers/bus/ti-sysc.c
View file @ 8bdbf169
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/clkdev.h> #include <linux/clkdev.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/list.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm_domain.h> #include <linux/pm_domain.h>
...@@ -15,15 +16,47 @@ ...@@ -15,15 +16,47 @@
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/sys_soc.h>
#include <linux/iopoll.h> #include <linux/iopoll.h>
#include <linux/platform_data/ti-sysc.h> #include <linux/platform_data/ti-sysc.h>
#include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/bus/ti-sysc.h>
#define DIS_ISP BIT(2)
#define DIS_IVA BIT(1)
#define DIS_SGX BIT(0)
#define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
#define MAX_MODULE_SOFTRESET_WAIT 10000 #define MAX_MODULE_SOFTRESET_WAIT 10000
static const char * const reg_names[] = { "rev", "sysc", "syss", }; enum sysc_soc {
SOC_UNKNOWN,
SOC_2420,
SOC_2430,
SOC_3430,
SOC_3630,
SOC_4430,
SOC_4460,
SOC_4470,
SOC_5430,
SOC_AM3,
SOC_AM4,
SOC_DRA7,
};
struct sysc_address {
unsigned long base;
struct list_head node;
};
struct sysc_soc_info {
unsigned long general_purpose:1;
enum sysc_soc soc;
struct mutex list_lock; /* disabled modules list lock */
struct list_head disabled_modules;
};
enum sysc_clocks { enum sysc_clocks {
SYSC_FCK, SYSC_FCK,
...@@ -39,6 +72,8 @@ enum sysc_clocks { ...@@ -39,6 +72,8 @@ enum sysc_clocks {
SYSC_MAX_CLOCKS, SYSC_MAX_CLOCKS,
}; };
static struct sysc_soc_info *sysc_soc;
static const char * const reg_names[] = { "rev", "sysc", "syss", };
static const char * const clock_names[SYSC_MAX_CLOCKS] = { static const char * const clock_names[SYSC_MAX_CLOCKS] = {
"fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
"opt5", "opt6", "opt7", "opt5", "opt6", "opt7",
...@@ -70,11 +105,13 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = { ...@@ -70,11 +105,13 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = {
* @child_needs_resume: runtime resume needed for child on resume from suspend * @child_needs_resume: runtime resume needed for child on resume from suspend
* @disable_on_idle: status flag used for disabling modules with resets * @disable_on_idle: status flag used for disabling modules with resets
* @idle_work: work structure used to perform delayed idle on a module * @idle_work: work structure used to perform delayed idle on a module
* @clk_enable_quirk: module specific clock enable quirk * @pre_reset_quirk: module specific pre-reset quirk
* @clk_disable_quirk: module specific clock disable quirk * @post_reset_quirk: module specific post-reset quirk
* @reset_done_quirk: module specific reset done quirk * @reset_done_quirk: module specific reset done quirk
* @module_enable_quirk: module specific enable quirk * @module_enable_quirk: module specific enable quirk
* @module_disable_quirk: module specific disable quirk * @module_disable_quirk: module specific disable quirk
* @module_unlock_quirk: module specific sysconfig unlock quirk
* @module_lock_quirk: module specific sysconfig lock quirk
*/ */
struct sysc { struct sysc {
struct device *dev; struct device *dev;
...@@ -97,11 +134,13 @@ struct sysc { ...@@ -97,11 +134,13 @@ struct sysc {
unsigned int needs_resume:1; unsigned int needs_resume:1;
unsigned int child_needs_resume:1; unsigned int child_needs_resume:1;
struct delayed_work idle_work; struct delayed_work idle_work;
void (*clk_enable_quirk)(struct sysc *sysc); void (*pre_reset_quirk)(struct sysc *sysc);
void (*clk_disable_quirk)(struct sysc *sysc); void (*post_reset_quirk)(struct sysc *sysc);
void (*reset_done_quirk)(struct sysc *sysc); void (*reset_done_quirk)(struct sysc *sysc);
void (*module_enable_quirk)(struct sysc *sysc); void (*module_enable_quirk)(struct sysc *sysc);
void (*module_disable_quirk)(struct sysc *sysc); void (*module_disable_quirk)(struct sysc *sysc);
void (*module_unlock_quirk)(struct sysc *sysc);
void (*module_lock_quirk)(struct sysc *sysc);
}; };
static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
...@@ -624,7 +663,7 @@ static void sysc_check_one_child(struct sysc *ddata, ...@@ -624,7 +663,7 @@ static void sysc_check_one_child(struct sysc *ddata,
const char *name; const char *name;
name = of_get_property(np, "ti,hwmods", NULL); name = of_get_property(np, "ti,hwmods", NULL);
if (name) if (name && !of_device_is_compatible(np, "ti,sysc"))
dev_warn(ddata->dev, "really a child ti,hwmods property?"); dev_warn(ddata->dev, "really a child ti,hwmods property?");
sysc_check_quirk_stdout(ddata, np); sysc_check_quirk_stdout(ddata, np);
...@@ -861,6 +900,22 @@ static void sysc_show_registers(struct sysc *ddata) ...@@ -861,6 +900,22 @@ static void sysc_show_registers(struct sysc *ddata)
buf); buf);
} }
/**
* sysc_write_sysconfig - handle sysconfig quirks for register write
* @ddata: device driver data
* @value: register value
*/
static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
{
if (ddata->module_unlock_quirk)
ddata->module_unlock_quirk(ddata);
sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
if (ddata->module_lock_quirk)
ddata->module_lock_quirk(ddata);
}
#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
#define SYSC_CLOCACT_ICK 2 #define SYSC_CLOCACT_ICK 2
...@@ -907,7 +962,7 @@ static int sysc_enable_module(struct device *dev) ...@@ -907,7 +962,7 @@ static int sysc_enable_module(struct device *dev)
reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
reg |= best_mode << regbits->sidle_shift; reg |= best_mode << regbits->sidle_shift;
sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); sysc_write_sysconfig(ddata, reg);
set_midle: set_midle:
/* Set MIDLE mode */ /* Set MIDLE mode */
...@@ -926,14 +981,14 @@ static int sysc_enable_module(struct device *dev) ...@@ -926,14 +981,14 @@ static int sysc_enable_module(struct device *dev)
reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
reg |= best_mode << regbits->midle_shift; reg |= best_mode << regbits->midle_shift;
sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); sysc_write_sysconfig(ddata, reg);
set_autoidle: set_autoidle:
/* Autoidle bit must enabled separately if available */ /* Autoidle bit must enabled separately if available */
if (regbits->autoidle_shift >= 0 && if (regbits->autoidle_shift >= 0 &&
ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
reg |= 1 << regbits->autoidle_shift; reg |= 1 << regbits->autoidle_shift;
sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); sysc_write_sysconfig(ddata, reg);
} }
if (ddata->module_enable_quirk) if (ddata->module_enable_quirk)
...@@ -991,7 +1046,7 @@ static int sysc_disable_module(struct device *dev) ...@@ -991,7 +1046,7 @@ static int sysc_disable_module(struct device *dev)
reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
reg |= best_mode << regbits->midle_shift; reg |= best_mode << regbits->midle_shift;
sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); sysc_write_sysconfig(ddata, reg);
set_sidle: set_sidle:
/* Set SIDLE mode */ /* Set SIDLE mode */
...@@ -1014,7 +1069,7 @@ static int sysc_disable_module(struct device *dev) ...@@ -1014,7 +1069,7 @@ static int sysc_disable_module(struct device *dev)
if (regbits->autoidle_shift >= 0 && if (regbits->autoidle_shift >= 0 &&
ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
reg |= 1 << regbits->autoidle_shift; reg |= 1 << regbits->autoidle_shift;
sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); sysc_write_sysconfig(ddata, reg);
return 0; return 0;
} }
...@@ -1216,16 +1271,16 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { ...@@ -1216,16 +1271,16 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
SYSC_QUIRK_LEGACY_IDLE), SYSC_QUIRK_LEGACY_IDLE),
SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
SYSC_QUIRK_LEGACY_IDLE), SYSC_QUIRK_LEGACY_IDLE),
SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
SYSC_QUIRK_LEGACY_IDLE), SYSC_QUIRK_LEGACY_IDLE),
SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
0), 0),
/* Some timers on omap4 and later */ /* Some timers on omap4 and later */
SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff, SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff,
0), 0),
SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff, SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff,
0), 0),
SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
...@@ -1238,19 +1293,27 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { ...@@ -1238,19 +1293,27 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
/* Quirks that need to be set based on the module address */ /* Quirks that need to be set based on the module address */
SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff, SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
SYSC_QUIRK_SWSUP_SIDLE), SYSC_QUIRK_SWSUP_SIDLE),
/* Quirks that need to be set based on detected module */ /* Quirks that need to be set based on detected module */
SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
SYSC_MODULE_QUIRK_AESS), SYSC_MODULE_QUIRK_AESS),
SYSC_QUIRK("dcan", 0x48480000, 0x20, -1, -1, 0xa3170504, 0xffffffff, SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
SYSC_QUIRK_CLKDM_NOAUTO), SYSC_QUIRK_CLKDM_NOAUTO),
SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -1, 0x500a0200, 0xffffffff, SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
SYSC_QUIRK_CLKDM_NOAUTO), SYSC_QUIRK_CLKDM_NOAUTO),
SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -1, 0x500a0200, 0xffffffff, SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
SYSC_QUIRK_CLKDM_NOAUTO), SYSC_QUIRK_CLKDM_NOAUTO),
SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
SYSC_QUIRK_OPT_CLKS_NEEDED),
SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
SYSC_MODULE_QUIRK_HDQ1W), SYSC_MODULE_QUIRK_HDQ1W),
SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
...@@ -1263,71 +1326,91 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { ...@@ -1263,71 +1326,91 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
SYSC_MODULE_QUIRK_I2C), SYSC_MODULE_QUIRK_I2C),
SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
SYSC_MODULE_QUIRK_I2C), SYSC_MODULE_QUIRK_I2C),
SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0), SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
SYSC_MODULE_QUIRK_SGX), SYSC_MODULE_QUIRK_SGX),
SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
SYSC_MODULE_QUIRK_RTC_UNLOCK),
SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -1, 0x4ea2080d, 0xffffffff, SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
SYSC_MODULE_QUIRK_WDT), SYSC_MODULE_QUIRK_WDT),
/* PRUSS on am3, am4 and am5 */
SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
SYSC_MODULE_QUIRK_PRUSS),
/* Watchdog on am3 and am4 */ /* Watchdog on am3 and am4 */
SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
#ifdef DEBUG #ifdef DEBUG
SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0), SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0), SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0), SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
0xffff00f0, 0), 0xffff00f0, 0),
SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0), SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0), SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0), SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0), SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0), SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0), SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0), SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0), SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 0),
SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0), SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0), SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0), SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0), SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0), SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0), SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0), SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0), SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0), SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0), SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0), SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0), SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0), SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0), SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0), SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0), SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0), SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0), SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0), SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0), SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0), SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0), SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0), SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0), SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0), SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, 0),
SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0), SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
#endif #endif
}; };
...@@ -1349,16 +1432,13 @@ static void sysc_init_early_quirks(struct sysc *ddata) ...@@ -1349,16 +1432,13 @@ static void sysc_init_early_quirks(struct sysc *ddata)
if (q->base != ddata->module_pa) if (q->base != ddata->module_pa)
continue; continue;
if (q->rev_offset >= 0 && if (q->rev_offset != ddata->offsets[SYSC_REVISION])
q->rev_offset != ddata->offsets[SYSC_REVISION])
continue; continue;
if (q->sysc_offset >= 0 && if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
continue; continue;
if (q->syss_offset >= 0 && if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
continue; continue;
ddata->name = q->name; ddata->name = q->name;
...@@ -1378,16 +1458,13 @@ static void sysc_init_revision_quirks(struct sysc *ddata) ...@@ -1378,16 +1458,13 @@ static void sysc_init_revision_quirks(struct sysc *ddata)
if (q->base && q->base != ddata->module_pa) if (q->base && q->base != ddata->module_pa)
continue; continue;
if (q->rev_offset >= 0 && if (q->rev_offset != ddata->offsets[SYSC_REVISION])
q->rev_offset != ddata->offsets[SYSC_REVISION])
continue; continue;
if (q->sysc_offset >= 0 && if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
continue; continue;
if (q->syss_offset >= 0 && if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
continue; continue;
if (q->revision == ddata->revision || if (q->revision == ddata->revision ||
...@@ -1399,8 +1476,130 @@ static void sysc_init_revision_quirks(struct sysc *ddata) ...@@ -1399,8 +1476,130 @@ static void sysc_init_revision_quirks(struct sysc *ddata)
} }
} }
/*
* DSS needs dispc outputs disabled to reset modules. Returns mask of
* enabled DSS interrupts. Eventually we may be able to do this on
* dispc init rather than top-level DSS init.
*/
static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
bool disable)
{
bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
int manager_count;
bool framedonetv_irq;
u32 val, irq_mask = 0;
switch (sysc_soc->soc) {
case SOC_2420 ... SOC_3630:
manager_count = 2;
framedonetv_irq = false;
break;
case SOC_4430 ... SOC_4470:
manager_count = 3;
break;
case SOC_5430:
case SOC_DRA7:
manager_count = 4;
break;
case SOC_AM4:
manager_count = 1;
break;
case SOC_UNKNOWN:
default:
return 0;
};
/* Remap the whole module range to be able to reset dispc outputs */
devm_iounmap(ddata->dev, ddata->module_va);
ddata->module_va = devm_ioremap(ddata->dev,
ddata->module_pa,
ddata->module_size);
if (!ddata->module_va)
return -EIO;
/* DISP_CONTROL */
val = sysc_read(ddata, dispc_offset + 0x40);
lcd_en = val & lcd_en_mask;
digit_en = val & digit_en_mask;
if (lcd_en)
irq_mask |= BIT(0); /* FRAMEDONE */
if (digit_en) {
if (framedonetv_irq)
irq_mask |= BIT(24); /* FRAMEDONETV */
else
irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
}
if (disable & (lcd_en | digit_en))
sysc_write(ddata, dispc_offset + 0x40,
val & ~(lcd_en_mask | digit_en_mask));
if (manager_count <= 2)
return irq_mask;
/* DISPC_CONTROL2 */
val = sysc_read(ddata, dispc_offset + 0x238);
lcd2_en = val & lcd_en_mask;
if (lcd2_en)
irq_mask |= BIT(22); /* FRAMEDONE2 */
if (disable && lcd2_en)
sysc_write(ddata, dispc_offset + 0x238,
val & ~lcd_en_mask);
if (manager_count <= 3)
return irq_mask;
/* DISPC_CONTROL3 */
val = sysc_read(ddata, dispc_offset + 0x848);
lcd3_en = val & lcd_en_mask;
if (lcd3_en)
irq_mask |= BIT(30); /* FRAMEDONE3 */
if (disable && lcd3_en)
sysc_write(ddata, dispc_offset + 0x848,
val & ~lcd_en_mask);
return irq_mask;
}
/* DSS needs child outputs disabled and SDI registers cleared for reset */
static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
{
const int dispc_offset = 0x1000;
int error;
u32 irq_mask, val;
/* Get enabled outputs */
irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
if (!irq_mask)
return;
/* Clear IRQSTATUS */
sysc_write(ddata, dispc_offset + 0x18, irq_mask);
/* Disable outputs */
val = sysc_quirk_dispc(ddata, dispc_offset, true);
/* Poll IRQSTATUS */
error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
val, val != irq_mask, 100, 50);
if (error)
dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
__func__, val, irq_mask);
if (sysc_soc->soc == SOC_3430) {
/* Clear DSS_SDI_CONTROL */
sysc_write(ddata, 0x44, 0);
/* Clear DSS_PLL_CONTROL */
sysc_write(ddata, 0x48, 0);
}
/* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
sysc_write(ddata, 0x40, 0);
}
/* 1-wire needs module's internal clocks enabled for reset */ /* 1-wire needs module's internal clocks enabled for reset */
static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata) static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
{ {
int offset = 0x0c; /* HDQ_CTRL_STATUS */ int offset = 0x0c; /* HDQ_CTRL_STATUS */
u16 val; u16 val;
...@@ -1418,7 +1617,7 @@ static void sysc_module_enable_quirk_aess(struct sysc *ddata) ...@@ -1418,7 +1617,7 @@ static void sysc_module_enable_quirk_aess(struct sysc *ddata)
sysc_write(ddata, offset, 1); sysc_write(ddata, offset, 1);
} }
/* I2C needs extra enable bit toggling for reset */ /* I2C needs to be disabled for reset */
static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
{ {
int offset; int offset;
...@@ -1439,14 +1638,48 @@ static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) ...@@ -1439,14 +1638,48 @@ static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
sysc_write(ddata, offset, val); sysc_write(ddata, offset, val);
} }
static void sysc_clk_enable_quirk_i2c(struct sysc *ddata) static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
{
sysc_clk_quirk_i2c(ddata, false);
}
static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
{ {
sysc_clk_quirk_i2c(ddata, true); sysc_clk_quirk_i2c(ddata, true);
} }
static void sysc_clk_disable_quirk_i2c(struct sysc *ddata) /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
{ {
sysc_clk_quirk_i2c(ddata, false); u32 val, kick0_val = 0, kick1_val = 0;
unsigned long flags;
int error;
if (!lock) {
kick0_val = 0x83e70b13;
kick1_val = 0x95a4f1e0;
}
local_irq_save(flags);
/* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
error = readl_poll_timeout(ddata->module_va + 0x44, val,
!(val & BIT(0)), 100, 50);
if (error)
dev_warn(ddata->dev, "rtc busy timeout\n");
/* Now we have ~15 microseconds to read/write various registers */
sysc_write(ddata, 0x6c, kick0_val);
sysc_write(ddata, 0x70, kick1_val);
local_irq_restore(flags);
}
static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
{
sysc_quirk_rtc(ddata, false);
}
static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
{
sysc_quirk_rtc(ddata, true);
} }
/* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
...@@ -1482,20 +1715,30 @@ static void sysc_reset_done_quirk_wdt(struct sysc *ddata) ...@@ -1482,20 +1715,30 @@ static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
dev_warn(ddata->dev, "wdt disable step2 failed\n"); dev_warn(ddata->dev, "wdt disable step2 failed\n");
} }
/* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
{
u32 reg;
reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
reg |= SYSC_PRUSS_STANDBY_INIT;
sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
}
static void sysc_init_module_quirks(struct sysc *ddata) static void sysc_init_module_quirks(struct sysc *ddata)
{ {
if (ddata->legacy_mode || !ddata->name) if (ddata->legacy_mode || !ddata->name)
return; return;
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w; ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
return; return;
} }
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c; ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c; ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
return; return;
} }
...@@ -1503,6 +1746,16 @@ static void sysc_init_module_quirks(struct sysc *ddata) ...@@ -1503,6 +1746,16 @@ static void sysc_init_module_quirks(struct sysc *ddata)
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
ddata->module_enable_quirk = sysc_module_enable_quirk_aess; ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
return;
}
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
...@@ -1510,6 +1763,9 @@ static void sysc_init_module_quirks(struct sysc *ddata) ...@@ -1510,6 +1763,9 @@ static void sysc_init_module_quirks(struct sysc *ddata)
ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
} }
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
} }
static int sysc_clockdomain_init(struct sysc *ddata) static int sysc_clockdomain_init(struct sysc *ddata)
...@@ -1571,7 +1827,7 @@ static int sysc_reset(struct sysc *ddata) ...@@ -1571,7 +1827,7 @@ static int sysc_reset(struct sysc *ddata)
sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
syss_offset = ddata->offsets[SYSC_SYSSTATUS]; syss_offset = ddata->offsets[SYSC_SYSSTATUS];
if (ddata->legacy_mode || sysc_offset < 0 || if (ddata->legacy_mode ||
ddata->cap->regbits->srst_shift < 0 || ddata->cap->regbits->srst_shift < 0 ||
ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
return 0; return 0;
...@@ -1583,19 +1839,21 @@ static int sysc_reset(struct sysc *ddata) ...@@ -1583,19 +1839,21 @@ static int sysc_reset(struct sysc *ddata)
else else
syss_done = ddata->cfg.syss_mask; syss_done = ddata->cfg.syss_mask;
if (ddata->clk_disable_quirk) if (ddata->pre_reset_quirk)
ddata->clk_disable_quirk(ddata); ddata->pre_reset_quirk(ddata);
sysc_val = sysc_read_sysconfig(ddata); if (sysc_offset >= 0) {
sysc_val |= sysc_mask; sysc_val = sysc_read_sysconfig(ddata);
sysc_write(ddata, sysc_offset, sysc_val); sysc_val |= sysc_mask;
sysc_write(ddata, sysc_offset, sysc_val);
}
if (ddata->cfg.srst_udelay) if (ddata->cfg.srst_udelay)
usleep_range(ddata->cfg.srst_udelay, usleep_range(ddata->cfg.srst_udelay,
ddata->cfg.srst_udelay * 2); ddata->cfg.srst_udelay * 2);
if (ddata->clk_enable_quirk) if (ddata->post_reset_quirk)
ddata->clk_enable_quirk(ddata); ddata->post_reset_quirk(ddata);
/* Poll on reset status */ /* Poll on reset status */
if (syss_offset >= 0) { if (syss_offset >= 0) {
...@@ -2313,6 +2571,16 @@ static const struct sysc_capabilities sysc_dra7_mcan = { ...@@ -2313,6 +2571,16 @@ static const struct sysc_capabilities sysc_dra7_mcan = {
.mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
}; };
/*
* PRUSS found on some AM33xx, AM437x and AM57xx SoCs
*/
static const struct sysc_capabilities sysc_pruss = {
.type = TI_SYSC_PRUSS,
.sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
.regbits = &sysc_regbits_omap4_simple,
.mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
};
static int sysc_init_pdata(struct sysc *ddata) static int sysc_init_pdata(struct sysc *ddata)
{ {
struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
...@@ -2386,6 +2654,154 @@ static void ti_sysc_idle(struct work_struct *work) ...@@ -2386,6 +2654,154 @@ static void ti_sysc_idle(struct work_struct *work)
pm_runtime_put_sync(ddata->dev); pm_runtime_put_sync(ddata->dev);
} }
/*
* SoC model and features detection. Only needed for SoCs that need
* special handling for quirks, no need to list others.
*/
static const struct soc_device_attribute sysc_soc_match[] = {
SOC_FLAG("OMAP242*", SOC_2420),
SOC_FLAG("OMAP243*", SOC_2430),
SOC_FLAG("OMAP3[45]*", SOC_3430),
SOC_FLAG("OMAP3[67]*", SOC_3630),
SOC_FLAG("OMAP443*", SOC_4430),
SOC_FLAG("OMAP446*", SOC_4460),
SOC_FLAG("OMAP447*", SOC_4470),
SOC_FLAG("OMAP54*", SOC_5430),
SOC_FLAG("AM433", SOC_AM3),
SOC_FLAG("AM43*", SOC_AM4),
SOC_FLAG("DRA7*", SOC_DRA7),
{ /* sentinel */ },
};
/*
* List of SoCs variants with disabled features. By default we assume all
* devices in the device tree are available so no need to list those SoCs.
*/
static const struct soc_device_attribute sysc_soc_feat_match[] = {
/* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
SOC_FLAG("AM3505", DIS_SGX),
SOC_FLAG("OMAP3525", DIS_SGX),
SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
/* OMAP3630/DM3730 variants with some accelerators disabled */
SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
SOC_FLAG("DM3725", DIS_SGX),
SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
SOC_FLAG("OMAP3621", DIS_ISP),
{ /* sentinel */ },
};
static int sysc_add_disabled(unsigned long base)
{
struct sysc_address *disabled_module;
disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
if (!disabled_module)
return -ENOMEM;
disabled_module->base = base;
mutex_lock(&sysc_soc->list_lock);
list_add(&disabled_module->node, &sysc_soc->disabled_modules);
mutex_unlock(&sysc_soc->list_lock);
return 0;
}
/*
* One time init to detect the booted SoC and disable unavailable features.
* Note that we initialize static data shared across all ti-sysc instances
* so ddata is only used for SoC type. This can be called from module_init
* once we no longer need to rely on platform data.
*/
static int sysc_init_soc(struct sysc *ddata)
{
const struct soc_device_attribute *match;
struct ti_sysc_platform_data *pdata;
unsigned long features = 0;
if (sysc_soc)
return 0;
sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
if (!sysc_soc)
return -ENOMEM;
mutex_init(&sysc_soc->list_lock);
INIT_LIST_HEAD(&sysc_soc->disabled_modules);
sysc_soc->general_purpose = true;
pdata = dev_get_platdata(ddata->dev);
if (pdata && pdata->soc_type_gp)
sysc_soc->general_purpose = pdata->soc_type_gp();
match = soc_device_match(sysc_soc_match);
if (match && match->data)
sysc_soc->soc = (int)match->data;
match = soc_device_match(sysc_soc_feat_match);
if (!match)
return 0;
if (match->data)
features = (unsigned long)match->data;
/*
* Add disabled devices to the list based on the module base.
* Note that this must be done before we attempt to access the
* device and have module revision checks working.
*/
if (features & DIS_ISP)
sysc_add_disabled(0x480bd400);
if (features & DIS_IVA)
sysc_add_disabled(0x5d000000);
if (features & DIS_SGX)
sysc_add_disabled(0x50000000);
return 0;
}
static void sysc_cleanup_soc(void)
{
struct sysc_address *disabled_module;
struct list_head *pos, *tmp;
if (!sysc_soc)
return;
mutex_lock(&sysc_soc->list_lock);
list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
disabled_module = list_entry(pos, struct sysc_address, node);
list_del(pos);
kfree(disabled_module);
}
mutex_unlock(&sysc_soc->list_lock);
}
static int sysc_check_disabled_devices(struct sysc *ddata)
{
struct sysc_address *disabled_module;
struct list_head *pos;
int error = 0;
mutex_lock(&sysc_soc->list_lock);
list_for_each(pos, &sysc_soc->disabled_modules) {
disabled_module = list_entry(pos, struct sysc_address, node);
if (ddata->module_pa == disabled_module->base) {
dev_dbg(ddata->dev, "module disabled for this SoC\n");
error = -ENODEV;
break;
}
}
mutex_unlock(&sysc_soc->list_lock);
return error;
}
static const struct of_device_id sysc_match_table[] = { static const struct of_device_id sysc_match_table[] = {
{ .compatible = "simple-bus", }, { .compatible = "simple-bus", },
{ /* sentinel */ }, { /* sentinel */ },
...@@ -2404,6 +2820,10 @@ static int sysc_probe(struct platform_device *pdev) ...@@ -2404,6 +2820,10 @@ static int sysc_probe(struct platform_device *pdev)
ddata->dev = &pdev->dev; ddata->dev = &pdev->dev;
platform_set_drvdata(pdev, ddata); platform_set_drvdata(pdev, ddata);
error = sysc_init_soc(ddata);
if (error)
return error;
error = sysc_init_match(ddata); error = sysc_init_match(ddata);
if (error) if (error)
return error; return error;
...@@ -2434,6 +2854,10 @@ static int sysc_probe(struct platform_device *pdev) ...@@ -2434,6 +2854,10 @@ static int sysc_probe(struct platform_device *pdev)
sysc_init_early_quirks(ddata); sysc_init_early_quirks(ddata);
error = sysc_check_disabled_devices(ddata);
if (error)
return error;
error = sysc_get_clocks(ddata); error = sysc_get_clocks(ddata);
if (error) if (error)
return error; return error;
...@@ -2538,6 +2962,7 @@ static const struct of_device_id sysc_match[] = { ...@@ -2538,6 +2962,7 @@ static const struct of_device_id sysc_match[] = {
{ .compatible = "ti,sysc-usb-host-fs", { .compatible = "ti,sysc-usb-host-fs",
.data = &sysc_omap4_usb_host_fs, }, .data = &sysc_omap4_usb_host_fs, },
{ .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
{ .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
{ }, { },
}; };
MODULE_DEVICE_TABLE(of, sysc_match); MODULE_DEVICE_TABLE(of, sysc_match);
...@@ -2564,6 +2989,7 @@ static void __exit sysc_exit(void) ...@@ -2564,6 +2989,7 @@ static void __exit sysc_exit(void)
{ {
bus_unregister_notifier(&platform_bus_type, &sysc_nb); bus_unregister_notifier(&platform_bus_type, &sysc_nb);
platform_driver_unregister(&sysc_driver); platform_driver_unregister(&sysc_driver);
sysc_cleanup_soc();
} }
module_exit(sysc_exit); module_exit(sysc_exit);
......
drivers/clk/ti/clk-814x.c
View file @ 8bdbf169
...@@ -25,7 +25,6 @@ static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst ...@@ -25,7 +25,6 @@ static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst
{ DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
{ DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
{ DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" }, { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
{ DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
{ DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
...@@ -39,9 +38,15 @@ static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst ...@@ -39,9 +38,15 @@ static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst
{ 0 }, { 0 },
}; };
static const struct
omap_clkctrl_reg_data dm814_alwon_ethernet_clkctrl_regs[] __initconst = {
{ 0, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
};
const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = { const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
{ 0x48180500, dm814_default_clkctrl_regs }, { 0x48180500, dm814_default_clkctrl_regs },
{ 0x48181400, dm814_alwon_clkctrl_regs }, { 0x48181400, dm814_alwon_clkctrl_regs },
{ 0x481815d4, dm814_alwon_ethernet_clkctrl_regs },
{ 0 }, { 0 },
}; };
......
drivers/gpu/drm/omapdrm/dss/dss.c
View file @ 8bdbf169
...@@ -1339,9 +1339,15 @@ static int dss_component_compare(struct device *dev, void *data) ...@@ -1339,9 +1339,15 @@ static int dss_component_compare(struct device *dev, void *data)
return dev == child; return dev == child;
} }
struct dss_component_match_data {
struct device *dev;
struct component_match **match;
};
static int dss_add_child_component(struct device *dev, void *data) static int dss_add_child_component(struct device *dev, void *data)
{ {
struct component_match **match = data; struct dss_component_match_data *cmatch = data;
struct component_match **match = cmatch->match;
/* /*
* HACK * HACK
...@@ -1352,7 +1358,17 @@ static int dss_add_child_component(struct device *dev, void *data) ...@@ -1352,7 +1358,17 @@ static int dss_add_child_component(struct device *dev, void *data)
if (strstr(dev_name(dev), "rfbi")) if (strstr(dev_name(dev), "rfbi"))
return 0; return 0;
component_match_add(dev->parent, match, dss_component_compare, dev); /*
* Handle possible interconnect target modules defined within the DSS.
* The DSS components can be children of an interconnect target module
* after the device tree has been updated for the module data.
* See also omapdss_boot_init() for compatible fixup.
*/
if (strstr(dev_name(dev), "target-module"))
return device_for_each_child(dev, cmatch,
dss_add_child_component);
component_match_add(cmatch->dev, match, dss_component_compare, dev);
return 0; return 0;
} }
...@@ -1395,6 +1411,7 @@ static int dss_probe_hardware(struct dss_device *dss) ...@@ -1395,6 +1411,7 @@ static int dss_probe_hardware(struct dss_device *dss)
static int dss_probe(struct platform_device *pdev) static int dss_probe(struct platform_device *pdev)
{ {
const struct soc_device_attribute *soc; const struct soc_device_attribute *soc;
struct dss_component_match_data cmatch;
struct component_match *match = NULL; struct component_match *match = NULL;
struct resource *dss_mem; struct resource *dss_mem;
struct dss_device *dss; struct dss_device *dss;
...@@ -1472,7 +1489,9 @@ static int dss_probe(struct platform_device *pdev) ...@@ -1472,7 +1489,9 @@ static int dss_probe(struct platform_device *pdev)
omapdss_gather_components(&pdev->dev); omapdss_gather_components(&pdev->dev);
device_for_each_child(&pdev->dev, &match, dss_add_child_component); cmatch.dev = &pdev->dev;
cmatch.match = &match;
device_for_each_child(&pdev->dev, &cmatch, dss_add_child_component);
r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
if (r) if (r)
......
drivers/gpu/drm/omapdrm/dss/omapdss-boot-init.c
View file @ 8bdbf169
...@@ -183,9 +183,24 @@ static const struct of_device_id omapdss_of_fixups_whitelist[] __initconst = { ...@@ -183,9 +183,24 @@ static const struct of_device_id omapdss_of_fixups_whitelist[] __initconst = {
{}, {},
}; };
static void __init omapdss_find_children(struct device_node *np)
{
struct device_node *child;
for_each_available_child_of_node(np, child) {
if (!of_find_property(child, "compatible", NULL))
continue;
omapdss_walk_device(child, true);
if (of_device_is_compatible(child, "ti,sysc"))
omapdss_find_children(child);
}
}
static int __init omapdss_boot_init(void) static int __init omapdss_boot_init(void)
{ {
struct device_node *dss, *child; struct device_node *dss;
INIT_LIST_HEAD(&dss_conv_list); INIT_LIST_HEAD(&dss_conv_list);
...@@ -195,13 +210,7 @@ static int __init omapdss_boot_init(void) ...@@ -195,13 +210,7 @@ static int __init omapdss_boot_init(void)
return 0; return 0;
omapdss_walk_device(dss, true); omapdss_walk_device(dss, true);
omapdss_find_children(dss);
for_each_available_child_of_node(dss, child) {
if (!of_find_property(child, "compatible", NULL))
continue;
omapdss_walk_device(child, true);
}
while (!list_empty(&dss_conv_list)) { while (!list_empty(&dss_conv_list)) {
struct dss_conv_node *n; struct dss_conv_node *n;
......
include/dt-bindings/bus/ti-sysc.h
View file @ 8bdbf169
...@@ -18,6 +18,10 @@ ...@@ -18,6 +18,10 @@
#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) #define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4)
/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */
#define SYSC_PRUSS_SUB_MWAIT (1 << 5)
#define SYSC_PRUSS_STANDBY_INIT (1 << 4)
/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ /* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
#define SYSC_IDLE_FORCE 0 #define SYSC_IDLE_FORCE 0
#define SYSC_IDLE_NO 1 #define SYSC_IDLE_NO 1
......
include/dt-bindings/clock/dm814.h
View file @ 8bdbf169
...@@ -34,4 +34,9 @@ ...@@ -34,4 +34,9 @@
#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220) #define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220)
#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224) #define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224)
/* alwon_ethernet clocks */
#define DM814_ETHERNET_CLKCTRL_OFFSET 0x1d4
#define DM814_ETHERNET_CLKCTRL_INDEX(offset) ((offset) - DM814_ETHERNET_CLKCTRL_OFFSET)
#define DM814_ETHERNET_CPGMAC0_CLKCTRL DM814_ETHERNET_CLKCTRL_INDEX(0x1d4)
#endif #endif
include/linux/platform_data/ti-sysc.h
View file @ 8bdbf169
...@@ -17,6 +17,7 @@ enum ti_sysc_module_type { ...@@ -17,6 +17,7 @@ enum ti_sysc_module_type {
TI_SYSC_OMAP4_MCASP, TI_SYSC_OMAP4_MCASP,
TI_SYSC_OMAP4_USB_HOST_FS, TI_SYSC_OMAP4_USB_HOST_FS,
TI_SYSC_DRA7_MCAN, TI_SYSC_DRA7_MCAN,
TI_SYSC_PRUSS,
}; };
struct ti_sysc_cookie { struct ti_sysc_cookie {
...@@ -49,6 +50,9 @@ struct sysc_regbits { ...@@ -49,6 +50,9 @@ struct sysc_regbits {
s8 emufree_shift; s8 emufree_shift;
}; };
#define SYSC_MODULE_QUIRK_PRUSS BIT(24)
#define SYSC_MODULE_QUIRK_DSS_RESET BIT(23)
#define SYSC_MODULE_QUIRK_RTC_UNLOCK BIT(22)
#define SYSC_QUIRK_CLKDM_NOAUTO BIT(21) #define SYSC_QUIRK_CLKDM_NOAUTO BIT(21)
#define SYSC_QUIRK_FORCE_MSTANDBY BIT(20) #define SYSC_QUIRK_FORCE_MSTANDBY BIT(20)
#define SYSC_MODULE_QUIRK_AESS BIT(19) #define SYSC_MODULE_QUIRK_AESS BIT(19)
...@@ -141,6 +145,7 @@ struct clk; ...@@ -141,6 +145,7 @@ struct clk;
struct ti_sysc_platform_data { struct ti_sysc_platform_data {
struct of_dev_auxdata *auxdata; struct of_dev_auxdata *auxdata;
bool (*soc_type_gp)(void);
int (*init_clockdomain)(struct device *dev, struct clk *fck, int (*init_clockdomain)(struct device *dev, struct clk *fck,
struct clk *ick, struct ti_sysc_cookie *cookie); struct clk *ick, struct ti_sysc_cookie *cookie);
void (*clkdm_deny_idle)(struct device *dev, void (*clkdm_deny_idle)(struct device *dev,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7