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Commit 8dfe8f29 authored by Haavard Skinnemoen's avatar Haavard Skinnemoen
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[AVR32] Clean up OCD register usage 

Generate a new set of OCD register definitions in asm/ocd.h and rename
__mfdr() and __mtdr() to ocd_read() and ocd_write() respectively.

The bitfield definitions are a lot more complete now, and they are
entirely based on bit numbers, not masks. This is because OCD
registers are frequently accessed from assembly code, where bit
numbers are a lot more useful (can be fed directly to sbr, bfins,
etc.)

Bitfields that consist of more than one bit have two definitions:
_START, which indicates the number of the first bit, and _SIZE, which
indicates the number of bits. These directly correspond to the
parameters taken by the bfextu, bfexts and bfins instructions.
Signed-off-by: default avatarHaavard Skinnemoen <hskinnemoen@atmel.com>
parent 320516b7
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Showing with 563 additions and 101 deletions
arch/avr32/kernel/entry-avr32b.S
View file @ 8dfe8f29
......@@ -270,8 +270,8 @@ syscall_exit_work:
lsl r3, 1
sbr r3, 30
sbr r3, 0
mtdr DBGREG_BWA2A, r2
mtdr DBGREG_BWC2A, r3
mtdr OCD_BWA2A, r2
mtdr OCD_BWC2A, r3
rjmp syscall_exit_cont
......@@ -521,8 +521,8 @@ fault_exit_work:
lsl r3, 1
sbr r3, 30
sbr r3, 0
mtdr DBGREG_BWA2A, r2
mtdr DBGREG_BWC2A, r3
mtdr OCD_BWA2A, r2
mtdr OCD_BWC2A, r3
rjmp fault_resume_user
/* If we get a debug trap from privileged context we end up here */
......@@ -636,9 +636,9 @@ debug_resume_user:
3: bld r1, TIF_SINGLE_STEP
brcc debug_restore_all
mfdr r2, DBGREG_DC
sbr r2, DC_SS_BIT
mtdr DBGREG_DC, r2
mfdr r2, OCD_DC
sbr r2, OCD_DC_SS_BIT
mtdr OCD_DC, r2
rjmp debug_restore_all
.set rsr_int0, SYSREG_RSR_INT0
......
arch/avr32/kernel/kprobes.c
View file @ 8dfe8f29
......@@ -70,9 +70,9 @@ static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
BUG_ON(!(sysreg_read(SR) & SYSREG_BIT(SR_D)));
dc = __mfdr(DBGREG_DC);
dc |= DC_SS;
__mtdr(DBGREG_DC, dc);
dc = ocd_read(DC);
dc |= 1 << OCD_DC_SS_BIT;
ocd_write(DC, dc);
/*
* We must run the instruction from its original location
......@@ -91,9 +91,9 @@ static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs)
pr_debug("resuming execution at PC=%08lx\n", regs->pc);
dc = __mfdr(DBGREG_DC);
dc &= ~DC_SS;
__mtdr(DBGREG_DC, dc);
dc = ocd_read(DC);
dc &= ~(1 << OCD_DC_SS_BIT);
ocd_write(DC, dc);
*p->addr = BREAKPOINT_INSTRUCTION;
flush_icache_range((unsigned long)p->addr,
......@@ -261,7 +261,7 @@ int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
int __init arch_init_kprobes(void)
{
printk("KPROBES: Enabling monitor mode (MM|DBE)...\n");
__mtdr(DBGREG_DC, DC_MM | DC_DBE);
ocd_write(DC, (1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT));
/* TODO: Register kretprobe trampoline */
return 0;
......
arch/avr32/kernel/process.c
View file @ 8dfe8f29
......@@ -55,8 +55,8 @@ void machine_power_off(void)
void machine_restart(char *cmd)
{
__mtdr(DBGREG_DC, DC_DBE);
__mtdr(DBGREG_DC, DC_RES);
ocd_write(DC, (1 << OCD_DC_DBE_BIT));
ocd_write(DC, (1 << OCD_DC_RES_BIT));
while (1) ;
}
......
arch/avr32/kernel/ptrace.c
View file @ 8dfe8f29
......@@ -159,7 +159,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
request, child->pid, addr, data);
pr_debug("ptrace: Enabling monitor mode...\n");
__mtdr(DBGREG_DC, __mfdr(DBGREG_DC) | DC_MM | DC_DBE);
ocd_write(DC, ocd_read(DC) | (1 << OCD_DC_MM_BIT)
| (1 << OCD_DC_DBE_BIT));
switch (request) {
/* Read the word at location addr in the child process */
......@@ -240,7 +241,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
break;
}
pr_debug("sys_ptrace returning %d (DC = 0x%08lx)\n", ret, __mfdr(DBGREG_DC));
pr_debug("sys_ptrace returning %d (DC = 0x%08lx)\n",
ret, ocd_read(DC));
return ret;
}
......@@ -276,11 +278,11 @@ asmlinkage void do_debug_priv(struct pt_regs *regs)
unsigned long dc, ds;
unsigned long die_val;
ds = __mfdr(DBGREG_DS);
ds = ocd_read(DS);
pr_debug("do_debug_priv: pc = %08lx, ds = %08lx\n", regs->pc, ds);
if (ds & DS_SSS)
if (ds & (1 << OCD_DS_SSS_BIT))
die_val = DIE_SSTEP;
else
die_val = DIE_BREAKPOINT;
......@@ -288,14 +290,14 @@ asmlinkage void do_debug_priv(struct pt_regs *regs)
if (notify_die(die_val, "ptrace", regs, 0, 0, SIGTRAP) == NOTIFY_STOP)
return;
if (likely(ds & DS_SSS)) {
if (likely(ds & (1 << OCD_DS_SSS_BIT))) {
extern void itlb_miss(void);
extern void tlb_miss_common(void);
struct thread_info *ti;
dc = __mfdr(DBGREG_DC);
dc &= ~DC_SS;
__mtdr(DBGREG_DC, dc);
dc = ocd_read(DC);
dc &= ~(1 << OCD_DC_SS_BIT);
ocd_write(DC, dc);
ti = current_thread_info();
set_ti_thread_flag(ti, TIF_BREAKPOINT);
......@@ -303,8 +305,8 @@ asmlinkage void do_debug_priv(struct pt_regs *regs)
/* The TLB miss handlers don't check thread flags */
if ((regs->pc >= (unsigned long)&itlb_miss)
&& (regs->pc <= (unsigned long)&tlb_miss_common)) {
__mtdr(DBGREG_BWA2A, sysreg_read(RAR_EX));
__mtdr(DBGREG_BWC2A, 0x40000001 | (get_asid() << 1));
ocd_write(BWA2A, sysreg_read(RAR_EX));
ocd_write(BWC2A, 0x40000001 | (get_asid() << 1));
}
/*
......@@ -329,22 +331,22 @@ asmlinkage void do_debug(struct pt_regs *regs)
{
unsigned long dc, ds;
ds = __mfdr(DBGREG_DS);
ds = ocd_read(DS);
pr_debug("do_debug: pc = %08lx, ds = %08lx\n", regs->pc, ds);
if (test_thread_flag(TIF_BREAKPOINT)) {
pr_debug("TIF_BREAKPOINT set\n");
/* We're taking care of it */
clear_thread_flag(TIF_BREAKPOINT);
__mtdr(DBGREG_BWC2A, 0);
ocd_write(BWC2A, 0);
}
if (test_thread_flag(TIF_SINGLE_STEP)) {
pr_debug("TIF_SINGLE_STEP set, ds = 0x%08lx\n", ds);
if (ds & DS_SSS) {
dc = __mfdr(DBGREG_DC);
dc &= ~DC_SS;
__mtdr(DBGREG_DC, dc);
if (ds & (1 << OCD_DS_SSS_BIT)) {
dc = ocd_read(DC);
dc &= ~(1 << OCD_DC_SS_BIT);
ocd_write(DC, dc);
clear_thread_flag(TIF_SINGLE_STEP);
ptrace_break(current, regs);
......
arch/avr32/kernel/traps.c
View file @ 8dfe8f29
......@@ -39,7 +39,7 @@ void NORET_TYPE die(const char *str, struct pt_regs *regs, long err)
printk("FRAME_POINTER ");
#endif
if (current_cpu_data.features & AVR32_FEATURE_OCD) {
unsigned long did = __mfdr(DBGREG_DID);
unsigned long did = ocd_read(DID);
printk("chip: 0x%03lx:0x%04lx rev %lu\n",
(did >> 1) & 0x7ff,
(did >> 12) & 0x7fff,
......
include/asm-avr32/ocd.h
View file @ 8dfe8f29
/*
* AVR32 OCD Registers
* AVR32 OCD Interface and register definitions
*
* Copyright (C) 2004-2006 Atmel Corporation
* Copyright (C) 2004-2007 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -10,69 +10,529 @@
#ifndef __ASM_AVR32_OCD_H
#define __ASM_AVR32_OCD_H
/* Debug Registers */
#define DBGREG_DID 0
#define DBGREG_DC 8
#define DBGREG_DS 16
#define DBGREG_RWCS 28
#define DBGREG_RWA 36
#define DBGREG_RWD 40
#define DBGREG_WT 44
#define DBGREG_DTC 52
#define DBGREG_DTSA0 56
#define DBGREG_DTSA1 60
#define DBGREG_DTEA0 72
#define DBGREG_DTEA1 76
#define DBGREG_BWC0A 88
#define DBGREG_BWC0B 92
#define DBGREG_BWC1A 96
#define DBGREG_BWC1B 100
#define DBGREG_BWC2A 104
#define DBGREG_BWC2B 108
#define DBGREG_BWC3A 112
#define DBGREG_BWC3B 116
#define DBGREG_BWA0A 120
#define DBGREG_BWA0B 124
#define DBGREG_BWA1A 128
#define DBGREG_BWA1B 132
#define DBGREG_BWA2A 136
#define DBGREG_BWA2B 140
#define DBGREG_BWA3A 144
#define DBGREG_BWA3B 148
#define DBGREG_BWD3A 153
#define DBGREG_BWD3B 156
#define DBGREG_PID 284
#define SABAH_OCD 0x01
#define SABAH_ICACHE 0x02
#define SABAH_MEM_CACHED 0x04
#define SABAH_MEM_UNCACHED 0x05
/* Fields in the Development Control register */
#define DC_SS_BIT 8
#define DC_SS (1 << DC_SS_BIT)
#define DC_DBE (1 << 13)
#define DC_RID (1 << 27)
#define DC_ORP (1 << 28)
#define DC_MM (1 << 29)
#define DC_RES (1 << 30)
/* Fields in the Development Status register */
#define DS_SSS (1 << 0)
#define DS_SWB (1 << 1)
#define DS_HWB (1 << 2)
#define DS_BP_SHIFT 8
#define DS_BP_MASK (0xff << DS_BP_SHIFT)
#define __mfdr(addr) \
({ \
register unsigned long value; \
asm volatile("mfdr %0, %1" : "=r"(value) : "i"(addr)); \
value; \
})
#define __mtdr(addr, value) \
asm volatile("mtdr %0, %1" : : "i"(addr), "r"(value))
/* OCD Register offsets. Abbreviations used below:
*
* BP Breakpoint
* Comm Communication
* DT Data Trace
* PC Program Counter
* PID Process ID
* R/W Read/Write
* WP Watchpoint
*/
#define OCD_DID 0x0000 /* Device ID */
#define OCD_DC 0x0008 /* Development Control */
#define OCD_DS 0x0010 /* Development Status */
#define OCD_RWCS 0x001c /* R/W Access Control */
#define OCD_RWA 0x0024 /* R/W Access Address */
#define OCD_RWD 0x0028 /* R/W Access Data */
#define OCD_WT 0x002c /* Watchpoint Trigger */
#define OCD_DTC 0x0034 /* Data Trace Control */
#define OCD_DTSA0 0x0038 /* DT Start Addr Channel 0 */
#define OCD_DTSA1 0x003c /* DT Start Addr Channel 1 */
#define OCD_DTEA0 0x0048 /* DT End Addr Channel 0 */
#define OCD_DTEA1 0x004c /* DT End Addr Channel 1 */
#define OCD_BWC0A 0x0058 /* PC BP/WP Control 0A */
#define OCD_BWC0B 0x005c /* PC BP/WP Control 0B */
#define OCD_BWC1A 0x0060 /* PC BP/WP Control 1A */
#define OCD_BWC1B 0x0064 /* PC BP/WP Control 1B */
#define OCD_BWC2A 0x0068 /* PC BP/WP Control 2A */
#define OCD_BWC2B 0x006c /* PC BP/WP Control 2B */
#define OCD_BWC3A 0x0070 /* Data BP/WP Control 3A */
#define OCD_BWC3B 0x0074 /* Data BP/WP Control 3B */
#define OCD_BWA0A 0x0078 /* PC BP/WP Address 0A */
#define OCD_BWA0B 0x007c /* PC BP/WP Address 0B */
#define OCD_BWA1A 0x0080 /* PC BP/WP Address 1A */
#define OCD_BWA1B 0x0084 /* PC BP/WP Address 1B */
#define OCD_BWA2A 0x0088 /* PC BP/WP Address 2A */
#define OCD_BWA2B 0x008c /* PC BP/WP Address 2B */
#define OCD_BWA3A 0x0090 /* Data BP/WP Address 3A */
#define OCD_BWA3B 0x0094 /* Data BP/WP Address 3B */
#define OCD_NXCFG 0x0100 /* Nexus Configuration */
#define OCD_DINST 0x0104 /* Debug Instruction */
#define OCD_DPC 0x0108 /* Debug Program Counter */
#define OCD_CPUCM 0x010c /* CPU Control Mask */
#define OCD_DCCPU 0x0110 /* Debug Comm CPU */
#define OCD_DCEMU 0x0114 /* Debug Comm Emulator */
#define OCD_DCSR 0x0118 /* Debug Comm Status */
#define OCD_PID 0x011c /* Ownership Trace PID */
#define OCD_EPC0 0x0120 /* Event Pair Control 0 */
#define OCD_EPC1 0x0124 /* Event Pair Control 1 */
#define OCD_EPC2 0x0128 /* Event Pair Control 2 */
#define OCD_EPC3 0x012c /* Event Pair Control 3 */
#define OCD_AXC 0x0130 /* AUX port Control */
/* Bits in DID */
#define OCD_DID_MID_START 1
#define OCD_DID_MID_SIZE 11
#define OCD_DID_PN_START 12
#define OCD_DID_PN_SIZE 16
#define OCD_DID_RN_START 28
#define OCD_DID_RN_SIZE 4
/* Bits in DC */
#define OCD_DC_TM_START 0
#define OCD_DC_TM_SIZE 2
#define OCD_DC_EIC_START 3
#define OCD_DC_EIC_SIZE 2
#define OCD_DC_OVC_START 5
#define OCD_DC_OVC_SIZE 3
#define OCD_DC_SS_BIT 8
#define OCD_DC_DBR_BIT 12
#define OCD_DC_DBE_BIT 13
#define OCD_DC_EOS_START 20
#define OCD_DC_EOS_SIZE 2
#define OCD_DC_SQA_BIT 22
#define OCD_DC_IRP_BIT 23
#define OCD_DC_IFM_BIT 24
#define OCD_DC_TOZ_BIT 25
#define OCD_DC_TSR_BIT 26
#define OCD_DC_RID_BIT 27
#define OCD_DC_ORP_BIT 28
#define OCD_DC_MM_BIT 29
#define OCD_DC_RES_BIT 30
#define OCD_DC_ABORT_BIT 31
/* Bits in DS */
#define OCD_DS_SSS_BIT 0
#define OCD_DS_SWB_BIT 1
#define OCD_DS_HWB_BIT 2
#define OCD_DS_HWE_BIT 3
#define OCD_DS_STP_BIT 4
#define OCD_DS_DBS_BIT 5
#define OCD_DS_BP_START 8
#define OCD_DS_BP_SIZE 8
#define OCD_DS_INC_BIT 24
#define OCD_DS_BOZ_BIT 25
#define OCD_DS_DBA_BIT 26
#define OCD_DS_EXB_BIT 27
#define OCD_DS_NTBF_BIT 28
/* Bits in RWCS */
#define OCD_RWCS_DV_BIT 0
#define OCD_RWCS_ERR_BIT 1
#define OCD_RWCS_CNT_START 2
#define OCD_RWCS_CNT_SIZE 14
#define OCD_RWCS_CRC_BIT 19
#define OCD_RWCS_NTBC_START 20
#define OCD_RWCS_NTBC_SIZE 2
#define OCD_RWCS_NTE_BIT 22
#define OCD_RWCS_NTAP_BIT 23
#define OCD_RWCS_WRAPPED_BIT 24
#define OCD_RWCS_CCTRL_START 25
#define OCD_RWCS_CCTRL_SIZE 2
#define OCD_RWCS_SZ_START 27
#define OCD_RWCS_SZ_SIZE 3
#define OCD_RWCS_RW_BIT 30
#define OCD_RWCS_AC_BIT 31
/* Bits in RWA */
#define OCD_RWA_RWA_START 0
#define OCD_RWA_RWA_SIZE 32
/* Bits in RWD */
#define OCD_RWD_RWD_START 0
#define OCD_RWD_RWD_SIZE 32
/* Bits in WT */
#define OCD_WT_DTE_START 20
#define OCD_WT_DTE_SIZE 3
#define OCD_WT_DTS_START 23
#define OCD_WT_DTS_SIZE 3
#define OCD_WT_PTE_START 26
#define OCD_WT_PTE_SIZE 3
#define OCD_WT_PTS_START 29
#define OCD_WT_PTS_SIZE 3
/* Bits in DTC */
#define OCD_DTC_T0WP_BIT 0
#define OCD_DTC_T1WP_BIT 1
#define OCD_DTC_ASID0EN_BIT 2
#define OCD_DTC_ASID0_START 3
#define OCD_DTC_ASID0_SIZE 8
#define OCD_DTC_ASID1EN_BIT 11
#define OCD_DTC_ASID1_START 12
#define OCD_DTC_ASID1_SIZE 8
#define OCD_DTC_RWT1_START 28
#define OCD_DTC_RWT1_SIZE 2
#define OCD_DTC_RWT0_START 30
#define OCD_DTC_RWT0_SIZE 2
/* Bits in DTSA0 */
#define OCD_DTSA0_DTSA_START 0
#define OCD_DTSA0_DTSA_SIZE 32
/* Bits in DTSA1 */
#define OCD_DTSA1_DTSA_START 0
#define OCD_DTSA1_DTSA_SIZE 32
/* Bits in DTEA0 */
#define OCD_DTEA0_DTEA_START 0
#define OCD_DTEA0_DTEA_SIZE 32
/* Bits in DTEA1 */
#define OCD_DTEA1_DTEA_START 0
#define OCD_DTEA1_DTEA_SIZE 32
/* Bits in BWC0A */
#define OCD_BWC0A_ASIDEN_BIT 0
#define OCD_BWC0A_ASID_START 1
#define OCD_BWC0A_ASID_SIZE 8
#define OCD_BWC0A_EOC_BIT 14
#define OCD_BWC0A_AME_BIT 25
#define OCD_BWC0A_BWE_START 30
#define OCD_BWC0A_BWE_SIZE 2
/* Bits in BWC0B */
#define OCD_BWC0B_ASIDEN_BIT 0
#define OCD_BWC0B_ASID_START 1
#define OCD_BWC0B_ASID_SIZE 8
#define OCD_BWC0B_EOC_BIT 14
#define OCD_BWC0B_AME_BIT 25
#define OCD_BWC0B_BWE_START 30
#define OCD_BWC0B_BWE_SIZE 2
/* Bits in BWC1A */
#define OCD_BWC1A_ASIDEN_BIT 0
#define OCD_BWC1A_ASID_START 1
#define OCD_BWC1A_ASID_SIZE 8
#define OCD_BWC1A_EOC_BIT 14
#define OCD_BWC1A_AME_BIT 25
#define OCD_BWC1A_BWE_START 30
#define OCD_BWC1A_BWE_SIZE 2
/* Bits in BWC1B */
#define OCD_BWC1B_ASIDEN_BIT 0
#define OCD_BWC1B_ASID_START 1
#define OCD_BWC1B_ASID_SIZE 8
#define OCD_BWC1B_EOC_BIT 14
#define OCD_BWC1B_AME_BIT 25
#define OCD_BWC1B_BWE_START 30
#define OCD_BWC1B_BWE_SIZE 2
/* Bits in BWC2A */
#define OCD_BWC2A_ASIDEN_BIT 0
#define OCD_BWC2A_ASID_START 1
#define OCD_BWC2A_ASID_SIZE 8
#define OCD_BWC2A_EOC_BIT 14
#define OCD_BWC2A_AMB_START 20
#define OCD_BWC2A_AMB_SIZE 5
#define OCD_BWC2A_AME_BIT 25
#define OCD_BWC2A_BWE_START 30
#define OCD_BWC2A_BWE_SIZE 2
/* Bits in BWC2B */
#define OCD_BWC2B_ASIDEN_BIT 0
#define OCD_BWC2B_ASID_START 1
#define OCD_BWC2B_ASID_SIZE 8
#define OCD_BWC2B_EOC_BIT 14
#define OCD_BWC2B_AME_BIT 25
#define OCD_BWC2B_BWE_START 30
#define OCD_BWC2B_BWE_SIZE 2
/* Bits in BWC3A */
#define OCD_BWC3A_ASIDEN_BIT 0
#define OCD_BWC3A_ASID_START 1
#define OCD_BWC3A_ASID_SIZE 8
#define OCD_BWC3A_SIZE_START 9
#define OCD_BWC3A_SIZE_SIZE 3
#define OCD_BWC3A_EOC_BIT 14
#define OCD_BWC3A_BWO_START 16
#define OCD_BWC3A_BWO_SIZE 2
#define OCD_BWC3A_BME_START 20
#define OCD_BWC3A_BME_SIZE 4
#define OCD_BWC3A_BRW_START 28
#define OCD_BWC3A_BRW_SIZE 2
#define OCD_BWC3A_BWE_START 30
#define OCD_BWC3A_BWE_SIZE 2
/* Bits in BWC3B */
#define OCD_BWC3B_ASIDEN_BIT 0
#define OCD_BWC3B_ASID_START 1
#define OCD_BWC3B_ASID_SIZE 8
#define OCD_BWC3B_SIZE_START 9
#define OCD_BWC3B_SIZE_SIZE 3
#define OCD_BWC3B_EOC_BIT 14
#define OCD_BWC3B_BWO_START 16
#define OCD_BWC3B_BWO_SIZE 2
#define OCD_BWC3B_BME_START 20
#define OCD_BWC3B_BME_SIZE 4
#define OCD_BWC3B_BRW_START 28
#define OCD_BWC3B_BRW_SIZE 2
#define OCD_BWC3B_BWE_START 30
#define OCD_BWC3B_BWE_SIZE 2
/* Bits in BWA0A */
#define OCD_BWA0A_BWA_START 0
#define OCD_BWA0A_BWA_SIZE 32
/* Bits in BWA0B */
#define OCD_BWA0B_BWA_START 0
#define OCD_BWA0B_BWA_SIZE 32
/* Bits in BWA1A */
#define OCD_BWA1A_BWA_START 0
#define OCD_BWA1A_BWA_SIZE 32
/* Bits in BWA1B */
#define OCD_BWA1B_BWA_START 0
#define OCD_BWA1B_BWA_SIZE 32
/* Bits in BWA2A */
#define OCD_BWA2A_BWA_START 0
#define OCD_BWA2A_BWA_SIZE 32
/* Bits in BWA2B */
#define OCD_BWA2B_BWA_START 0
#define OCD_BWA2B_BWA_SIZE 32
/* Bits in BWA3A */
#define OCD_BWA3A_BWA_START 0
#define OCD_BWA3A_BWA_SIZE 32
/* Bits in BWA3B */
#define OCD_BWA3B_BWA_START 0
#define OCD_BWA3B_BWA_SIZE 32
/* Bits in NXCFG */
#define OCD_NXCFG_NXARCH_START 0
#define OCD_NXCFG_NXARCH_SIZE 4
#define OCD_NXCFG_NXOCD_START 4
#define OCD_NXCFG_NXOCD_SIZE 4
#define OCD_NXCFG_NXPCB_START 8
#define OCD_NXCFG_NXPCB_SIZE 4
#define OCD_NXCFG_NXDB_START 12
#define OCD_NXCFG_NXDB_SIZE 4
#define OCD_NXCFG_MXMSEO_BIT 16
#define OCD_NXCFG_NXMDO_START 17
#define OCD_NXCFG_NXMDO_SIZE 4
#define OCD_NXCFG_NXPT_BIT 21
#define OCD_NXCFG_NXOT_BIT 22
#define OCD_NXCFG_NXDWT_BIT 23
#define OCD_NXCFG_NXDRT_BIT 24
#define OCD_NXCFG_NXDTC_START 25
#define OCD_NXCFG_NXDTC_SIZE 3
#define OCD_NXCFG_NXDMA_BIT 28
/* Bits in DINST */
#define OCD_DINST_DINST_START 0
#define OCD_DINST_DINST_SIZE 32
/* Bits in CPUCM */
#define OCD_CPUCM_BEM_BIT 1
#define OCD_CPUCM_FEM_BIT 2
#define OCD_CPUCM_REM_BIT 3
#define OCD_CPUCM_IBEM_BIT 4
#define OCD_CPUCM_IEEM_BIT 5
/* Bits in DCCPU */
#define OCD_DCCPU_DATA_START 0
#define OCD_DCCPU_DATA_SIZE 32
/* Bits in DCEMU */
#define OCD_DCEMU_DATA_START 0
#define OCD_DCEMU_DATA_SIZE 32
/* Bits in DCSR */
#define OCD_DCSR_CPUD_BIT 0
#define OCD_DCSR_EMUD_BIT 1
/* Bits in PID */
#define OCD_PID_PROCESS_START 0
#define OCD_PID_PROCESS_SIZE 32
/* Bits in EPC0 */
#define OCD_EPC0_RNG_START 0
#define OCD_EPC0_RNG_SIZE 2
#define OCD_EPC0_CE_BIT 4
#define OCD_EPC0_ECNT_START 16
#define OCD_EPC0_ECNT_SIZE 16
/* Bits in EPC1 */
#define OCD_EPC1_RNG_START 0
#define OCD_EPC1_RNG_SIZE 2
#define OCD_EPC1_ATB_BIT 5
#define OCD_EPC1_AM_BIT 6
/* Bits in EPC2 */
#define OCD_EPC2_RNG_START 0
#define OCD_EPC2_RNG_SIZE 2
#define OCD_EPC2_DB_START 2
#define OCD_EPC2_DB_SIZE 2
/* Bits in EPC3 */
#define OCD_EPC3_RNG_START 0
#define OCD_EPC3_RNG_SIZE 2
#define OCD_EPC3_DWE_BIT 2
/* Bits in AXC */
#define OCD_AXC_DIV_START 0
#define OCD_AXC_DIV_SIZE 4
#define OCD_AXC_AXE_BIT 8
#define OCD_AXC_AXS_BIT 9
#define OCD_AXC_DDR_BIT 10
#define OCD_AXC_LS_BIT 11
#define OCD_AXC_REX_BIT 12
#define OCD_AXC_REXTEN_BIT 13
/* Constants for DC:EIC */
#define OCD_EIC_PROGRAM_AND_DATA_TRACE 0
#define OCD_EIC_BREAKPOINT 1
#define OCD_EIC_NOP 2
/* Constants for DC:OVC */
#define OCD_OVC_OVERRUN 0
#define OCD_OVC_DELAY_CPU_BTM 1
#define OCD_OVC_DELAY_CPU_DTM 2
#define OCD_OVC_DELAY_CPU_BTM_DTM 3
/* Constants for DC:EOS */
#define OCD_EOS_NOP 0
#define OCD_EOS_DEBUG_MODE 1
#define OCD_EOS_BREAKPOINT_WATCHPOINT 2
#define OCD_EOS_THQ 3
/* Constants for RWCS:NTBC */
#define OCD_NTBC_OVERWRITE 0
#define OCD_NTBC_DISABLE 1
#define OCD_NTBC_BREAKPOINT 2
/* Constants for RWCS:CCTRL */
#define OCD_CCTRL_AUTO 0
#define OCD_CCTRL_CACHED 1
#define OCD_CCTRL_UNCACHED 2
/* Constants for RWCS:SZ */
#define OCD_SZ_BYTE 0
#define OCD_SZ_HALFWORD 1
#define OCD_SZ_WORD 2
/* Constants for WT:PTS */
#define OCD_PTS_DISABLED 0
#define OCD_PTS_PROGRAM_0B 1
#define OCD_PTS_PROGRAM_1A 2
#define OCD_PTS_PROGRAM_1B 3
#define OCD_PTS_PROGRAM_2A 4
#define OCD_PTS_PROGRAM_2B 5
#define OCD_PTS_DATA_3A 6
#define OCD_PTS_DATA_3B 7
/* Constants for DTC:RWT1 */
#define OCD_RWT1_NO_TRACE 0
#define OCD_RWT1_DATA_READ 1
#define OCD_RWT1_DATA_WRITE 2
#define OCD_RWT1_DATA_READ_WRITE 3
/* Constants for DTC:RWT0 */
#define OCD_RWT0_NO_TRACE 0
#define OCD_RWT0_DATA_READ 1
#define OCD_RWT0_DATA_WRITE 2
#define OCD_RWT0_DATA_READ_WRITE 3
/* Constants for BWC0A:BWE */
#define OCD_BWE_DISABLED 0
#define OCD_BWE_BREAKPOINT_ENABLED 1
#define OCD_BWE_WATCHPOINT_ENABLED 3
/* Constants for BWC0B:BWE */
#define OCD_BWE_DISABLED 0
#define OCD_BWE_BREAKPOINT_ENABLED 1
#define OCD_BWE_WATCHPOINT_ENABLED 3
/* Constants for BWC1A:BWE */
#define OCD_BWE_DISABLED 0
#define OCD_BWE_BREAKPOINT_ENABLED 1
#define OCD_BWE_WATCHPOINT_ENABLED 3
/* Constants for BWC1B:BWE */
#define OCD_BWE_DISABLED 0
#define OCD_BWE_BREAKPOINT_ENABLED 1
#define OCD_BWE_WATCHPOINT_ENABLED 3
/* Constants for BWC2A:BWE */
#define OCD_BWE_DISABLED 0
#define OCD_BWE_BREAKPOINT_ENABLED 1
#define OCD_BWE_WATCHPOINT_ENABLED 3
/* Constants for BWC2B:BWE */
#define OCD_BWE_DISABLED 0
#define OCD_BWE_BREAKPOINT_ENABLED 1
#define OCD_BWE_WATCHPOINT_ENABLED 3
/* Constants for BWC3A:SIZE */
#define OCD_SIZE_BYTE_ACCESS 4
#define OCD_SIZE_HALFWORD_ACCESS 5
#define OCD_SIZE_WORD_ACCESS 6
#define OCD_SIZE_DOUBLE_WORD_ACCESS 7
/* Constants for BWC3A:BRW */
#define OCD_BRW_READ_BREAK 0
#define OCD_BRW_WRITE_BREAK 1
#define OCD_BRW_ANY_ACCES_BREAK 2
/* Constants for BWC3A:BWE */
#define OCD_BWE_DISABLED 0
#define OCD_BWE_BREAKPOINT_ENABLED 1
#define OCD_BWE_WATCHPOINT_ENABLED 3
/* Constants for BWC3B:SIZE */
#define OCD_SIZE_BYTE_ACCESS 4
#define OCD_SIZE_HALFWORD_ACCESS 5
#define OCD_SIZE_WORD_ACCESS 6
#define OCD_SIZE_DOUBLE_WORD_ACCESS 7
/* Constants for BWC3B:BRW */
#define OCD_BRW_READ_BREAK 0
#define OCD_BRW_WRITE_BREAK 1
#define OCD_BRW_ANY_ACCES_BREAK 2
/* Constants for BWC3B:BWE */
#define OCD_BWE_DISABLED 0
#define OCD_BWE_BREAKPOINT_ENABLED 1
#define OCD_BWE_WATCHPOINT_ENABLED 3
/* Constants for EPC0:RNG */
#define OCD_RNG_DISABLED 0
#define OCD_RNG_EXCLUSIVE 1
#define OCD_RNG_INCLUSIVE 2
/* Constants for EPC1:RNG */
#define OCD_RNG_DISABLED 0
#define OCD_RNG_EXCLUSIVE 1
#define OCD_RNG_INCLUSIVE 2
/* Constants for EPC2:RNG */
#define OCD_RNG_DISABLED 0
#define OCD_RNG_EXCLUSIVE 1
#define OCD_RNG_INCLUSIVE 2
/* Constants for EPC2:DB */
#define OCD_DB_DISABLED 0
#define OCD_DB_CHAINED_B 1
#define OCD_DB_CHAINED_A 2
#define OCD_DB_AHAINED_A_AND_B 3
/* Constants for EPC3:RNG */
#define OCD_RNG_DISABLED 0
#define OCD_RNG_EXCLUSIVE 1
#define OCD_RNG_INCLUSIVE 2
#ifndef __ASSEMBLER__
/* Register access macros */
static inline unsigned long __ocd_read(unsigned int reg)
{
return __builtin_mfdr(reg);
}
static inline void __ocd_write(unsigned int reg, unsigned long value)
{
__builtin_mtdr(reg, value);
}
#define ocd_read(reg) __ocd_read(OCD_##reg)
#define ocd_write(reg, value) __ocd_write(OCD_##reg, value)
#endif /* !__ASSEMBLER__ */
#endif /* __ASM_AVR32_OCD_H */
include/asm-avr32/system.h
View file @ 8dfe8f29
......@@ -35,8 +35,8 @@
#include <asm/ocd.h>
#define finish_arch_switch(prev) \
do { \
__mtdr(DBGREG_PID, prev->pid); \
__mtdr(DBGREG_PID, current->pid); \
ocd_write(PID, prev->pid); \
ocd_write(PID, current->pid); \
} while(0)
#endif
......
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