Commit 8e8e9a0b authored by Alexander Duyck's avatar Alexander Duyck Committed by Jeff Kirsher

ixgbe: Fix SR-IOV VLAN pool configuration

The code for checking the PF bit in ixgbe_set_vf_vlan_msg was using the
wrong offset and as a result it was pulling the VLAN off of the PF even if
there were VFs numbered greater than 40 that still had the VLAN enabled.
Signed-off-by: default avatarAlexander Duyck <aduyck@mirantis.com>
Tested-by: default avatarPhil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 530fd82a
...@@ -887,10 +887,10 @@ static int ixgbe_set_vf_vlan_msg(struct ixgbe_adapter *adapter, ...@@ -887,10 +887,10 @@ static int ixgbe_set_vf_vlan_msg(struct ixgbe_adapter *adapter,
bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2)); bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2));
bits &= ~(1 << VMDQ_P(0)); bits &= ~(1 << VMDQ_P(0));
bits |= IXGBE_READ_REG(hw, bits |= IXGBE_READ_REG(hw,
IXGBE_VLVFB(reg_ndx * 2) + 1); IXGBE_VLVFB(reg_ndx * 2 + 1));
} else { } else {
bits = IXGBE_READ_REG(hw, bits = IXGBE_READ_REG(hw,
IXGBE_VLVFB(reg_ndx * 2) + 1); IXGBE_VLVFB(reg_ndx * 2 + 1));
bits &= ~(1 << (VMDQ_P(0) - 32)); bits &= ~(1 << (VMDQ_P(0) - 32));
bits |= IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2)); bits |= IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2));
} }
......
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