Commit 951a730a authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'blackfin-for-linus' of...

Merge tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux

Pull blackfin updates from Steven Miao.

* tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux:
  blackfin: Ignore generated uImages
  blackfin: Add STMMAC platform data to enable dwmac1000 driver on BF60x.
  bf609: adv7343: add S-Video and Component output support
  bf609: add adv7343 video encoder support
  clock: add stmmac clock for ethernet driver
  blackfin: scb: Add SCB1 to SCB9 config options and data.
  blackfin: scb: Add system crossbar init code.
parents 0898d2aa 08b67faa
vmImage* vmImage*
vmlinux* vmlinux*
uImage*
/*
* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
*
* Copyright 2012 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#define SCB_SLOT_OFFSET 24
#define SCB_MI_MAX_SLOT 32
struct scb_mi_prio {
unsigned long scb_mi_arbr;
unsigned long scb_mi_arbw;
unsigned char scb_mi_slots;
unsigned char scb_mi_prio[SCB_MI_MAX_SLOT];
};
extern struct scb_mi_prio scb_data[];
extern void init_scb(void);
...@@ -35,6 +35,9 @@ ...@@ -35,6 +35,9 @@
#ifdef CONFIG_BF60x #ifdef CONFIG_BF60x
#include <mach/pm.h> #include <mach/pm.h>
#endif #endif
#ifdef CONFIG_SCB_PRIORITY
#include <asm/scb.h>
#endif
u16 _bfin_swrst; u16 _bfin_swrst;
EXPORT_SYMBOL(_bfin_swrst); EXPORT_SYMBOL(_bfin_swrst);
...@@ -1101,6 +1104,9 @@ void __init setup_arch(char **cmdline_p) ...@@ -1101,6 +1104,9 @@ void __init setup_arch(char **cmdline_p)
#endif #endif
init_exception_vectors(); init_exception_vectors();
bfin_cache_init(); /* Initialize caches for the boot CPU */ bfin_cache_init(); /* Initialize caches for the boot CPU */
#ifdef CONFIG_SCB_PRIORITY
init_scb();
#endif
} }
static int __init topology_init(void) static int __init topology_init(void)
......
...@@ -59,6 +59,1661 @@ config SEC_IRQ_PRIORITY_LEVELS ...@@ -59,6 +59,1661 @@ config SEC_IRQ_PRIORITY_LEVELS
Divide the total number of interrupt priority levels into sub-levels. Divide the total number of interrupt priority levels into sub-levels.
There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels. There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
comment "System Cross Bar Priority Assignment"
config SCB_PRIORITY
bool "Init System Cross Bar Priority"
default n
menuconfig SCB0_MI0
bool "SCB0 Master Interface 0 (DDR)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
Core 0 -- 0
Core 1 -- 2
SCB1 -- 9
SCB2 -- 10
SCB3 -- 11
SCB4 -- 12
SCB5 -- 5
SCB6 -- 6
SCB7 -- 8
SCB8 -- 7
SCB9 -- 4
USB -- 13
if SCB0_MI0
config SCB0_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 13
config SCB0_MI0_SLOT1
int "Slot 1 slave interface id"
default 2
range 0 13
config SCB0_MI0_SLOT2
int "Slot 2 slave interface id"
default 4
range 0 13
config SCB0_MI0_SLOT3
int "Slot 3 slave interface id"
default 5
range 0 13
config SCB0_MI0_SLOT4
int "Slot 4 slave interface id"
default 6
range 0 13
config SCB0_MI0_SLOT5
int "Slot 5 slave interface id"
default 7
range 0 13
config SCB0_MI0_SLOT6
int "Slot 6 slave interface id"
default 8
range 0 13
config SCB0_MI0_SLOT7
int "Slot 7 slave interface id"
default 9
range 0 13
config SCB0_MI0_SLOT8
int "Slot 8 slave interface id"
default 10
range 0 13
config SCB0_MI0_SLOT9
int "Slot 9 slave interface id"
default 11
range 0 13
config SCB0_MI0_SLOT10
int "Slot 10 slave interface id"
default 13
range 0 13
config SCB0_MI0_SLOT11
int "Slot 11 slave interface id"
default 12
range 0 13
config SCB0_MI0_SLOT12
int "Slot 12 slave interface id"
default 0
range 0 13
config SCB0_MI0_SLOT13
int "Slot 13 slave interface id"
default 2
range 0 13
config SCB0_MI0_SLOT14
int "Slot 14 slave interface id"
default 4
range 0 13
config SCB0_MI0_SLOT15
int "Slot 15 slave interface id"
default 5
range 0 13
config SCB0_MI0_SLOT16
int "Slot 16 slave interface id"
default 6
range 0 13
config SCB0_MI0_SLOT17
int "Slot 17 slave interface id"
default 7
range 0 13
config SCB0_MI0_SLOT18
int "Slot 18 slave interface id"
default 8
range 0 13
config SCB0_MI0_SLOT19
int "Slot 19 slave interface id"
default 9
range 0 13
config SCB0_MI0_SLOT20
int "Slot 20 slave interface id"
default 10
range 0 13
config SCB0_MI0_SLOT21
int "Slot 21 slave interface id"
default 11
range 0 13
config SCB0_MI0_SLOT22
int "Slot 22 slave interface id"
default 13
range 0 13
config SCB0_MI0_SLOT23
int "Slot 23 slave interface id"
default 12
range 0 13
config SCB0_MI0_SLOT24
int "Slot 24 slave interface id"
default 0
range 0 13
config SCB0_MI0_SLOT25
int "Slot 25 slave interface id"
default 2
range 0 13
config SCB0_MI0_SLOT26
int "Slot 26 slave interface id"
default 4
range 0 13
config SCB0_MI0_SLOT27
int "Slot 27 slave interface id"
default 5
range 0 13
config SCB0_MI0_SLOT28
int "Slot 28 slave interface id"
default 6
range 0 13
config SCB0_MI0_SLOT29
int "Slot 29 slave interface id"
default 7
range 0 13
config SCB0_MI0_SLOT30
int "Slot 30 slave interface id"
default 8
range 0 13
config SCB0_MI0_SLOT31
int "Slot 31 slave interface id"
default 13
range 0 13
endif # SCB0_MI0
menuconfig SCB0_MI1
bool "SCB0 Master Interface 1 (SMC)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
Core 0 -- 0
Core 1 -- 2
SCB1 -- 9
SCB2 -- 10
SCB3 -- 11
SCB4 -- 12
SCB5 -- 5
SCB6 -- 6
SCB7 -- 8
SCB8 -- 7
SCB9 -- 4
USB -- 13
if SCB0_MI1
config SCB0_MI1_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 13
config SCB0_MI1_SLOT1
int "Slot 1 slave interface id"
default 2
range 0 13
config SCB0_MI1_SLOT2
int "Slot 2 slave interface id"
default 4
range 0 13
config SCB0_MI1_SLOT3
int "Slot 3 slave interface id"
default 5
range 0 13
config SCB0_MI1_SLOT4
int "Slot 4 slave interface id"
default 6
range 0 13
config SCB0_MI1_SLOT5
int "Slot 5 slave interface id"
default 7
range 0 13
config SCB0_MI1_SLOT6
int "Slot 6 slave interface id"
default 8
range 0 13
config SCB0_MI1_SLOT7
int "Slot 7 slave interface id"
default 9
range 0 13
config SCB0_MI1_SLOT8
int "Slot 8 slave interface id"
default 10
range 0 13
config SCB0_MI1_SLOT9
int "Slot 9 slave interface id"
default 11
range 0 13
config SCB0_MI1_SLOT10
int "Slot 10 slave interface id"
default 13
range 0 13
config SCB0_MI1_SLOT11
int "Slot 11 slave interface id"
default 12
range 0 13
config SCB0_MI1_SLOT12
int "Slot 12 slave interface id"
default 0
range 0 13
config SCB0_MI1_SLOT13
int "Slot 13 slave interface id"
default 2
range 0 13
config SCB0_MI1_SLOT14
int "Slot 14 slave interface id"
default 4
range 0 13
config SCB0_MI1_SLOT15
int "Slot 15 slave interface id"
default 5
range 0 13
config SCB0_MI1_SLOT16
int "Slot 16 slave interface id"
default 6
range 0 13
config SCB0_MI1_SLOT17
int "Slot 17 slave interface id"
default 7
range 0 13
config SCB0_MI1_SLOT18
int "Slot 18 slave interface id"
default 8
range 0 13
config SCB0_MI1_SLOT19
int "Slot 19 slave interface id"
default 9
range 0 13
config SCB0_MI1_SLOT20
int "Slot 20 slave interface id"
default 10
range 0 13
config SCB0_MI1_SLOT21
int "Slot 21 slave interface id"
default 11
range 0 13
config SCB0_MI1_SLOT22
int "Slot 22 slave interface id"
default 13
range 0 13
config SCB0_MI1_SLOT23
int "Slot 23 slave interface id"
default 12
range 0 13
config SCB0_MI1_SLOT24
int "Slot 24 slave interface id"
default 0
range 0 13
config SCB0_MI1_SLOT25
int "Slot 25 slave interface id"
default 2
range 0 13
config SCB0_MI1_SLOT26
int "Slot 26 slave interface id"
default 4
range 0 13
config SCB0_MI1_SLOT27
int "Slot 27 slave interface id"
default 5
range 0 13
config SCB0_MI1_SLOT28
int "Slot 28 slave interface id"
default 6
range 0 13
config SCB0_MI1_SLOT29
int "Slot 29 slave interface id"
default 7
range 0 13
config SCB0_MI1_SLOT30
int "Slot 30 slave interface id"
default 8
range 0 13
config SCB0_MI1_SLOT31
int "Slot 31 slave interface id"
default 13
range 0 13
endif # SCB0_MI1
menuconfig SCB0_MI2
bool "SCB0 Master Interface 2 (Data L2)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
Core 0 -- 0
Core 1 -- 2
SCB1 -- 9
SCB2 -- 10
SCB3 -- 11
SCB4 -- 12
SCB5 -- 5
SCB6 -- 6
SCB7 -- 8
SCB8 -- 7
SCB9 -- 4
USB -- 13
if SCB0_MI2
config SCB0_MI2_SLOT0
int "Slot 0 slave interface id"
default 4
range 0 13
config SCB0_MI2_SLOT1
int "Slot 1 slave interface id"
default 5
range 0 13
config SCB0_MI2_SLOT2
int "Slot 2 slave interface id"
default 6
range 0 13
config SCB0_MI2_SLOT3
int "Slot 3 slave interface id"
default 7
range 0 13
config SCB0_MI2_SLOT4
int "Slot 4 slave interface id"
default 8
range 0 13
config SCB0_MI2_SLOT5
int "Slot 5 slave interface id"
default 9
range 0 13
config SCB0_MI2_SLOT6
int "Slot 6 slave interface id"
default 10
range 0 13
config SCB0_MI2_SLOT7
int "Slot 7 slave interface id"
default 11
range 0 13
config SCB0_MI2_SLOT8
int "Slot 8 slave interface id"
default 13
range 0 13
config SCB0_MI2_SLOT9
int "Slot 9 slave interface id"
default 12
range 0 13
config SCB0_MI2_SLOT10
int "Slot 10 slave interface id"
default 4
range 0 13
config SCB0_MI2_SLOT11
int "Slot 11 slave interface id"
default 5
range 0 13
config SCB0_MI2_SLOT12
int "Slot 12 slave interface id"
default 6
range 0 13
config SCB0_MI2_SLOT13
int "Slot 13 slave interface id"
default 7
range 0 13
config SCB0_MI2_SLOT14
int "Slot 14 slave interface id"
default 8
range 0 13
config SCB0_MI2_SLOT15
int "Slot 15 slave interface id"
default 9
range 0 13
config SCB0_MI2_SLOT16
int "Slot 16 slave interface id"
default 10
range 0 13
config SCB0_MI2_SLOT17
int "Slot 17 slave interface id"
default 11
range 0 13
config SCB0_MI2_SLOT18
int "Slot 18 slave interface id"
default 13
range 0 13
config SCB0_MI2_SLOT19
int "Slot 19 slave interface id"
default 12
range 0 13
config SCB0_MI2_SLOT20
int "Slot 20 slave interface id"
default 4
range 0 13
config SCB0_MI2_SLOT21
int "Slot 21 slave interface id"
default 5
range 0 13
config SCB0_MI2_SLOT22
int "Slot 22 slave interface id"
default 6
range 0 13
config SCB0_MI2_SLOT23
int "Slot 23 slave interface id"
default 7
range 0 13
config SCB0_MI2_SLOT24
int "Slot 24 slave interface id"
default 8
range 0 13
config SCB0_MI2_SLOT25
int "Slot 25 slave interface id"
default 9
range 0 13
config SCB0_MI2_SLOT26
int "Slot 26 slave interface id"
default 10
range 0 13
config SCB0_MI2_SLOT27
int "Slot 27 slave interface id"
default 11
range 0 13
config SCB0_MI2_SLOT28
int "Slot 28 slave interface id"
default 13
range 0 13
config SCB0_MI2_SLOT29
int "Slot 29 slave interface id"
default 12
range 0 13
config SCB0_MI2_SLOT30
int "Slot 30 slave interface id"
default 4
range 0 13
config SCB0_MI2_SLOT31
int "Slot 31 slave interface id"
default 7
range 0 13
endif # SCB0_MI2
menuconfig SCB0_MI3
bool "SCB0 Master Interface 3 (L1A)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
Core 0 -- 0
Core 1 -- 2
SCB1 -- 9
SCB2 -- 10
SCB3 -- 11
SCB4 -- 12
SCB5 -- 5
SCB6 -- 6
SCB7 -- 8
SCB8 -- 7
SCB9 -- 4
USB -- 13
if SCB0_MI3
config SCB0_MI3_SLOT0
int "Slot 0 slave interface id"
default 4
range 0 13
config SCB0_MI3_SLOT1
int "Slot 1 slave interface id"
default 5
range 0 13
config SCB0_MI3_SLOT2
int "Slot 2 slave interface id"
default 6
range 0 13
config SCB0_MI3_SLOT3
int "Slot 3 slave interface id"
default 7
range 0 13
config SCB0_MI3_SLOT4
int "Slot 4 slave interface id"
default 8
range 0 13
config SCB0_MI3_SLOT5
int "Slot 5 slave interface id"
default 9
range 0 13
config SCB0_MI3_SLOT6
int "Slot 6 slave interface id"
default 10
range 0 13
config SCB0_MI3_SLOT7
int "Slot 7 slave interface id"
default 11
range 0 13
config SCB0_MI3_SLOT8
int "Slot 8 slave interface id"
default 13
range 0 13
config SCB0_MI3_SLOT9
int "Slot 9 slave interface id"
default 12
range 0 13
config SCB0_MI3_SLOT10
int "Slot 10 slave interface id"
default 4
range 0 13
config SCB0_MI3_SLOT11
int "Slot 11 slave interface id"
default 5
range 0 13
config SCB0_MI3_SLOT12
int "Slot 12 slave interface id"
default 6
range 0 13
config SCB0_MI3_SLOT13
int "Slot 13 slave interface id"
default 7
range 0 13
config SCB0_MI3_SLOT14
int "Slot 14 slave interface id"
default 8
range 0 13
config SCB0_MI3_SLOT15
int "Slot 15 slave interface id"
default 9
range 0 13
config SCB0_MI3_SLOT16
int "Slot 16 slave interface id"
default 10
range 0 13
config SCB0_MI3_SLOT17
int "Slot 17 slave interface id"
default 11
range 0 13
config SCB0_MI3_SLOT18
int "Slot 18 slave interface id"
default 13
range 0 13
config SCB0_MI3_SLOT19
int "Slot 19 slave interface id"
default 12
range 0 13
config SCB0_MI3_SLOT20
int "Slot 20 slave interface id"
default 4
range 0 13
config SCB0_MI3_SLOT21
int "Slot 21 slave interface id"
default 5
range 0 13
config SCB0_MI3_SLOT22
int "Slot 22 slave interface id"
default 6
range 0 13
config SCB0_MI3_SLOT23
int "Slot 23 slave interface id"
default 7
range 0 13
config SCB0_MI3_SLOT24
int "Slot 24 slave interface id"
default 8
range 0 13
config SCB0_MI3_SLOT25
int "Slot 25 slave interface id"
default 9
range 0 13
config SCB0_MI3_SLOT26
int "Slot 26 slave interface id"
default 10
range 0 13
config SCB0_MI3_SLOT27
int "Slot 27 slave interface id"
default 11
range 0 13
config SCB0_MI3_SLOT28
int "Slot 28 slave interface id"
default 13
range 0 13
config SCB0_MI3_SLOT29
int "Slot 29 slave interface id"
default 12
range 0 13
config SCB0_MI3_SLOT30
int "Slot 30 slave interface id"
default 4
range 0 13
config SCB0_MI3_SLOT31
int "Slot 31 slave interface id"
default 7
range 0 13
endif # SCB0_MI3
menuconfig SCB0_MI4
bool "SCB0 Master Interface 4 (L1B)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
Core 0 -- 0
Core 1 -- 2
SCB1 -- 9
SCB2 -- 10
SCB3 -- 11
SCB4 -- 12
SCB5 -- 5
SCB6 -- 6
SCB7 -- 8
SCB8 -- 7
SCB9 -- 4
USB -- 13
if SCB0_MI4
config SCB0_MI4_SLOT0
int "Slot 0 slave interface id"
default 4
range 0 13
config SCB0_MI4_SLOT1
int "Slot 1 slave interface id"
default 5
range 0 13
config SCB0_MI4_SLOT2
int "Slot 2 slave interface id"
default 6
range 0 13
config SCB0_MI4_SLOT3
int "Slot 3 slave interface id"
default 7
range 0 13
config SCB0_MI4_SLOT4
int "Slot 4 slave interface id"
default 8
range 0 13
config SCB0_MI4_SLOT5
int "Slot 5 slave interface id"
default 9
range 0 13
config SCB0_MI4_SLOT6
int "Slot 6 slave interface id"
default 10
range 0 13
config SCB0_MI4_SLOT7
int "Slot 7 slave interface id"
default 11
range 0 13
config SCB0_MI4_SLOT8
int "Slot 8 slave interface id"
default 13
range 0 13
config SCB0_MI4_SLOT9
int "Slot 9 slave interface id"
default 12
range 0 13
config SCB0_MI4_SLOT10
int "Slot 10 slave interface id"
default 4
range 0 13
config SCB0_MI4_SLOT11
int "Slot 11 slave interface id"
default 5
range 0 13
config SCB0_MI4_SLOT12
int "Slot 12 slave interface id"
default 6
range 0 13
config SCB0_MI4_SLOT13
int "Slot 13 slave interface id"
default 7
range 0 13
config SCB0_MI4_SLOT14
int "Slot 14 slave interface id"
default 8
range 0 13
config SCB0_MI4_SLOT15
int "Slot 15 slave interface id"
default 9
range 0 13
config SCB0_MI4_SLOT16
int "Slot 16 slave interface id"
default 10
range 0 13
config SCB0_MI4_SLOT17
int "Slot 17 slave interface id"
default 11
range 0 13
config SCB0_MI4_SLOT18
int "Slot 18 slave interface id"
default 13
range 0 13
config SCB0_MI4_SLOT19
int "Slot 19 slave interface id"
default 12
range 0 13
config SCB0_MI4_SLOT20
int "Slot 20 slave interface id"
default 4
range 0 13
config SCB0_MI4_SLOT21
int "Slot 21 slave interface id"
default 5
range 0 13
config SCB0_MI4_SLOT22
int "Slot 22 slave interface id"
default 6
range 0 13
config SCB0_MI4_SLOT23
int "Slot 23 slave interface id"
default 7
range 0 13
config SCB0_MI4_SLOT24
int "Slot 24 slave interface id"
default 8
range 0 13
config SCB0_MI4_SLOT25
int "Slot 25 slave interface id"
default 9
range 0 13
config SCB0_MI4_SLOT26
int "Slot 26 slave interface id"
default 10
range 0 13
config SCB0_MI4_SLOT27
int "Slot 27 slave interface id"
default 11
range 0 13
config SCB0_MI4_SLOT28
int "Slot 28 slave interface id"
default 13
range 0 13
config SCB0_MI4_SLOT29
int "Slot 29 slave interface id"
default 12
range 0 13
config SCB0_MI4_SLOT30
int "Slot 30 slave interface id"
default 4
range 0 13
config SCB0_MI4_SLOT31
int "Slot 31 slave interface id"
default 7
range 0 13
endif # SCB0_MI4
menuconfig SCB0_MI5
bool "SCB0 Master Interface 5 (SMMR)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
MMR0 -- 1
MMR1 -- 3
SCB2 -- 10
SCB4 -- 12
if SCB0_MI5
config SCB0_MI5_SLOT0
int "Slot 0 slave interface id"
default 1
range 0 13
config SCB0_MI5_SLOT1
int "Slot 1 slave interface id"
default 3
range 0 13
config SCB0_MI5_SLOT2
int "Slot 2 slave interface id"
default 10
range 0 13
config SCB0_MI5_SLOT3
int "Slot 3 slave interface id"
default 12
range 0 13
config SCB0_MI5_SLOT4
int "Slot 4 slave interface id"
default 1
range 0 13
config SCB0_MI5_SLOT5
int "Slot 5 slave interface id"
default 3
range 0 13
config SCB0_MI5_SLOT6
int "Slot 6 slave interface id"
default 10
range 0 13
config SCB0_MI5_SLOT7
int "Slot 7 slave interface id"
default 12
range 0 13
config SCB0_MI5_SLOT8
int "Slot 8 slave interface id"
default 1
range 0 13
config SCB0_MI5_SLOT9
int "Slot 9 slave interface id"
default 3
range 0 13
config SCB0_MI5_SLOT10
int "Slot 10 slave interface id"
default 10
range 0 13
config SCB0_MI5_SLOT11
int "Slot 11 slave interface id"
default 12
range 0 13
config SCB0_MI5_SLOT12
int "Slot 12 slave interface id"
default 1
range 0 13
config SCB0_MI5_SLOT13
int "Slot 13 slave interface id"
default 3
range 0 13
config SCB0_MI5_SLOT14
int "Slot 14 slave interface id"
default 10
range 0 13
config SCB0_MI5_SLOT15
int "Slot 15 slave interface id"
default 12
range 0 13
endif # SCB0_MI5
menuconfig SCB1_MI0
bool "SCB1 Master Interface 0"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
SPORT0A -- 0
SPORT0B -- 1
SPORT1A -- 2
SPORT1B -- 3
SPORT2A -- 4
SPORT2B -- 5
SPI0TX -- 6
SPI0RX -- 7
SPI1TX -- 8
SPI1RX -- 9
if SCB1_MI0
config SCB1_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 9
config SCB1_MI0_SLOT1
int "Slot 1 slave interface id"
default 1
range 0 9
config SCB1_MI0_SLOT2
int "Slot 2 slave interface id"
default 2
range 0 9
config SCB1_MI0_SLOT3
int "Slot 3 slave interface id"
default 3
range 0 9
config SCB1_MI0_SLOT4
int "Slot 4 slave interface id"
default 4
range 0 9
config SCB1_MI0_SLOT5
int "Slot 5 slave interface id"
default 5
range 0 9
config SCB1_MI0_SLOT6
int "Slot 6 slave interface id"
default 6
range 0 9
config SCB1_MI0_SLOT7
int "Slot 7 slave interface id"
default 7
range 0 9
config SCB1_MI0_SLOT8
int "Slot 8 slave interface id"
default 8
range 0 9
config SCB1_MI0_SLOT9
int "Slot 9 slave interface id"
default 9
range 0 9
config SCB1_MI0_SLOT10
int "Slot 10 slave interface id"
default 0
range 0 9
config SCB1_MI0_SLOT11
int "Slot 11 slave interface id"
default 1
range 0 9
config SCB1_MI0_SLOT12
int "Slot 12 slave interface id"
default 2
range 0 9
config SCB1_MI0_SLOT13
int "Slot 13 slave interface id"
default 3
range 0 9
config SCB1_MI0_SLOT14
int "Slot 14 slave interface id"
default 4
range 0 9
config SCB1_MI0_SLOT15
int "Slot 15 slave interface id"
default 5
range 0 9
config SCB1_MI0_SLOT16
int "Slot 16 slave interface id"
default 6
range 0 13
config SCB1_MI0_SLOT17
int "Slot 17 slave interface id"
default 7
range 0 13
config SCB1_MI0_SLOT18
int "Slot 18 slave interface id"
default 8
range 0 13
config SCB1_MI0_SLOT19
int "Slot 19 slave interface id"
default 9
range 0 13
endif # SCB1_MI0
menuconfig SCB2_MI0
bool "SCB2 Master Interface 0"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
RSI -- 0
SDU DMA -- 1
SDU -- 2
EMAC0 -- 3
EMAC1 -- 4
if SCB2_MI0
config SCB2_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 4
config SCB2_MI0_SLOT1
int "Slot 1 slave interface id"
default 1
range 0 4
config SCB2_MI0_SLOT2
int "Slot 2 slave interface id"
default 2
range 0 4
config SCB2_MI0_SLOT3
int "Slot 3 slave interface id"
default 3
range 0 4
config SCB2_MI0_SLOT4
int "Slot 4 slave interface id"
default 4
range 0 4
config SCB2_MI0_SLOT5
int "Slot 5 slave interface id"
default 0
range 0 4
config SCB2_MI0_SLOT6
int "Slot 6 slave interface id"
default 1
range 0 4
config SCB2_MI0_SLOT7
int "Slot 7 slave interface id"
default 2
range 0 4
config SCB2_MI0_SLOT8
int "Slot 8 slave interface id"
default 3
range 0 4
config SCB2_MI0_SLOT9
int "Slot 9 slave interface id"
default 4
range 0 4
endif # SCB2_MI0
menuconfig SCB3_MI0
bool "SCB3 Master Interface 0"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
LP0 -- 0
LP1 -- 1
LP2 -- 2
LP3 -- 3
UART0TX -- 4
UART0RX -- 5
UART1TX -- 4
UART1RX -- 5
if SCB3_MI0
config SCB3_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 7
config SCB3_MI0_SLOT1
int "Slot 1 slave interface id"
default 1
range 0 7
config SCB3_MI0_SLOT2
int "Slot 2 slave interface id"
default 2
range 0 7
config SCB3_MI0_SLOT3
int "Slot 3 slave interface id"
default 3
range 0 7
config SCB3_MI0_SLOT4
int "Slot 4 slave interface id"
default 4
range 0 7
config SCB3_MI0_SLOT5
int "Slot 5 slave interface id"
default 5
range 0 7
config SCB3_MI0_SLOT6
int "Slot 6 slave interface id"
default 6
range 0 7
config SCB3_MI0_SLOT7
int "Slot 7 slave interface id"
default 7
range 0 7
config SCB3_MI0_SLOT8
int "Slot 8 slave interface id"
default 0
range 0 7
config SCB3_MI0_SLOT9
int "Slot 9 slave interface id"
default 1
range 0 7
config SCB3_MI0_SLOT10
int "Slot 10 slave interface id"
default 2
range 0 7
config SCB3_MI0_SLOT11
int "Slot 11 slave interface id"
default 3
range 0 7
config SCB3_MI0_SLOT12
int "Slot 12 slave interface id"
default 4
range 0 7
config SCB3_MI0_SLOT13
int "Slot 13 slave interface id"
default 5
range 0 7
config SCB3_MI0_SLOT14
int "Slot 14 slave interface id"
default 6
range 0 7
config SCB3_MI0_SLOT15
int "Slot 15 slave interface id"
default 7
range 0 7
endif # SCB3_MI0
menuconfig SCB4_MI0
bool "SCB4 Master Interface 0"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
MDA21 -- 0
MDA22 -- 1
MDA23 -- 2
MDA24 -- 3
MDA25 -- 4
MDA26 -- 5
MDA27 -- 6
MDA28 -- 7
if SCB4_MI0
config SCB4_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 7
config SCB4_MI0_SLOT1
int "Slot 1 slave interface id"
default 1
range 0 7
config SCB4_MI0_SLOT2
int "Slot 2 slave interface id"
default 2
range 0 7
config SCB4_MI0_SLOT3
int "Slot 3 slave interface id"
default 3
range 0 7
config SCB4_MI0_SLOT4
int "Slot 4 slave interface id"
default 4
range 0 7
config SCB4_MI0_SLOT5
int "Slot 5 slave interface id"
default 5
range 0 7
config SCB4_MI0_SLOT6
int "Slot 6 slave interface id"
default 6
range 0 7
config SCB4_MI0_SLOT7
int "Slot 7 slave interface id"
default 7
range 0 7
config SCB4_MI0_SLOT8
int "Slot 8 slave interface id"
default 0
range 0 7
config SCB4_MI0_SLOT9
int "Slot 9 slave interface id"
default 1
range 0 7
config SCB4_MI0_SLOT10
int "Slot 10 slave interface id"
default 2
range 0 7
config SCB4_MI0_SLOT11
int "Slot 11 slave interface id"
default 3
range 0 7
config SCB4_MI0_SLOT12
int "Slot 12 slave interface id"
default 4
range 0 7
config SCB4_MI0_SLOT13
int "Slot 13 slave interface id"
default 5
range 0 7
config SCB4_MI0_SLOT14
int "Slot 14 slave interface id"
default 6
range 0 7
config SCB4_MI0_SLOT15
int "Slot 15 slave interface id"
default 7
range 0 7
endif # SCB4_MI0
menuconfig SCB5_MI0
bool "SCB5 Master Interface 0"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
PPI0 MDA29 -- 0
PPI0 MDA30 -- 1
PPI2 MDA31 -- 2
PPI2 MDA32 -- 3
if SCB5_MI0
config SCB5_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 3
config SCB5_MI0_SLOT1
int "Slot 1 slave interface id"
default 1
range 0 3
config SCB5_MI0_SLOT2
int "Slot 2 slave interface id"
default 2
range 0 3
config SCB5_MI0_SLOT3
int "Slot 3 slave interface id"
default 3
range 0 3
config SCB5_MI0_SLOT4
int "Slot 4 slave interface id"
default 0
range 0 3
config SCB5_MI0_SLOT5
int "Slot 5 slave interface id"
default 1
range 0 3
config SCB5_MI0_SLOT6
int "Slot 6 slave interface id"
default 2
range 0 3
config SCB5_MI0_SLOT7
int "Slot 7 slave interface id"
default 3
range 0 3
endif # SCB5_MI0
menuconfig SCB6_MI0
bool "SCB6 Master Interface 0"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
PPI1 MDA33 -- 0
PPI1 MDA34 -- 1
if SCB6_MI0
config SCB6_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 1
config SCB6_MI0_SLOT1
int "Slot 1 slave interface id"
default 1
range 0 1
config SCB6_MI0_SLOT2
int "Slot 2 slave interface id"
default 0
range 0 1
config SCB6_MI0_SLOT3
int "Slot 3 slave interface id"
default 1
range 0 1
endif # SCB6_MI0
menuconfig SCB7_MI0
bool "SCB7 Master Interface 0"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
PIXC0 -- 0
PIXC1 -- 1
PIXC2 -- 2
if SCB7_MI0
config SCB7_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 2
config SCB7_MI0_SLOT1
int "Slot 1 slave interface id"
default 1
range 0 2
config SCB7_MI0_SLOT2
int "Slot 2 slave interface id"
default 2
range 0 2
config SCB7_MI0_SLOT3
int "Slot 3 slave interface id"
default 0
range 0 2
config SCB7_MI0_SLOT4
int "Slot 4 slave interface id"
default 1
range 0 2
config SCB7_MI0_SLOT5
int "Slot 5 slave interface id"
default 2
range 0 2
endif # SCB7_MI0
menuconfig SCB8_MI0
bool "SCB8 Master Interface 0"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
PVP CPDOB -- 0
PVP CPDOC -- 1
PVP CPCO -- 2
PVP CPCI -- 3
if SCB8_MI0
config SCB8_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 3
config SCB8_MI0_SLOT1
int "Slot 1 slave interface id"
default 1
range 0 3
config SCB8_MI0_SLOT2
int "Slot 2 slave interface id"
default 2
range 0 3
config SCB8_MI0_SLOT3
int "Slot 3 slave interface id"
default 3
range 0 3
config SCB8_MI0_SLOT4
int "Slot 4 slave interface id"
default 0
range 0 3
config SCB8_MI0_SLOT5
int "Slot 5 slave interface id"
default 1
range 0 3
config SCB8_MI0_SLOT6
int "Slot 6 slave interface id"
default 2
range 0 3
config SCB8_MI0_SLOT7
int "Slot 7 slave interface id"
default 3
range 0 3
endif # SCB8_MI0
menuconfig SCB9_MI0
bool "SCB9 Master Interface 0"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
PVP MPDO -- 0
PVP MPDI -- 1
PVP MPCO -- 2
PVP MPCI -- 3
PVP CPDOA -- 4
if SCB9_MI0
config SCB9_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 4
config SCB9_MI0_SLOT1
int "Slot 1 slave interface id"
default 1
range 0 4
config SCB9_MI0_SLOT2
int "Slot 2 slave interface id"
default 2
range 0 4
config SCB9_MI0_SLOT3
int "Slot 3 slave interface id"
default 3
range 0 4
config SCB9_MI0_SLOT4
int "Slot 4 slave interface id"
default 4
range 0 4
config SCB9_MI0_SLOT5
int "Slot 5 slave interface id"
default 0
range 0 4
config SCB9_MI0_SLOT6
int "Slot 6 slave interface id"
default 1
range 0 4
config SCB9_MI0_SLOT7
int "Slot 7 slave interface id"
default 2
range 0 4
config SCB9_MI0_SLOT8
int "Slot 8 slave interface id"
default 3
range 0 4
config SCB9_MI0_SLOT9
int "Slot 9 slave interface id"
default 4
range 0 4
endif # SCB9_MI0
endmenu endmenu
endif endif
...@@ -4,3 +4,4 @@ ...@@ -4,3 +4,4 @@
obj-y := dma.o clock.o ints-priority.o obj-y := dma.o clock.o ints-priority.o
obj-$(CONFIG_PM) += pm.o dpm.o obj-$(CONFIG_PM) += pm.o dpm.o
obj-$(CONFIG_SCB_PRIORITY) += scb.o
...@@ -104,6 +104,7 @@ static struct platform_device bfin_rotary_device = { ...@@ -104,6 +104,7 @@ static struct platform_device bfin_rotary_device = {
#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE) #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
#include <linux/stmmac.h> #include <linux/stmmac.h>
#include <linux/phy.h>
static unsigned short pins[] = P_RMII0; static unsigned short pins[] = P_RMII0;
...@@ -111,11 +112,26 @@ static struct stmmac_mdio_bus_data phy_private_data = { ...@@ -111,11 +112,26 @@ static struct stmmac_mdio_bus_data phy_private_data = {
.phy_mask = 1, .phy_mask = 1,
}; };
static struct stmmac_dma_cfg eth_dma_cfg = {
.pbl = 2,
};
int stmmac_ptp_clk_init(struct platform_device *pdev)
{
bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
return 0;
}
static struct plat_stmmacenet_data eth_private_data = { static struct plat_stmmacenet_data eth_private_data = {
.has_gmac = 1,
.bus_id = 0, .bus_id = 0,
.enh_desc = 1, .enh_desc = 1,
.phy_addr = 1, .phy_addr = 1,
.mdio_bus_data = &phy_private_data, .mdio_bus_data = &phy_private_data,
.dma_cfg = &eth_dma_cfg,
.force_thresh_dma_mode = 1,
.interface = PHY_INTERFACE_MODE_RMII,
.init = stmmac_ptp_clk_init,
}; };
static struct platform_device bfin_eth_device = { static struct platform_device bfin_eth_device = {
...@@ -1107,6 +1123,81 @@ static struct bfin_display_config bfin_display_data = { ...@@ -1107,6 +1123,81 @@ static struct bfin_display_config bfin_display_data = {
}; };
#endif #endif
#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
#include <media/adv7343.h>
static struct v4l2_output adv7343_outputs[] = {
{
.index = 0,
.name = "Composite",
.type = V4L2_OUTPUT_TYPE_ANALOG,
.std = V4L2_STD_ALL,
.capabilities = V4L2_OUT_CAP_STD,
},
{
.index = 1,
.name = "S-Video",
.type = V4L2_OUTPUT_TYPE_ANALOG,
.std = V4L2_STD_ALL,
.capabilities = V4L2_OUT_CAP_STD,
},
{
.index = 2,
.name = "Component",
.type = V4L2_OUTPUT_TYPE_ANALOG,
.std = V4L2_STD_ALL,
.capabilities = V4L2_OUT_CAP_STD,
},
};
static struct disp_route adv7343_routes[] = {
{
.output = ADV7343_COMPOSITE_ID,
},
{
.output = ADV7343_SVIDEO_ID,
},
{
.output = ADV7343_COMPONENT_ID,
},
};
static struct adv7343_platform_data adv7343_data = {
.mode_config = {
.sleep_mode = false,
.pll_control = false,
.dac_1 = true,
.dac_2 = true,
.dac_3 = true,
.dac_4 = true,
.dac_5 = true,
.dac_6 = true,
},
.sd_config = {
.sd_dac_out1 = false,
.sd_dac_out2 = false,
},
};
static struct bfin_display_config bfin_display_data = {
.card_name = "BF609",
.outputs = adv7343_outputs,
.num_outputs = ARRAY_SIZE(adv7343_outputs),
.routes = adv7343_routes,
.i2c_adapter_id = 0,
.board_info = {
.type = "adv7343",
.addr = 0x2b,
.platform_data = (void *)&adv7343_data,
},
.ppi_info = &ppi_info_disp,
.ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
| EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
| EPPI_CTL_NON656 | EPPI_CTL_DIR),
};
#endif
static struct platform_device bfin_display_device = { static struct platform_device bfin_display_device = {
.name = "bfin_display", .name = "bfin_display",
.dev = { .dev = {
......
...@@ -220,6 +220,12 @@ unsigned long sys_clk_get_rate(struct clk *clk) ...@@ -220,6 +220,12 @@ unsigned long sys_clk_get_rate(struct clk *clk)
} }
} }
unsigned long dummy_get_rate(struct clk *clk)
{
clk->parent->rate = clk_get_rate(clk->parent);
return clk->parent->rate;
}
unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate) unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
{ {
unsigned long max_rate; unsigned long max_rate;
...@@ -283,6 +289,10 @@ static struct clk_ops sys_clk_ops = { ...@@ -283,6 +289,10 @@ static struct clk_ops sys_clk_ops = {
.round_rate = sys_clk_round_rate, .round_rate = sys_clk_round_rate,
}; };
static struct clk_ops dummy_clk_ops = {
.get_rate = dummy_get_rate,
};
static struct clk sys_clkin = { static struct clk sys_clkin = {
.name = "SYS_CLKIN", .name = "SYS_CLKIN",
.rate = CONFIG_CLKIN_HZ, .rate = CONFIG_CLKIN_HZ,
...@@ -364,6 +374,12 @@ static struct clk oclk = { ...@@ -364,6 +374,12 @@ static struct clk oclk = {
.parent = &pll_clk, .parent = &pll_clk,
}; };
static struct clk ethclk = {
.name = "stmmaceth",
.parent = &sclk0,
.ops = &dummy_clk_ops,
};
static struct clk_lookup bf609_clks[] = { static struct clk_lookup bf609_clks[] = {
CLK(sys_clkin, NULL, "SYS_CLKIN"), CLK(sys_clkin, NULL, "SYS_CLKIN"),
CLK(pll_clk, NULL, "PLLCLK"), CLK(pll_clk, NULL, "PLLCLK"),
...@@ -375,6 +391,7 @@ static struct clk_lookup bf609_clks[] = { ...@@ -375,6 +391,7 @@ static struct clk_lookup bf609_clks[] = {
CLK(sclk1, NULL, "SCLK1"), CLK(sclk1, NULL, "SCLK1"),
CLK(dclk, NULL, "DCLK"), CLK(dclk, NULL, "DCLK"),
CLK(oclk, NULL, "OCLK"), CLK(oclk, NULL, "OCLK"),
CLK(ethclk, NULL, "stmmaceth"),
}; };
int __init clk_init(void) int __init clk_init(void)
......
...@@ -839,6 +839,16 @@ ...@@ -839,6 +839,16 @@
#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */ #define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */ #define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
/* ==================================================
Pads Controller Registers
================================================== */
/* =========================
PADS0
========================= */
#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */
#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */
#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */
/* ========================= /* =========================
PINT Registers PINT Registers
......
/*
* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
*
* Copyright 2012 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <asm/blackfin.h>
#include <asm/scb.h>
struct scb_mi_prio scb_data[] = {
#ifdef CONFIG_SCB0_MI0
{ REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
CONFIG_SCB0_MI0_SLOT0,
CONFIG_SCB0_MI0_SLOT1,
CONFIG_SCB0_MI0_SLOT2,
CONFIG_SCB0_MI0_SLOT3,
CONFIG_SCB0_MI0_SLOT4,
CONFIG_SCB0_MI0_SLOT5,
CONFIG_SCB0_MI0_SLOT6,
CONFIG_SCB0_MI0_SLOT7,
CONFIG_SCB0_MI0_SLOT8,
CONFIG_SCB0_MI0_SLOT9,
CONFIG_SCB0_MI0_SLOT10,
CONFIG_SCB0_MI0_SLOT11,
CONFIG_SCB0_MI0_SLOT12,
CONFIG_SCB0_MI0_SLOT13,
CONFIG_SCB0_MI0_SLOT14,
CONFIG_SCB0_MI0_SLOT15,
CONFIG_SCB0_MI0_SLOT16,
CONFIG_SCB0_MI0_SLOT17,
CONFIG_SCB0_MI0_SLOT18,
CONFIG_SCB0_MI0_SLOT19,
CONFIG_SCB0_MI0_SLOT20,
CONFIG_SCB0_MI0_SLOT21,
CONFIG_SCB0_MI0_SLOT22,
CONFIG_SCB0_MI0_SLOT23,
CONFIG_SCB0_MI0_SLOT24,
CONFIG_SCB0_MI0_SLOT25,
CONFIG_SCB0_MI0_SLOT26,
CONFIG_SCB0_MI0_SLOT27,
CONFIG_SCB0_MI0_SLOT28,
CONFIG_SCB0_MI0_SLOT29,
CONFIG_SCB0_MI0_SLOT30,
CONFIG_SCB0_MI0_SLOT31
},
},
#endif
#ifdef CONFIG_SCB0_MI1
{ REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
CONFIG_SCB0_MI1_SLOT0,
CONFIG_SCB0_MI1_SLOT1,
CONFIG_SCB0_MI1_SLOT2,
CONFIG_SCB0_MI1_SLOT3,
CONFIG_SCB0_MI1_SLOT4,
CONFIG_SCB0_MI1_SLOT5,
CONFIG_SCB0_MI1_SLOT6,
CONFIG_SCB0_MI1_SLOT7,
CONFIG_SCB0_MI1_SLOT8,
CONFIG_SCB0_MI1_SLOT9,
CONFIG_SCB0_MI1_SLOT10,
CONFIG_SCB0_MI1_SLOT11,
CONFIG_SCB0_MI1_SLOT12,
CONFIG_SCB0_MI1_SLOT13,
CONFIG_SCB0_MI1_SLOT14,
CONFIG_SCB0_MI1_SLOT15,
CONFIG_SCB0_MI1_SLOT16,
CONFIG_SCB0_MI1_SLOT17,
CONFIG_SCB0_MI1_SLOT18,
CONFIG_SCB0_MI1_SLOT19,
CONFIG_SCB0_MI1_SLOT20,
CONFIG_SCB0_MI1_SLOT21,
CONFIG_SCB0_MI1_SLOT22,
CONFIG_SCB0_MI1_SLOT23,
CONFIG_SCB0_MI1_SLOT24,
CONFIG_SCB0_MI1_SLOT25,
CONFIG_SCB0_MI1_SLOT26,
CONFIG_SCB0_MI1_SLOT27,
CONFIG_SCB0_MI1_SLOT28,
CONFIG_SCB0_MI1_SLOT29,
CONFIG_SCB0_MI1_SLOT30,
CONFIG_SCB0_MI1_SLOT31
},
},
#endif
#ifdef CONFIG_SCB0_MI2
{ REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
CONFIG_SCB0_MI2_SLOT0,
CONFIG_SCB0_MI2_SLOT1,
CONFIG_SCB0_MI2_SLOT2,
CONFIG_SCB0_MI2_SLOT3,
CONFIG_SCB0_MI2_SLOT4,
CONFIG_SCB0_MI2_SLOT5,
CONFIG_SCB0_MI2_SLOT6,
CONFIG_SCB0_MI2_SLOT7,
CONFIG_SCB0_MI2_SLOT8,
CONFIG_SCB0_MI2_SLOT9,
CONFIG_SCB0_MI2_SLOT10,
CONFIG_SCB0_MI2_SLOT11,
CONFIG_SCB0_MI2_SLOT12,
CONFIG_SCB0_MI2_SLOT13,
CONFIG_SCB0_MI2_SLOT14,
CONFIG_SCB0_MI2_SLOT15,
CONFIG_SCB0_MI2_SLOT16,
CONFIG_SCB0_MI2_SLOT17,
CONFIG_SCB0_MI2_SLOT18,
CONFIG_SCB0_MI2_SLOT19,
CONFIG_SCB0_MI2_SLOT20,
CONFIG_SCB0_MI2_SLOT21,
CONFIG_SCB0_MI2_SLOT22,
CONFIG_SCB0_MI2_SLOT23,
CONFIG_SCB0_MI2_SLOT24,
CONFIG_SCB0_MI2_SLOT25,
CONFIG_SCB0_MI2_SLOT26,
CONFIG_SCB0_MI2_SLOT27,
CONFIG_SCB0_MI2_SLOT28,
CONFIG_SCB0_MI2_SLOT29,
CONFIG_SCB0_MI2_SLOT30,
CONFIG_SCB0_MI2_SLOT31
},
},
#endif
#ifdef CONFIG_SCB0_MI3
{ REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
CONFIG_SCB0_MI3_SLOT0,
CONFIG_SCB0_MI3_SLOT1,
CONFIG_SCB0_MI3_SLOT2,
CONFIG_SCB0_MI3_SLOT3,
CONFIG_SCB0_MI3_SLOT4,
CONFIG_SCB0_MI3_SLOT5,
CONFIG_SCB0_MI3_SLOT6,
CONFIG_SCB0_MI3_SLOT7,
CONFIG_SCB0_MI3_SLOT8,
CONFIG_SCB0_MI3_SLOT9,
CONFIG_SCB0_MI3_SLOT10,
CONFIG_SCB0_MI3_SLOT11,
CONFIG_SCB0_MI3_SLOT12,
CONFIG_SCB0_MI3_SLOT13,
CONFIG_SCB0_MI3_SLOT14,
CONFIG_SCB0_MI3_SLOT15,
CONFIG_SCB0_MI3_SLOT16,
CONFIG_SCB0_MI3_SLOT17,
CONFIG_SCB0_MI3_SLOT18,
CONFIG_SCB0_MI3_SLOT19,
CONFIG_SCB0_MI3_SLOT20,
CONFIG_SCB0_MI3_SLOT21,
CONFIG_SCB0_MI3_SLOT22,
CONFIG_SCB0_MI3_SLOT23,
CONFIG_SCB0_MI3_SLOT24,
CONFIG_SCB0_MI3_SLOT25,
CONFIG_SCB0_MI3_SLOT26,
CONFIG_SCB0_MI3_SLOT27,
CONFIG_SCB0_MI3_SLOT28,
CONFIG_SCB0_MI3_SLOT29,
CONFIG_SCB0_MI3_SLOT30,
CONFIG_SCB0_MI3_SLOT31
},
},
#endif
#ifdef CONFIG_SCB0_MI4
{ REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
CONFIG_SCB0_MI4_SLOT0,
CONFIG_SCB0_MI4_SLOT1,
CONFIG_SCB0_MI4_SLOT2,
CONFIG_SCB0_MI4_SLOT3,
CONFIG_SCB0_MI4_SLOT4,
CONFIG_SCB0_MI4_SLOT5,
CONFIG_SCB0_MI4_SLOT6,
CONFIG_SCB0_MI4_SLOT7,
CONFIG_SCB0_MI4_SLOT8,
CONFIG_SCB0_MI4_SLOT9,
CONFIG_SCB0_MI4_SLOT10,
CONFIG_SCB0_MI4_SLOT11,
CONFIG_SCB0_MI4_SLOT12,
CONFIG_SCB0_MI4_SLOT13,
CONFIG_SCB0_MI4_SLOT14,
CONFIG_SCB0_MI4_SLOT15,
CONFIG_SCB0_MI4_SLOT16,
CONFIG_SCB0_MI4_SLOT17,
CONFIG_SCB0_MI4_SLOT18,
CONFIG_SCB0_MI4_SLOT19,
CONFIG_SCB0_MI4_SLOT20,
CONFIG_SCB0_MI4_SLOT21,
CONFIG_SCB0_MI4_SLOT22,
CONFIG_SCB0_MI4_SLOT23,
CONFIG_SCB0_MI4_SLOT24,
CONFIG_SCB0_MI4_SLOT25,
CONFIG_SCB0_MI4_SLOT26,
CONFIG_SCB0_MI4_SLOT27,
CONFIG_SCB0_MI4_SLOT28,
CONFIG_SCB0_MI4_SLOT29,
CONFIG_SCB0_MI4_SLOT30,
CONFIG_SCB0_MI4_SLOT31
},
},
#endif
#ifdef CONFIG_SCB0_MI5
{ REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
CONFIG_SCB0_MI5_SLOT0,
CONFIG_SCB0_MI5_SLOT1,
CONFIG_SCB0_MI5_SLOT2,
CONFIG_SCB0_MI5_SLOT3,
CONFIG_SCB0_MI5_SLOT4,
CONFIG_SCB0_MI5_SLOT5,
CONFIG_SCB0_MI5_SLOT6,
CONFIG_SCB0_MI5_SLOT7,
CONFIG_SCB0_MI5_SLOT8,
CONFIG_SCB0_MI5_SLOT9,
CONFIG_SCB0_MI5_SLOT10,
CONFIG_SCB0_MI5_SLOT11,
CONFIG_SCB0_MI5_SLOT12,
CONFIG_SCB0_MI5_SLOT13,
CONFIG_SCB0_MI5_SLOT14,
CONFIG_SCB0_MI5_SLOT15
},
},
#endif
#ifdef CONFIG_SCB1_MI0
{ REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, {
CONFIG_SCB1_MI0_SLOT0,
CONFIG_SCB1_MI0_SLOT1,
CONFIG_SCB1_MI0_SLOT2,
CONFIG_SCB1_MI0_SLOT3,
CONFIG_SCB1_MI0_SLOT4,
CONFIG_SCB1_MI0_SLOT5,
CONFIG_SCB1_MI0_SLOT6,
CONFIG_SCB1_MI0_SLOT7,
CONFIG_SCB1_MI0_SLOT8,
CONFIG_SCB1_MI0_SLOT9,
CONFIG_SCB1_MI0_SLOT10,
CONFIG_SCB1_MI0_SLOT11,
CONFIG_SCB1_MI0_SLOT12,
CONFIG_SCB1_MI0_SLOT13,
CONFIG_SCB1_MI0_SLOT14,
CONFIG_SCB1_MI0_SLOT15,
CONFIG_SCB1_MI0_SLOT16,
CONFIG_SCB1_MI0_SLOT17,
CONFIG_SCB1_MI0_SLOT18,
CONFIG_SCB1_MI0_SLOT19
},
},
#endif
#ifdef CONFIG_SCB2_MI0
{ REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, {
CONFIG_SCB2_MI0_SLOT0,
CONFIG_SCB2_MI0_SLOT1,
CONFIG_SCB2_MI0_SLOT2,
CONFIG_SCB2_MI0_SLOT3,
CONFIG_SCB2_MI0_SLOT4,
CONFIG_SCB2_MI0_SLOT5,
CONFIG_SCB2_MI0_SLOT6,
CONFIG_SCB2_MI0_SLOT7,
CONFIG_SCB2_MI0_SLOT8,
CONFIG_SCB2_MI0_SLOT9
},
},
#endif
#ifdef CONFIG_SCB3_MI0
{ REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, {
CONFIG_SCB3_MI0_SLOT0,
CONFIG_SCB3_MI0_SLOT1,
CONFIG_SCB3_MI0_SLOT2,
CONFIG_SCB3_MI0_SLOT3,
CONFIG_SCB3_MI0_SLOT4,
CONFIG_SCB3_MI0_SLOT5,
CONFIG_SCB3_MI0_SLOT6,
CONFIG_SCB3_MI0_SLOT7,
CONFIG_SCB3_MI0_SLOT8,
CONFIG_SCB3_MI0_SLOT9,
CONFIG_SCB3_MI0_SLOT10,
CONFIG_SCB3_MI0_SLOT11,
CONFIG_SCB3_MI0_SLOT12,
CONFIG_SCB3_MI0_SLOT13,
CONFIG_SCB3_MI0_SLOT14,
CONFIG_SCB3_MI0_SLOT15
},
},
#endif
#ifdef CONFIG_SCB4_MI0
{ REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, {
CONFIG_SCB4_MI0_SLOT0,
CONFIG_SCB4_MI0_SLOT1,
CONFIG_SCB4_MI0_SLOT2,
CONFIG_SCB4_MI0_SLOT3,
CONFIG_SCB4_MI0_SLOT4,
CONFIG_SCB4_MI0_SLOT5,
CONFIG_SCB4_MI0_SLOT6,
CONFIG_SCB4_MI0_SLOT7,
CONFIG_SCB4_MI0_SLOT8,
CONFIG_SCB4_MI0_SLOT9,
CONFIG_SCB4_MI0_SLOT10,
CONFIG_SCB4_MI0_SLOT11,
CONFIG_SCB4_MI0_SLOT12,
CONFIG_SCB4_MI0_SLOT13,
CONFIG_SCB4_MI0_SLOT14,
CONFIG_SCB4_MI0_SLOT15
},
},
#endif
#ifdef CONFIG_SCB5_MI0
{ REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, {
CONFIG_SCB5_MI0_SLOT0,
CONFIG_SCB5_MI0_SLOT1,
CONFIG_SCB5_MI0_SLOT2,
CONFIG_SCB5_MI0_SLOT3,
CONFIG_SCB5_MI0_SLOT4,
CONFIG_SCB5_MI0_SLOT5,
CONFIG_SCB5_MI0_SLOT6,
CONFIG_SCB5_MI0_SLOT7
},
},
#endif
#ifdef CONFIG_SCB6_MI0
{ REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, {
CONFIG_SCB6_MI0_SLOT0,
CONFIG_SCB6_MI0_SLOT1,
CONFIG_SCB6_MI0_SLOT2,
CONFIG_SCB6_MI0_SLOT3
},
},
#endif
#ifdef CONFIG_SCB7_MI0
{ REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, {
CONFIG_SCB7_MI0_SLOT0,
CONFIG_SCB7_MI0_SLOT1,
CONFIG_SCB7_MI0_SLOT2,
CONFIG_SCB7_MI0_SLOT3,
CONFIG_SCB7_MI0_SLOT4,
CONFIG_SCB7_MI0_SLOT5
},
},
#endif
#ifdef CONFIG_SCB8_MI0
{ REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, {
CONFIG_SCB8_MI0_SLOT0,
CONFIG_SCB8_MI0_SLOT1,
CONFIG_SCB8_MI0_SLOT2,
CONFIG_SCB8_MI0_SLOT3,
CONFIG_SCB8_MI0_SLOT4,
CONFIG_SCB8_MI0_SLOT5,
CONFIG_SCB8_MI0_SLOT6,
CONFIG_SCB8_MI0_SLOT7
},
},
#endif
#ifdef CONFIG_SCB9_MI0
{ REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, {
CONFIG_SCB9_MI0_SLOT0,
CONFIG_SCB9_MI0_SLOT1,
CONFIG_SCB9_MI0_SLOT2,
CONFIG_SCB9_MI0_SLOT3,
CONFIG_SCB9_MI0_SLOT4,
CONFIG_SCB9_MI0_SLOT5,
CONFIG_SCB9_MI0_SLOT6,
CONFIG_SCB9_MI0_SLOT7,
CONFIG_SCB9_MI0_SLOT8,
CONFIG_SCB9_MI0_SLOT9
},
},
#endif
{ 0, }
};
...@@ -10,6 +10,7 @@ obj-$(CONFIG_PM) += pm.o ...@@ -10,6 +10,7 @@ obj-$(CONFIG_PM) += pm.o
ifneq ($(CONFIG_BF60x),y) ifneq ($(CONFIG_BF60x),y)
obj-$(CONFIG_PM) += dpmc_modes.o obj-$(CONFIG_PM) += dpmc_modes.o
endif endif
obj-$(CONFIG_SCB_PRIORITY) += scb-init.o
obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
/*
* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
*
* Copyright 2012 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <asm/scb.h>
__attribute__((l1_text))
inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots,
unsigned char *scb_mi_prio)
{
unsigned int i;
for (i = 0; i < slots; ++i)
bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]);
}
__attribute__((l1_text))
inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots,
unsigned char *scb_mi_prio)
{
unsigned int i;
for (i = 0; i < slots; ++i) {
bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i);
scb_mi_prio[i] = bfin_read32(scb_mi_arbw);
}
}
__attribute__((l1_text))
void init_scb(void)
{
unsigned int i, j;
unsigned char scb_tmp_prio[32];
pr_info("Init System Crossbar\n");
for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) {
scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio);
pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr);
scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio);
for (j = 0; j < scb_data[i].scb_mi_slots; ++j)
pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]);
}
}
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