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Commit 95c8bc36 authored by Antti Seppälä's avatar Antti Seppälä Committed by Felipe Balbi
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usb: dwc2: Use platform endianness when accessing registers 

This patch switches calls to readl/writel to their
dwc2_readl/dwc2_writel equivalents which preserve platform endianness.

This patch is necessary to access dwc2 registers correctly on big-endian
systems such as the mips based SoCs made by Lantiq. Then dwc2 can be
used to replace ifx-hcd driver for Lantiq platforms found e.g. in
OpenWrt.

The patch was autogenerated with the following commands:
$EDITOR core.h
sed -i "s/\<readl\>/dwc2_readl/g" *.c hcd.h hw.h
sed -i "s/\<writel\>/dwc2_writel/g" *.c hcd.h hw.h

Some files were then hand-edited to fix checkpatch.pl warnings about
too long lines.
Signed-off-by: default avatarAntti Seppälä <a.seppala@gmail.com>
Signed-off-by: default avatarVincent Pelletier <plr.vincent@gmail.com>
Signed-off-by: default avatarJohn Youn <johnyoun@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent bba787a8
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Showing with 591 additions and 572 deletions
drivers/usb/dwc2/core.c
View file @ 95c8bc36
...@@ -73,13 +73,13 @@ static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) ...@@ -73,13 +73,13 @@ static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
/* Backup Host regs */ /* Backup Host regs */
hr = &hsotg->hr_backup; hr = &hsotg->hr_backup;
hr->hcfg = readl(hsotg->regs + HCFG); hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
hr->haintmsk = readl(hsotg->regs + HAINTMSK); hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
for (i = 0; i < hsotg->core_params->host_channels; ++i) for (i = 0; i < hsotg->core_params->host_channels; ++i)
hr->hcintmsk[i] = readl(hsotg->regs + HCINTMSK(i)); hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
hr->hprt0 = readl(hsotg->regs + HPRT0); hr->hprt0 = dwc2_readl(hsotg->regs + HPRT0);
hr->hfir = readl(hsotg->regs + HFIR); hr->hfir = dwc2_readl(hsotg->regs + HFIR);
hr->valid = true; hr->valid = true;
return 0; return 0;
...@@ -108,14 +108,14 @@ static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) ...@@ -108,14 +108,14 @@ static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
} }
hr->valid = false; hr->valid = false;
writel(hr->hcfg, hsotg->regs + HCFG); dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
writel(hr->haintmsk, hsotg->regs + HAINTMSK); dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
for (i = 0; i < hsotg->core_params->host_channels; ++i) for (i = 0; i < hsotg->core_params->host_channels; ++i)
writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
writel(hr->hprt0, hsotg->regs + HPRT0); dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
writel(hr->hfir, hsotg->regs + HFIR); dwc2_writel(hr->hfir, hsotg->regs + HFIR);
return 0; return 0;
} }
...@@ -146,15 +146,15 @@ static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) ...@@ -146,15 +146,15 @@ static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
/* Backup dev regs */ /* Backup dev regs */
dr = &hsotg->dr_backup; dr = &hsotg->dr_backup;
dr->dcfg = readl(hsotg->regs + DCFG); dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
dr->dctl = readl(hsotg->regs + DCTL); dr->dctl = dwc2_readl(hsotg->regs + DCTL);
dr->daintmsk = readl(hsotg->regs + DAINTMSK); dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
dr->diepmsk = readl(hsotg->regs + DIEPMSK); dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
dr->doepmsk = readl(hsotg->regs + DOEPMSK); dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
for (i = 0; i < hsotg->num_of_eps; i++) { for (i = 0; i < hsotg->num_of_eps; i++) {
/* Backup IN EPs */ /* Backup IN EPs */
dr->diepctl[i] = readl(hsotg->regs + DIEPCTL(i)); dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
/* Ensure DATA PID is correctly configured */ /* Ensure DATA PID is correctly configured */
if (dr->diepctl[i] & DXEPCTL_DPID) if (dr->diepctl[i] & DXEPCTL_DPID)
...@@ -162,11 +162,11 @@ static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) ...@@ -162,11 +162,11 @@ static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
else else
dr->diepctl[i] |= DXEPCTL_SETD0PID; dr->diepctl[i] |= DXEPCTL_SETD0PID;
dr->dieptsiz[i] = readl(hsotg->regs + DIEPTSIZ(i)); dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
dr->diepdma[i] = readl(hsotg->regs + DIEPDMA(i)); dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
/* Backup OUT EPs */ /* Backup OUT EPs */
dr->doepctl[i] = readl(hsotg->regs + DOEPCTL(i)); dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
/* Ensure DATA PID is correctly configured */ /* Ensure DATA PID is correctly configured */
if (dr->doepctl[i] & DXEPCTL_DPID) if (dr->doepctl[i] & DXEPCTL_DPID)
...@@ -174,8 +174,8 @@ static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) ...@@ -174,8 +174,8 @@ static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
else else
dr->doepctl[i] |= DXEPCTL_SETD0PID; dr->doepctl[i] |= DXEPCTL_SETD0PID;
dr->doeptsiz[i] = readl(hsotg->regs + DOEPTSIZ(i)); dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
dr->doepdma[i] = readl(hsotg->regs + DOEPDMA(i)); dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
} }
dr->valid = true; dr->valid = true;
return 0; return 0;
...@@ -205,28 +205,28 @@ static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) ...@@ -205,28 +205,28 @@ static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
} }
dr->valid = false; dr->valid = false;
writel(dr->dcfg, hsotg->regs + DCFG); dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
writel(dr->dctl, hsotg->regs + DCTL); dwc2_writel(dr->dctl, hsotg->regs + DCTL);
writel(dr->daintmsk, hsotg->regs + DAINTMSK); dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
writel(dr->diepmsk, hsotg->regs + DIEPMSK); dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
writel(dr->doepmsk, hsotg->regs + DOEPMSK); dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
for (i = 0; i < hsotg->num_of_eps; i++) { for (i = 0; i < hsotg->num_of_eps; i++) {
/* Restore IN EPs */ /* Restore IN EPs */
writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
/* Restore OUT EPs */ /* Restore OUT EPs */
writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
} }
/* Set the Power-On Programming done bit */ /* Set the Power-On Programming done bit */
dctl = readl(hsotg->regs + DCTL); dctl = dwc2_readl(hsotg->regs + DCTL);
dctl |= DCTL_PWRONPRGDONE; dctl |= DCTL_PWRONPRGDONE;
writel(dctl, hsotg->regs + DCTL); dwc2_writel(dctl, hsotg->regs + DCTL);
return 0; return 0;
} }
...@@ -253,16 +253,16 @@ static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) ...@@ -253,16 +253,16 @@ static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
/* Backup global regs */ /* Backup global regs */
gr = &hsotg->gr_backup; gr = &hsotg->gr_backup;
gr->gotgctl = readl(hsotg->regs + GOTGCTL); gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
gr->gintmsk = readl(hsotg->regs + GINTMSK); gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gr->gahbcfg = readl(hsotg->regs + GAHBCFG); gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
gr->gusbcfg = readl(hsotg->regs + GUSBCFG); gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
gr->grxfsiz = readl(hsotg->regs + GRXFSIZ); gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
gr->gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ); gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
gr->hptxfsiz = readl(hsotg->regs + HPTXFSIZ); gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
gr->gdfifocfg = readl(hsotg->regs + GDFIFOCFG); gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
for (i = 0; i < MAX_EPS_CHANNELS; i++) for (i = 0; i < MAX_EPS_CHANNELS; i++)
gr->dtxfsiz[i] = readl(hsotg->regs + DPTXFSIZN(i)); gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
gr->valid = true; gr->valid = true;
return 0; return 0;
...@@ -291,17 +291,17 @@ static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) ...@@ -291,17 +291,17 @@ static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
} }
gr->valid = false; gr->valid = false;
writel(0xffffffff, hsotg->regs + GINTSTS); dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
writel(gr->gotgctl, hsotg->regs + GOTGCTL); dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
writel(gr->gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
writel(gr->gusbcfg, hsotg->regs + GUSBCFG); dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
writel(gr->gahbcfg, hsotg->regs + GAHBCFG); dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
writel(gr->grxfsiz, hsotg->regs + GRXFSIZ); dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ); dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ); dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG); dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
for (i = 0; i < MAX_EPS_CHANNELS; i++) for (i = 0; i < MAX_EPS_CHANNELS; i++)
writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
return 0; return 0;
} }
...@@ -320,17 +320,17 @@ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore) ...@@ -320,17 +320,17 @@ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
if (!hsotg->core_params->hibernation) if (!hsotg->core_params->hibernation)
return -ENOTSUPP; return -ENOTSUPP;
pcgcctl = readl(hsotg->regs + PCGCTL); pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
pcgcctl &= ~PCGCTL_STOPPCLK; pcgcctl &= ~PCGCTL_STOPPCLK;
writel(pcgcctl, hsotg->regs + PCGCTL); dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
pcgcctl = readl(hsotg->regs + PCGCTL); pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
pcgcctl &= ~PCGCTL_PWRCLMP; pcgcctl &= ~PCGCTL_PWRCLMP;
writel(pcgcctl, hsotg->regs + PCGCTL); dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
pcgcctl = readl(hsotg->regs + PCGCTL); pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
pcgcctl &= ~PCGCTL_RSTPDWNMODULE; pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
writel(pcgcctl, hsotg->regs + PCGCTL); dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
udelay(100); udelay(100);
if (restore) { if (restore) {
...@@ -398,18 +398,18 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg) ...@@ -398,18 +398,18 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
} }
/* Put the controller in low power state */ /* Put the controller in low power state */
pcgcctl = readl(hsotg->regs + PCGCTL); pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
pcgcctl |= PCGCTL_PWRCLMP; pcgcctl |= PCGCTL_PWRCLMP;
writel(pcgcctl, hsotg->regs + PCGCTL); dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
ndelay(20); ndelay(20);
pcgcctl |= PCGCTL_RSTPDWNMODULE; pcgcctl |= PCGCTL_RSTPDWNMODULE;
writel(pcgcctl, hsotg->regs + PCGCTL); dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
ndelay(20); ndelay(20);
pcgcctl |= PCGCTL_STOPPCLK; pcgcctl |= PCGCTL_STOPPCLK;
writel(pcgcctl, hsotg->regs + PCGCTL); dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
return ret; return ret;
} }
...@@ -425,10 +425,10 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) ...@@ -425,10 +425,10 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
u32 intmsk; u32 intmsk;
/* Clear any pending OTG Interrupts */ /* Clear any pending OTG Interrupts */
writel(0xffffffff, hsotg->regs + GOTGINT); dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
/* Clear any pending interrupts */ /* Clear any pending interrupts */
writel(0xffffffff, hsotg->regs + GINTSTS); dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
/* Enable the interrupts in the GINTMSK */ /* Enable the interrupts in the GINTMSK */
intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
...@@ -441,7 +441,7 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) ...@@ -441,7 +441,7 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
GINTSTS_SESSREQINT; GINTSTS_SESSREQINT;
writel(intmsk, hsotg->regs + GINTMSK); dwc2_writel(intmsk, hsotg->regs + GINTMSK);
} }
/* /*
...@@ -464,10 +464,10 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) ...@@ -464,10 +464,10 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
} }
dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
hcfg = readl(hsotg->regs + HCFG); hcfg = dwc2_readl(hsotg->regs + HCFG);
hcfg &= ~HCFG_FSLSPCLKSEL_MASK; hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
writel(hcfg, hsotg->regs + HCFG); dwc2_writel(hcfg, hsotg->regs + HCFG);
} }
/* /*
...@@ -485,7 +485,7 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg) ...@@ -485,7 +485,7 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
/* Wait for AHB master IDLE state */ /* Wait for AHB master IDLE state */
do { do {
usleep_range(20000, 40000); usleep_range(20000, 40000);
greset = readl(hsotg->regs + GRSTCTL); greset = dwc2_readl(hsotg->regs + GRSTCTL);
if (++count > 50) { if (++count > 50) {
dev_warn(hsotg->dev, dev_warn(hsotg->dev,
"%s() HANG! AHB Idle GRSTCTL=%0x\n", "%s() HANG! AHB Idle GRSTCTL=%0x\n",
...@@ -497,10 +497,10 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg) ...@@ -497,10 +497,10 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
/* Core Soft Reset */ /* Core Soft Reset */
count = 0; count = 0;
greset |= GRSTCTL_CSFTRST; greset |= GRSTCTL_CSFTRST;
writel(greset, hsotg->regs + GRSTCTL); dwc2_writel(greset, hsotg->regs + GRSTCTL);
do { do {
usleep_range(20000, 40000); usleep_range(20000, 40000);
greset = readl(hsotg->regs + GRSTCTL); greset = dwc2_readl(hsotg->regs + GRSTCTL);
if (++count > 50) { if (++count > 50) {
dev_warn(hsotg->dev, dev_warn(hsotg->dev,
"%s() HANG! Soft Reset GRSTCTL=%0x\n", "%s() HANG! Soft Reset GRSTCTL=%0x\n",
...@@ -510,20 +510,20 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg) ...@@ -510,20 +510,20 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
} while (greset & GRSTCTL_CSFTRST); } while (greset & GRSTCTL_CSFTRST);
if (hsotg->dr_mode == USB_DR_MODE_HOST) { if (hsotg->dr_mode == USB_DR_MODE_HOST) {
gusbcfg = readl(hsotg->regs + GUSBCFG); gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
gusbcfg &= ~GUSBCFG_FORCEDEVMODE; gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
gusbcfg |= GUSBCFG_FORCEHOSTMODE; gusbcfg |= GUSBCFG_FORCEHOSTMODE;
writel(gusbcfg, hsotg->regs + GUSBCFG); dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
} else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
gusbcfg = readl(hsotg->regs + GUSBCFG); gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
gusbcfg |= GUSBCFG_FORCEDEVMODE; gusbcfg |= GUSBCFG_FORCEDEVMODE;
writel(gusbcfg, hsotg->regs + GUSBCFG); dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
} else if (hsotg->dr_mode == USB_DR_MODE_OTG) { } else if (hsotg->dr_mode == USB_DR_MODE_OTG) {
gusbcfg = readl(hsotg->regs + GUSBCFG); gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
gusbcfg &= ~GUSBCFG_FORCEDEVMODE; gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
writel(gusbcfg, hsotg->regs + GUSBCFG); dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
} }
/* /*
...@@ -546,9 +546,9 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) ...@@ -546,9 +546,9 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
*/ */
if (select_phy) { if (select_phy) {
dev_dbg(hsotg->dev, "FS PHY selected\n"); dev_dbg(hsotg->dev, "FS PHY selected\n");
usbcfg = readl(hsotg->regs + GUSBCFG); usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
usbcfg |= GUSBCFG_PHYSEL; usbcfg |= GUSBCFG_PHYSEL;
writel(usbcfg, hsotg->regs + GUSBCFG); dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
/* Reset after a PHY select */ /* Reset after a PHY select */
retval = dwc2_core_reset(hsotg); retval = dwc2_core_reset(hsotg);
...@@ -571,18 +571,18 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) ...@@ -571,18 +571,18 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
/* Program GUSBCFG.OtgUtmiFsSel to I2C */ /* Program GUSBCFG.OtgUtmiFsSel to I2C */
usbcfg = readl(hsotg->regs + GUSBCFG); usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
writel(usbcfg, hsotg->regs + GUSBCFG); dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
/* Program GI2CCTL.I2CEn */ /* Program GI2CCTL.I2CEn */
i2cctl = readl(hsotg->regs + GI2CCTL); i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
i2cctl &= ~GI2CCTL_I2CEN; i2cctl &= ~GI2CCTL_I2CEN;
writel(i2cctl, hsotg->regs + GI2CCTL); dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
i2cctl |= GI2CCTL_I2CEN; i2cctl |= GI2CCTL_I2CEN;
writel(i2cctl, hsotg->regs + GI2CCTL); dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
} }
return retval; return retval;
...@@ -596,7 +596,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) ...@@ -596,7 +596,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
if (!select_phy) if (!select_phy)
return 0; return 0;
usbcfg = readl(hsotg->regs + GUSBCFG); usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
/* /*
* HS PHY parameters. These parameters are preserved during soft reset * HS PHY parameters. These parameters are preserved during soft reset
...@@ -624,7 +624,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) ...@@ -624,7 +624,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
break; break;
} }
writel(usbcfg, hsotg->regs + GUSBCFG); dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
/* Reset after setting the PHY parameters */ /* Reset after setting the PHY parameters */
retval = dwc2_core_reset(hsotg); retval = dwc2_core_reset(hsotg);
...@@ -659,15 +659,15 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) ...@@ -659,15 +659,15 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
hsotg->core_params->ulpi_fs_ls > 0) { hsotg->core_params->ulpi_fs_ls > 0) {
dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
usbcfg = readl(hsotg->regs + GUSBCFG); usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
usbcfg |= GUSBCFG_ULPI_FS_LS; usbcfg |= GUSBCFG_ULPI_FS_LS;
usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
writel(usbcfg, hsotg->regs + GUSBCFG); dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
} else { } else {
usbcfg = readl(hsotg->regs + GUSBCFG); usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
usbcfg &= ~GUSBCFG_ULPI_FS_LS; usbcfg &= ~GUSBCFG_ULPI_FS_LS;
usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
writel(usbcfg, hsotg->regs + GUSBCFG); dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
} }
return retval; return retval;
...@@ -675,7 +675,7 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) ...@@ -675,7 +675,7 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
{ {
u32 ahbcfg = readl(hsotg->regs + GAHBCFG); u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
switch (hsotg->hw_params.arch) { switch (hsotg->hw_params.arch) {
case GHWCFG2_EXT_DMA_ARCH: case GHWCFG2_EXT_DMA_ARCH:
...@@ -714,7 +714,7 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) ...@@ -714,7 +714,7 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
if (hsotg->core_params->dma_enable > 0) if (hsotg->core_params->dma_enable > 0)
ahbcfg |= GAHBCFG_DMA_EN; ahbcfg |= GAHBCFG_DMA_EN;
writel(ahbcfg, hsotg->regs + GAHBCFG); dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
return 0; return 0;
} }
...@@ -723,7 +723,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) ...@@ -723,7 +723,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
{ {
u32 usbcfg; u32 usbcfg;
usbcfg = readl(hsotg->regs + GUSBCFG); usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
switch (hsotg->hw_params.op_mode) { switch (hsotg->hw_params.op_mode) {
...@@ -751,7 +751,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) ...@@ -751,7 +751,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
break; break;
} }
writel(usbcfg, hsotg->regs + GUSBCFG); dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
} }
/** /**
...@@ -769,7 +769,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq) ...@@ -769,7 +769,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq)
dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
usbcfg = readl(hsotg->regs + GUSBCFG); usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
/* Set ULPI External VBUS bit if needed */ /* Set ULPI External VBUS bit if needed */
usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
...@@ -782,7 +782,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq) ...@@ -782,7 +782,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq)
if (hsotg->core_params->ts_dline > 0) if (hsotg->core_params->ts_dline > 0)
usbcfg |= GUSBCFG_TERMSELDLPULSE; usbcfg |= GUSBCFG_TERMSELDLPULSE;
writel(usbcfg, hsotg->regs + GUSBCFG); dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
/* Reset the Controller */ /* Reset the Controller */
retval = dwc2_core_reset(hsotg); retval = dwc2_core_reset(hsotg);
...@@ -808,11 +808,11 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq) ...@@ -808,11 +808,11 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq)
dwc2_gusbcfg_init(hsotg); dwc2_gusbcfg_init(hsotg);
/* Program the GOTGCTL register */ /* Program the GOTGCTL register */
otgctl = readl(hsotg->regs + GOTGCTL); otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
otgctl &= ~GOTGCTL_OTGVER; otgctl &= ~GOTGCTL_OTGVER;
if (hsotg->core_params->otg_ver > 0) if (hsotg->core_params->otg_ver > 0)
otgctl |= GOTGCTL_OTGVER; otgctl |= GOTGCTL_OTGVER;
writel(otgctl, hsotg->regs + GOTGCTL); dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
/* Clear the SRP success bit for FS-I2c */ /* Clear the SRP success bit for FS-I2c */
...@@ -848,16 +848,16 @@ void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) ...@@ -848,16 +848,16 @@ void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, "%s()\n", __func__); dev_dbg(hsotg->dev, "%s()\n", __func__);
/* Disable all interrupts */ /* Disable all interrupts */
writel(0, hsotg->regs + GINTMSK); dwc2_writel(0, hsotg->regs + GINTMSK);
writel(0, hsotg->regs + HAINTMSK); dwc2_writel(0, hsotg->regs + HAINTMSK);
/* Enable the common interrupts */ /* Enable the common interrupts */
dwc2_enable_common_interrupts(hsotg); dwc2_enable_common_interrupts(hsotg);
/* Enable host mode interrupts without disturbing common interrupts */ /* Enable host mode interrupts without disturbing common interrupts */
intmsk = readl(hsotg->regs + GINTMSK); intmsk = dwc2_readl(hsotg->regs + GINTMSK);
intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
writel(intmsk, hsotg->regs + GINTMSK); dwc2_writel(intmsk, hsotg->regs + GINTMSK);
} }
/** /**
...@@ -867,12 +867,12 @@ void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) ...@@ -867,12 +867,12 @@ void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
*/ */
void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
{ {
u32 intmsk = readl(hsotg->regs + GINTMSK); u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
/* Disable host mode interrupts without disturbing common interrupts */ /* Disable host mode interrupts without disturbing common interrupts */
intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
writel(intmsk, hsotg->regs + GINTMSK); dwc2_writel(intmsk, hsotg->regs + GINTMSK);
} }
/* /*
...@@ -952,36 +952,37 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) ...@@ -952,36 +952,37 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
dwc2_calculate_dynamic_fifo(hsotg); dwc2_calculate_dynamic_fifo(hsotg);
/* Rx FIFO */ /* Rx FIFO */
grxfsiz = readl(hsotg->regs + GRXFSIZ); grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
grxfsiz &= ~GRXFSIZ_DEPTH_MASK; grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
grxfsiz |= params->host_rx_fifo_size << grxfsiz |= params->host_rx_fifo_size <<
GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
writel(grxfsiz, hsotg->regs + GRXFSIZ); dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ)); dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
dwc2_readl(hsotg->regs + GRXFSIZ));
/* Non-periodic Tx FIFO */ /* Non-periodic Tx FIFO */
dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
readl(hsotg->regs + GNPTXFSIZ)); dwc2_readl(hsotg->regs + GNPTXFSIZ));
nptxfsiz = params->host_nperio_tx_fifo_size << nptxfsiz = params->host_nperio_tx_fifo_size <<
FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
nptxfsiz |= params->host_rx_fifo_size << nptxfsiz |= params->host_rx_fifo_size <<
FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
readl(hsotg->regs + GNPTXFSIZ)); dwc2_readl(hsotg->regs + GNPTXFSIZ));
/* Periodic Tx FIFO */ /* Periodic Tx FIFO */
dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
readl(hsotg->regs + HPTXFSIZ)); dwc2_readl(hsotg->regs + HPTXFSIZ));
hptxfsiz = params->host_perio_tx_fifo_size << hptxfsiz = params->host_perio_tx_fifo_size <<
FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
hptxfsiz |= (params->host_rx_fifo_size + hptxfsiz |= (params->host_rx_fifo_size +
params->host_nperio_tx_fifo_size) << params->host_nperio_tx_fifo_size) <<
FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
writel(hptxfsiz, hsotg->regs + HPTXFSIZ); dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
readl(hsotg->regs + HPTXFSIZ)); dwc2_readl(hsotg->regs + HPTXFSIZ));
if (hsotg->core_params->en_multiple_tx_fifo > 0 && if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
...@@ -989,14 +990,14 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) ...@@ -989,14 +990,14 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
* Global DFIFOCFG calculation for Host mode - * Global DFIFOCFG calculation for Host mode -
* include RxFIFO, NPTXFIFO and HPTXFIFO * include RxFIFO, NPTXFIFO and HPTXFIFO
*/ */
dfifocfg = readl(hsotg->regs + GDFIFOCFG); dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
dfifocfg |= (params->host_rx_fifo_size + dfifocfg |= (params->host_rx_fifo_size +
params->host_nperio_tx_fifo_size + params->host_nperio_tx_fifo_size +
params->host_perio_tx_fifo_size) << params->host_perio_tx_fifo_size) <<
GDFIFOCFG_EPINFOBASE_SHIFT & GDFIFOCFG_EPINFOBASE_SHIFT &
GDFIFOCFG_EPINFOBASE_MASK; GDFIFOCFG_EPINFOBASE_MASK;
writel(dfifocfg, hsotg->regs + GDFIFOCFG); dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
} }
} }
...@@ -1017,14 +1018,14 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg) ...@@ -1017,14 +1018,14 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
/* Restart the Phy Clock */ /* Restart the Phy Clock */
writel(0, hsotg->regs + PCGCTL); dwc2_writel(0, hsotg->regs + PCGCTL);
/* Initialize Host Configuration Register */ /* Initialize Host Configuration Register */
dwc2_init_fs_ls_pclk_sel(hsotg); dwc2_init_fs_ls_pclk_sel(hsotg);
if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
hcfg = readl(hsotg->regs + HCFG); hcfg = dwc2_readl(hsotg->regs + HCFG);
hcfg |= HCFG_FSLSSUPP; hcfg |= HCFG_FSLSSUPP;
writel(hcfg, hsotg->regs + HCFG); dwc2_writel(hcfg, hsotg->regs + HCFG);
} }
/* /*
...@@ -1033,9 +1034,9 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg) ...@@ -1033,9 +1034,9 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
* and its value must not be changed during runtime. * and its value must not be changed during runtime.
*/ */
if (hsotg->core_params->reload_ctl > 0) { if (hsotg->core_params->reload_ctl > 0) {
hfir = readl(hsotg->regs + HFIR); hfir = dwc2_readl(hsotg->regs + HFIR);
hfir |= HFIR_RLDCTRL; hfir |= HFIR_RLDCTRL;
writel(hfir, hsotg->regs + HFIR); dwc2_writel(hfir, hsotg->regs + HFIR);
} }
if (hsotg->core_params->dma_desc_enable > 0) { if (hsotg->core_params->dma_desc_enable > 0) {
...@@ -1051,9 +1052,9 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg) ...@@ -1051,9 +1052,9 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
"falling back to buffer DMA mode.\n"); "falling back to buffer DMA mode.\n");
hsotg->core_params->dma_desc_enable = 0; hsotg->core_params->dma_desc_enable = 0;
} else { } else {
hcfg = readl(hsotg->regs + HCFG); hcfg = dwc2_readl(hsotg->regs + HCFG);
hcfg |= HCFG_DESCDMA; hcfg |= HCFG_DESCDMA;
writel(hcfg, hsotg->regs + HCFG); dwc2_writel(hcfg, hsotg->regs + HCFG);
} }
} }
...@@ -1062,18 +1063,18 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg) ...@@ -1062,18 +1063,18 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
/* TODO - check this */ /* TODO - check this */
/* Clear Host Set HNP Enable in the OTG Control Register */ /* Clear Host Set HNP Enable in the OTG Control Register */
otgctl = readl(hsotg->regs + GOTGCTL); otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
otgctl &= ~GOTGCTL_HSTSETHNPEN; otgctl &= ~GOTGCTL_HSTSETHNPEN;
writel(otgctl, hsotg->regs + GOTGCTL); dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
/* Make sure the FIFOs are flushed */ /* Make sure the FIFOs are flushed */
dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
dwc2_flush_rx_fifo(hsotg); dwc2_flush_rx_fifo(hsotg);
/* Clear Host Set HNP Enable in the OTG Control Register */ /* Clear Host Set HNP Enable in the OTG Control Register */
otgctl = readl(hsotg->regs + GOTGCTL); otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
otgctl &= ~GOTGCTL_HSTSETHNPEN; otgctl &= ~GOTGCTL_HSTSETHNPEN;
writel(otgctl, hsotg->regs + GOTGCTL); dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
if (hsotg->core_params->dma_desc_enable <= 0) { if (hsotg->core_params->dma_desc_enable <= 0) {
int num_channels, i; int num_channels, i;
...@@ -1082,25 +1083,25 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg) ...@@ -1082,25 +1083,25 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
/* Flush out any leftover queued requests */ /* Flush out any leftover queued requests */
num_channels = hsotg->core_params->host_channels; num_channels = hsotg->core_params->host_channels;
for (i = 0; i < num_channels; i++) { for (i = 0; i < num_channels; i++) {
hcchar = readl(hsotg->regs + HCCHAR(i)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
hcchar &= ~HCCHAR_CHENA; hcchar &= ~HCCHAR_CHENA;
hcchar |= HCCHAR_CHDIS; hcchar |= HCCHAR_CHDIS;
hcchar &= ~HCCHAR_EPDIR; hcchar &= ~HCCHAR_EPDIR;
writel(hcchar, hsotg->regs + HCCHAR(i)); dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
} }
/* Halt all channels to put them into a known state */ /* Halt all channels to put them into a known state */
for (i = 0; i < num_channels; i++) { for (i = 0; i < num_channels; i++) {
int count = 0; int count = 0;
hcchar = readl(hsotg->regs + HCCHAR(i)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
hcchar &= ~HCCHAR_EPDIR; hcchar &= ~HCCHAR_EPDIR;
writel(hcchar, hsotg->regs + HCCHAR(i)); dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
dev_dbg(hsotg->dev, "%s: Halt channel %d\n", dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
__func__, i); __func__, i);
do { do {
hcchar = readl(hsotg->regs + HCCHAR(i)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
if (++count > 1000) { if (++count > 1000) {
dev_err(hsotg->dev, dev_err(hsotg->dev,
"Unable to clear enable on channel %d\n", "Unable to clear enable on channel %d\n",
...@@ -1121,7 +1122,7 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg) ...@@ -1121,7 +1122,7 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
!!(hprt0 & HPRT0_PWR)); !!(hprt0 & HPRT0_PWR));
if (!(hprt0 & HPRT0_PWR)) { if (!(hprt0 & HPRT0_PWR)) {
hprt0 |= HPRT0_PWR; hprt0 |= HPRT0_PWR;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
} }
} }
...@@ -1201,7 +1202,7 @@ static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, ...@@ -1201,7 +1202,7 @@ static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
break; break;
} }
writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
if (dbg_hc(chan)) if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
} }
...@@ -1238,7 +1239,7 @@ static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, ...@@ -1238,7 +1239,7 @@ static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
} }
} }
writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
if (dbg_hc(chan)) if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
} }
...@@ -1259,16 +1260,16 @@ static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, ...@@ -1259,16 +1260,16 @@ static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
} }
/* Enable the top level host channel interrupt */ /* Enable the top level host channel interrupt */
intmsk = readl(hsotg->regs + HAINTMSK); intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
intmsk |= 1 << chan->hc_num; intmsk |= 1 << chan->hc_num;
writel(intmsk, hsotg->regs + HAINTMSK); dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
if (dbg_hc(chan)) if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
/* Make sure host channel interrupts are enabled */ /* Make sure host channel interrupts are enabled */
intmsk = readl(hsotg->regs + GINTMSK); intmsk = dwc2_readl(hsotg->regs + GINTMSK);
intmsk |= GINTSTS_HCHINT; intmsk |= GINTSTS_HCHINT;
writel(intmsk, hsotg->regs + GINTMSK); dwc2_writel(intmsk, hsotg->regs + GINTMSK);
if (dbg_hc(chan)) if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
} }
...@@ -1297,7 +1298,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) ...@@ -1297,7 +1298,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
/* Clear old interrupt conditions for this host channel */ /* Clear old interrupt conditions for this host channel */
hcintmsk = 0xffffffff; hcintmsk = 0xffffffff;
hcintmsk &= ~HCINTMSK_RESERVED14_31; hcintmsk &= ~HCINTMSK_RESERVED14_31;
writel(hcintmsk, hsotg->regs + HCINT(hc_num)); dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
/* Enable channel interrupts required for this transfer */ /* Enable channel interrupts required for this transfer */
dwc2_hc_enable_ints(hsotg, chan); dwc2_hc_enable_ints(hsotg, chan);
...@@ -1314,7 +1315,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) ...@@ -1314,7 +1315,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
hcchar |= HCCHAR_LSPDDEV; hcchar |= HCCHAR_LSPDDEV;
hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
writel(hcchar, hsotg->regs + HCCHAR(hc_num)); dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
if (dbg_hc(chan)) { if (dbg_hc(chan)) {
dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
hc_num, hcchar); hc_num, hcchar);
...@@ -1368,7 +1369,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) ...@@ -1368,7 +1369,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
} }
} }
writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
} }
/** /**
...@@ -1420,14 +1421,14 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, ...@@ -1420,14 +1421,14 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
u32 hcintmsk = HCINTMSK_CHHLTD; u32 hcintmsk = HCINTMSK_CHHLTD;
dev_vdbg(hsotg->dev, "dequeue/error\n"); dev_vdbg(hsotg->dev, "dequeue/error\n");
writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
/* /*
* Make sure no other interrupts besides halt are currently * Make sure no other interrupts besides halt are currently
* pending. Handling another interrupt could cause a crash due * pending. Handling another interrupt could cause a crash due
* to the QTD and QH state. * to the QTD and QH state.
*/ */
writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
/* /*
* Make sure the halt status is set to URB_DEQUEUE or AHB_ERR * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
...@@ -1436,7 +1437,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, ...@@ -1436,7 +1437,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
*/ */
chan->halt_status = halt_status; chan->halt_status = halt_status;
hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
if (!(hcchar & HCCHAR_CHENA)) { if (!(hcchar & HCCHAR_CHENA)) {
/* /*
* The channel is either already halted or it hasn't * The channel is either already halted or it hasn't
...@@ -1464,7 +1465,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, ...@@ -1464,7 +1465,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
return; return;
} }
hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
/* No need to set the bit in DDMA for disabling the channel */ /* No need to set the bit in DDMA for disabling the channel */
/* TODO check it everywhere channel is disabled */ /* TODO check it everywhere channel is disabled */
...@@ -1487,7 +1488,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, ...@@ -1487,7 +1488,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
chan->ep_type == USB_ENDPOINT_XFER_BULK) { chan->ep_type == USB_ENDPOINT_XFER_BULK) {
dev_vdbg(hsotg->dev, "control/bulk\n"); dev_vdbg(hsotg->dev, "control/bulk\n");
nptxsts = readl(hsotg->regs + GNPTXSTS); nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
dev_vdbg(hsotg->dev, "Disabling channel\n"); dev_vdbg(hsotg->dev, "Disabling channel\n");
hcchar &= ~HCCHAR_CHENA; hcchar &= ~HCCHAR_CHENA;
...@@ -1495,7 +1496,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, ...@@ -1495,7 +1496,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
} else { } else {
if (dbg_perio()) if (dbg_perio())
dev_vdbg(hsotg->dev, "isoc/intr\n"); dev_vdbg(hsotg->dev, "isoc/intr\n");
hptxsts = readl(hsotg->regs + HPTXSTS); hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
hsotg->queuing_high_bandwidth) { hsotg->queuing_high_bandwidth) {
if (dbg_perio()) if (dbg_perio())
...@@ -1508,7 +1509,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, ...@@ -1508,7 +1509,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
dev_vdbg(hsotg->dev, "DMA enabled\n"); dev_vdbg(hsotg->dev, "DMA enabled\n");
} }
writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
chan->halt_status = halt_status; chan->halt_status = halt_status;
if (hcchar & HCCHAR_CHENA) { if (hcchar & HCCHAR_CHENA) {
...@@ -1555,10 +1556,10 @@ void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) ...@@ -1555,10 +1556,10 @@ void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
* Clear channel interrupt enables and any unhandled channel interrupt * Clear channel interrupt enables and any unhandled channel interrupt
* conditions * conditions
*/ */
writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
hcintmsk = 0xffffffff; hcintmsk = 0xffffffff;
hcintmsk &= ~HCINTMSK_RESERVED14_31; hcintmsk &= ~HCINTMSK_RESERVED14_31;
writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
} }
/** /**
...@@ -1644,13 +1645,13 @@ static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, ...@@ -1644,13 +1645,13 @@ static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
if (((unsigned long)data_buf & 0x3) == 0) { if (((unsigned long)data_buf & 0x3) == 0) {
/* xfer_buf is DWORD aligned */ /* xfer_buf is DWORD aligned */
for (i = 0; i < dword_count; i++, data_buf++) for (i = 0; i < dword_count; i++, data_buf++)
writel(*data_buf, data_fifo); dwc2_writel(*data_buf, data_fifo);
} else { } else {
/* xfer_buf is not DWORD aligned */ /* xfer_buf is not DWORD aligned */
for (i = 0; i < dword_count; i++, data_buf++) { for (i = 0; i < dword_count; i++, data_buf++) {
u32 data = data_buf[0] | data_buf[1] << 8 | u32 data = data_buf[0] | data_buf[1] << 8 |
data_buf[2] << 16 | data_buf[3] << 24; data_buf[2] << 16 | data_buf[3] << 24;
writel(data, data_fifo); dwc2_writel(data, data_fifo);
} }
} }
...@@ -1803,7 +1804,7 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, ...@@ -1803,7 +1804,7 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
TSIZ_SC_MC_PID_MASK; TSIZ_SC_MC_PID_MASK;
writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
if (dbg_hc(chan)) { if (dbg_hc(chan)) {
dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
hctsiz, chan->hc_num); hctsiz, chan->hc_num);
...@@ -1831,7 +1832,7 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, ...@@ -1831,7 +1832,7 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
} else { } else {
dma_addr = chan->xfer_dma; dma_addr = chan->xfer_dma;
} }
writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
if (dbg_hc(chan)) if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
(unsigned long)dma_addr, chan->hc_num); (unsigned long)dma_addr, chan->hc_num);
...@@ -1839,13 +1840,13 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, ...@@ -1839,13 +1840,13 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
/* Start the split */ /* Start the split */
if (chan->do_split) { if (chan->do_split) {
u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
hcsplt |= HCSPLT_SPLTENA; hcsplt |= HCSPLT_SPLTENA;
writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
} }
hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
hcchar &= ~HCCHAR_MULTICNT_MASK; hcchar &= ~HCCHAR_MULTICNT_MASK;
hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
HCCHAR_MULTICNT_MASK; HCCHAR_MULTICNT_MASK;
...@@ -1865,7 +1866,7 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, ...@@ -1865,7 +1866,7 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
(hcchar & HCCHAR_MULTICNT_MASK) >> (hcchar & HCCHAR_MULTICNT_MASK) >>
HCCHAR_MULTICNT_SHIFT); HCCHAR_MULTICNT_SHIFT);
writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
if (dbg_hc(chan)) if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
chan->hc_num); chan->hc_num);
...@@ -1924,18 +1925,18 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, ...@@ -1924,18 +1925,18 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
} }
writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK; hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK;
/* Always start from first descriptor */ /* Always start from first descriptor */
hc_dma &= ~HCDMA_CTD_MASK; hc_dma &= ~HCDMA_CTD_MASK;
writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num)); dwc2_writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
if (dbg_hc(chan)) if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n", dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n",
hc_dma, chan->hc_num); hc_dma, chan->hc_num);
hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
hcchar &= ~HCCHAR_MULTICNT_MASK; hcchar &= ~HCCHAR_MULTICNT_MASK;
hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
HCCHAR_MULTICNT_MASK; HCCHAR_MULTICNT_MASK;
...@@ -1954,7 +1955,7 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, ...@@ -1954,7 +1955,7 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
(hcchar & HCCHAR_MULTICNT_MASK) >> (hcchar & HCCHAR_MULTICNT_MASK) >>
HCCHAR_MULTICNT_SHIFT); HCCHAR_MULTICNT_SHIFT);
writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
if (dbg_hc(chan)) if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
chan->hc_num); chan->hc_num);
...@@ -2011,7 +2012,7 @@ int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, ...@@ -2011,7 +2012,7 @@ int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
* transfer completes, the extra requests for the channel will * transfer completes, the extra requests for the channel will
* be flushed. * be flushed.
*/ */
u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
hcchar |= HCCHAR_CHENA; hcchar |= HCCHAR_CHENA;
...@@ -2019,7 +2020,7 @@ int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, ...@@ -2019,7 +2020,7 @@ int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
if (dbg_hc(chan)) if (dbg_hc(chan))
dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
hcchar); hcchar);
writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
chan->requests++; chan->requests++;
return 1; return 1;
} }
...@@ -2029,7 +2030,7 @@ int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, ...@@ -2029,7 +2030,7 @@ int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
if (chan->xfer_count < chan->xfer_len) { if (chan->xfer_count < chan->xfer_len) {
if (chan->ep_type == USB_ENDPOINT_XFER_INT || if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
chan->ep_type == USB_ENDPOINT_XFER_ISOC) { chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
u32 hcchar = readl(hsotg->regs + u32 hcchar = dwc2_readl(hsotg->regs +
HCCHAR(chan->hc_num)); HCCHAR(chan->hc_num));
dwc2_hc_set_even_odd_frame(hsotg, chan, dwc2_hc_set_even_odd_frame(hsotg, chan,
...@@ -2066,12 +2067,12 @@ void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) ...@@ -2066,12 +2067,12 @@ void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
hctsiz = TSIZ_DOPNG; hctsiz = TSIZ_DOPNG;
hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
hcchar |= HCCHAR_CHENA; hcchar |= HCCHAR_CHENA;
hcchar &= ~HCCHAR_CHDIS; hcchar &= ~HCCHAR_CHDIS;
writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
} }
/** /**
...@@ -2090,8 +2091,8 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) ...@@ -2090,8 +2091,8 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
u32 hprt0; u32 hprt0;
int clock = 60; /* default value */ int clock = 60; /* default value */
usbcfg = readl(hsotg->regs + GUSBCFG); usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
hprt0 = readl(hsotg->regs + HPRT0); hprt0 = dwc2_readl(hsotg->regs + HPRT0);
if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
!(usbcfg & GUSBCFG_PHYIF16)) !(usbcfg & GUSBCFG_PHYIF16))
...@@ -2147,7 +2148,7 @@ void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) ...@@ -2147,7 +2148,7 @@ void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
for (i = 0; i < word_count; i++, data_buf++) for (i = 0; i < word_count; i++, data_buf++)
*data_buf = readl(fifo); *data_buf = dwc2_readl(fifo);
} }
/** /**
...@@ -2167,56 +2168,56 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) ...@@ -2167,56 +2168,56 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, "Host Global Registers\n"); dev_dbg(hsotg->dev, "Host Global Registers\n");
addr = hsotg->regs + HCFG; addr = hsotg->regs + HCFG;
dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HFIR; addr = hsotg->regs + HFIR;
dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HFNUM; addr = hsotg->regs + HFNUM;
dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HPTXSTS; addr = hsotg->regs + HPTXSTS;
dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HAINT; addr = hsotg->regs + HAINT;
dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HAINTMSK; addr = hsotg->regs + HAINTMSK;
dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
if (hsotg->core_params->dma_desc_enable > 0) { if (hsotg->core_params->dma_desc_enable > 0) {
addr = hsotg->regs + HFLBADDR; addr = hsotg->regs + HFLBADDR;
dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
} }
addr = hsotg->regs + HPRT0; addr = hsotg->regs + HPRT0;
dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
for (i = 0; i < hsotg->core_params->host_channels; i++) { for (i = 0; i < hsotg->core_params->host_channels; i++) {
dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
addr = hsotg->regs + HCCHAR(i); addr = hsotg->regs + HCCHAR(i);
dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HCSPLT(i); addr = hsotg->regs + HCSPLT(i);
dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HCINT(i); addr = hsotg->regs + HCINT(i);
dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HCINTMSK(i); addr = hsotg->regs + HCINTMSK(i);
dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HCTSIZ(i); addr = hsotg->regs + HCTSIZ(i);
dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HCDMA(i); addr = hsotg->regs + HCDMA(i);
dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
if (hsotg->core_params->dma_desc_enable > 0) { if (hsotg->core_params->dma_desc_enable > 0) {
addr = hsotg->regs + HCDMAB(i); addr = hsotg->regs + HCDMAB(i);
dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
} }
} }
#endif #endif
...@@ -2238,80 +2239,80 @@ void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) ...@@ -2238,80 +2239,80 @@ void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, "Core Global Registers\n"); dev_dbg(hsotg->dev, "Core Global Registers\n");
addr = hsotg->regs + GOTGCTL; addr = hsotg->regs + GOTGCTL;
dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GOTGINT; addr = hsotg->regs + GOTGINT;
dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GAHBCFG; addr = hsotg->regs + GAHBCFG;
dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GUSBCFG; addr = hsotg->regs + GUSBCFG;
dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GRSTCTL; addr = hsotg->regs + GRSTCTL;
dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GINTSTS; addr = hsotg->regs + GINTSTS;
dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GINTMSK; addr = hsotg->regs + GINTMSK;
dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GRXSTSR; addr = hsotg->regs + GRXSTSR;
dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GRXFSIZ; addr = hsotg->regs + GRXFSIZ;
dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GNPTXFSIZ; addr = hsotg->regs + GNPTXFSIZ;
dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GNPTXSTS; addr = hsotg->regs + GNPTXSTS;
dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GI2CCTL; addr = hsotg->regs + GI2CCTL;
dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GPVNDCTL; addr = hsotg->regs + GPVNDCTL;
dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GGPIO; addr = hsotg->regs + GGPIO;
dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GUID; addr = hsotg->regs + GUID;
dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GSNPSID; addr = hsotg->regs + GSNPSID;
dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GHWCFG1; addr = hsotg->regs + GHWCFG1;
dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GHWCFG2; addr = hsotg->regs + GHWCFG2;
dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GHWCFG3; addr = hsotg->regs + GHWCFG3;
dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GHWCFG4; addr = hsotg->regs + GHWCFG4;
dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GLPMCFG; addr = hsotg->regs + GLPMCFG;
dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GPWRDN; addr = hsotg->regs + GPWRDN;
dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + GDFIFOCFG; addr = hsotg->regs + GDFIFOCFG;
dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + HPTXFSIZ; addr = hsotg->regs + HPTXFSIZ;
dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
addr = hsotg->regs + PCGCTL; addr = hsotg->regs + PCGCTL;
dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
(unsigned long)addr, readl(addr)); (unsigned long)addr, dwc2_readl(addr));
#endif #endif
} }
...@@ -2330,15 +2331,15 @@ void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) ...@@ -2330,15 +2331,15 @@ void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
greset = GRSTCTL_TXFFLSH; greset = GRSTCTL_TXFFLSH;
greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
writel(greset, hsotg->regs + GRSTCTL); dwc2_writel(greset, hsotg->regs + GRSTCTL);
do { do {
greset = readl(hsotg->regs + GRSTCTL); greset = dwc2_readl(hsotg->regs + GRSTCTL);
if (++count > 10000) { if (++count > 10000) {
dev_warn(hsotg->dev, dev_warn(hsotg->dev,
"%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
__func__, greset, __func__, greset,
readl(hsotg->regs + GNPTXSTS)); dwc2_readl(hsotg->regs + GNPTXSTS));
break; break;
} }
udelay(1); udelay(1);
...@@ -2361,10 +2362,10 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) ...@@ -2361,10 +2362,10 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
dev_vdbg(hsotg->dev, "%s()\n", __func__); dev_vdbg(hsotg->dev, "%s()\n", __func__);
greset = GRSTCTL_RXFFLSH; greset = GRSTCTL_RXFFLSH;
writel(greset, hsotg->regs + GRSTCTL); dwc2_writel(greset, hsotg->regs + GRSTCTL);
do { do {
greset = readl(hsotg->regs + GRSTCTL); greset = dwc2_readl(hsotg->regs + GRSTCTL);
if (++count > 10000) { if (++count > 10000) {
dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
__func__, greset); __func__, greset);
...@@ -3062,7 +3063,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) ...@@ -3062,7 +3063,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
* 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
* as in "OTG version 2.xx" or "OTG version 3.xx". * as in "OTG version 2.xx" or "OTG version 3.xx".
*/ */
hw->snpsid = readl(hsotg->regs + GSNPSID); hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
if ((hw->snpsid & 0xfffff000) != 0x4f542000 && if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
(hw->snpsid & 0xfffff000) != 0x4f543000) { (hw->snpsid & 0xfffff000) != 0x4f543000) {
dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
...@@ -3074,11 +3075,11 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) ...@@ -3074,11 +3075,11 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
hwcfg1 = readl(hsotg->regs + GHWCFG1); hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
hwcfg2 = readl(hsotg->regs + GHWCFG2); hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
hwcfg3 = readl(hsotg->regs + GHWCFG3); hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
hwcfg4 = readl(hsotg->regs + GHWCFG4); hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
grxfsiz = readl(hsotg->regs + GRXFSIZ); grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
...@@ -3087,18 +3088,18 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) ...@@ -3087,18 +3088,18 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
/* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */ /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
gusbcfg = readl(hsotg->regs + GUSBCFG); gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
gusbcfg |= GUSBCFG_FORCEHOSTMODE; gusbcfg |= GUSBCFG_FORCEHOSTMODE;
writel(gusbcfg, hsotg->regs + GUSBCFG); dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
usleep_range(100000, 150000); usleep_range(100000, 150000);
gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ); gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
hptxfsiz = readl(hsotg->regs + HPTXFSIZ); hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
gusbcfg = readl(hsotg->regs + GUSBCFG); gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
writel(gusbcfg, hsotg->regs + GUSBCFG); dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
usleep_range(100000, 150000); usleep_range(100000, 150000);
/* hwcfg2 */ /* hwcfg2 */
...@@ -3233,7 +3234,7 @@ u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) ...@@ -3233,7 +3234,7 @@ u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
{ {
if (readl(hsotg->regs + GSNPSID) == 0xffffffff) if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
return false; return false;
else else
return true; return true;
...@@ -3247,10 +3248,10 @@ bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) ...@@ -3247,10 +3248,10 @@ bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
*/ */
void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
{ {
u32 ahbcfg = readl(hsotg->regs + GAHBCFG); u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
ahbcfg |= GAHBCFG_GLBL_INTR_EN; ahbcfg |= GAHBCFG_GLBL_INTR_EN;
writel(ahbcfg, hsotg->regs + GAHBCFG); dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
} }
/** /**
...@@ -3261,10 +3262,10 @@ void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) ...@@ -3261,10 +3262,10 @@ void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
*/ */
void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
{ {
u32 ahbcfg = readl(hsotg->regs + GAHBCFG); u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
writel(ahbcfg, hsotg->regs + GAHBCFG); dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
} }
MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
......
drivers/usb/dwc2/core.h
View file @ 95c8bc36
...@@ -44,16 +44,32 @@ ...@@ -44,16 +44,32 @@
#include <linux/usb/phy.h> #include <linux/usb/phy.h>
#include "hw.h" #include "hw.h"
#ifdef DWC2_LOG_WRITES static inline u32 dwc2_readl(const void __iomem *addr)
static inline void do_write(u32 value, void *addr)
{ {
writel(value, addr); u32 value = __raw_readl(addr);
pr_info("INFO:: wrote %08x to %p\n", value, addr);
/* In order to preserve endianness __raw_* operation is used. Therefore
* a barrier is needed to ensure IO access is not re-ordered across
* reads or writes
*/
mb();
return value;
} }
#undef writel static inline void dwc2_writel(u32 value, void __iomem *addr)
#define writel(v, a) do_write(v, a) {
__raw_writel(value, addr);
/*
* In order to preserve endianness __raw_* operation is used. Therefore
* a barrier is needed to ensure IO access is not re-ordered across
* reads or writes
*/
mb();
#ifdef DWC2_LOG_WRITES
pr_info("INFO:: wrote %08x to %p\n", value, addr);
#endif #endif
}
/* Maximum number of Endpoints/HostChannels */ /* Maximum number of Endpoints/HostChannels */
#define MAX_EPS_CHANNELS 16 #define MAX_EPS_CHANNELS 16
......
drivers/usb/dwc2/core_intr.c
View file @ 95c8bc36
...@@ -80,15 +80,15 @@ static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) ...@@ -80,15 +80,15 @@ static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
*/ */
static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
{ {
u32 hprt0 = readl(hsotg->regs + HPRT0); u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
if (hprt0 & HPRT0_ENACHG) { if (hprt0 & HPRT0_ENACHG) {
hprt0 &= ~HPRT0_ENA; hprt0 &= ~HPRT0_ENA;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
} }
/* Clear interrupt */ /* Clear interrupt */
writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS);
} }
/** /**
...@@ -102,7 +102,7 @@ static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) ...@@ -102,7 +102,7 @@ static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
dwc2_is_host_mode(hsotg) ? "Host" : "Device"); dwc2_is_host_mode(hsotg) ? "Host" : "Device");
/* Clear interrupt */ /* Clear interrupt */
writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
} }
/** /**
...@@ -117,8 +117,8 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ...@@ -117,8 +117,8 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
u32 gotgctl; u32 gotgctl;
u32 gintmsk; u32 gintmsk;
gotgint = readl(hsotg->regs + GOTGINT); gotgint = dwc2_readl(hsotg->regs + GOTGINT);
gotgctl = readl(hsotg->regs + GOTGCTL); gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
dwc2_op_state_str(hsotg)); dwc2_op_state_str(hsotg));
...@@ -126,7 +126,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ...@@ -126,7 +126,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
" ++OTG Interrupt: Session End Detected++ (%s)\n", " ++OTG Interrupt: Session End Detected++ (%s)\n",
dwc2_op_state_str(hsotg)); dwc2_op_state_str(hsotg));
gotgctl = readl(hsotg->regs + GOTGCTL); gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
if (dwc2_is_device_mode(hsotg)) if (dwc2_is_device_mode(hsotg))
dwc2_hsotg_disconnect(hsotg); dwc2_hsotg_disconnect(hsotg);
...@@ -152,15 +152,15 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ...@@ -152,15 +152,15 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
hsotg->lx_state = DWC2_L0; hsotg->lx_state = DWC2_L0;
} }
gotgctl = readl(hsotg->regs + GOTGCTL); gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
gotgctl &= ~GOTGCTL_DEVHNPEN; gotgctl &= ~GOTGCTL_DEVHNPEN;
writel(gotgctl, hsotg->regs + GOTGCTL); dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
} }
if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
" ++OTG Interrupt: Session Request Success Status Change++\n"); " ++OTG Interrupt: Session Request Success Status Change++\n");
gotgctl = readl(hsotg->regs + GOTGCTL); gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
if (gotgctl & GOTGCTL_SESREQSCS) { if (gotgctl & GOTGCTL_SESREQSCS) {
if (hsotg->core_params->phy_type == if (hsotg->core_params->phy_type ==
DWC2_PHY_TYPE_PARAM_FS DWC2_PHY_TYPE_PARAM_FS
...@@ -168,9 +168,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ...@@ -168,9 +168,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
hsotg->srp_success = 1; hsotg->srp_success = 1;
} else { } else {
/* Clear Session Request */ /* Clear Session Request */
gotgctl = readl(hsotg->regs + GOTGCTL); gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
gotgctl &= ~GOTGCTL_SESREQ; gotgctl &= ~GOTGCTL_SESREQ;
writel(gotgctl, hsotg->regs + GOTGCTL); dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
} }
} }
} }
...@@ -180,7 +180,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ...@@ -180,7 +180,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
* Print statements during the HNP interrupt handling * Print statements during the HNP interrupt handling
* can cause it to fail * can cause it to fail
*/ */
gotgctl = readl(hsotg->regs + GOTGCTL); gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
/* /*
* WA for 3.00a- HW is not setting cur_mode, even sometimes * WA for 3.00a- HW is not setting cur_mode, even sometimes
* this does not help * this does not help
...@@ -200,9 +200,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ...@@ -200,9 +200,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
* interrupt does not get handled and Linux * interrupt does not get handled and Linux
* complains loudly. * complains loudly.
*/ */
gintmsk = readl(hsotg->regs + GINTMSK); gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gintmsk &= ~GINTSTS_SOF; gintmsk &= ~GINTSTS_SOF;
writel(gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
/* /*
* Call callback function with spin lock * Call callback function with spin lock
...@@ -216,9 +216,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ...@@ -216,9 +216,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
hsotg->op_state = OTG_STATE_B_HOST; hsotg->op_state = OTG_STATE_B_HOST;
} }
} else { } else {
gotgctl = readl(hsotg->regs + GOTGCTL); gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
writel(gotgctl, hsotg->regs + GOTGCTL); dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
dev_dbg(hsotg->dev, "HNP Failed\n"); dev_dbg(hsotg->dev, "HNP Failed\n");
dev_err(hsotg->dev, dev_err(hsotg->dev,
"Device Not Connected/Responding\n"); "Device Not Connected/Responding\n");
...@@ -244,9 +244,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ...@@ -244,9 +244,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
hsotg->op_state = OTG_STATE_A_PERIPHERAL; hsotg->op_state = OTG_STATE_A_PERIPHERAL;
} else { } else {
/* Need to disable SOF interrupt immediately */ /* Need to disable SOF interrupt immediately */
gintmsk = readl(hsotg->regs + GINTMSK); gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gintmsk &= ~GINTSTS_SOF; gintmsk &= ~GINTSTS_SOF;
writel(gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
spin_unlock(&hsotg->lock); spin_unlock(&hsotg->lock);
dwc2_hcd_start(hsotg); dwc2_hcd_start(hsotg);
spin_lock(&hsotg->lock); spin_lock(&hsotg->lock);
...@@ -261,7 +261,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ...@@ -261,7 +261,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
/* Clear GOTGINT */ /* Clear GOTGINT */
writel(gotgint, hsotg->regs + GOTGINT); dwc2_writel(gotgint, hsotg->regs + GOTGINT);
} }
/** /**
...@@ -276,11 +276,11 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) ...@@ -276,11 +276,11 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
*/ */
static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
{ {
u32 gintmsk = readl(hsotg->regs + GINTMSK); u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
/* Need to disable SOF interrupt immediately */ /* Need to disable SOF interrupt immediately */
gintmsk &= ~GINTSTS_SOF; gintmsk &= ~GINTSTS_SOF;
writel(gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
dwc2_is_host_mode(hsotg) ? "Host" : "Device"); dwc2_is_host_mode(hsotg) ? "Host" : "Device");
...@@ -297,7 +297,7 @@ static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) ...@@ -297,7 +297,7 @@ static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
} }
/* Clear interrupt */ /* Clear interrupt */
writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
} }
/** /**
...@@ -316,7 +316,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) ...@@ -316,7 +316,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, "++Session Request Interrupt++\n"); dev_dbg(hsotg->dev, "++Session Request Interrupt++\n");
/* Clear interrupt */ /* Clear interrupt */
writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
/* /*
* Report disconnect if there is any previous session established * Report disconnect if there is any previous session established
...@@ -339,13 +339,14 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) ...@@ -339,13 +339,14 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
if (dwc2_is_device_mode(hsotg)) { if (dwc2_is_device_mode(hsotg)) {
dev_dbg(hsotg->dev, "DSTS=0x%0x\n", readl(hsotg->regs + DSTS)); dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
dwc2_readl(hsotg->regs + DSTS));
if (hsotg->lx_state == DWC2_L2) { if (hsotg->lx_state == DWC2_L2) {
u32 dctl = readl(hsotg->regs + DCTL); u32 dctl = dwc2_readl(hsotg->regs + DCTL);
/* Clear Remote Wakeup Signaling */ /* Clear Remote Wakeup Signaling */
dctl &= ~DCTL_RMTWKUPSIG; dctl &= ~DCTL_RMTWKUPSIG;
writel(dctl, hsotg->regs + DCTL); dwc2_writel(dctl, hsotg->regs + DCTL);
ret = dwc2_exit_hibernation(hsotg, true); ret = dwc2_exit_hibernation(hsotg, true);
if (ret && (ret != -ENOTSUPP)) if (ret && (ret != -ENOTSUPP))
dev_err(hsotg->dev, "exit hibernation failed\n"); dev_err(hsotg->dev, "exit hibernation failed\n");
...@@ -356,11 +357,11 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) ...@@ -356,11 +357,11 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
hsotg->lx_state = DWC2_L0; hsotg->lx_state = DWC2_L0;
} else { } else {
if (hsotg->lx_state != DWC2_L1) { if (hsotg->lx_state != DWC2_L1) {
u32 pcgcctl = readl(hsotg->regs + PCGCTL); u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
/* Restart the Phy Clock */ /* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK; pcgcctl &= ~PCGCTL_STOPPCLK;
writel(pcgcctl, hsotg->regs + PCGCTL); dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
mod_timer(&hsotg->wkp_timer, mod_timer(&hsotg->wkp_timer,
jiffies + msecs_to_jiffies(71)); jiffies + msecs_to_jiffies(71));
} else { } else {
...@@ -370,7 +371,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) ...@@ -370,7 +371,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
} }
/* Clear interrupt */ /* Clear interrupt */
writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
} }
/* /*
...@@ -389,7 +390,7 @@ static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) ...@@ -389,7 +390,7 @@ static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
/* Change to L3 (OFF) state */ /* Change to L3 (OFF) state */
hsotg->lx_state = DWC2_L3; hsotg->lx_state = DWC2_L3;
writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
} }
/* /*
...@@ -412,7 +413,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) ...@@ -412,7 +413,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
* Check the Device status register to determine if the Suspend * Check the Device status register to determine if the Suspend
* state is active * state is active
*/ */
dsts = readl(hsotg->regs + DSTS); dsts = dwc2_readl(hsotg->regs + DSTS);
dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts); dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n", "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
...@@ -465,7 +466,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) ...@@ -465,7 +466,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
clear_int: clear_int:
/* Clear interrupt */ /* Clear interrupt */
writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
} }
#define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
...@@ -483,9 +484,9 @@ static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) ...@@ -483,9 +484,9 @@ static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
u32 gahbcfg; u32 gahbcfg;
u32 gintmsk_common = GINTMSK_COMMON; u32 gintmsk_common = GINTMSK_COMMON;
gintsts = readl(hsotg->regs + GINTSTS); gintsts = dwc2_readl(hsotg->regs + GINTSTS);
gintmsk = readl(hsotg->regs + GINTMSK); gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gahbcfg = readl(hsotg->regs + GAHBCFG); gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
/* If any common interrupts set */ /* If any common interrupts set */
if (gintsts & gintmsk_common) if (gintsts & gintmsk_common)
......
drivers/usb/dwc2/debugfs.c
View file @ 95c8bc36
...@@ -76,7 +76,7 @@ static int testmode_show(struct seq_file *s, void *unused) ...@@ -76,7 +76,7 @@ static int testmode_show(struct seq_file *s, void *unused)
int dctl; int dctl;
spin_lock_irqsave(&hsotg->lock, flags); spin_lock_irqsave(&hsotg->lock, flags);
dctl = readl(hsotg->regs + DCTL); dctl = dwc2_readl(hsotg->regs + DCTL);
dctl &= DCTL_TSTCTL_MASK; dctl &= DCTL_TSTCTL_MASK;
dctl >>= DCTL_TSTCTL_SHIFT; dctl >>= DCTL_TSTCTL_SHIFT;
spin_unlock_irqrestore(&hsotg->lock, flags); spin_unlock_irqrestore(&hsotg->lock, flags);
...@@ -137,38 +137,38 @@ static int state_show(struct seq_file *seq, void *v) ...@@ -137,38 +137,38 @@ static int state_show(struct seq_file *seq, void *v)
int idx; int idx;
seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
readl(regs + DCFG), dwc2_readl(regs + DCFG),
readl(regs + DCTL), dwc2_readl(regs + DCTL),
readl(regs + DSTS)); dwc2_readl(regs + DSTS));
seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
readl(regs + DIEPMSK), readl(regs + DOEPMSK)); dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK));
seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
readl(regs + GINTMSK), dwc2_readl(regs + GINTMSK),
readl(regs + GINTSTS)); dwc2_readl(regs + GINTSTS));
seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
readl(regs + DAINTMSK), dwc2_readl(regs + DAINTMSK),
readl(regs + DAINT)); dwc2_readl(regs + DAINT));
seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
readl(regs + GNPTXSTS), dwc2_readl(regs + GNPTXSTS),
readl(regs + GRXSTSR)); dwc2_readl(regs + GRXSTSR));
seq_puts(seq, "\nEndpoint status:\n"); seq_puts(seq, "\nEndpoint status:\n");
for (idx = 0; idx < hsotg->num_of_eps; idx++) { for (idx = 0; idx < hsotg->num_of_eps; idx++) {
u32 in, out; u32 in, out;
in = readl(regs + DIEPCTL(idx)); in = dwc2_readl(regs + DIEPCTL(idx));
out = readl(regs + DOEPCTL(idx)); out = dwc2_readl(regs + DOEPCTL(idx));
seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
idx, in, out); idx, in, out);
in = readl(regs + DIEPTSIZ(idx)); in = dwc2_readl(regs + DIEPTSIZ(idx));
out = readl(regs + DOEPTSIZ(idx)); out = dwc2_readl(regs + DOEPTSIZ(idx));
seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
in, out); in, out);
...@@ -208,9 +208,9 @@ static int fifo_show(struct seq_file *seq, void *v) ...@@ -208,9 +208,9 @@ static int fifo_show(struct seq_file *seq, void *v)
int idx; int idx;
seq_puts(seq, "Non-periodic FIFOs:\n"); seq_puts(seq, "Non-periodic FIFOs:\n");
seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ)); seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ));
val = readl(regs + GNPTXFSIZ); val = dwc2_readl(regs + GNPTXFSIZ);
seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
val >> FIFOSIZE_DEPTH_SHIFT, val >> FIFOSIZE_DEPTH_SHIFT,
val & FIFOSIZE_DEPTH_MASK); val & FIFOSIZE_DEPTH_MASK);
...@@ -218,7 +218,7 @@ static int fifo_show(struct seq_file *seq, void *v) ...@@ -218,7 +218,7 @@ static int fifo_show(struct seq_file *seq, void *v)
seq_puts(seq, "\nPeriodic TXFIFOs:\n"); seq_puts(seq, "\nPeriodic TXFIFOs:\n");
for (idx = 1; idx < hsotg->num_of_eps; idx++) { for (idx = 1; idx < hsotg->num_of_eps; idx++) {
val = readl(regs + DPTXFSIZN(idx)); val = dwc2_readl(regs + DPTXFSIZN(idx));
seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
val >> FIFOSIZE_DEPTH_SHIFT, val >> FIFOSIZE_DEPTH_SHIFT,
...@@ -270,20 +270,20 @@ static int ep_show(struct seq_file *seq, void *v) ...@@ -270,20 +270,20 @@ static int ep_show(struct seq_file *seq, void *v)
/* first show the register state */ /* first show the register state */
seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
readl(regs + DIEPCTL(index)), dwc2_readl(regs + DIEPCTL(index)),
readl(regs + DOEPCTL(index))); dwc2_readl(regs + DOEPCTL(index)));
seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
readl(regs + DIEPDMA(index)), dwc2_readl(regs + DIEPDMA(index)),
readl(regs + DOEPDMA(index))); dwc2_readl(regs + DOEPDMA(index)));
seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
readl(regs + DIEPINT(index)), dwc2_readl(regs + DIEPINT(index)),
readl(regs + DOEPINT(index))); dwc2_readl(regs + DOEPINT(index)));
seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
readl(regs + DIEPTSIZ(index)), dwc2_readl(regs + DIEPTSIZ(index)),
readl(regs + DOEPTSIZ(index))); dwc2_readl(regs + DOEPTSIZ(index)));
seq_puts(seq, "\n"); seq_puts(seq, "\n");
seq_printf(seq, "mps %d\n", ep->ep.maxpacket); seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
......
drivers/usb/dwc2/gadget.c
View file @ 95c8bc36
...@@ -56,12 +56,12 @@ static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) ...@@ -56,12 +56,12 @@ static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
static inline void __orr32(void __iomem *ptr, u32 val) static inline void __orr32(void __iomem *ptr, u32 val)
{ {
writel(readl(ptr) | val, ptr); dwc2_writel(dwc2_readl(ptr) | val, ptr);
} }
static inline void __bic32(void __iomem *ptr, u32 val) static inline void __bic32(void __iomem *ptr, u32 val)
{ {
writel(readl(ptr) & ~val, ptr); dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
} }
static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
...@@ -107,14 +107,14 @@ static inline bool using_dma(struct dwc2_hsotg *hsotg) ...@@ -107,14 +107,14 @@ static inline bool using_dma(struct dwc2_hsotg *hsotg)
*/ */
static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
{ {
u32 gsintmsk = readl(hsotg->regs + GINTMSK); u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
u32 new_gsintmsk; u32 new_gsintmsk;
new_gsintmsk = gsintmsk | ints; new_gsintmsk = gsintmsk | ints;
if (new_gsintmsk != gsintmsk) { if (new_gsintmsk != gsintmsk) {
dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
writel(new_gsintmsk, hsotg->regs + GINTMSK); dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
} }
} }
...@@ -125,13 +125,13 @@ static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) ...@@ -125,13 +125,13 @@ static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
*/ */
static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
{ {
u32 gsintmsk = readl(hsotg->regs + GINTMSK); u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
u32 new_gsintmsk; u32 new_gsintmsk;
new_gsintmsk = gsintmsk & ~ints; new_gsintmsk = gsintmsk & ~ints;
if (new_gsintmsk != gsintmsk) if (new_gsintmsk != gsintmsk)
writel(new_gsintmsk, hsotg->regs + GINTMSK); dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
} }
/** /**
...@@ -156,12 +156,12 @@ static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, ...@@ -156,12 +156,12 @@ static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
bit <<= 16; bit <<= 16;
local_irq_save(flags); local_irq_save(flags);
daint = readl(hsotg->regs + DAINTMSK); daint = dwc2_readl(hsotg->regs + DAINTMSK);
if (en) if (en)
daint |= bit; daint |= bit;
else else
daint &= ~bit; daint &= ~bit;
writel(daint, hsotg->regs + DAINTMSK); dwc2_writel(daint, hsotg->regs + DAINTMSK);
local_irq_restore(flags); local_irq_restore(flags);
} }
...@@ -181,8 +181,8 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) ...@@ -181,8 +181,8 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
hsotg->fifo_map = 0; hsotg->fifo_map = 0;
/* set RX/NPTX FIFO sizes */ /* set RX/NPTX FIFO sizes */
writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
(hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
hsotg->regs + GNPTXFSIZ); hsotg->regs + GNPTXFSIZ);
...@@ -210,7 +210,7 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) ...@@ -210,7 +210,7 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
"insufficient fifo memory"); "insufficient fifo memory");
addr += hsotg->g_tx_fifo_sz[ep]; addr += hsotg->g_tx_fifo_sz[ep];
writel(val, hsotg->regs + DPTXFSIZN(ep)); dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
} }
/* /*
...@@ -218,13 +218,13 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) ...@@ -218,13 +218,13 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
* all fifos are flushed before continuing * all fifos are flushed before continuing
*/ */
writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
/* wait until the fifos are both flushed */ /* wait until the fifos are both flushed */
timeout = 100; timeout = 100;
while (1) { while (1) {
val = readl(hsotg->regs + GRSTCTL); val = dwc2_readl(hsotg->regs + GRSTCTL);
if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
break; break;
...@@ -317,7 +317,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, ...@@ -317,7 +317,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_req *hs_req) struct dwc2_hsotg_req *hs_req)
{ {
bool periodic = is_ep_periodic(hs_ep); bool periodic = is_ep_periodic(hs_ep);
u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
int buf_pos = hs_req->req.actual; int buf_pos = hs_req->req.actual;
int to_write = hs_ep->size_loaded; int to_write = hs_ep->size_loaded;
void *data; void *data;
...@@ -332,7 +332,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, ...@@ -332,7 +332,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
return 0; return 0;
if (periodic && !hsotg->dedicated_fifos) { if (periodic && !hsotg->dedicated_fifos) {
u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
int size_left; int size_left;
int size_done; int size_done;
...@@ -373,7 +373,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, ...@@ -373,7 +373,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
return -ENOSPC; return -ENOSPC;
} }
} else if (hsotg->dedicated_fifos && hs_ep->index != 0) { } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
can_write &= 0xffff; can_write &= 0xffff;
can_write *= 4; can_write *= 4;
...@@ -550,11 +550,11 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ...@@ -550,11 +550,11 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
__func__, readl(hsotg->regs + epctrl_reg), index, __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
hs_ep->dir_in ? "in" : "out"); hs_ep->dir_in ? "in" : "out");
/* If endpoint is stalled, we will restart request later */ /* If endpoint is stalled, we will restart request later */
ctrl = readl(hsotg->regs + epctrl_reg); ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
if (ctrl & DXEPCTL_STALL) { if (ctrl & DXEPCTL_STALL) {
dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
...@@ -618,7 +618,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ...@@ -618,7 +618,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
hs_ep->req = hs_req; hs_ep->req = hs_req;
/* write size / packets */ /* write size / packets */
writel(epsize, hsotg->regs + epsize_reg); dwc2_writel(epsize, hsotg->regs + epsize_reg);
if (using_dma(hsotg) && !continuing) { if (using_dma(hsotg) && !continuing) {
unsigned int dma_reg; unsigned int dma_reg;
...@@ -629,7 +629,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ...@@ -629,7 +629,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
*/ */
dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
writel(ureq->dma, hsotg->regs + dma_reg); dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
__func__, &ureq->dma, dma_reg); __func__, &ureq->dma, dma_reg);
...@@ -645,7 +645,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ...@@ -645,7 +645,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
writel(ctrl, hsotg->regs + epctrl_reg); dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
/* /*
* set these, it seems that DMA support increments past the end * set these, it seems that DMA support increments past the end
...@@ -667,7 +667,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ...@@ -667,7 +667,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
* to debugging to see what is going on. * to debugging to see what is going on.
*/ */
if (dir_in) if (dir_in)
writel(DIEPMSK_INTKNTXFEMPMSK, dwc2_writel(DIEPMSK_INTKNTXFEMPMSK,
hsotg->regs + DIEPINT(index)); hsotg->regs + DIEPINT(index));
/* /*
...@@ -676,13 +676,13 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ...@@ -676,13 +676,13 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
*/ */
/* check ep is enabled */ /* check ep is enabled */
if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
index, readl(hsotg->regs + epctrl_reg)); index, dwc2_readl(hsotg->regs + epctrl_reg));
dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
__func__, readl(hsotg->regs + epctrl_reg)); __func__, dwc2_readl(hsotg->regs + epctrl_reg));
/* enable ep interrupts */ /* enable ep interrupts */
dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
...@@ -901,7 +901,7 @@ static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, ...@@ -901,7 +901,7 @@ static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
*/ */
int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
{ {
int dctl = readl(hsotg->regs + DCTL); int dctl = dwc2_readl(hsotg->regs + DCTL);
dctl &= ~DCTL_TSTCTL_MASK; dctl &= ~DCTL_TSTCTL_MASK;
switch (testmode) { switch (testmode) {
...@@ -915,7 +915,7 @@ int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) ...@@ -915,7 +915,7 @@ int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
default: default:
return -EINVAL; return -EINVAL;
} }
writel(dctl, hsotg->regs + DCTL); dwc2_writel(dctl, hsotg->regs + DCTL);
return 0; return 0;
} }
...@@ -1174,14 +1174,14 @@ static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) ...@@ -1174,14 +1174,14 @@ static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
* taken effect, so no need to clear later. * taken effect, so no need to clear later.
*/ */
ctrl = readl(hsotg->regs + reg); ctrl = dwc2_readl(hsotg->regs + reg);
ctrl |= DXEPCTL_STALL; ctrl |= DXEPCTL_STALL;
ctrl |= DXEPCTL_CNAK; ctrl |= DXEPCTL_CNAK;
writel(ctrl, hsotg->regs + reg); dwc2_writel(ctrl, hsotg->regs + reg);
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
ctrl, reg, readl(hsotg->regs + reg)); ctrl, reg, dwc2_readl(hsotg->regs + reg));
/* /*
* complete won't be called, so we enqueue * complete won't be called, so we enqueue
...@@ -1225,11 +1225,11 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, ...@@ -1225,11 +1225,11 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
switch (ctrl->bRequest) { switch (ctrl->bRequest) {
case USB_REQ_SET_ADDRESS: case USB_REQ_SET_ADDRESS:
hsotg->connected = 1; hsotg->connected = 1;
dcfg = readl(hsotg->regs + DCFG); dcfg = dwc2_readl(hsotg->regs + DCFG);
dcfg &= ~DCFG_DEVADDR_MASK; dcfg &= ~DCFG_DEVADDR_MASK;
dcfg |= (le16_to_cpu(ctrl->wValue) << dcfg |= (le16_to_cpu(ctrl->wValue) <<
DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
writel(dcfg, hsotg->regs + DCFG); dwc2_writel(dcfg, hsotg->regs + DCFG);
dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
...@@ -1347,15 +1347,15 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, ...@@ -1347,15 +1347,15 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
index); index);
writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
DXEPTSIZ_XFERSIZE(0), hsotg->regs + DXEPTSIZ_XFERSIZE(0), hsotg->regs +
epsiz_reg); epsiz_reg);
ctrl = readl(hsotg->regs + epctl_reg); ctrl = dwc2_readl(hsotg->regs + epctl_reg);
ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
ctrl |= DXEPCTL_USBACTEP; ctrl |= DXEPCTL_USBACTEP;
writel(ctrl, hsotg->regs + epctl_reg); dwc2_writel(ctrl, hsotg->regs + epctl_reg);
} }
/** /**
...@@ -1449,7 +1449,7 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) ...@@ -1449,7 +1449,7 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
if (!hs_req) { if (!hs_req) {
u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx)); u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
int ptr; int ptr;
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
...@@ -1458,7 +1458,7 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) ...@@ -1458,7 +1458,7 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
/* dump the data from the FIFO, we've nothing we can do */ /* dump the data from the FIFO, we've nothing we can do */
for (ptr = 0; ptr < size; ptr += 4) for (ptr = 0; ptr < size; ptr += 4)
(void)readl(fifo); (void)dwc2_readl(fifo);
return; return;
} }
...@@ -1523,7 +1523,7 @@ static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) ...@@ -1523,7 +1523,7 @@ static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
*/ */
static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
{ {
u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum)); u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
struct dwc2_hsotg_req *hs_req = hs_ep->req; struct dwc2_hsotg_req *hs_req = hs_ep->req;
struct usb_request *req = &hs_req->req; struct usb_request *req = &hs_req->req;
...@@ -1595,7 +1595,7 @@ static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) ...@@ -1595,7 +1595,7 @@ static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
{ {
u32 dsts; u32 dsts;
dsts = readl(hsotg->regs + DSTS); dsts = dwc2_readl(hsotg->regs + DSTS);
dsts &= DSTS_SOFFN_MASK; dsts &= DSTS_SOFFN_MASK;
dsts >>= DSTS_SOFFN_SHIFT; dsts >>= DSTS_SOFFN_SHIFT;
...@@ -1620,7 +1620,7 @@ static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) ...@@ -1620,7 +1620,7 @@ static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
*/ */
static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
{ {
u32 grxstsr = readl(hsotg->regs + GRXSTSP); u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
u32 epnum, status, size; u32 epnum, status, size;
WARN_ON(using_dma(hsotg)); WARN_ON(using_dma(hsotg));
...@@ -1651,7 +1651,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) ...@@ -1651,7 +1651,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
dwc2_hsotg_read_frameno(hsotg), dwc2_hsotg_read_frameno(hsotg),
readl(hsotg->regs + DOEPCTL(0))); dwc2_readl(hsotg->regs + DOEPCTL(0)));
/* /*
* Call dwc2_hsotg_handle_outdone here if it was not called from * Call dwc2_hsotg_handle_outdone here if it was not called from
* GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
...@@ -1669,7 +1669,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) ...@@ -1669,7 +1669,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
dwc2_hsotg_read_frameno(hsotg), dwc2_hsotg_read_frameno(hsotg),
readl(hsotg->regs + DOEPCTL(0))); dwc2_readl(hsotg->regs + DOEPCTL(0)));
WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
...@@ -1748,15 +1748,15 @@ static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, ...@@ -1748,15 +1748,15 @@ static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
} }
if (dir_in) { if (dir_in) {
reg = readl(regs + DIEPCTL(ep)); reg = dwc2_readl(regs + DIEPCTL(ep));
reg &= ~DXEPCTL_MPS_MASK; reg &= ~DXEPCTL_MPS_MASK;
reg |= mpsval; reg |= mpsval;
writel(reg, regs + DIEPCTL(ep)); dwc2_writel(reg, regs + DIEPCTL(ep));
} else { } else {
reg = readl(regs + DOEPCTL(ep)); reg = dwc2_readl(regs + DOEPCTL(ep));
reg &= ~DXEPCTL_MPS_MASK; reg &= ~DXEPCTL_MPS_MASK;
reg |= mpsval; reg |= mpsval;
writel(reg, regs + DOEPCTL(ep)); dwc2_writel(reg, regs + DOEPCTL(ep));
} }
return; return;
...@@ -1775,14 +1775,14 @@ static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) ...@@ -1775,14 +1775,14 @@ static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
int timeout; int timeout;
int val; int val;
writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
hsotg->regs + GRSTCTL); hsotg->regs + GRSTCTL);
/* wait until the fifo is flushed */ /* wait until the fifo is flushed */
timeout = 100; timeout = 100;
while (1) { while (1) {
val = readl(hsotg->regs + GRSTCTL); val = dwc2_readl(hsotg->regs + GRSTCTL);
if ((val & (GRSTCTL_TXFFLSH)) == 0) if ((val & (GRSTCTL_TXFFLSH)) == 0)
break; break;
...@@ -1843,7 +1843,7 @@ static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, ...@@ -1843,7 +1843,7 @@ static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep) struct dwc2_hsotg_ep *hs_ep)
{ {
struct dwc2_hsotg_req *hs_req = hs_ep->req; struct dwc2_hsotg_req *hs_req = hs_ep->req;
u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
int size_left, size_done; int size_left, size_done;
if (!hs_req) { if (!hs_req) {
...@@ -1934,11 +1934,11 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, ...@@ -1934,11 +1934,11 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
u32 ints; u32 ints;
u32 ctrl; u32 ctrl;
ints = readl(hsotg->regs + epint_reg); ints = dwc2_readl(hsotg->regs + epint_reg);
ctrl = readl(hsotg->regs + epctl_reg); ctrl = dwc2_readl(hsotg->regs + epctl_reg);
/* Clear endpoint interrupts */ /* Clear endpoint interrupts */
writel(ints, hsotg->regs + epint_reg); dwc2_writel(ints, hsotg->regs + epint_reg);
if (!hs_ep) { if (!hs_ep) {
dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
...@@ -1959,13 +1959,13 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, ...@@ -1959,13 +1959,13 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
ctrl |= DXEPCTL_SETEVENFR; ctrl |= DXEPCTL_SETEVENFR;
else else
ctrl |= DXEPCTL_SETODDFR; ctrl |= DXEPCTL_SETODDFR;
writel(ctrl, hsotg->regs + epctl_reg); dwc2_writel(ctrl, hsotg->regs + epctl_reg);
} }
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
__func__, readl(hsotg->regs + epctl_reg), __func__, dwc2_readl(hsotg->regs + epctl_reg),
readl(hsotg->regs + epsiz_reg)); dwc2_readl(hsotg->regs + epsiz_reg));
/* /*
* we get OutDone from the FIFO, so we only need to look * we get OutDone from the FIFO, so we only need to look
...@@ -1990,16 +1990,16 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, ...@@ -1990,16 +1990,16 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
if (dir_in) { if (dir_in) {
int epctl = readl(hsotg->regs + epctl_reg); int epctl = dwc2_readl(hsotg->regs + epctl_reg);
dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
if ((epctl & DXEPCTL_STALL) && if ((epctl & DXEPCTL_STALL) &&
(epctl & DXEPCTL_EPTYPE_BULK)) { (epctl & DXEPCTL_EPTYPE_BULK)) {
int dctl = readl(hsotg->regs + DCTL); int dctl = dwc2_readl(hsotg->regs + DCTL);
dctl |= DCTL_CGNPINNAK; dctl |= DCTL_CGNPINNAK;
writel(dctl, hsotg->regs + DCTL); dwc2_writel(dctl, hsotg->regs + DCTL);
} }
} }
} }
...@@ -2061,7 +2061,7 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, ...@@ -2061,7 +2061,7 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
*/ */
static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
{ {
u32 dsts = readl(hsotg->regs + DSTS); u32 dsts = dwc2_readl(hsotg->regs + DSTS);
int ep0_mps = 0, ep_mps = 8; int ep0_mps = 0, ep_mps = 8;
/* /*
...@@ -2128,8 +2128,8 @@ static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) ...@@ -2128,8 +2128,8 @@ static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
dwc2_hsotg_enqueue_setup(hsotg); dwc2_hsotg_enqueue_setup(hsotg);
dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
readl(hsotg->regs + DIEPCTL0), dwc2_readl(hsotg->regs + DIEPCTL0),
readl(hsotg->regs + DOEPCTL0)); dwc2_readl(hsotg->regs + DOEPCTL0));
} }
/** /**
...@@ -2156,7 +2156,7 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg, ...@@ -2156,7 +2156,7 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg,
if (!hsotg->dedicated_fifos) if (!hsotg->dedicated_fifos)
return; return;
size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
if (size < ep->fifo_size) if (size < ep->fifo_size)
dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
} }
...@@ -2240,11 +2240,11 @@ static int dwc2_hsotg_corereset(struct dwc2_hsotg *hsotg) ...@@ -2240,11 +2240,11 @@ static int dwc2_hsotg_corereset(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, "resetting core\n"); dev_dbg(hsotg->dev, "resetting core\n");
/* issue soft reset */ /* issue soft reset */
writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); dwc2_writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
timeout = 10000; timeout = 10000;
do { do {
grstctl = readl(hsotg->regs + GRSTCTL); grstctl = dwc2_readl(hsotg->regs + GRSTCTL);
} while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0); } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
if (grstctl & GRSTCTL_CSFTRST) { if (grstctl & GRSTCTL_CSFTRST) {
...@@ -2255,7 +2255,7 @@ static int dwc2_hsotg_corereset(struct dwc2_hsotg *hsotg) ...@@ -2255,7 +2255,7 @@ static int dwc2_hsotg_corereset(struct dwc2_hsotg *hsotg)
timeout = 10000; timeout = 10000;
while (1) { while (1) {
u32 grstctl = readl(hsotg->regs + GRSTCTL); u32 grstctl = dwc2_readl(hsotg->regs + GRSTCTL);
if (timeout-- < 0) { if (timeout-- < 0) {
dev_info(hsotg->dev, dev_info(hsotg->dev,
...@@ -2295,7 +2295,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, ...@@ -2295,7 +2295,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
/* set the PLL on, remove the HNP/SRP and set the PHY */ /* set the PLL on, remove the HNP/SRP and set the PHY */
val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
(val << GUSBCFG_USBTRDTIM_SHIFT), hsotg->regs + GUSBCFG); (val << GUSBCFG_USBTRDTIM_SHIFT), hsotg->regs + GUSBCFG);
dwc2_hsotg_init_fifo(hsotg); dwc2_hsotg_init_fifo(hsotg);
...@@ -2303,15 +2303,15 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, ...@@ -2303,15 +2303,15 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
if (!is_usb_reset) if (!is_usb_reset)
__orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG); dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
/* Clear any pending OTG interrupts */ /* Clear any pending OTG interrupts */
writel(0xffffffff, hsotg->regs + GOTGINT); dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
/* Clear any pending interrupts */ /* Clear any pending interrupts */
writel(0xffffffff, hsotg->regs + GINTSTS); dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | dwc2_writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST | GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
GINTSTS_RESETDET | GINTSTS_ENUMDONE | GINTSTS_RESETDET | GINTSTS_ENUMDONE |
...@@ -2320,14 +2320,14 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, ...@@ -2320,14 +2320,14 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
hsotg->regs + GINTMSK); hsotg->regs + GINTMSK);
if (using_dma(hsotg)) if (using_dma(hsotg))
writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
(GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
hsotg->regs + GAHBCFG); hsotg->regs + GAHBCFG);
else else
writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | dwc2_writel(((hsotg->dedicated_fifos) ?
(GAHBCFG_NP_TXF_EMP_LVL |
GAHBCFG_P_TXF_EMP_LVL) : 0) | GAHBCFG_P_TXF_EMP_LVL) : 0) |
GAHBCFG_GLBL_INTR_EN, GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
hsotg->regs + GAHBCFG);
/* /*
* If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
...@@ -2335,7 +2335,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, ...@@ -2335,7 +2335,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
* interrupts. * interrupts.
*/ */
writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
...@@ -2346,17 +2346,17 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, ...@@ -2346,17 +2346,17 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
* don't need XferCompl, we get that from RXFIFO in slave mode. In * don't need XferCompl, we get that from RXFIFO in slave mode. In
* DMA mode we may need this. * DMA mode we may need this.
*/ */
writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
DIEPMSK_TIMEOUTMSK) : 0) | DIEPMSK_TIMEOUTMSK) : 0) |
DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
DOEPMSK_SETUPMSK, DOEPMSK_SETUPMSK,
hsotg->regs + DOEPMSK); hsotg->regs + DOEPMSK);
writel(0, hsotg->regs + DAINTMSK); dwc2_writel(0, hsotg->regs + DAINTMSK);
dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
readl(hsotg->regs + DIEPCTL0), dwc2_readl(hsotg->regs + DIEPCTL0),
readl(hsotg->regs + DOEPCTL0)); dwc2_readl(hsotg->regs + DOEPCTL0));
/* enable in and out endpoint interrupts */ /* enable in and out endpoint interrupts */
dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
...@@ -2379,7 +2379,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, ...@@ -2379,7 +2379,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
__bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
} }
dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
/* /*
* DxEPCTL_USBActEp says RO in manual, but seems to be set by * DxEPCTL_USBActEp says RO in manual, but seems to be set by
...@@ -2387,23 +2387,23 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, ...@@ -2387,23 +2387,23 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
*/ */
/* set to read 1 8byte packet */ /* set to read 1 8byte packet */
writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
DXEPCTL_CNAK | DXEPCTL_EPENA | DXEPCTL_CNAK | DXEPCTL_EPENA |
DXEPCTL_USBACTEP, DXEPCTL_USBACTEP,
hsotg->regs + DOEPCTL0); hsotg->regs + DOEPCTL0);
/* enable, but don't activate EP0in */ /* enable, but don't activate EP0in */
writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
dwc2_hsotg_enqueue_setup(hsotg); dwc2_hsotg_enqueue_setup(hsotg);
dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
readl(hsotg->regs + DIEPCTL0), dwc2_readl(hsotg->regs + DIEPCTL0),
readl(hsotg->regs + DOEPCTL0)); dwc2_readl(hsotg->regs + DOEPCTL0));
/* clear global NAKs */ /* clear global NAKs */
val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
...@@ -2443,8 +2443,8 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) ...@@ -2443,8 +2443,8 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
spin_lock(&hsotg->lock); spin_lock(&hsotg->lock);
irq_retry: irq_retry:
gintsts = readl(hsotg->regs + GINTSTS); gintsts = dwc2_readl(hsotg->regs + GINTSTS);
gintmsk = readl(hsotg->regs + GINTMSK); gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
__func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
...@@ -2452,14 +2452,14 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) ...@@ -2452,14 +2452,14 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
gintsts &= gintmsk; gintsts &= gintmsk;
if (gintsts & GINTSTS_ENUMDONE) { if (gintsts & GINTSTS_ENUMDONE) {
writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
dwc2_hsotg_irq_enumdone(hsotg); dwc2_hsotg_irq_enumdone(hsotg);
} }
if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
u32 daint = readl(hsotg->regs + DAINT); u32 daint = dwc2_readl(hsotg->regs + DAINT);
u32 daintmsk = readl(hsotg->regs + DAINTMSK); u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
u32 daint_out, daint_in; u32 daint_out, daint_in;
int ep; int ep;
...@@ -2485,7 +2485,7 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) ...@@ -2485,7 +2485,7 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
if (gintsts & GINTSTS_RESETDET) { if (gintsts & GINTSTS_RESETDET) {
dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
/* This event must be used only if controller is suspended */ /* This event must be used only if controller is suspended */
if (hsotg->lx_state == DWC2_L2) { if (hsotg->lx_state == DWC2_L2) {
...@@ -2496,13 +2496,13 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) ...@@ -2496,13 +2496,13 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
u32 usb_status = readl(hsotg->regs + GOTGCTL); u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
readl(hsotg->regs + GNPTXSTS)); dwc2_readl(hsotg->regs + GNPTXSTS));
writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
/* Report disconnection if it is not already done. */ /* Report disconnection if it is not already done. */
dwc2_hsotg_disconnect(hsotg); dwc2_hsotg_disconnect(hsotg);
...@@ -2556,7 +2556,7 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) ...@@ -2556,7 +2556,7 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
if (gintsts & GINTSTS_ERLYSUSP) { if (gintsts & GINTSTS_ERLYSUSP) {
dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
} }
/* /*
...@@ -2568,7 +2568,7 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) ...@@ -2568,7 +2568,7 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
if (gintsts & GINTSTS_GOUTNAKEFF) { if (gintsts & GINTSTS_GOUTNAKEFF) {
dev_info(hsotg->dev, "GOUTNakEff triggered\n"); dev_info(hsotg->dev, "GOUTNakEff triggered\n");
writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); dwc2_writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
dwc2_hsotg_dump(hsotg); dwc2_hsotg_dump(hsotg);
} }
...@@ -2576,7 +2576,7 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) ...@@ -2576,7 +2576,7 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
if (gintsts & GINTSTS_GINNAKEFF) { if (gintsts & GINTSTS_GINNAKEFF) {
dev_info(hsotg->dev, "GINNakEff triggered\n"); dev_info(hsotg->dev, "GINNakEff triggered\n");
writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); dwc2_writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
dwc2_hsotg_dump(hsotg); dwc2_hsotg_dump(hsotg);
} }
...@@ -2634,7 +2634,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep, ...@@ -2634,7 +2634,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
/* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
epctrl = readl(hsotg->regs + epctrl_reg); epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
__func__, epctrl, epctrl_reg); __func__, epctrl, epctrl_reg);
...@@ -2718,7 +2718,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep, ...@@ -2718,7 +2718,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
for (i = 1; i < hsotg->num_of_eps; ++i) { for (i = 1; i < hsotg->num_of_eps; ++i) {
if (hsotg->fifo_map & (1<<i)) if (hsotg->fifo_map & (1<<i))
continue; continue;
val = readl(hsotg->regs + DPTXFSIZN(i)); val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
if (val < size) if (val < size)
continue; continue;
...@@ -2747,9 +2747,9 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep, ...@@ -2747,9 +2747,9 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
__func__, epctrl); __func__, epctrl);
writel(epctrl, hsotg->regs + epctrl_reg); dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
__func__, readl(hsotg->regs + epctrl_reg)); __func__, dwc2_readl(hsotg->regs + epctrl_reg));
/* enable the endpoint interrupt */ /* enable the endpoint interrupt */
dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
...@@ -2788,13 +2788,13 @@ static int dwc2_hsotg_ep_disable(struct usb_ep *ep) ...@@ -2788,13 +2788,13 @@ static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
hs_ep->fifo_index = 0; hs_ep->fifo_index = 0;
hs_ep->fifo_size = 0; hs_ep->fifo_size = 0;
ctrl = readl(hsotg->regs + epctrl_reg); ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
ctrl &= ~DXEPCTL_EPENA; ctrl &= ~DXEPCTL_EPENA;
ctrl &= ~DXEPCTL_USBACTEP; ctrl &= ~DXEPCTL_USBACTEP;
ctrl |= DXEPCTL_SNAK; ctrl |= DXEPCTL_SNAK;
dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
writel(ctrl, hsotg->regs + epctrl_reg); dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
/* disable endpoint interrupts */ /* disable endpoint interrupts */
dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
...@@ -2877,7 +2877,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value) ...@@ -2877,7 +2877,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value)
if (hs_ep->dir_in) { if (hs_ep->dir_in) {
epreg = DIEPCTL(index); epreg = DIEPCTL(index);
epctl = readl(hs->regs + epreg); epctl = dwc2_readl(hs->regs + epreg);
if (value) { if (value) {
epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
...@@ -2890,11 +2890,11 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value) ...@@ -2890,11 +2890,11 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value)
xfertype == DXEPCTL_EPTYPE_INTERRUPT) xfertype == DXEPCTL_EPTYPE_INTERRUPT)
epctl |= DXEPCTL_SETD0PID; epctl |= DXEPCTL_SETD0PID;
} }
writel(epctl, hs->regs + epreg); dwc2_writel(epctl, hs->regs + epreg);
} else { } else {
epreg = DOEPCTL(index); epreg = DOEPCTL(index);
epctl = readl(hs->regs + epreg); epctl = dwc2_readl(hs->regs + epreg);
if (value) if (value)
epctl |= DXEPCTL_STALL; epctl |= DXEPCTL_STALL;
...@@ -2905,7 +2905,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value) ...@@ -2905,7 +2905,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value)
xfertype == DXEPCTL_EPTYPE_INTERRUPT) xfertype == DXEPCTL_EPTYPE_INTERRUPT)
epctl |= DXEPCTL_SETD0PID; epctl |= DXEPCTL_SETD0PID;
} }
writel(epctl, hs->regs + epreg); dwc2_writel(epctl, hs->regs + epreg);
} }
hs_ep->halted = value; hs_ep->halted = value;
...@@ -2996,15 +2996,15 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) ...@@ -2996,15 +2996,15 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
u32 trdtim; u32 trdtim;
/* unmask subset of endpoint interrupts */ /* unmask subset of endpoint interrupts */
writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
hsotg->regs + DIEPMSK); hsotg->regs + DIEPMSK);
writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
hsotg->regs + DOEPMSK); hsotg->regs + DOEPMSK);
writel(0, hsotg->regs + DAINTMSK); dwc2_writel(0, hsotg->regs + DAINTMSK);
/* Be in disconnected state until gadget is registered */ /* Be in disconnected state until gadget is registered */
__orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
...@@ -3012,14 +3012,14 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) ...@@ -3012,14 +3012,14 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
/* setup fifos */ /* setup fifos */
dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
readl(hsotg->regs + GRXFSIZ), dwc2_readl(hsotg->regs + GRXFSIZ),
readl(hsotg->regs + GNPTXFSIZ)); dwc2_readl(hsotg->regs + GNPTXFSIZ));
dwc2_hsotg_init_fifo(hsotg); dwc2_hsotg_init_fifo(hsotg);
/* set the PLL on, remove the HNP/SRP and set the PHY */ /* set the PLL on, remove the HNP/SRP and set the PHY */
trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
(trdtim << GUSBCFG_USBTRDTIM_SHIFT), (trdtim << GUSBCFG_USBTRDTIM_SHIFT),
hsotg->regs + GUSBCFG); hsotg->regs + GUSBCFG);
...@@ -3310,9 +3310,9 @@ static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, ...@@ -3310,9 +3310,9 @@ static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
if (using_dma(hsotg)) { if (using_dma(hsotg)) {
u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
if (dir_in) if (dir_in)
writel(next, hsotg->regs + DIEPCTL(epnum)); dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
else else
writel(next, hsotg->regs + DOEPCTL(epnum)); dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
} }
} }
...@@ -3330,7 +3330,7 @@ static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) ...@@ -3330,7 +3330,7 @@ static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
/* check hardware configuration */ /* check hardware configuration */
cfg = readl(hsotg->regs + GHWCFG2); cfg = dwc2_readl(hsotg->regs + GHWCFG2);
hsotg->num_of_eps = (cfg >> GHWCFG2_NUM_DEV_EP_SHIFT) & 0xF; hsotg->num_of_eps = (cfg >> GHWCFG2_NUM_DEV_EP_SHIFT) & 0xF;
/* Add ep0 */ /* Add ep0 */
hsotg->num_of_eps++; hsotg->num_of_eps++;
...@@ -3342,7 +3342,7 @@ static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) ...@@ -3342,7 +3342,7 @@ static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
/* Same dwc2_hsotg_ep is used in both directions for ep0 */ /* Same dwc2_hsotg_ep is used in both directions for ep0 */
hsotg->eps_out[0] = hsotg->eps_in[0]; hsotg->eps_out[0] = hsotg->eps_in[0];
cfg = readl(hsotg->regs + GHWCFG1); cfg = dwc2_readl(hsotg->regs + GHWCFG1);
for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
ep_type = cfg & 3; ep_type = cfg & 3;
/* Direction in or both */ /* Direction in or both */
...@@ -3361,10 +3361,10 @@ static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) ...@@ -3361,10 +3361,10 @@ static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
} }
} }
cfg = readl(hsotg->regs + GHWCFG3); cfg = dwc2_readl(hsotg->regs + GHWCFG3);
hsotg->fifo_mem = (cfg >> GHWCFG3_DFIFO_DEPTH_SHIFT); hsotg->fifo_mem = (cfg >> GHWCFG3_DFIFO_DEPTH_SHIFT);
cfg = readl(hsotg->regs + GHWCFG4); cfg = dwc2_readl(hsotg->regs + GHWCFG4);
hsotg->dedicated_fifos = (cfg >> GHWCFG4_DED_FIFO_SHIFT) & 1; hsotg->dedicated_fifos = (cfg >> GHWCFG4_DED_FIFO_SHIFT) & 1;
dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
...@@ -3387,19 +3387,19 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) ...@@ -3387,19 +3387,19 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
int idx; int idx;
dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
readl(regs + DCFG), readl(regs + DCTL), dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
readl(regs + DIEPMSK)); dwc2_readl(regs + DIEPMSK));
dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
readl(regs + GAHBCFG), readl(regs + GHWCFG1)); dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ)); dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
/* show periodic fifo settings */ /* show periodic fifo settings */
for (idx = 1; idx < hsotg->num_of_eps; idx++) { for (idx = 1; idx < hsotg->num_of_eps; idx++) {
val = readl(regs + DPTXFSIZN(idx)); val = dwc2_readl(regs + DPTXFSIZN(idx));
dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
val >> FIFOSIZE_DEPTH_SHIFT, val >> FIFOSIZE_DEPTH_SHIFT,
val & FIFOSIZE_STARTADDR_MASK); val & FIFOSIZE_STARTADDR_MASK);
...@@ -3408,21 +3408,21 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) ...@@ -3408,21 +3408,21 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
for (idx = 0; idx < hsotg->num_of_eps; idx++) { for (idx = 0; idx < hsotg->num_of_eps; idx++) {
dev_info(dev, dev_info(dev,
"ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
readl(regs + DIEPCTL(idx)), dwc2_readl(regs + DIEPCTL(idx)),
readl(regs + DIEPTSIZ(idx)), dwc2_readl(regs + DIEPTSIZ(idx)),
readl(regs + DIEPDMA(idx))); dwc2_readl(regs + DIEPDMA(idx)));
val = readl(regs + DOEPCTL(idx)); val = dwc2_readl(regs + DOEPCTL(idx));
dev_info(dev, dev_info(dev,
"ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
idx, readl(regs + DOEPCTL(idx)), idx, dwc2_readl(regs + DOEPCTL(idx)),
readl(regs + DOEPTSIZ(idx)), dwc2_readl(regs + DOEPTSIZ(idx)),
readl(regs + DOEPDMA(idx))); dwc2_readl(regs + DOEPDMA(idx)));
} }
dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE)); dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
#endif #endif
} }
......
drivers/usb/dwc2/hcd.c
View file @ 95c8bc36
...@@ -80,10 +80,10 @@ static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, ...@@ -80,10 +80,10 @@ static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
if (chan == NULL) if (chan == NULL)
return; return;
hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num)); hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num)); hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
...@@ -207,7 +207,7 @@ void dwc2_hcd_start(struct dwc2_hsotg *hsotg) ...@@ -207,7 +207,7 @@ void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
*/ */
hprt0 = dwc2_read_hprt0(hsotg); hprt0 = dwc2_read_hprt0(hsotg);
hprt0 |= HPRT0_RST; hprt0 |= HPRT0_RST;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
} }
queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
...@@ -228,11 +228,11 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) ...@@ -228,11 +228,11 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
channel = hsotg->hc_ptr_array[i]; channel = hsotg->hc_ptr_array[i];
if (!list_empty(&channel->hc_list_entry)) if (!list_empty(&channel->hc_list_entry))
continue; continue;
hcchar = readl(hsotg->regs + HCCHAR(i)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
if (hcchar & HCCHAR_CHENA) { if (hcchar & HCCHAR_CHENA) {
hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
hcchar |= HCCHAR_CHDIS; hcchar |= HCCHAR_CHDIS;
writel(hcchar, hsotg->regs + HCCHAR(i)); dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
} }
} }
} }
...@@ -241,11 +241,11 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) ...@@ -241,11 +241,11 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
channel = hsotg->hc_ptr_array[i]; channel = hsotg->hc_ptr_array[i];
if (!list_empty(&channel->hc_list_entry)) if (!list_empty(&channel->hc_list_entry))
continue; continue;
hcchar = readl(hsotg->regs + HCCHAR(i)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
if (hcchar & HCCHAR_CHENA) { if (hcchar & HCCHAR_CHENA) {
/* Halt the channel */ /* Halt the channel */
hcchar |= HCCHAR_CHDIS; hcchar |= HCCHAR_CHDIS;
writel(hcchar, hsotg->regs + HCCHAR(i)); dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
} }
dwc2_hc_cleanup(hsotg, channel); dwc2_hc_cleanup(hsotg, channel);
...@@ -287,11 +287,11 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) ...@@ -287,11 +287,11 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
* interrupt mask and status bits and disabling subsequent host * interrupt mask and status bits and disabling subsequent host
* channel interrupts. * channel interrupts.
*/ */
intr = readl(hsotg->regs + GINTMSK); intr = dwc2_readl(hsotg->regs + GINTMSK);
intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
writel(intr, hsotg->regs + GINTMSK); dwc2_writel(intr, hsotg->regs + GINTMSK);
intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
writel(intr, hsotg->regs + GINTSTS); dwc2_writel(intr, hsotg->regs + GINTSTS);
/* /*
* Turn off the vbus power only if the core has transitioned to device * Turn off the vbus power only if the core has transitioned to device
...@@ -301,7 +301,7 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) ...@@ -301,7 +301,7 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
if (dwc2_is_device_mode(hsotg)) { if (dwc2_is_device_mode(hsotg)) {
if (hsotg->op_state != OTG_STATE_A_SUSPEND) { if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
writel(0, hsotg->regs + HPRT0); dwc2_writel(0, hsotg->regs + HPRT0);
} }
dwc2_disable_host_interrupts(hsotg); dwc2_disable_host_interrupts(hsotg);
...@@ -354,7 +354,7 @@ void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) ...@@ -354,7 +354,7 @@ void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
/* Turn off the vbus power */ /* Turn off the vbus power */
dev_dbg(hsotg->dev, "PortPower off\n"); dev_dbg(hsotg->dev, "PortPower off\n");
writel(0, hsotg->regs + HPRT0); dwc2_writel(0, hsotg->regs + HPRT0);
} }
/* Caller must hold driver lock */ /* Caller must hold driver lock */
...@@ -378,7 +378,7 @@ static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, ...@@ -378,7 +378,7 @@ static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
if ((dev_speed == USB_SPEED_LOW) && if ((dev_speed == USB_SPEED_LOW) &&
(hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
(hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
u32 hprt0 = readl(hsotg->regs + HPRT0); u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
if (prtspd == HPRT0_SPD_FULL_SPEED) if (prtspd == HPRT0_SPD_FULL_SPEED)
...@@ -397,7 +397,7 @@ static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, ...@@ -397,7 +397,7 @@ static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
return retval; return retval;
} }
intr_mask = readl(hsotg->regs + GINTMSK); intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
if (!(intr_mask & GINTSTS_SOF)) { if (!(intr_mask & GINTSTS_SOF)) {
enum dwc2_transaction_type tr_type; enum dwc2_transaction_type tr_type;
...@@ -1070,7 +1070,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -1070,7 +1070,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
if (dbg_perio()) if (dbg_perio())
dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
tx_status = readl(hsotg->regs + HPTXSTS); tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT; TXSTS_QSPCAVAIL_SHIFT;
fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
...@@ -1085,7 +1085,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -1085,7 +1085,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
qh_ptr = hsotg->periodic_sched_assigned.next; qh_ptr = hsotg->periodic_sched_assigned.next;
while (qh_ptr != &hsotg->periodic_sched_assigned) { while (qh_ptr != &hsotg->periodic_sched_assigned) {
tx_status = readl(hsotg->regs + HPTXSTS); tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT; TXSTS_QSPCAVAIL_SHIFT;
if (qspcavail == 0) { if (qspcavail == 0) {
...@@ -1145,7 +1145,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -1145,7 +1145,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
} }
if (hsotg->core_params->dma_enable <= 0) { if (hsotg->core_params->dma_enable <= 0) {
tx_status = readl(hsotg->regs + HPTXSTS); tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT; TXSTS_QSPCAVAIL_SHIFT;
fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
...@@ -1168,9 +1168,9 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -1168,9 +1168,9 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
* level to ensure that new requests are loaded as * level to ensure that new requests are loaded as
* soon as possible.) * soon as possible.)
*/ */
gintmsk = readl(hsotg->regs + GINTMSK); gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gintmsk |= GINTSTS_PTXFEMP; gintmsk |= GINTSTS_PTXFEMP;
writel(gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
} else { } else {
/* /*
* Disable the Tx FIFO empty interrupt since there are * Disable the Tx FIFO empty interrupt since there are
...@@ -1179,9 +1179,9 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -1179,9 +1179,9 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
* handlers to queue more transactions as transfer * handlers to queue more transactions as transfer
* states change. * states change.
*/ */
gintmsk = readl(hsotg->regs + GINTMSK); gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gintmsk &= ~GINTSTS_PTXFEMP; gintmsk &= ~GINTSTS_PTXFEMP;
writel(gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
} }
} }
} }
...@@ -1210,7 +1210,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -1210,7 +1210,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
tx_status = readl(hsotg->regs + GNPTXSTS); tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT; TXSTS_QSPCAVAIL_SHIFT;
fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
...@@ -1233,7 +1233,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -1233,7 +1233,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
* available in the request queue or the Tx FIFO * available in the request queue or the Tx FIFO
*/ */
do { do {
tx_status = readl(hsotg->regs + GNPTXSTS); tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT; TXSTS_QSPCAVAIL_SHIFT;
if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
...@@ -1270,7 +1270,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -1270,7 +1270,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
} while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
if (hsotg->core_params->dma_enable <= 0) { if (hsotg->core_params->dma_enable <= 0) {
tx_status = readl(hsotg->regs + GNPTXSTS); tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT; TXSTS_QSPCAVAIL_SHIFT;
fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
...@@ -1290,9 +1290,9 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -1290,9 +1290,9 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
* level to ensure that new requests are loaded as * level to ensure that new requests are loaded as
* soon as possible.) * soon as possible.)
*/ */
gintmsk = readl(hsotg->regs + GINTMSK); gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gintmsk |= GINTSTS_NPTXFEMP; gintmsk |= GINTSTS_NPTXFEMP;
writel(gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
} else { } else {
/* /*
* Disable the Tx FIFO empty interrupt since there are * Disable the Tx FIFO empty interrupt since there are
...@@ -1301,9 +1301,9 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -1301,9 +1301,9 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
* handlers to queue more transactions as transfer * handlers to queue more transactions as transfer
* states change. * states change.
*/ */
gintmsk = readl(hsotg->regs + GINTMSK); gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gintmsk &= ~GINTSTS_NPTXFEMP; gintmsk &= ~GINTSTS_NPTXFEMP;
writel(gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
} }
} }
} }
...@@ -1341,10 +1341,10 @@ void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, ...@@ -1341,10 +1341,10 @@ void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
* Ensure NP Tx FIFO empty interrupt is disabled when * Ensure NP Tx FIFO empty interrupt is disabled when
* there are no non-periodic transfers to process * there are no non-periodic transfers to process
*/ */
u32 gintmsk = readl(hsotg->regs + GINTMSK); u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gintmsk &= ~GINTSTS_NPTXFEMP; gintmsk &= ~GINTSTS_NPTXFEMP;
writel(gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
} }
} }
} }
...@@ -1358,7 +1358,7 @@ static void dwc2_conn_id_status_change(struct work_struct *work) ...@@ -1358,7 +1358,7 @@ static void dwc2_conn_id_status_change(struct work_struct *work)
dev_dbg(hsotg->dev, "%s()\n", __func__); dev_dbg(hsotg->dev, "%s()\n", __func__);
gotgctl = readl(hsotg->regs + GOTGCTL); gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
!!(gotgctl & GOTGCTL_CONID_B)); !!(gotgctl & GOTGCTL_CONID_B));
...@@ -1421,9 +1421,9 @@ static void dwc2_wakeup_detected(unsigned long data) ...@@ -1421,9 +1421,9 @@ static void dwc2_wakeup_detected(unsigned long data)
hprt0 = dwc2_read_hprt0(hsotg); hprt0 = dwc2_read_hprt0(hsotg);
dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
hprt0 &= ~HPRT0_RES; hprt0 &= ~HPRT0_RES;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
readl(hsotg->regs + HPRT0)); dwc2_readl(hsotg->regs + HPRT0));
dwc2_hcd_rem_wakeup(hsotg); dwc2_hcd_rem_wakeup(hsotg);
...@@ -1451,30 +1451,30 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) ...@@ -1451,30 +1451,30 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
spin_lock_irqsave(&hsotg->lock, flags); spin_lock_irqsave(&hsotg->lock, flags);
if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
gotgctl = readl(hsotg->regs + GOTGCTL); gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
gotgctl |= GOTGCTL_HSTSETHNPEN; gotgctl |= GOTGCTL_HSTSETHNPEN;
writel(gotgctl, hsotg->regs + GOTGCTL); dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
hsotg->op_state = OTG_STATE_A_SUSPEND; hsotg->op_state = OTG_STATE_A_SUSPEND;
} }
hprt0 = dwc2_read_hprt0(hsotg); hprt0 = dwc2_read_hprt0(hsotg);
hprt0 |= HPRT0_SUSP; hprt0 |= HPRT0_SUSP;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
/* Update lx_state */ /* Update lx_state */
hsotg->lx_state = DWC2_L2; hsotg->lx_state = DWC2_L2;
/* Suspend the Phy Clock */ /* Suspend the Phy Clock */
pcgctl = readl(hsotg->regs + PCGCTL); pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
pcgctl |= PCGCTL_STOPPCLK; pcgctl |= PCGCTL_STOPPCLK;
writel(pcgctl, hsotg->regs + PCGCTL); dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
udelay(10); udelay(10);
/* For HNP the bus must be suspended for at least 200ms */ /* For HNP the bus must be suspended for at least 200ms */
if (dwc2_host_is_b_hnp_enabled(hsotg)) { if (dwc2_host_is_b_hnp_enabled(hsotg)) {
pcgctl = readl(hsotg->regs + PCGCTL); pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
pcgctl &= ~PCGCTL_STOPPCLK; pcgctl &= ~PCGCTL_STOPPCLK;
writel(pcgctl, hsotg->regs + PCGCTL); dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
spin_unlock_irqrestore(&hsotg->lock, flags); spin_unlock_irqrestore(&hsotg->lock, flags);
...@@ -1523,23 +1523,23 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, ...@@ -1523,23 +1523,23 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
"ClearPortFeature USB_PORT_FEAT_ENABLE\n"); "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
hprt0 = dwc2_read_hprt0(hsotg); hprt0 = dwc2_read_hprt0(hsotg);
hprt0 |= HPRT0_ENA; hprt0 |= HPRT0_ENA;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
break; break;
case USB_PORT_FEAT_SUSPEND: case USB_PORT_FEAT_SUSPEND:
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
writel(0, hsotg->regs + PCGCTL); dwc2_writel(0, hsotg->regs + PCGCTL);
usleep_range(20000, 40000); usleep_range(20000, 40000);
hprt0 = dwc2_read_hprt0(hsotg); hprt0 = dwc2_read_hprt0(hsotg);
hprt0 |= HPRT0_RES; hprt0 |= HPRT0_RES;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
hprt0 &= ~HPRT0_SUSP; hprt0 &= ~HPRT0_SUSP;
msleep(USB_RESUME_TIMEOUT); msleep(USB_RESUME_TIMEOUT);
hprt0 &= ~HPRT0_RES; hprt0 &= ~HPRT0_RES;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
break; break;
case USB_PORT_FEAT_POWER: case USB_PORT_FEAT_POWER:
...@@ -1547,7 +1547,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, ...@@ -1547,7 +1547,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
"ClearPortFeature USB_PORT_FEAT_POWER\n"); "ClearPortFeature USB_PORT_FEAT_POWER\n");
hprt0 = dwc2_read_hprt0(hsotg); hprt0 = dwc2_read_hprt0(hsotg);
hprt0 &= ~HPRT0_PWR; hprt0 &= ~HPRT0_PWR;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
break; break;
case USB_PORT_FEAT_INDICATOR: case USB_PORT_FEAT_INDICATOR:
...@@ -1668,7 +1668,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, ...@@ -1668,7 +1668,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
break; break;
} }
hprt0 = readl(hsotg->regs + HPRT0); hprt0 = dwc2_readl(hsotg->regs + HPRT0);
dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
if (hprt0 & HPRT0_CONNSTS) if (hprt0 & HPRT0_CONNSTS)
...@@ -1733,18 +1733,18 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, ...@@ -1733,18 +1733,18 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
"SetPortFeature - USB_PORT_FEAT_POWER\n"); "SetPortFeature - USB_PORT_FEAT_POWER\n");
hprt0 = dwc2_read_hprt0(hsotg); hprt0 = dwc2_read_hprt0(hsotg);
hprt0 |= HPRT0_PWR; hprt0 |= HPRT0_PWR;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
break; break;
case USB_PORT_FEAT_RESET: case USB_PORT_FEAT_RESET:
hprt0 = dwc2_read_hprt0(hsotg); hprt0 = dwc2_read_hprt0(hsotg);
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"SetPortFeature - USB_PORT_FEAT_RESET\n"); "SetPortFeature - USB_PORT_FEAT_RESET\n");
pcgctl = readl(hsotg->regs + PCGCTL); pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
writel(pcgctl, hsotg->regs + PCGCTL); dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
/* ??? Original driver does this */ /* ??? Original driver does this */
writel(0, hsotg->regs + PCGCTL); dwc2_writel(0, hsotg->regs + PCGCTL);
hprt0 = dwc2_read_hprt0(hsotg); hprt0 = dwc2_read_hprt0(hsotg);
/* Clear suspend bit if resetting from suspend state */ /* Clear suspend bit if resetting from suspend state */
...@@ -1759,13 +1759,13 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, ...@@ -1759,13 +1759,13 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
hprt0 |= HPRT0_PWR | HPRT0_RST; hprt0 |= HPRT0_PWR | HPRT0_RST;
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"In host mode, hprt0=%08x\n", hprt0); "In host mode, hprt0=%08x\n", hprt0);
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
} }
/* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
usleep_range(50000, 70000); usleep_range(50000, 70000);
hprt0 &= ~HPRT0_RST; hprt0 &= ~HPRT0_RST;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
hsotg->lx_state = DWC2_L0; /* Now back to On state */ hsotg->lx_state = DWC2_L0; /* Now back to On state */
break; break;
...@@ -1781,7 +1781,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, ...@@ -1781,7 +1781,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
"SetPortFeature - USB_PORT_FEAT_TEST\n"); "SetPortFeature - USB_PORT_FEAT_TEST\n");
hprt0 &= ~HPRT0_TSTCTL_MASK; hprt0 &= ~HPRT0_TSTCTL_MASK;
hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
break; break;
default: default:
...@@ -1838,7 +1838,7 @@ static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) ...@@ -1838,7 +1838,7 @@ static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
{ {
u32 hfnum = readl(hsotg->regs + HFNUM); u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
#ifdef DWC2_DEBUG_SOF #ifdef DWC2_DEBUG_SOF
dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
...@@ -1941,11 +1941,11 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) ...@@ -1941,11 +1941,11 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
if (chan->xfer_started) { if (chan->xfer_started) {
u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
hfnum = readl(hsotg->regs + HFNUM); hfnum = dwc2_readl(hsotg->regs + HFNUM);
hcchar = readl(hsotg->regs + HCCHAR(i)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
hctsiz = readl(hsotg->regs + HCTSIZ(i)); hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
hcint = readl(hsotg->regs + HCINT(i)); hcint = dwc2_readl(hsotg->regs + HCINT(i));
hcintmsk = readl(hsotg->regs + HCINTMSK(i)); hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
...@@ -1993,12 +1993,12 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) ...@@ -1993,12 +1993,12 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, " periodic_channels: %d\n", dev_dbg(hsotg->dev, " periodic_channels: %d\n",
hsotg->periodic_channels); hsotg->periodic_channels);
dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
np_tx_status = readl(hsotg->regs + GNPTXSTS); np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
(np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
(np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
p_tx_status = readl(hsotg->regs + HPTXSTS); p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
(p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
...@@ -2262,7 +2262,7 @@ static void dwc2_hcd_reset_func(struct work_struct *work) ...@@ -2262,7 +2262,7 @@ static void dwc2_hcd_reset_func(struct work_struct *work)
dev_dbg(hsotg->dev, "USB RESET function called\n"); dev_dbg(hsotg->dev, "USB RESET function called\n");
hprt0 = dwc2_read_hprt0(hsotg); hprt0 = dwc2_read_hprt0(hsotg);
hprt0 &= ~HPRT0_RST; hprt0 &= ~HPRT0_RST;
writel(hprt0, hsotg->regs + HPRT0); dwc2_writel(hprt0, hsotg->regs + HPRT0);
hsotg->flags.b.port_reset_change = 1; hsotg->flags.b.port_reset_change = 1;
} }
...@@ -2790,17 +2790,17 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) ...@@ -2790,17 +2790,17 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
hsotg->status_buf = NULL; hsotg->status_buf = NULL;
} }
ahbcfg = readl(hsotg->regs + GAHBCFG); ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
/* Disable all interrupts */ /* Disable all interrupts */
ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
writel(ahbcfg, hsotg->regs + GAHBCFG); dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
writel(0, hsotg->regs + GINTMSK); dwc2_writel(0, hsotg->regs + GINTMSK);
if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
dctl = readl(hsotg->regs + DCTL); dctl = dwc2_readl(hsotg->regs + DCTL);
dctl |= DCTL_SFTDISCON; dctl |= DCTL_SFTDISCON;
writel(dctl, hsotg->regs + DCTL); dwc2_writel(dctl, hsotg->regs + DCTL);
} }
if (hsotg->wq_otg) { if (hsotg->wq_otg) {
...@@ -2841,7 +2841,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) ...@@ -2841,7 +2841,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
retval = -ENOMEM; retval = -ENOMEM;
hcfg = readl(hsotg->regs + HCFG); hcfg = dwc2_readl(hsotg->regs + HCFG);
dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
......
drivers/usb/dwc2/hcd.h
View file @ 95c8bc36
...@@ -371,10 +371,10 @@ static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) ...@@ -371,10 +371,10 @@ static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
*/ */
static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
{ {
u32 mask = readl(hsotg->regs + HCINTMSK(chnum)); u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
mask &= ~intr; mask &= ~intr;
writel(mask, hsotg->regs + HCINTMSK(chnum)); dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum));
} }
/* /*
...@@ -382,11 +382,11 @@ static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) ...@@ -382,11 +382,11 @@ static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
*/ */
static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
{ {
return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
} }
static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
{ {
return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
} }
/* /*
...@@ -395,7 +395,7 @@ static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) ...@@ -395,7 +395,7 @@ static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
*/ */
static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
{ {
u32 hprt0 = readl(hsotg->regs + HPRT0); u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
return hprt0; return hprt0;
...@@ -580,7 +580,8 @@ static inline u16 dwc2_micro_frame_num(u16 frame) ...@@ -580,7 +580,8 @@ static inline u16 dwc2_micro_frame_num(u16 frame)
*/ */
static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
{ {
return readl(hsotg->regs + GINTSTS) & readl(hsotg->regs + GINTMSK); return dwc2_readl(hsotg->regs + GINTSTS) &
dwc2_readl(hsotg->regs + GINTMSK);
} }
static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
...@@ -732,7 +733,7 @@ do { \ ...@@ -732,7 +733,7 @@ do { \
qtd_list_entry); \ qtd_list_entry); \
if (usb_pipeint(_qtd_->urb->pipe) && \ if (usb_pipeint(_qtd_->urb->pipe) && \
(_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \
_hfnum_.d32 = readl((_hcd_)->regs + HFNUM); \ _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \
switch (_hfnum_.b.frnum & 0x7) { \ switch (_hfnum_.b.frnum & 0x7) { \
case 7: \ case 7: \
(_hcd_)->hfnum_7_samples_##_letter_++; \ (_hcd_)->hfnum_7_samples_##_letter_++; \
......
drivers/usb/dwc2/hcd_ddma.c
View file @ 95c8bc36
...@@ -169,19 +169,19 @@ static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en) ...@@ -169,19 +169,19 @@ static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en)
spin_lock_irqsave(&hsotg->lock, flags); spin_lock_irqsave(&hsotg->lock, flags);
hcfg = readl(hsotg->regs + HCFG); hcfg = dwc2_readl(hsotg->regs + HCFG);
if (hcfg & HCFG_PERSCHEDENA) { if (hcfg & HCFG_PERSCHEDENA) {
/* already enabled */ /* already enabled */
spin_unlock_irqrestore(&hsotg->lock, flags); spin_unlock_irqrestore(&hsotg->lock, flags);
return; return;
} }
writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR); dwc2_writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR);
hcfg &= ~HCFG_FRLISTEN_MASK; hcfg &= ~HCFG_FRLISTEN_MASK;
hcfg |= fr_list_en | HCFG_PERSCHEDENA; hcfg |= fr_list_en | HCFG_PERSCHEDENA;
dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n"); dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n");
writel(hcfg, hsotg->regs + HCFG); dwc2_writel(hcfg, hsotg->regs + HCFG);
spin_unlock_irqrestore(&hsotg->lock, flags); spin_unlock_irqrestore(&hsotg->lock, flags);
} }
...@@ -193,7 +193,7 @@ static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg) ...@@ -193,7 +193,7 @@ static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg)
spin_lock_irqsave(&hsotg->lock, flags); spin_lock_irqsave(&hsotg->lock, flags);
hcfg = readl(hsotg->regs + HCFG); hcfg = dwc2_readl(hsotg->regs + HCFG);
if (!(hcfg & HCFG_PERSCHEDENA)) { if (!(hcfg & HCFG_PERSCHEDENA)) {
/* already disabled */ /* already disabled */
spin_unlock_irqrestore(&hsotg->lock, flags); spin_unlock_irqrestore(&hsotg->lock, flags);
...@@ -202,7 +202,7 @@ static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg) ...@@ -202,7 +202,7 @@ static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg)
hcfg &= ~HCFG_PERSCHEDENA; hcfg &= ~HCFG_PERSCHEDENA;
dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n"); dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n");
writel(hcfg, hsotg->regs + HCFG); dwc2_writel(hcfg, hsotg->regs + HCFG);
spin_unlock_irqrestore(&hsotg->lock, flags); spin_unlock_irqrestore(&hsotg->lock, flags);
} }
......
drivers/usb/dwc2/hcd_intr.c
View file @ 95c8bc36
...@@ -148,7 +148,7 @@ static void dwc2_sof_intr(struct dwc2_hsotg *hsotg) ...@@ -148,7 +148,7 @@ static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
dwc2_hcd_queue_transactions(hsotg, tr_type); dwc2_hcd_queue_transactions(hsotg, tr_type);
/* Clear interrupt */ /* Clear interrupt */
writel(GINTSTS_SOF, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
} }
/* /*
...@@ -164,7 +164,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) ...@@ -164,7 +164,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
if (dbg_perio()) if (dbg_perio())
dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
grxsts = readl(hsotg->regs + GRXSTSP); grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
chan = hsotg->hc_ptr_array[chnum]; chan = hsotg->hc_ptr_array[chnum];
if (!chan) { if (!chan) {
...@@ -247,11 +247,11 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, ...@@ -247,11 +247,11 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
/* Every time when port enables calculate HFIR.FrInterval */ /* Every time when port enables calculate HFIR.FrInterval */
hfir = readl(hsotg->regs + HFIR); hfir = dwc2_readl(hsotg->regs + HFIR);
hfir &= ~HFIR_FRINT_MASK; hfir &= ~HFIR_FRINT_MASK;
hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
HFIR_FRINT_MASK; HFIR_FRINT_MASK;
writel(hfir, hsotg->regs + HFIR); dwc2_writel(hfir, hsotg->regs + HFIR);
/* Check if we need to adjust the PHY clock speed for low power */ /* Check if we need to adjust the PHY clock speed for low power */
if (!params->host_support_fs_ls_low_power) { if (!params->host_support_fs_ls_low_power) {
...@@ -260,7 +260,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, ...@@ -260,7 +260,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
return; return;
} }
usbcfg = readl(hsotg->regs + GUSBCFG); usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
...@@ -268,11 +268,11 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, ...@@ -268,11 +268,11 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
/* Set PHY low power clock select for FS/LS devices */ /* Set PHY low power clock select for FS/LS devices */
usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
writel(usbcfg, hsotg->regs + GUSBCFG); dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
do_reset = 1; do_reset = 1;
} }
hcfg = readl(hsotg->regs + HCFG); hcfg = dwc2_readl(hsotg->regs + HCFG);
fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >> fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
HCFG_FSLSPCLKSEL_SHIFT; HCFG_FSLSPCLKSEL_SHIFT;
...@@ -286,7 +286,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, ...@@ -286,7 +286,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ; fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
hcfg &= ~HCFG_FSLSPCLKSEL_MASK; hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
writel(hcfg, hsotg->regs + HCFG); dwc2_writel(hcfg, hsotg->regs + HCFG);
do_reset = 1; do_reset = 1;
} }
} else { } else {
...@@ -297,7 +297,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, ...@@ -297,7 +297,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ; fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
hcfg &= ~HCFG_FSLSPCLKSEL_MASK; hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
writel(hcfg, hsotg->regs + HCFG); dwc2_writel(hcfg, hsotg->regs + HCFG);
do_reset = 1; do_reset = 1;
} }
} }
...@@ -305,7 +305,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, ...@@ -305,7 +305,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
/* Not low power */ /* Not low power */
if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
writel(usbcfg, hsotg->regs + GUSBCFG); dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
do_reset = 1; do_reset = 1;
} }
} }
...@@ -332,7 +332,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg) ...@@ -332,7 +332,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
hprt0 = readl(hsotg->regs + HPRT0); hprt0 = dwc2_readl(hsotg->regs + HPRT0);
hprt0_modify = hprt0; hprt0_modify = hprt0;
/* /*
...@@ -388,7 +388,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg) ...@@ -388,7 +388,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
} }
/* Clear Port Interrupts */ /* Clear Port Interrupts */
writel(hprt0_modify, hsotg->regs + HPRT0); dwc2_writel(hprt0_modify, hsotg->regs + HPRT0);
} }
/* /*
...@@ -408,7 +408,7 @@ static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg, ...@@ -408,7 +408,7 @@ static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
{ {
u32 hctsiz, count, length; u32 hctsiz, count, length;
hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
if (halt_status == DWC2_HC_XFER_COMPLETE) { if (halt_status == DWC2_HC_XFER_COMPLETE) {
if (chan->ep_is_in) { if (chan->ep_is_in) {
...@@ -491,7 +491,7 @@ static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg, ...@@ -491,7 +491,7 @@ static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
urb->status = 0; urb->status = 0;
} }
hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
__func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
...@@ -514,7 +514,7 @@ void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, ...@@ -514,7 +514,7 @@ void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
struct dwc2_host_chan *chan, int chnum, struct dwc2_host_chan *chan, int chnum,
struct dwc2_qtd *qtd) struct dwc2_qtd *qtd)
{ {
u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
...@@ -771,9 +771,9 @@ static void dwc2_release_channel(struct dwc2_hsotg *hsotg, ...@@ -771,9 +771,9 @@ static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
} }
} }
haintmsk = readl(hsotg->regs + HAINTMSK); haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
haintmsk &= ~(1 << chan->hc_num); haintmsk &= ~(1 << chan->hc_num);
writel(haintmsk, hsotg->regs + HAINTMSK); dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
/* Try to queue more transfers now that there's a free channel */ /* Try to queue more transfers now that there's a free channel */
tr_type = dwc2_hcd_select_transactions(hsotg); tr_type = dwc2_hcd_select_transactions(hsotg);
...@@ -820,9 +820,9 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, ...@@ -820,9 +820,9 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
* is enabled so that the non-periodic schedule will * is enabled so that the non-periodic schedule will
* be processed * be processed
*/ */
gintmsk = readl(hsotg->regs + GINTMSK); gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gintmsk |= GINTSTS_NPTXFEMP; gintmsk |= GINTSTS_NPTXFEMP;
writel(gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
} else { } else {
dev_vdbg(hsotg->dev, "isoc/intr\n"); dev_vdbg(hsotg->dev, "isoc/intr\n");
/* /*
...@@ -839,9 +839,9 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, ...@@ -839,9 +839,9 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
* enabled so that the periodic schedule will be * enabled so that the periodic schedule will be
* processed * processed
*/ */
gintmsk = readl(hsotg->regs + GINTMSK); gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
gintmsk |= GINTSTS_PTXFEMP; gintmsk |= GINTSTS_PTXFEMP;
writel(gintmsk, hsotg->regs + GINTMSK); dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
} }
} }
} }
...@@ -906,7 +906,7 @@ static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg, ...@@ -906,7 +906,7 @@ static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
struct dwc2_qtd *qtd, struct dwc2_qtd *qtd,
enum dwc2_halt_status halt_status) enum dwc2_halt_status halt_status)
{ {
u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
qtd->error_count = 0; qtd->error_count = 0;
...@@ -1184,7 +1184,7 @@ static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg, ...@@ -1184,7 +1184,7 @@ static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
urb->actual_length += xfer_length; urb->actual_length += xfer_length;
hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
__func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
...@@ -1505,10 +1505,10 @@ static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg, ...@@ -1505,10 +1505,10 @@ static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
dwc2_hc_handle_tt_clear(hsotg, chan, qtd); dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
hcchar = readl(hsotg->regs + HCCHAR(chnum)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
hcsplt = readl(hsotg->regs + HCSPLT(chnum)); hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
hc_dma = readl(hsotg->regs + HCDMA(chnum)); hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
...@@ -1721,10 +1721,10 @@ static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg, ...@@ -1721,10 +1721,10 @@ static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
* This code is here only as a check. This condition should * This code is here only as a check. This condition should
* never happen. Ignore the halt if it does occur. * never happen. Ignore the halt if it does occur.
*/ */
hcchar = readl(hsotg->regs + HCCHAR(chnum)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
hcsplt = readl(hsotg->regs + HCSPLT(chnum)); hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
__func__); __func__);
...@@ -1748,7 +1748,7 @@ static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg, ...@@ -1748,7 +1748,7 @@ static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
* when the halt interrupt occurs. Halt the channel again if it does * when the halt interrupt occurs. Halt the channel again if it does
* occur. * occur.
*/ */
hcchar = readl(hsotg->regs + HCCHAR(chnum)); hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
if (hcchar & HCCHAR_CHDIS) { if (hcchar & HCCHAR_CHDIS) {
dev_warn(hsotg->dev, dev_warn(hsotg->dev,
"%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
...@@ -1808,7 +1808,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, ...@@ -1808,7 +1808,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
return; return;
} }
hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
if (chan->hcint & HCINTMSK_XFERCOMPL) { if (chan->hcint & HCINTMSK_XFERCOMPL) {
/* /*
...@@ -1903,7 +1903,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, ...@@ -1903,7 +1903,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
dev_err(hsotg->dev, dev_err(hsotg->dev,
"hcint 0x%08x, intsts 0x%08x\n", "hcint 0x%08x, intsts 0x%08x\n",
chan->hcint, chan->hcint,
readl(hsotg->regs + GINTSTS)); dwc2_readl(hsotg->regs + GINTSTS));
goto error; goto error;
} }
} }
...@@ -1958,11 +1958,11 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) ...@@ -1958,11 +1958,11 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
chan = hsotg->hc_ptr_array[chnum]; chan = hsotg->hc_ptr_array[chnum];
hcint = readl(hsotg->regs + HCINT(chnum)); hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
if (!chan) { if (!chan) {
dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
writel(hcint, hsotg->regs + HCINT(chnum)); dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
return; return;
} }
...@@ -1974,7 +1974,7 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) ...@@ -1974,7 +1974,7 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
hcint, hcintmsk, hcint & hcintmsk); hcint, hcintmsk, hcint & hcintmsk);
} }
writel(hcint, hsotg->regs + HCINT(chnum)); dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
chan->hcint = hcint; chan->hcint = hcint;
hcint &= hcintmsk; hcint &= hcintmsk;
...@@ -2066,7 +2066,7 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg) ...@@ -2066,7 +2066,7 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
u32 haint; u32 haint;
int i; int i;
haint = readl(hsotg->regs + HAINT); haint = dwc2_readl(hsotg->regs + HAINT);
if (dbg_perio()) { if (dbg_perio()) {
dev_vdbg(hsotg->dev, "%s()\n", __func__); dev_vdbg(hsotg->dev, "%s()\n", __func__);
...@@ -2134,8 +2134,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg) ...@@ -2134,8 +2134,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
"DWC OTG HCD Finished Servicing Interrupts\n"); "DWC OTG HCD Finished Servicing Interrupts\n");
dev_vdbg(hsotg->dev, dev_vdbg(hsotg->dev,
"DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
readl(hsotg->regs + GINTSTS), dwc2_readl(hsotg->regs + GINTSTS),
readl(hsotg->regs + GINTMSK)); dwc2_readl(hsotg->regs + GINTMSK));
} }
} }
......
drivers/usb/dwc2/hcd_queue.c
View file @ 95c8bc36
...@@ -115,7 +115,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, ...@@ -115,7 +115,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
if (qh->ep_type == USB_ENDPOINT_XFER_INT) if (qh->ep_type == USB_ENDPOINT_XFER_INT)
qh->interval = 8; qh->interval = 8;
#endif #endif
hprt = readl(hsotg->regs + HPRT0); hprt = dwc2_readl(hsotg->regs + HPRT0);
prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
if (prtspd == HPRT0_SPD_HIGH_SPEED && if (prtspd == HPRT0_SPD_HIGH_SPEED &&
(dev_speed == USB_SPEED_LOW || (dev_speed == USB_SPEED_LOW ||
...@@ -595,9 +595,9 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) ...@@ -595,9 +595,9 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
if (status) if (status)
return status; return status;
if (!hsotg->periodic_qh_count) { if (!hsotg->periodic_qh_count) {
intr_mask = readl(hsotg->regs + GINTMSK); intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
intr_mask |= GINTSTS_SOF; intr_mask |= GINTSTS_SOF;
writel(intr_mask, hsotg->regs + GINTMSK); dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
} }
hsotg->periodic_qh_count++; hsotg->periodic_qh_count++;
...@@ -632,9 +632,9 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) ...@@ -632,9 +632,9 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
dwc2_deschedule_periodic(hsotg, qh); dwc2_deschedule_periodic(hsotg, qh);
hsotg->periodic_qh_count--; hsotg->periodic_qh_count--;
if (!hsotg->periodic_qh_count) { if (!hsotg->periodic_qh_count) {
intr_mask = readl(hsotg->regs + GINTMSK); intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
intr_mask &= ~GINTSTS_SOF; intr_mask &= ~GINTSTS_SOF;
writel(intr_mask, hsotg->regs + GINTMSK); dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
} }
} }
......
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