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Commit 96ecfc4e authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
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V4L/DVB (4551): Added register aliases for saa711x registers, instead of using reg numbers 

Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@infradead.org>
parent 236f16d2
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drivers/media/video/saa7115.c
View file @ 96ecfc4e
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/ */
#include "saa711x_regs.h"
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/module.h> #include <linux/module.h>
...@@ -111,385 +112,470 @@ static inline int saa7115_read(struct i2c_client *client, u8 reg) ...@@ -111,385 +112,470 @@ static inline int saa7115_read(struct i2c_client *client, u8 reg)
static const unsigned char saa7115_init_auto_input[] = { static const unsigned char saa7115_init_auto_input[] = {
/* Front-End Part */ /* Front-End Part */
0x01, 0x48, /* white peak control disabled */ R_01_INC_DELAY, 0x48, /* white peak control disabled */
0x03, 0x20, /* was 0x30. 0x20: long vertical blanking */ R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */
0x04, 0x90, /* analog gain set to 0 */ R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */
0x05, 0x90, /* analog gain set to 0 */ R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */
/* Decoder Part */ /* Decoder Part */
0x06, 0xeb, /* horiz sync begin = -21 */ R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */
0x07, 0xe0, /* horiz sync stop = -17 */ R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */
0x0a, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */ R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */
0x0b, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */ R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */
0x0c, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */ R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */
0x0d, 0x00, /* chrominance hue control */ R_0D_CHROMA_HUE_CNTL, 0x00,
0x0f, 0x00, /* chrominance gain control: use automicatic mode */ R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */
0x10, 0x06, /* chrominance/luminance control: active adaptive combfilter */ R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */
0x11, 0x00, /* delay control */ R_11_MODE_DELAY_CNTL, 0x00,
0x12, 0x9d, /* RTS0 output control: VGATE */ R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */
0x13, 0x80, /* X-port output control: ITU656 standard mode, RTCO output enable RTCE */ R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */
0x14, 0x00, /* analog/ADC/auto compatibility control */ R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
0x18, 0x40, /* raw data gain 0x00 = nominal */ R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */
0x19, 0x80, /* raw data offset 0x80 = 0 LSB */ R_19_RAW_DATA_OFF_CNTL, 0x80,
0x1a, 0x77, /* color killer level control 0x77 = recommended */ R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */
0x1b, 0x42, /* misc chroma control 0x42 = recommended */ R_1B_MISC_TVVCRDET, 0x42, /* recommended value */
0x1c, 0xa9, /* combfilter control 0xA9 = recommended */ R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */
0x1d, 0x01, /* combfilter control 0x01 = recommended */ R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */
/* Power Device Control */ /* Power Device Control */
0x88, 0xd0, /* reset device */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */
0x88, 0xf0, /* set device programmed, all in operational mode */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */
0x00, 0x00 0x00, 0x00
}; };
static const unsigned char saa7115_cfg_reset_scaler[] = { static const unsigned char saa7115_cfg_reset_scaler[] = {
0x87, 0x00, /* disable I-port output */ R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */
0x88, 0xd0, /* reset scaler */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
0x88, 0xf0, /* activate scaler */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
0x87, 0x01, /* enable I-port output */ R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */
0x00, 0x00 0x00, 0x00
}; };
/* ============== SAA7715 VIDEO templates ============= */ /* ============== SAA7715 VIDEO templates ============= */
static const unsigned char saa7115_cfg_60hz_fullres_x[] = { static const unsigned char saa7115_cfg_60hz_fullres_x[] = {
0xcc, 0xd0, /* hsize low (output), hor. output window size = 0x2d0 = 720 */ /* hsize = 0x2d0 = 720 */
0xcd, 0x02, /* hsize hi (output) */ R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
/* Why not in 60hz-Land, too? */ /* Why not in 60hz-Land, too? */
0xd0, 0x01, /* downscale = 1 */ R_D0_B_HORIZ_PRESCALING, 0x01, /* downscale = 1 */
0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */ /* hor lum scaling 0x0400 = 1 */
0xd9, 0x04, R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
0xdd, 0x02, /* H-scaling incr chroma */
/* must be hor lum scaling / 2 */
R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
0x00, 0x00 0x00, 0x00
}; };
static const unsigned char saa7115_cfg_60hz_fullres_y[] = { static const unsigned char saa7115_cfg_60hz_fullres_y[] = {
0xce, 0xf8, /* vsize low (output), ver. output window size = 248 (but 60hz is 240?) */ /* output window size = 248 (but 60hz is 240?) */
0xcf, 0x00, /* vsize hi (output) */ R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0xf8,
R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
/* Why not in 60hz-Land, too? */ /* Why not in 60hz-Land, too? */
0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */ R_D5_B_LUMA_CONTRAST_CNTL, 0x40, /* Lum contrast, nominal value = 0x40 */
0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */ R_D6_B_CHROMA_SATURATION_CNTL, 0x40, /* Chroma satur. nominal value = 0x80 */
0xe0, 0x00, /* V-scaling incr luma low */ R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
0xe1, 0x04, /* " hi */ R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
0xe2, 0x00, /* V-scaling incr chroma low */
0xe3, 0x04, /* " hi */ R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
0x00, 0x00 0x00, 0x00
}; };
static const unsigned char saa7115_cfg_60hz_video[] = { static const unsigned char saa7115_cfg_60hz_video[] = {
0x80, 0x00, /* reset tasks */ R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
0x88, 0xd0, /* reset scaler */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
0x15, 0x03, /* VGATE pulse start */ R_15_VGATE_START_FID_CHG, 0x03,
0x16, 0x11, /* VGATE pulse stop */ R_16_VGATE_STOP, 0x11,
0x17, 0x9c, /* VGATE MSB and other values */ R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
0x08, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */ R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */
0x0e, 0x07, /* lots of different stuff... video autodetection is on */ R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */
0x5a, 0x06, /* Vertical offset, standard 60hz value for ITU656 line counting */ R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */
/* Task A */ /* Task A */
0x90, 0x80, /* Task Handling Control */ R_90_A_TASK_HANDLING_CNTL, 0x80,
0x91, 0x48, /* X-port formats/config */ R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
0x92, 0x40, /* Input Ref. signal Def. */ R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
0x93, 0x84, /* I-port config */ R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
0x94, 0x01, /* hoffset low (input), 0x0002 is minimum */
0x95, 0x00, /* hoffset hi (input) */ /* hoffset low (input), 0x0002 is minimum */
0x96, 0xd0, /* hsize low (input), 0x02d0 = 720 */ R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
0x97, 0x02, /* hsize hi (input) */ R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
0x98, 0x05, /* voffset low (input) */
0x99, 0x00, /* voffset hi (input) */ /* hsize low (input), 0x02d0 = 720 */
0x9a, 0x0c, /* vsize low (input), 0x0c = 12 */ R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
0x9b, 0x00, /* vsize hi (input) */ R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
0x9c, 0xa0, /* hsize low (output), 0x05a0 = 1440 */
0x9d, 0x05, /* hsize hi (output) */ R_98_A_VERT_INPUT_WINDOW_START, 0x05,
0x9e, 0x0c, /* vsize low (output), 0x0c = 12 */ R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
0x9f, 0x00, /* vsize hi (output) */
R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
/* Task B */ /* Task B */
0xc0, 0x00, /* Task Handling Control */ R_C0_B_TASK_HANDLING_CNTL, 0x00,
0xc1, 0x08, /* X-port formats/config */ R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
0xc2, 0x00, /* Input Ref. signal Def. */ R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
0xc3, 0x80, /* I-port config */ R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
0xc4, 0x02, /* hoffset low (input), 0x0002 is minimum */
0xc5, 0x00, /* hoffset hi (input) */ /* 0x0002 is minimum */
0xc6, 0xd0, /* hsize low (input), 0x02d0 = 720 */ R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
0xc7, 0x02, /* hsize hi (input) */ R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
0xc8, 0x12, /* voffset low (input), 0x12 = 18 */
0xc9, 0x00, /* voffset hi (input) */ /* 0x02d0 = 720 */
0xca, 0xf8, /* vsize low (input), 0xf8 = 248 */ R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
0xcb, 0x00, /* vsize hi (input) */ R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
0xcc, 0xd0, /* hsize low (output), 0x02d0 = 720 */
0xcd, 0x02, /* hsize hi (output) */ /* vwindow start 0x12 = 18 */
R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
0xf0, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */ R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
0xf1, 0x05, /* low bit with 0xF0 */
0xf5, 0xad, /* Set pulse generator register */ /* vwindow length 0xf8 = 248 */
0xf6, 0x01, R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0xf8,
R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
0x87, 0x00, /* Disable I-port output */
0x88, 0xd0, /* reset scaler */ /* hwindow 0x02d0 = 720 */
0x80, 0x20, /* Activate only task "B", continuous mode (was 0xA0) */ R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
0x88, 0xf0, /* activate scaler */ R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
0x87, 0x01, /* Enable I-port output */
R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */
R_F5_PULSGEN_LINE_LENGTH, 0xad,
R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* Disable I-port output */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B", continuous mode (was 0xA0) */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
0x00, 0x00 0x00, 0x00
}; };
static const unsigned char saa7115_cfg_50hz_fullres_x[] = { static const unsigned char saa7115_cfg_50hz_fullres_x[] = {
0xcc, 0xd0, /* hsize low (output), 720 same as 60hz */ /* hsize low (output), 720 same as 60hz */
0xcd, 0x02, /* hsize hi (output) */ R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
0xd0, 0x01, /* down scale = 1 */ R_D0_B_HORIZ_PRESCALING, 0x01, /* down scale = 1 */
0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */ R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00, /* hor lum scaling 0x0400 = 1 */
0xd9, 0x04, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */
0xdd, 0x02, /* H-scaling incr chroma */ /* must be hor lum scaling / 2 */
R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
0x00, 0x00 0x00, 0x00
}; };
static const unsigned char saa7115_cfg_50hz_fullres_y[] = { static const unsigned char saa7115_cfg_50hz_fullres_y[] = {
0xce, 0x20, /* vsize low (output), 0x0120 = 288 */ /* vsize low (output), 0x0120 = 288 */
0xcf, 0x01, /* vsize hi (output) */ R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0x20,
R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01,
R_D5_B_LUMA_CONTRAST_CNTL, 0x40, /* Lum contrast, nominal value = 0x40 */
R_D6_B_CHROMA_SATURATION_CNTL, 0x40, /* Chroma satur. nominal value = 0x80 */
0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */ R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */ R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
0xe0, 0x00, /* V-scaling incr luma low */ R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
0xe1, 0x04, /* " hi */ R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
0xe2, 0x00, /* V-scaling incr chroma low */
0xe3, 0x04, /* " hi */
0x00, 0x00 0x00, 0x00
}; };
static const unsigned char saa7115_cfg_50hz_video[] = { static const unsigned char saa7115_cfg_50hz_video[] = {
0x80, 0x00, /* reset tasks */ R_80_GLOBAL_CNTL_1, 0x00,
0x88, 0xd0, /* reset scaler */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
0x15, 0x37, /* VGATE start */ R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */
0x16, 0x16, /* VGATE stop */ R_16_VGATE_STOP, 0x16,
0x17, 0x99, /* VGATE MSB and other values */ R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
0x08, 0x28, /* 0x28 = PAL */ R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */
0x0e, 0x07, /* chrominance control 1 */ R_0E_CHROMA_CNTL_1, 0x07,
0x5a, 0x03, /* Vertical offset, standard 50hz value */ R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */
/* Task A */ /* Task A */
0x90, 0x81, /* Task Handling Control */ R_90_A_TASK_HANDLING_CNTL, 0x81,
0x91, 0x48, /* X-port formats/config */ R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
0x92, 0x40, /* Input Ref. signal Def. */ R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
0x93, 0x84, /* I-port config */ R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
/* This is weird: the datasheet says that you should use 2 as the minimum value, */ /* This is weird: the datasheet says that you should use 2 as the minimum value, */
/* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
0x94, 0x00, /* hoffset low (input), 0x0002 is minimum */ /* hoffset low (input), 0x0002 is minimum */
0x95, 0x00, /* hoffset hi (input) */ R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
0x96, 0xd0, /* hsize low (input), 0x02d0 = 720 */ R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
0x97, 0x02, /* hsize hi (input) */
0x98, 0x03, /* voffset low (input) */ /* hsize low (input), 0x02d0 = 720 */
0x99, 0x00, /* voffset hi (input) */ R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
0x9a, 0x12, /* vsize low (input), 0x12 = 18 */ R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
0x9b, 0x00, /* vsize hi (input) */
0x9c, 0xa0, /* hsize low (output), 0x05a0 = 1440 */ R_98_A_VERT_INPUT_WINDOW_START, 0x03,
0x9d, 0x05, /* hsize hi (output) */ R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
0x9e, 0x12, /* vsize low (output), 0x12 = 18 */
0x9f, 0x00, /* vsize hi (output) */ /* vsize 0x12 = 18 */
R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
/* hsize 0x05a0 = 1440 */
R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */
R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */
R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */
/* Task B */ /* Task B */
0xc0, 0x00, /* Task Handling Control */ R_C0_B_TASK_HANDLING_CNTL, 0x00,
0xc1, 0x08, /* X-port formats/config */ R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
0xc2, 0x00, /* Input Ref. signal Def. */ R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
0xc3, 0x80, /* I-port config */ R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
0xc4, 0x00, /* hoffset low (input), 0x0002 is minimum. See comment at 0x94 above. */
0xc5, 0x00, /* hoffset hi (input) */ /* This is weird: the datasheet says that you should use 2 as the minimum value, */
0xc6, 0xd0, /* hsize low (input), 0x02d0 = 720 */ /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
0xc7, 0x02, /* hsize hi (input) */ /* hoffset low (input), 0x0002 is minimum. See comment above. */
0xc8, 0x16, /* voffset low (input), 0x16 = 22 */ R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
0xc9, 0x00, /* voffset hi (input) */ R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
0xca, 0x20, /* vsize low (input), 0x0120 = 288 */
0xcb, 0x01, /* vsize hi (input) */ /* hsize 0x02d0 = 720 */
0xcc, 0xd0, /* hsize low (output), 0x02d0 = 720 */ R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
0xcd, 0x02, /* hsize hi (output) */ R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
0xce, 0x20, /* vsize low (output), 0x0120 = 288 */
0xcf, 0x01, /* vsize hi (output) */ /* voffset 0x16 = 22 */
R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
0xf0, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */ R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
0xf1, 0x05, /* low bit with 0xF0, (was 0x05) */
0xf5, 0xb0, /* Set pulse generator register */ /* vsize 0x0120 = 288 */
0xf6, 0x01, R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
0x87, 0x00, /* Disable I-port output */
0x88, 0xd0, /* reset scaler (was 0xD0) */ /* hsize 0x02d0 = 720 */
0x80, 0x20, /* Activate only task "B" */ R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
0x88, 0xf0, /* activate scaler */ R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
0x87, 0x01, /* Enable I-port output */
/* vsize 0x0120 = 288 */
R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0x20,
R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01,
R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */
R_F5_PULSGEN_LINE_LENGTH, 0xb0,
R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* Disable I-port output */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler (was 0xD0) */
R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
0x00, 0x00 0x00, 0x00
}; };
/* ============== SAA7715 VIDEO templates (end) ======= */ /* ============== SAA7715 VIDEO templates (end) ======= */
static const unsigned char saa7115_cfg_vbi_on[] = { static const unsigned char saa7115_cfg_vbi_on[] = {
0x80, 0x00, /* reset tasks */ R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
0x88, 0xd0, /* reset scaler */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
0x80, 0x30, /* Activate both tasks */ R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */
0x88, 0xf0, /* activate scaler */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
0x87, 0x01, /* Enable I-port output */ R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
0x00, 0x00 0x00, 0x00
}; };
static const unsigned char saa7115_cfg_vbi_off[] = { static const unsigned char saa7115_cfg_vbi_off[] = {
0x80, 0x00, /* reset tasks */ R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
0x88, 0xd0, /* reset scaler */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
0x80, 0x20, /* Activate only task "B" */ R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */
0x88, 0xf0, /* activate scaler */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
0x87, 0x01, /* Enable I-port output */ R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
0x00, 0x00 0x00, 0x00
}; };
static const unsigned char saa7113_init_auto_input[] = { static const unsigned char saa7113_init_auto_input[] = {
0x01, 0x08, /* PH7113_INCREMENT_DELAY - (1) (1) (1) (1) IDEL3 IDEL2 IDELL1 IDEL0 */ R_01_INC_DELAY, 0x08,
0x02, 0xc2, /* PH7113_ANALOG_INPUT_CONTR_1 - FUSE1 FUSE0 GUDL1 GUDL0 MODE3 MODE2 MODE1 MODE0 */ R_02_INPUT_CNTL_1, 0xc2,
0x03, 0x30, /* PH7113_ANALOG_INPUT_CONTR_2 - (1) HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18 */ R_03_INPUT_CNTL_2, 0x30,
0x04, 0x00, /* PH7113_ANALOG_INPUT_CONTR_3 - GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 */ R_04_INPUT_CNTL_3, 0x00,
0x05, 0x00, /* PH7113_ANALOG_INPUT_CONTR_4 - GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 */ R_05_INPUT_CNTL_4, 0x00,
0x06, 0x89, /* PH7113_HORIZONTAL_SYNC_START - HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 */ R_06_H_SYNC_START, 0x89,
0x07, 0x0d, /* PH7113_HORIZONTAL_SYNC_STOP - HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 */ R_07_H_SYNC_STOP, 0x0d,
0x08, 0x88, /* PH7113_SYNC_CONTROL - AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0 */ R_08_SYNC_CNTL, 0x88,
0x09, 0x01, /* PH7113_LUMINANCE_CONTROL - BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0 */ R_09_LUMA_CNTL, 0x01,
0x0a, 0x80, /* PH7113_LUMINANCE_BRIGHTNESS - BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 */ R_0A_LUMA_BRIGHT_CNTL, 0x80,
0x0b, 0x47, /* PH7113_LUMINANCE_CONTRAST - CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 */ R_0B_LUMA_CONTRAST_CNTL, 0x47,
0x0c, 0x40, /* PH7113_CHROMA_SATURATION - SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 */ R_0C_CHROMA_SAT_CNTL, 0x40,
0x0d, 0x00, /* PH7113_CHROMA_HUE_CONTROL - HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 */ R_0D_CHROMA_HUE_CNTL, 0x00,
0x0e, 0x01, /* PH7113_CHROMA_CONTROL - CDTO CSTD2 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0 */ R_0E_CHROMA_CNTL_1, 0x01,
0x0f, 0x2a, /* PH7113_CHROMA_GAIN_CONTROL - ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 */ R_0F_CHROMA_GAIN_CNTL, 0x2a,
0x10, 0x08, /* PH7113_FORMAT_DELAY_CONTROL - OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0 */ R_10_CHROMA_CNTL_2, 0x08,
0x11, 0x0c, /* PH7113_OUTPUT_CONTROL_1 - GPSW1 CM99 GPSW0 HLSEL OEYC OERT VIPB COLO */ R_11_MODE_DELAY_CNTL, 0x0c,
0x12, 0x07, /* PH7113_OUTPUT_CONTROL_2 - RTSE13 RTSE12 RTSE11 RTSE10 RTSE03 RTSE02 RTSE01 RTSE00 */ R_12_RT_SIGNAL_CNTL, 0x07,
0x13, 0x00, /* PH7113_OUTPUT_CONTROL_3 - ADLSB (1) (1) OLDSB FIDP (1) AOSL1 AOSL0 */ R_13_RT_X_PORT_OUT_CNTL, 0x00,
0x14, 0x00, /* RESERVED 14 - (1) (1) (1) (1) (1) (1) (1) (1) */ R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
0x15, 0x00, /* PH7113_V_GATE1_START - VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 */ R_15_VGATE_START_FID_CHG, 0x00,
0x16, 0x00, /* PH7113_V_GATE1_STOP - VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 */ R_16_VGATE_STOP, 0x00,
0x17, 0x00, /* PH7113_V_GATE1_MSB - (1) (1) (1) (1) (1) (1) VSTO8 VSTA8 */ R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
0x00, 0x00 0x00, 0x00
}; };
static const unsigned char saa7115_init_misc[] = { static const unsigned char saa7115_init_misc[] = {
0x81, 0x01, /* reg 0x15,0x16 define blanking window */ R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
0x82, 0x00, 0x82, 0x00, /* Reserved register - value should be zero*/
0x83, 0x01, /* I port settings */ R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
0x84, 0x20, R_84_I_PORT_SIGNAL_DEF, 0x20,
0x85, 0x21, R_85_I_PORT_SIGNAL_POLAR, 0x21,
0x86, 0xc5, R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
0x87, 0x01, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
/* Task A */ /* Task A */
0xa0, 0x01, /* down scale = 1 */ R_A0_A_HORIZ_PRESCALING, 0x01,
0xa1, 0x00, /* prescale accumulation length = 1 */ R_A1_A_ACCUMULATION_LENGTH, 0x00,
0xa2, 0x00, /* dc gain and fir prefilter control */ R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
0xa4, 0x80, /* Lum Brightness, nominal value = 0x80 */
0xa5, 0x40, /* Lum contrast, nominal value = 0x40 */ /* Configure controls at nominal value*/
0xa6, 0x40, /* Chroma satur. nominal value = 0x80 */ R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
0xa8, 0x00, /* hor lum scaling 0x0200 = 2 zoom */ R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
0xa9, 0x02, /* note: 2 x zoom ensures that VBI lines have same length as video lines. */ R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
0xaa, 0x00, /* H-phase offset Luma = 0 */
0xac, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ /* note: 2 x zoom ensures that VBI lines have same length as video lines. */
0xad, 0x01, /* H-scaling incr chroma */ R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
0xae, 0x00, /* H-phase offset chroma. must be offset luma / 2 */ R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
0xb0, 0x00, /* V-scaling incr luma low */ R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
0xb1, 0x04, /* " hi */
0xb2, 0x00, /* V-scaling incr chroma low */ /* must be horiz lum scaling / 2 */
0xb3, 0x04, /* " hi */ R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
0xb4, 0x01, /* V-scaling mode control */ R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
0xb8, 0x00, /* V-phase offset chroma 00 */
0xb9, 0x00, /* V-phase offset chroma 01 */ /* must be offset luma / 2 */
0xba, 0x00, /* V-phase offset chroma 10 */ R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
0xbb, 0x00, /* V-phase offset chroma 11 */
0xbc, 0x00, /* V-phase offset luma 00 */ R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
0xbd, 0x00, /* V-phase offset luma 01 */ R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
0xbe, 0x00, /* V-phase offset luma 10 */
0xbf, 0x00, /* V-phase offset luma 11 */ R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
/* Task B */ /* Task B */
0xd0, 0x01, /* down scale = 1 */ R_D0_B_HORIZ_PRESCALING, 0x01,
0xd1, 0x00, /* prescale accumulation length = 1 */ R_D1_B_ACCUMULATION_LENGTH, 0x00,
0xd2, 0x00, /* dc gain and fir prefilter control */ R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
0xd4, 0x80, /* Lum Brightness, nominal value = 0x80 */
0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */ /* Configure controls at nominal value*/
0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */ R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */ R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
0xd9, 0x04, R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
0xda, 0x00, /* H-phase offset Luma = 0 */
0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ /* hor lum scaling 0x0400 = 1 */
0xdd, 0x02, /* H-scaling incr chroma */ R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
0xde, 0x00, /* H-phase offset chroma. must be offset luma / 2 */ R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
0xe0, 0x00, /* V-scaling incr luma low */ R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
0xe1, 0x04, /* " hi */
0xe2, 0x00, /* V-scaling incr chroma low */ /* must be hor lum scaling / 2 */
0xe3, 0x04, /* " hi */ R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
0xe4, 0x01, /* V-scaling mode control */ R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
0xe8, 0x00, /* V-phase offset chroma 00 */
0xe9, 0x00, /* V-phase offset chroma 01 */ /* must be offset luma / 2 */
0xea, 0x00, /* V-phase offset chroma 10 */ R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
0xeb, 0x00, /* V-phase offset chroma 11 */
0xec, 0x00, /* V-phase offset luma 00 */ R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
0xed, 0x00, /* V-phase offset luma 01 */ R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
0xee, 0x00, /* V-phase offset luma 10 */
0xef, 0x00, /* V-phase offset luma 11 */ R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
0xf2, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */
0xf3, 0x46, R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
0xf4, 0x00,
0xf7, 0x4b, /* not the recommended settings! */ R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
0xf8, 0x00, R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
0xf9, 0x4b, R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
0xfa, 0x00, R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
0xfb, 0x4b,
0xff, 0x88, /* PLL2 lock detection settings: 71 lines 50% phase error */ R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */
R_F3_PLL_INCREMENT, 0x46,
R_F4_PLL2_STATUS, 0x00,
R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */
R_F8_PULSE_B_POS, 0x00,
R_F9_PULSE_B_POS_MSB, 0x4b,
R_FA_PULSE_C_POS, 0x00,
R_FB_PULSE_C_POS_MSB, 0x4b,
/* PLL2 lock detection settings: 71 lines 50% phase error */
R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
/* Turn off VBI */ /* Turn off VBI */
0x40, 0x20, /* No framing code errors allowed. */ R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */
0x41, 0xff, R_41_LCR_BASE, 0xff,
0x42, 0xff, R_41_LCR_BASE+1, 0xff,
0x43, 0xff, R_41_LCR_BASE+2, 0xff,
0x44, 0xff, R_41_LCR_BASE+3, 0xff,
0x45, 0xff, R_41_LCR_BASE+4, 0xff,
0x46, 0xff, R_41_LCR_BASE+5, 0xff,
0x47, 0xff, R_41_LCR_BASE+6, 0xff,
0x48, 0xff, R_41_LCR_BASE+7, 0xff,
0x49, 0xff, R_41_LCR_BASE+8, 0xff,
0x4a, 0xff, R_41_LCR_BASE+9, 0xff,
0x4b, 0xff, R_41_LCR_BASE+10, 0xff,
0x4c, 0xff, R_41_LCR_BASE+11, 0xff,
0x4d, 0xff, R_41_LCR_BASE+12, 0xff,
0x4e, 0xff, R_41_LCR_BASE+13, 0xff,
0x4f, 0xff, R_41_LCR_BASE+14, 0xff,
0x50, 0xff, R_41_LCR_BASE+15, 0xff,
0x51, 0xff, R_41_LCR_BASE+16, 0xff,
0x52, 0xff, R_41_LCR_BASE+17, 0xff,
0x53, 0xff, R_41_LCR_BASE+18, 0xff,
0x54, 0xff, R_41_LCR_BASE+19, 0xff,
0x55, 0xff, R_41_LCR_BASE+20, 0xff,
0x56, 0xff, R_41_LCR_BASE+21, 0xff,
0x57, 0xff, R_41_LCR_BASE+22, 0xff,
0x58, 0x40, R_58_PROGRAM_FRAMING_CODE, 0x40,
0x59, 0x47, R_59_H_OFF_FOR_SLICER, 0x47,
0x5b, 0x83, R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
0x5d, 0xbd, R_5D_DID, 0xbd,
0x5e, 0x35, R_5E_SDID, 0x35,
0x02, 0x84, /* input tuner -> input 4, amplifier active */ R_02_INPUT_CNTL_1, 0x84, /* input tuner -> input 4, amplifier active */
0x09, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */ R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */
0x80, 0x20, /* enable task B */ R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */
0x88, 0xd0, R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
0x88, 0xf0, R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
0x00, 0x00 0x00, 0x00
}; };
...@@ -617,15 +703,19 @@ static int saa7115_set_audio_clock_freq(struct i2c_client *client, u32 freq) ...@@ -617,15 +703,19 @@ static int saa7115_set_audio_clock_freq(struct i2c_client *client, u32 freq)
if (state->apll) if (state->apll)
acc |= 0x08; acc |= 0x08;
saa7115_write(client, 0x38, 0x03); saa7115_write(client, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
saa7115_write(client, 0x39, 0x10); saa7115_write(client, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);
saa7115_write(client, 0x3a, acc); saa7115_write(client, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
saa7115_write(client, 0x30, acpf & 0xff);
saa7115_write(client, 0x31, (acpf >> 8) & 0xff); saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
saa7115_write(client, 0x32, (acpf >> 16) & 0x03); saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
saa7115_write(client, 0x34, acni & 0xff); (acpf >> 8) & 0xff);
saa7115_write(client, 0x35, (acni >> 8) & 0xff); saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
saa7115_write(client, 0x36, (acni >> 16) & 0x3f); (acpf >> 16) & 0x03);
saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
state->audclk_freq = freq; state->audclk_freq = freq;
return 0; return 0;
} }
...@@ -642,7 +732,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c ...@@ -642,7 +732,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
} }
state->bright = ctrl->value; state->bright = ctrl->value;
saa7115_write(client, 0x0a, state->bright); saa7115_write(client, R_0A_LUMA_BRIGHT_CNTL, state->bright);
break; break;
case V4L2_CID_CONTRAST: case V4L2_CID_CONTRAST:
...@@ -652,7 +742,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c ...@@ -652,7 +742,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
} }
state->contrast = ctrl->value; state->contrast = ctrl->value;
saa7115_write(client, 0x0b, state->contrast); saa7115_write(client, R_0B_LUMA_CONTRAST_CNTL, state->contrast);
break; break;
case V4L2_CID_SATURATION: case V4L2_CID_SATURATION:
...@@ -662,7 +752,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c ...@@ -662,7 +752,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
} }
state->sat = ctrl->value; state->sat = ctrl->value;
saa7115_write(client, 0x0c, state->sat); saa7115_write(client, R_0C_CHROMA_SAT_CNTL, state->sat);
break; break;
case V4L2_CID_HUE: case V4L2_CID_HUE:
...@@ -672,7 +762,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c ...@@ -672,7 +762,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
} }
state->hue = ctrl->value; state->hue = ctrl->value;
saa7115_write(client, 0x0d, state->hue); saa7115_write(client, R_0D_CHROMA_HUE_CNTL, state->hue);
break; break;
default: default:
...@@ -709,7 +799,7 @@ static int saa7115_get_v4lctrl(struct i2c_client *client, struct v4l2_control *c ...@@ -709,7 +799,7 @@ static int saa7115_get_v4lctrl(struct i2c_client *client, struct v4l2_control *c
static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std) static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
{ {
struct saa7115_state *state = i2c_get_clientdata(client); struct saa7115_state *state = i2c_get_clientdata(client);
int taskb = saa7115_read(client, 0x80) & 0x10; int taskb = saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10;
/* Prevent unnecessary standard changes. During a standard /* Prevent unnecessary standard changes. During a standard
change the I-Port is temporarily disabled. Any devices change the I-Port is temporarily disabled. Any devices
...@@ -740,7 +830,7 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std) ...@@ -740,7 +830,7 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
100 reserved NTSC-Japan (3.58MHz) 100 reserved NTSC-Japan (3.58MHz)
*/ */
if (state->ident == V4L2_IDENT_SAA7113) { if (state->ident == V4L2_IDENT_SAA7113) {
u8 reg = saa7115_read(client, 0x0e) & 0x8f; u8 reg = saa7115_read(client, R_0E_CHROMA_CNTL_1) & 0x8f;
if (std == V4L2_STD_PAL_M) { if (std == V4L2_STD_PAL_M) {
reg |= 0x30; reg |= 0x30;
...@@ -751,7 +841,7 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std) ...@@ -751,7 +841,7 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
} else if (std == V4L2_STD_NTSC_M_JP) { } else if (std == V4L2_STD_NTSC_M_JP) {
reg |= 0x40; reg |= 0x40;
} }
saa7115_write(client, 0x0e, reg); saa7115_write(client, R_0E_CHROMA_CNTL_1, reg);
} }
...@@ -783,7 +873,7 @@ static void saa7115_log_status(struct i2c_client *client) ...@@ -783,7 +873,7 @@ static void saa7115_log_status(struct i2c_client *client)
v4l_info(client, "Audio frequency: %d Hz\n", state->audclk_freq); v4l_info(client, "Audio frequency: %d Hz\n", state->audclk_freq);
if (state->ident != V4L2_IDENT_SAA7115) { if (state->ident != V4L2_IDENT_SAA7115) {
/* status for the saa7114 */ /* status for the saa7114 */
reg1f = saa7115_read(client, 0x1f); reg1f = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
signalOk = (reg1f & 0xc1) == 0x81; signalOk = (reg1f & 0xc1) == 0x81;
v4l_info(client, "Video signal: %s\n", signalOk ? "ok" : "bad"); v4l_info(client, "Video signal: %s\n", signalOk ? "ok" : "bad");
v4l_info(client, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); v4l_info(client, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
...@@ -791,8 +881,8 @@ static void saa7115_log_status(struct i2c_client *client) ...@@ -791,8 +881,8 @@ static void saa7115_log_status(struct i2c_client *client)
} }
/* status for the saa7115 */ /* status for the saa7115 */
reg1e = saa7115_read(client, 0x1e); reg1e = saa7115_read(client, R_1E_STATUS_BYTE_1_VD_DEC);
reg1f = saa7115_read(client, 0x1f); reg1f = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80; signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
vcr = !(reg1f & 0x10); vcr = !(reg1f & 0x10);
...@@ -888,11 +978,13 @@ static void saa7115_set_lcr(struct i2c_client *client, struct v4l2_sliced_vbi_fo ...@@ -888,11 +978,13 @@ static void saa7115_set_lcr(struct i2c_client *client, struct v4l2_sliced_vbi_fo
/* write the lcr registers */ /* write the lcr registers */
for (i = 2; i <= 23; i++) { for (i = 2; i <= 23; i++) {
saa7115_write(client, i - 2 + 0x41, lcr[i]); saa7115_write(client, i - 2 + R_41_LCR_BASE, lcr[i]);
} }
/* enable/disable raw VBI capturing */ /* enable/disable raw VBI capturing */
saa7115_writeregs(client, fmt->service_set == 0 ? saa7115_cfg_vbi_on : saa7115_cfg_vbi_off); saa7115_writeregs(client, fmt->service_set == 0 ?
saa7115_cfg_vbi_on :
saa7115_cfg_vbi_off);
} }
static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt) static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt)
...@@ -911,10 +1003,10 @@ static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt ...@@ -911,10 +1003,10 @@ static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
return -EINVAL; return -EINVAL;
memset(sliced, 0, sizeof(*sliced)); memset(sliced, 0, sizeof(*sliced));
/* done if using raw VBI */ /* done if using raw VBI */
if (saa7115_read(client, 0x80) & 0x10) if (saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10)
return 0; return 0;
for (i = 2; i <= 23; i++) { for (i = 2; i <= 23; i++) {
u8 v = saa7115_read(client, i - 2 + 0x41); u8 v = saa7115_read(client, i - 2 + R_41_LCR_BASE);
sliced->service_lines[0][i] = lcr2vbi[v >> 4]; sliced->service_lines[0][i] = lcr2vbi[v >> 4];
sliced->service_lines[1][i] = lcr2vbi[v & 0xf]; sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
...@@ -952,11 +1044,15 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt ...@@ -952,11 +1044,15 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
/* probably have a valid size, let's set it */ /* probably have a valid size, let's set it */
/* Set output width/height */ /* Set output width/height */
/* width */ /* width */
saa7115_write(client, 0xcc, (u8) (pix->width & 0xff)); saa7115_write(client, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
saa7115_write(client, 0xcd, (u8) ((pix->width >> 8) & 0xff)); (u8) (pix->width & 0xff));
saa7115_write(client, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
(u8) ((pix->width >> 8) & 0xff));
/* height */ /* height */
saa7115_write(client, 0xce, (u8) (pix->height & 0xff)); saa7115_write(client, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
saa7115_write(client, 0xcf, (u8) ((pix->height >> 8) & 0xff)); (u8) (pix->height & 0xff));
saa7115_write(client, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
(u8) ((pix->height >> 8) & 0xff));
/* Scaling settings */ /* Scaling settings */
/* Hprescaler is floor(inres/outres) */ /* Hprescaler is floor(inres/outres) */
...@@ -970,15 +1066,20 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt ...@@ -970,15 +1066,20 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
v4l_dbg(1, debug, client, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC); v4l_dbg(1, debug, client, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
/* FIXME hardcodes to "Task B" /* FIXME hardcodes to "Task B"
* write H prescaler integer */ * write H prescaler integer */
saa7115_write(client, 0xd0, (u8) (HPSC & 0x3f)); saa7115_write(client, R_D0_B_HORIZ_PRESCALING,
(u8) (HPSC & 0x3f));
/* write H fine-scaling (luminance) */ /* write H fine-scaling (luminance) */
saa7115_write(client, 0xd8, (u8) (HFSC & 0xff)); saa7115_write(client, R_D8_B_HORIZ_LUMA_SCALING_INC,
saa7115_write(client, 0xd9, (u8) ((HFSC >> 8) & 0xff)); (u8) (HFSC & 0xff));
saa7115_write(client, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
(u8) ((HFSC >> 8) & 0xff));
/* write H fine-scaling (chrominance) /* write H fine-scaling (chrominance)
* must be lum/2, so i'll just bitshift :) */ * must be lum/2, so i'll just bitshift :) */
saa7115_write(client, 0xDC, (u8) ((HFSC >> 1) & 0xff)); saa7115_write(client, R_DC_B_HORIZ_CHROMA_SCALING,
saa7115_write(client, 0xDD, (u8) ((HFSC >> 9) & 0xff)); (u8) ((HFSC >> 1) & 0xff));
saa7115_write(client, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
(u8) ((HFSC >> 9) & 0xff));
} else { } else {
if (is_50hz) { if (is_50hz) {
v4l_dbg(1, debug, client, "Setting full 50hz width\n"); v4l_dbg(1, debug, client, "Setting full 50hz width\n");
...@@ -996,15 +1097,21 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt ...@@ -996,15 +1097,21 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
v4l_dbg(1, debug, client, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY); v4l_dbg(1, debug, client, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
/* Correct Contrast and Luminance */ /* Correct Contrast and Luminance */
saa7115_write(client, 0xd5, (u8) (64 * 1024 / VSCY)); saa7115_write(client, R_D5_B_LUMA_CONTRAST_CNTL,
saa7115_write(client, 0xd6, (u8) (64 * 1024 / VSCY)); (u8) (64 * 1024 / VSCY));
saa7115_write(client, R_D6_B_CHROMA_SATURATION_CNTL,
(u8) (64 * 1024 / VSCY));
/* write V fine-scaling (luminance) */ /* write V fine-scaling (luminance) */
saa7115_write(client, 0xe0, (u8) (VSCY & 0xff)); saa7115_write(client, R_E0_B_VERT_LUMA_SCALING_INC,
saa7115_write(client, 0xe1, (u8) ((VSCY >> 8) & 0xff)); (u8) (VSCY & 0xff));
saa7115_write(client, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
(u8) ((VSCY >> 8) & 0xff));
/* write V fine-scaling (chrominance) */ /* write V fine-scaling (chrominance) */
saa7115_write(client, 0xe2, (u8) (VSCY & 0xff)); saa7115_write(client, R_E2_B_VERT_CHROMA_SCALING_INC,
saa7115_write(client, 0xe3, (u8) ((VSCY >> 8) & 0xff)); (u8) (VSCY & 0xff));
saa7115_write(client, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
(u8) ((VSCY >> 8) & 0xff));
} else { } else {
if (is_50hz) { if (is_50hz) {
v4l_dbg(1, debug, client, "Setting full 50Hz height\n"); v4l_dbg(1, debug, client, "Setting full 50Hz height\n");
...@@ -1023,7 +1130,7 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt ...@@ -1023,7 +1130,7 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
The format is described in the saa7115 datasheet in Tables 25 and 26 The format is described in the saa7115 datasheet in Tables 25 and 26
and in Figure 33. and in Figure 33.
The current implementation uses SAV/EAV codes and not the ancillary data The current implementation uses SAV/EAV codes and not the ancillary data
headers. The vbi->p pointer points to the SDID byte right after the SAV headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV
code. */ code. */
static void saa7115_decode_vbi_line(struct i2c_client *client, static void saa7115_decode_vbi_line(struct i2c_client *client,
struct v4l2_decode_vbi_line *vbi) struct v4l2_decode_vbi_line *vbi)
...@@ -1113,7 +1220,7 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar ...@@ -1113,7 +1220,7 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar
if (state->radio) if (state->radio)
break; break;
status = saa7115_read(client, 0x1f); status = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
v4l_dbg(1, debug, client, "status: 0x%02x\n", status); v4l_dbg(1, debug, client, "status: 0x%02x\n", status);
vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0; vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
...@@ -1187,13 +1294,13 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar ...@@ -1187,13 +1294,13 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar
state->input = route->input; state->input = route->input;
/* select mode */ /* select mode */
saa7115_write(client, 0x02, saa7115_write(client, R_02_INPUT_CNTL_1,
(saa7115_read(client, 0x02) & 0xf0) | (saa7115_read(client, R_02_INPUT_CNTL_1) & 0xf0) |
state->input); state->input);
/* bypass chrominance trap for S-Video modes */ /* bypass chrominance trap for S-Video modes */
saa7115_write(client, 0x09, saa7115_write(client, R_09_LUMA_CNTL,
(saa7115_read(client, 0x09) & 0x7f) | (saa7115_read(client, R_09_LUMA_CNTL) & 0x7f) |
(state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0)); (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
break; break;
} }
...@@ -1205,7 +1312,9 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar ...@@ -1205,7 +1312,9 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar
if (state->enable != (cmd == VIDIOC_STREAMON)) { if (state->enable != (cmd == VIDIOC_STREAMON)) {
state->enable = (cmd == VIDIOC_STREAMON); state->enable = (cmd == VIDIOC_STREAMON);
saa7115_write(client, 0x87, state->enable); saa7115_write(client,
R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED,
state->enable);
} }
break; break;
...@@ -1392,7 +1501,7 @@ static int saa7115_attach(struct i2c_adapter *adapter, int address, int kind) ...@@ -1392,7 +1501,7 @@ static int saa7115_attach(struct i2c_adapter *adapter, int address, int kind)
i2c_attach_client(client); i2c_attach_client(client);
v4l_dbg(1, debug, client, "status: (1E) 0x%02x, (1F) 0x%02x\n", v4l_dbg(1, debug, client, "status: (1E) 0x%02x, (1F) 0x%02x\n",
saa7115_read(client, 0x1e), saa7115_read(client, 0x1f)); saa7115_read(client, R_1E_STATUS_BYTE_1_VD_DEC), saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC));
return 0; return 0;
} }
......
drivers/media/video/saa711x_regs.h 0 → 100644
View file @ 96ecfc4e
/* saa711x - Philips SAA711x video decoder register specifications
*
* Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@infradead.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define R_00_CHIP_VERSION 0x00
/* Video Decoder */
/* Video Decoder - Frontend part */
#define R_01_INC_DELAY 0x01
#define R_02_INPUT_CNTL_1 0x02
#define R_03_INPUT_CNTL_2 0x03
#define R_04_INPUT_CNTL_3 0x04
#define R_05_INPUT_CNTL_4 0x05
/* Video Decoder - Decoder part */
#define R_06_H_SYNC_START 0x06
#define R_07_H_SYNC_STOP 0x07
#define R_08_SYNC_CNTL 0x08
#define R_09_LUMA_CNTL 0x09
#define R_0A_LUMA_BRIGHT_CNTL 0x0a
#define R_0B_LUMA_CONTRAST_CNTL 0x0b
#define R_0C_CHROMA_SAT_CNTL 0x0c
#define R_0D_CHROMA_HUE_CNTL 0x0d
#define R_0E_CHROMA_CNTL_1 0x0e
#define R_0F_CHROMA_GAIN_CNTL 0x0f
#define R_10_CHROMA_CNTL_2 0x10
#define R_11_MODE_DELAY_CNTL 0x11
#define R_12_RT_SIGNAL_CNTL 0x12
#define R_13_RT_X_PORT_OUT_CNTL 0x13
#define R_14_ANAL_ADC_COMPAT_CNTL 0x14
#define R_15_VGATE_START_FID_CHG 0x15
#define R_16_VGATE_STOP 0x16
#define R_17_MISC_VGATE_CONF_AND_MSB 0x17
#define R_18_RAW_DATA_GAIN_CNTL 0x18
#define R_19_RAW_DATA_OFF_CNTL 0x19
#define R_1A_COLOR_KILL_LVL_CNTL 0x1a
#define R_1B_MISC_TVVCRDET 0x1b
#define R_1C_ENHAN_COMB_CTRL1 0x1c
#define R_1D_ENHAN_COMB_CTRL2 0x1d
#define R_1E_STATUS_BYTE_1_VD_DEC 0x1e
#define R_1F_STATUS_BYTE_2_VD_DEC 0x1f
/* Component processing and interrupt masking part */
#define R_23_INPUT_CNTL_5 0x23
#define R_24_INPUT_CNTL_6 0x24
#define R_25_INPUT_CNTL_7 0x25
#define R_29_COMP_DELAY 0x29
#define R_2A_COMP_BRIGHT_CNTL 0x2a
#define R_2B_COMP_CONTRAST_CNTL 0x2b
#define R_2C_COMP_SAT_CNTL 0x2c
#define R_2D_INTERRUPT_MASK_1 0x2d
#define R_2E_INTERRUPT_MASK_2 0x2e
#define R_2F_INTERRUPT_MASK_3 0x2f
/* Audio clock generator part */
#define R_30_AUD_MAST_CLK_CYCLES_PER_FIELD 0x30
#define R_34_AUD_MAST_CLK_NOMINAL_INC 0x34
#define R_38_CLK_RATIO_AMXCLK_TO_ASCLK 0x38
#define R_39_CLK_RATIO_ASCLK_TO_ALRCLK 0x39
#define R_3A_AUD_CLK_GEN_BASIC_SETUP 0x3a
/* General purpose VBI data slicer part */
#define R_40_SLICER_CNTL_1 0x40
#define R_41_LCR_BASE 0x41
#define R_58_PROGRAM_FRAMING_CODE 0x58
#define R_59_H_OFF_FOR_SLICER 0x59
#define R_5A_V_OFF_FOR_SLICER 0x5a
#define R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF 0x5b
#define R_5D_DID 0x5d
#define R_5E_SDID 0x5e
#define R_60_SLICER_STATUS_BYTE_0 0x60
#define R_61_SLICER_STATUS_BYTE_1 0x61
#define R_62_SLICER_STATUS_BYTE_2 0x62
/* X port, I port and the scaler part */
/* Task independent global settings */
#define R_80_GLOBAL_CNTL_1 0x80
#define R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F 0x81
#define R_83_X_PORT_I_O_ENA_AND_OUT_CLK 0x83
#define R_84_I_PORT_SIGNAL_DEF 0x84
#define R_85_I_PORT_SIGNAL_POLAR 0x85
#define R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT 0x86
#define R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED 0x87
#define R_88_POWER_SAVE_ADC_PORT_CNTL 0x88
#define R_8F_STATUS_INFO_SCALER 0x8f
/* Task A definition */
/* Basic settings and acquisition window definition */
#define R_90_A_TASK_HANDLING_CNTL 0x90
#define R_91_A_X_PORT_FORMATS_AND_CONF 0x91
#define R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL 0x92
#define R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF 0x93
#define R_94_A_HORIZ_INPUT_WINDOW_START 0x94
#define R_95_A_HORIZ_INPUT_WINDOW_START_MSB 0x95
#define R_96_A_HORIZ_INPUT_WINDOW_LENGTH 0x96
#define R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB 0x97
#define R_98_A_VERT_INPUT_WINDOW_START 0x98
#define R_99_A_VERT_INPUT_WINDOW_START_MSB 0x99
#define R_9A_A_VERT_INPUT_WINDOW_LENGTH 0x9a
#define R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB 0x9b
#define R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH 0x9c
#define R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0x9d
#define R_9E_A_VERT_OUTPUT_WINDOW_LENGTH 0x9e
#define R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB 0x9f
/* FIR filtering and prescaling */
#define R_A0_A_HORIZ_PRESCALING 0xa0
#define R_A1_A_ACCUMULATION_LENGTH 0xa1
#define R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xa2
#define R_A4_A_LUMA_BRIGHTNESS_CNTL 0xa4
#define R_A5_A_LUMA_CONTRAST_CNTL 0xa5
#define R_A6_A_CHROMA_SATURATION_CNTL 0xa6
/* Horizontal phase scaling */
#define R_A8_A_HORIZ_LUMA_SCALING_INC 0xa8
#define R_A9_A_HORIZ_LUMA_SCALING_INC_MSB 0xa9
#define R_AA_A_HORIZ_LUMA_PHASE_OFF 0xaa
#define R_AC_A_HORIZ_CHROMA_SCALING_INC 0xac
#define R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB 0xad
#define R_AE_A_HORIZ_CHROMA_PHASE_OFF 0xae
#define R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB 0xaf
/* Vertical scaling */
#define R_B0_A_VERT_LUMA_SCALING_INC 0xb0
#define R_B1_A_VERT_LUMA_SCALING_INC_MSB 0xb1
#define R_B2_A_VERT_CHROMA_SCALING_INC 0xb2
#define R_B3_A_VERT_CHROMA_SCALING_INC_MSB 0xb3
#define R_B4_A_VERT_SCALING_MODE_CNTL 0xb4
#define R_B8_A_VERT_CHROMA_PHASE_OFF_00 0xb8
#define R_B9_A_VERT_CHROMA_PHASE_OFF_01 0xb9
#define R_BA_A_VERT_CHROMA_PHASE_OFF_10 0xba
#define R_BB_A_VERT_CHROMA_PHASE_OFF_11 0xbb
#define R_BC_A_VERT_LUMA_PHASE_OFF_00 0xbc
#define R_BD_A_VERT_LUMA_PHASE_OFF_01 0xbd
#define R_BE_A_VERT_LUMA_PHASE_OFF_10 0xbe
#define R_BF_A_VERT_LUMA_PHASE_OFF_11 0xbf
/* Task B definition */
/* Basic settings and acquisition window definition */
#define R_C0_B_TASK_HANDLING_CNTL 0xc0
#define R_C1_B_X_PORT_FORMATS_AND_CONF 0xc1
#define R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION 0xc2
#define R_C3_B_I_PORT_FORMATS_AND_CONF 0xc3
#define R_C4_B_HORIZ_INPUT_WINDOW_START 0xc4
#define R_C5_B_HORIZ_INPUT_WINDOW_START_MSB 0xc5
#define R_C6_B_HORIZ_INPUT_WINDOW_LENGTH 0xc6
#define R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB 0xc7
#define R_C8_B_VERT_INPUT_WINDOW_START 0xc8
#define R_C9_B_VERT_INPUT_WINDOW_START_MSB 0xc9
#define R_CA_B_VERT_INPUT_WINDOW_LENGTH 0xca
#define R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB 0xcb
#define R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH 0xcc
#define R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0xcd
#define R_CE_B_VERT_OUTPUT_WINDOW_LENGTH 0xce
#define R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB 0xcf
/* FIR filtering and prescaling */
#define R_D0_B_HORIZ_PRESCALING 0xd0
#define R_D1_B_ACCUMULATION_LENGTH 0xd1
#define R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xd2
#define R_D4_B_LUMA_BRIGHTNESS_CNTL 0xd4
#define R_D5_B_LUMA_CONTRAST_CNTL 0xd5
#define R_D6_B_CHROMA_SATURATION_CNTL 0xd6
/* Horizontal phase scaling */
#define R_D8_B_HORIZ_LUMA_SCALING_INC 0xd8
#define R_D9_B_HORIZ_LUMA_SCALING_INC_MSB 0xd9
#define R_DA_B_HORIZ_LUMA_PHASE_OFF 0xda
#define R_DC_B_HORIZ_CHROMA_SCALING 0xdc
#define R_DD_B_HORIZ_CHROMA_SCALING_MSB 0xdd
#define R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA 0xde
/* Vertical scaling */
#define R_E0_B_VERT_LUMA_SCALING_INC 0xe0
#define R_E1_B_VERT_LUMA_SCALING_INC_MSB 0xe1
#define R_E2_B_VERT_CHROMA_SCALING_INC 0xe2
#define R_E3_B_VERT_CHROMA_SCALING_INC_MSB 0xe3
#define R_E4_B_VERT_SCALING_MODE_CNTL 0xe4
#define R_E8_B_VERT_CHROMA_PHASE_OFF_00 0xe8
#define R_E9_B_VERT_CHROMA_PHASE_OFF_01 0xe9
#define R_EA_B_VERT_CHROMA_PHASE_OFF_10 0xea
#define R_EB_B_VERT_CHROMA_PHASE_OFF_11 0xeb
#define R_EC_B_VERT_LUMA_PHASE_OFF_00 0xec
#define R_ED_B_VERT_LUMA_PHASE_OFF_01 0xed
#define R_EE_B_VERT_LUMA_PHASE_OFF_10 0xee
#define R_EF_B_VERT_LUMA_PHASE_OFF_11 0xef
/* second PLL (PLL2) and Pulsegenerator Programming */
#define R_F0_LFCO_PER_LINE 0xf0
#define R_F1_P_I_PARAM_SELECT 0xf1
#define R_F2_NOMINAL_PLL2_DTO 0xf2
#define R_F3_PLL_INCREMENT 0xf3
#define R_F4_PLL2_STATUS 0xf4
#define R_F5_PULSGEN_LINE_LENGTH 0xf5
#define R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG 0xf6
#define R_F7_PULSE_A_POS_MSB 0xf7
#define R_F8_PULSE_B_POS 0xf8
#define R_F9_PULSE_B_POS_MSB 0xf9
#define R_FA_PULSE_C_POS 0xfa
#define R_FB_PULSE_C_POS_MSB 0xfb
#define R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES 0xff
#if 0
/* Those structs will be used in the future for debug purposes */
struct saa711x_reg_descr {
u8 reg;
int count;
char *name;
};
struct saa711x_reg_descr saa711x_regs[] = {
/* REG COUNT NAME */
{R_00_CHIP_VERSION,1,
"Chip version"},
/* Video Decoder: R_01_INC_DELAY to R_1F_STATUS_BYTE_2_VD_DEC */
/* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
{R_01_INC_DELAY,1,
"Increment delay"},
{R_02_INPUT_CNTL_1,1,
"Analog input control 1"},
{R_03_INPUT_CNTL_2,1,
"Analog input control 2"},
{R_04_INPUT_CNTL_3,1,
"Analog input control 3"},
{R_05_INPUT_CNTL_4,1,
"Analog input control 4"},
/* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
{R_06_H_SYNC_START,1,
"Horizontal sync start"},
{R_07_H_SYNC_STOP,1,
"Horizontal sync stop"},
{R_08_SYNC_CNTL,1,
"Sync control"},
{R_09_LUMA_CNTL,1,
"Luminance control"},
{R_0A_LUMA_BRIGHT_CNTL,1,
"Luminance brightness control"},
{R_0B_LUMA_CONTRAST_CNTL,1,
"Luminance contrast control"},
{R_0C_CHROMA_SAT_CNTL,1,
"Chrominance saturation control"},
{R_0D_CHROMA_HUE_CNTL,1,
"Chrominance hue control"},
{R_0E_CHROMA_CNTL_1,1,
"Chrominance control 1"},
{R_0F_CHROMA_GAIN_CNTL,1,
"Chrominance gain control"},
{R_10_CHROMA_CNTL_2,1,
"Chrominance control 2"},
{R_11_MODE_DELAY_CNTL,1,
"Mode/delay control"},
{R_12_RT_SIGNAL_CNTL,1,
"RT signal control"},
{R_13_RT_X_PORT_OUT_CNTL,1,
"RT/X port output control"},
{R_14_ANAL_ADC_COMPAT_CNTL,1,
"Analog/ADC/compatibility control"},
{R_15_VGATE_START_FID_CHG, 1,
"VGATE start FID change"},
{R_16_VGATE_STOP,1,
"VGATE stop"},
{R_17_MISC_VGATE_CONF_AND_MSB, 1,
"Miscellaneous VGATE configuration and MSBs"},
{R_18_RAW_DATA_GAIN_CNTL,1,
"Raw data gain control",},
{R_19_RAW_DATA_OFF_CNTL,1,
"Raw data offset control",},
{R_1A_COLOR_KILL_LVL_CNTL,1,
"Color Killer Level Control"},
{ R_1B_MISC_TVVCRDET, 1,
"MISC /TVVCRDET"},
{ R_1C_ENHAN_COMB_CTRL1, 1,
"Enhanced comb ctrl1"},
{ R_1D_ENHAN_COMB_CTRL2, 1,
"Enhanced comb ctrl1"},
{R_1E_STATUS_BYTE_1_VD_DEC,1,
"Status byte 1 video decoder"},
{R_1F_STATUS_BYTE_2_VD_DEC,1,
"Status byte 2 video decoder"},
/* Component processing and interrupt masking part: 0x20h to R_2F_INTERRUPT_MASK_3 */
/* 0x20 to 0x22 - Reserved */
{R_23_INPUT_CNTL_5,1,
"Analog input control 5"},
{R_24_INPUT_CNTL_6,1,
"Analog input control 6"},
{R_25_INPUT_CNTL_7,1,
"Analog input control 7"},
/* 0x26 to 0x28 - Reserved */
{R_29_COMP_DELAY,1,
"Component delay"},
{R_2A_COMP_BRIGHT_CNTL,1,
"Component brightness control"},
{R_2B_COMP_CONTRAST_CNTL,1,
"Component contrast control"},
{R_2C_COMP_SAT_CNTL,1,
"Component saturation control"},
{R_2D_INTERRUPT_MASK_1,1,
"Interrupt mask 1"},
{R_2E_INTERRUPT_MASK_2,1,
"Interrupt mask 2"},
{R_2F_INTERRUPT_MASK_3,1,
"Interrupt mask 3"},
/* Audio clock generator part: R_30_AUD_MAST_CLK_CYCLES_PER_FIELD to 0x3f */
{R_30_AUD_MAST_CLK_CYCLES_PER_FIELD,3,
"Audio master clock cycles per field"},
/* 0x33 - Reserved */
{R_34_AUD_MAST_CLK_NOMINAL_INC,3,
"Audio master clock nominal increment"},
/* 0x37 - Reserved */
{R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1,
"Clock ratio AMXCLK to ASCLK"},
{R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1,
"Clock ratio ASCLK to ALRCLK"},
{R_3A_AUD_CLK_GEN_BASIC_SETUP,1,
"Audio clock generator basic setup"},
/* 0x3b-0x3f - Reserved */
/* General purpose VBI data slicer part: R_40_SLICER_CNTL_1 to 0x7f */
{R_40_SLICER_CNTL_1,1,
"Slicer control 1"},
{R_41_LCR,23,
"R_41_LCR"},
{R_58_PROGRAM_FRAMING_CODE,1,
"Programmable framing code"},
{R_59_H_OFF_FOR_SLICER,1,
"Horizontal offset for slicer"},
{R_5A_V_OFF_FOR_SLICER,1,
"Vertical offset for slicer"},
{R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1,
"Field offset and MSBs for horizontal and vertical offset"},
{R_5D_DID,1,
"Header and data identification (R_5D_DID)"},
{R_5E_SDID,1,
"Sliced data identification (R_5E_SDID) code"},
{R_60_SLICER_STATUS_BYTE_0,1,
"Slicer status byte 0"},
{R_61_SLICER_STATUS_BYTE_1,1,
"Slicer status byte 1"},
{R_62_SLICER_STATUS_BYTE_2,1,
"Slicer status byte 2"},
/* 0x63-0x7f - Reserved */
/* X port, I port and the scaler part: R_80_GLOBAL_CNTL_1 to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
/* Task independent global settings: R_80_GLOBAL_CNTL_1 to R_8F_STATUS_INFO_SCALER */
{R_80_GLOBAL_CNTL_1,1,
"Global control 1"},
{R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1,
"Vertical sync and Field ID source selection, retimed V and F signals"},
/* 0x82 - Reserved */
{R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1,
"X port I/O enable and output clock"},
{R_84_I_PORT_SIGNAL_DEF,1,
"I port signal definitions"},
{R_85_I_PORT_SIGNAL_POLAR,1,
"I port signal polarities"},
{R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1,
"I port FIFO flag control and arbitration"},
{R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 1,
"I port I/O enable output clock and gated"},
{R_88_POWER_SAVE_ADC_PORT_CNTL,1,
"Power save/ADC port control"},
/* 089-0x8e - Reserved */
{R_8F_STATUS_INFO_SCALER,1,
"Status information scaler part"},
/* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */
/* Task A: Basic settings and acquisition window definition */
{R_90_A_TASK_HANDLING_CNTL,1,
"Task A: Task handling control"},
{R_91_A_X_PORT_FORMATS_AND_CONF,1,
"Task A: X port formats and configuration"},
{R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1,
"Task A: X port input reference signal definition"},
{R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1,
"Task A: I port output formats and configuration"},
{R_94_A_HORIZ_INPUT_WINDOW_START,2,
"Task A: Horizontal input window start"},
{R_96_A_HORIZ_INPUT_WINDOW_LENGTH,2,
"Task A: Horizontal input window length"},
{R_98_A_VERT_INPUT_WINDOW_START,2,
"Task A: Vertical input window start"},
{R_9A_A_VERT_INPUT_WINDOW_LENGTH,2,
"Task A: Vertical input window length"},
{R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH,2,
"Task A: Horizontal output window length"},
{R_9E_A_VERT_OUTPUT_WINDOW_LENGTH,2,
"Task A: Vertical output window length"},
/* Task A: FIR filtering and prescaling */
{R_A0_A_HORIZ_PRESCALING,1,
"Task A: Horizontal prescaling"},
{R_A1_A_ACCUMULATION_LENGTH,1,
"Task A: Accumulation length"},
{R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
"Task A: Prescaler DC gain and FIR prefilter"},
/* 0xa3 - Reserved */
{R_A4_A_LUMA_BRIGHTNESS_CNTL,1,
"Task A: Luminance brightness control"},
{R_A5_A_LUMA_CONTRAST_CNTL,1,
"Task A: Luminance contrast control"},
{R_A6_A_CHROMA_SATURATION_CNTL,1,
"Task A: Chrominance saturation control"},
/* 0xa7 - Reserved */
/* Task A: Horizontal phase scaling */
{R_A8_A_HORIZ_LUMA_SCALING_INC,2,
"Task A: Horizontal luminance scaling increment"},
{R_AA_A_HORIZ_LUMA_PHASE_OFF,1,
"Task A: Horizontal luminance phase offset"},
/* 0xab - Reserved */
{R_AC_A_HORIZ_CHROMA_SCALING_INC,2,
"Task A: Horizontal chrominance scaling increment"},
{R_AE_A_HORIZ_CHROMA_PHASE_OFF,1,
"Task A: Horizontal chrominance phase offset"},
/* 0xaf - Reserved */
/* Task A: Vertical scaling */
{R_B0_A_VERT_LUMA_SCALING_INC,2,
"Task A: Vertical luminance scaling increment"},
{R_B2_A_VERT_CHROMA_SCALING_INC,2,
"Task A: Vertical chrominance scaling increment"},
{R_B4_A_VERT_SCALING_MODE_CNTL,1,
"Task A: Vertical scaling mode control"},
/* 0xb5-0xb7 - Reserved */
{R_B8_A_VERT_CHROMA_PHASE_OFF_00,1,
"Task A: Vertical chrominance phase offset '00'"},
{R_B9_A_VERT_CHROMA_PHASE_OFF_01,1,
"Task A: Vertical chrominance phase offset '01'"},
{R_BA_A_VERT_CHROMA_PHASE_OFF_10,1,
"Task A: Vertical chrominance phase offset '10'"},
{R_BB_A_VERT_CHROMA_PHASE_OFF_11,1,
"Task A: Vertical chrominance phase offset '11'"},
{R_BC_A_VERT_LUMA_PHASE_OFF_00,1,
"Task A: Vertical luminance phase offset '00'"},
{R_BD_A_VERT_LUMA_PHASE_OFF_01,1,
"Task A: Vertical luminance phase offset '01'"},
{R_BE_A_VERT_LUMA_PHASE_OFF_10,1,
"Task A: Vertical luminance phase offset '10'"},
{R_BF_A_VERT_LUMA_PHASE_OFF_11,1,
"Task A: Vertical luminance phase offset '11'"},
/* Task B definition: R_C0_B_TASK_HANDLING_CNTL to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
/* Task B: Basic settings and acquisition window definition */
{R_C0_B_TASK_HANDLING_CNTL,1,
"Task B: Task handling control"},
{R_C1_B_X_PORT_FORMATS_AND_CONF,1,
"Task B: X port formats and configuration"},
{R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1,
"Task B: Input reference signal definition"},
{R_C3_B_I_PORT_FORMATS_AND_CONF,1,
"Task B: I port formats and configuration"},
{R_C4_B_HORIZ_INPUT_WINDOW_START,2,
"Task B: Horizontal input window start"},
{R_C6_B_HORIZ_INPUT_WINDOW_LENGTH,2,
"Task B: Horizontal input window length"},
{R_C8_B_VERT_INPUT_WINDOW_START,2,
"Task B: Vertical input window start"},
{R_CA_B_VERT_INPUT_WINDOW_LENGTH,2,
"Task B: Vertical input window length"},
{R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,2,
"Task B: Horizontal output window length"},
{R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,2,
"Task B: Vertical output window length"},
/* Task B: FIR filtering and prescaling */
{R_D0_B_HORIZ_PRESCALING,1,
"Task B: Horizontal prescaling"},
{R_D1_B_ACCUMULATION_LENGTH,1,
"Task B: Accumulation length"},
{R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
"Task B: Prescaler DC gain and FIR prefilter"},
/* 0xd3 - Reserved */
{R_D4_B_LUMA_BRIGHTNESS_CNTL,1,
"Task B: Luminance brightness control"},
{R_D5_B_LUMA_CONTRAST_CNTL,1,
"Task B: Luminance contrast control"},
{R_D6_B_CHROMA_SATURATION_CNTL,1,
"Task B: Chrominance saturation control"},
/* 0xd7 - Reserved */
/* Task B: Horizontal phase scaling */
{R_D8_B_HORIZ_LUMA_SCALING_INC,2,
"Task B: Horizontal luminance scaling increment"},
{R_DA_B_HORIZ_LUMA_PHASE_OFF,1,
"Task B: Horizontal luminance phase offset"},
/* 0xdb - Reserved */
{R_DC_B_HORIZ_CHROMA_SCALING,2,
"Task B: Horizontal chrominance scaling"},
{R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1,
"Task B: Horizontal Phase Offset Chroma"},
/* 0xdf - Reserved */
/* Task B: Vertical scaling */
{R_E0_B_VERT_LUMA_SCALING_INC,2,
"Task B: Vertical luminance scaling increment"},
{R_E2_B_VERT_CHROMA_SCALING_INC,2,
"Task B: Vertical chrominance scaling increment"},
{R_E4_B_VERT_SCALING_MODE_CNTL,1,
"Task B: Vertical scaling mode control"},
/* 0xe5-0xe7 - Reserved */
{R_E8_B_VERT_CHROMA_PHASE_OFF_00,1,
"Task B: Vertical chrominance phase offset '00'"},
{R_E9_B_VERT_CHROMA_PHASE_OFF_01,1,
"Task B: Vertical chrominance phase offset '01'"},
{R_EA_B_VERT_CHROMA_PHASE_OFF_10,1,
"Task B: Vertical chrominance phase offset '10'"},
{R_EB_B_VERT_CHROMA_PHASE_OFF_11,1,
"Task B: Vertical chrominance phase offset '11'"},
{R_EC_B_VERT_LUMA_PHASE_OFF_00,1,
"Task B: Vertical luminance phase offset '00'"},
{R_ED_B_VERT_LUMA_PHASE_OFF_01,1,
"Task B: Vertical luminance phase offset '01'"},
{R_EE_B_VERT_LUMA_PHASE_OFF_10,1,
"Task B: Vertical luminance phase offset '10'"},
{R_EF_B_VERT_LUMA_PHASE_OFF_11,1,
"Task B: Vertical luminance phase offset '11'"},
/* second PLL (PLL2) and Pulsegenerator Programming */
{ R_F0_LFCO_PER_LINE, 1,
"LFCO's per line"},
{ R_F1_P_I_PARAM_SELECT,1,
"P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"},
{ R_F2_NOMINAL_PLL2_DTO,1,
"Nominal PLL2 DTO"},
{R_F3_PLL_INCREMENT,1,
"PLL2 Increment"},
{R_F4_PLL2_STATUS,1,
"PLL2 Status"},
{R_F5_PULSGEN_LINE_LENGTH,1,
"Pulsgen. line length"},
{R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1,
"Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"},
{R_F7_PULSE_A_POS_MSB,1,
"Pulse A Position"},
{R_F8_PULSE_B_POS,2,
"Pulse B Position"},
{R_FA_PULSE_C_POS,2,
"Pulse C Position"},
/* 0xfc to 0xfe - Reserved */
{R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1,
"S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
};
#endif
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