drm/amd/display: Remove OPP clock programming on plane disable

[Why]
Plane disable gets calls when we enable blank. On DCN2, we blank by using
DPG to display a black colour instead of using OTG blank. DPG runs off the
OPP clock, therefore we shouldn't disable the OPP clock when disabling the
plane. We do need to disable the OPP clock when disabling the entire pipe,
that will be addressed in a separate commit.
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

@@ -463,7 +463,6 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
-	int opp_id = hubp->opp_id;
 
 	dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 
@@ -479,11 +478,6 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 
 	dpp->funcs->dpp_dppclk_control(dpp, false, false);
 
-	if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
-		pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
-				pipe_ctx->stream_res.opp,
-				false);
-
 	hubp->power_gated = true;
 	dc->optimized_required = false; /* We're powering off, no need to optimize */