Commit 9a66af33 authored by Zefir Kurtisi's avatar Zefir Kurtisi Committed by John W. Linville

ath9k_hw: add DFS testing check

In order to enable DFS upstream we want to be sure
DFS has been tested for each chipset. Push for public
documentation of the requirements we want in place and
allow for enabling each chipset through a single upstream
commit.
Signed-off-by: default avatarZefir Kurtisi <zefir.kurtisi@neratec.com>
Signed-off-by: default avatarLuis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 9b203c8f
...@@ -212,4 +212,13 @@ static inline int ath9k_hw_fast_chan_change(struct ath_hw *ah, ...@@ -212,4 +212,13 @@ static inline int ath9k_hw_fast_chan_change(struct ath_hw *ah,
return ath9k_hw_private_ops(ah)->fast_chan_change(ah, chan, return ath9k_hw_private_ops(ah)->fast_chan_change(ah, chan,
ini_reloaded); ini_reloaded);
} }
static inline void ath9k_hw_set_radar_params(struct ath_hw *ah)
{
if (!ath9k_hw_private_ops(ah)->set_radar_params)
return;
ath9k_hw_private_ops(ah)->set_radar_params(ah, &ah->radar_conf);
}
#endif /* ATH9K_HW_OPS_H */ #endif /* ATH9K_HW_OPS_H */
...@@ -2277,6 +2277,30 @@ static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) ...@@ -2277,6 +2277,30 @@ static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
return chip_chainmask; return chip_chainmask;
} }
/**
* ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
* @ah: the atheros hardware data structure
*
* We enable DFS support upstream on chipsets which have passed a series
* of tests. The testing requirements are going to be documented. Desired
* test requirements are documented at:
*
* http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
*
* Once a new chipset gets properly tested an individual commit can be used
* to document the testing for DFS for that chipset.
*/
static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
{
switch (ah->hw_version.macVersion) {
/* AR9580 will likely be our first target to get testing on */
case AR_SREV_VERSION_9580:
default:
return false;
}
}
int ath9k_hw_fill_cap_info(struct ath_hw *ah) int ath9k_hw_fill_cap_info(struct ath_hw *ah)
{ {
struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
...@@ -2490,6 +2514,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) ...@@ -2490,6 +2514,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
pCap->pcie_lcr_offset = 0x80; pCap->pcie_lcr_offset = 0x80;
} }
if (ath9k_hw_dfs_tested(ah))
pCap->hw_caps |= ATH9K_HW_CAP_DFS;
tx_chainmask = pCap->tx_chainmask; tx_chainmask = pCap->tx_chainmask;
rx_chainmask = pCap->rx_chainmask; rx_chainmask = pCap->rx_chainmask;
while (tx_chainmask || rx_chainmask) { while (tx_chainmask || rx_chainmask) {
......
...@@ -211,6 +211,7 @@ enum ath9k_hw_caps { ...@@ -211,6 +211,7 @@ enum ath9k_hw_caps {
ATH9K_HW_CAP_APM = BIT(15), ATH9K_HW_CAP_APM = BIT(15),
ATH9K_HW_CAP_RTT = BIT(16), ATH9K_HW_CAP_RTT = BIT(16),
ATH9K_HW_CAP_MCI = BIT(17), ATH9K_HW_CAP_MCI = BIT(17),
ATH9K_HW_CAP_DFS = BIT(18),
}; };
struct ath9k_hw_capabilities { struct ath9k_hw_capabilities {
......
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