Commit 9b2b9a34 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman

staging: comedi: hwrdv_apci035: absorb private header

The header file hwdrv_apci035.h is only included by the source
file hwrdv_apci035.c. Absorb the header into the source and
delete the header.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Ian Abbott <abbotti@mev.co.uk>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 4d0c8ee8
...@@ -46,12 +46,74 @@ You should also find the complete GPL in the COPYING file accompanying this sour ...@@ -46,12 +46,74 @@ You should also find the complete GPL in the COPYING file accompanying this sour
+----------+-----------+------------------------------------------------+ +----------+-----------+------------------------------------------------+
*/ */
/* /* Card Specific information */
+----------------------------------------------------------------------------+ #define APCI035_ADDRESS_RANGE 255
| Included files |
+----------------------------------------------------------------------------+ /* Timer / Watchdog Related Defines */
*/ #define APCI035_TCW_SYNC_ENABLEDISABLE 0
#include "hwdrv_apci035.h" #define APCI035_TCW_RELOAD_VALUE 4
#define APCI035_TCW_TIMEBASE 8
#define APCI035_TCW_PROG 12
#define APCI035_TCW_TRIG_STATUS 16
#define APCI035_TCW_IRQ 20
#define APCI035_TCW_WARN_TIMEVAL 24
#define APCI035_TCW_WARN_TIMEBASE 28
#define ADDIDATA_TIMER 0
/* #define ADDIDATA_WATCHDOG 1 */
#define APCI035_TW1 0
#define APCI035_TW2 32
#define APCI035_TW3 64
#define APCI035_TW4 96
#define APCI035_AI_OFFSET 0
#define APCI035_TEMP 128
#define APCI035_ALR_SEQ 4
#define APCI035_START_STOP_INDEX 8
#define APCI035_ALR_START_STOP 12
#define APCI035_ALR_IRQ 16
#define APCI035_EOS 20
#define APCI035_CHAN_NO 24
#define APCI035_CHAN_VAL 28
#define APCI035_CONV_TIME_TIME_BASE 36
#define APCI035_RELOAD_CONV_TIME_VAL 32
#define APCI035_DELAY_TIME_TIME_BASE 44
#define APCI035_RELOAD_DELAY_TIME_VAL 40
#define ENABLE_EXT_TRIG 1
#define ENABLE_EXT_GATE 2
#define ENABLE_EXT_TRIG_GATE 3
#define ANALOG_INPUT 0
#define TEMPERATURE 1
#define RESISTANCE 2
#define ADDIDATA_GREATER_THAN_TEST 0
#define ADDIDATA_LESS_THAN_TEST 1
#define APCI035_MAXVOLT 2.5
#define ADDIDATA_UNIPOLAR 1
#define ADDIDATA_BIPOLAR 2
/* ADDIDATA Enable Disable */
#define ADDIDATA_ENABLE 1
#define ADDIDATA_DISABLE 0
/* ANALOG INPUT RANGE */
static struct comedi_lrange range_apci035_ai = {
8, {
BIP_RANGE(10),
BIP_RANGE(5),
BIP_RANGE(2),
BIP_RANGE(1),
UNI_RANGE(10),
UNI_RANGE(5),
UNI_RANGE(2),
UNI_RANGE(1)
}
};
static int i_WatchdogNbr = 0; static int i_WatchdogNbr = 0;
static int i_Temp = 0; static int i_Temp = 0;
static int i_Flag = 1; static int i_Flag = 1;
......
/*
* Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
*
* ADDI-DATA GmbH
* Dieselstrasse 3
* D-77833 Ottersweier
* Tel: +19(0)7223/9493-0
* Fax: +49(0)7223/9493-92
* http://www.addi-data.com
* info@addi-data.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
/* Card Specific information */
#define APCI035_ADDRESS_RANGE 255
/* ANALOG INPUT RANGE */
static struct comedi_lrange range_apci035_ai = { 8, {
BIP_RANGE(10),
BIP_RANGE(5),
BIP_RANGE(2),
BIP_RANGE(1),
UNI_RANGE(10),
UNI_RANGE(5),
UNI_RANGE(2),
UNI_RANGE(1)
}
};
/* Timer / Watchdog Related Defines */
#define APCI035_TCW_SYNC_ENABLEDISABLE 0
#define APCI035_TCW_RELOAD_VALUE 4
#define APCI035_TCW_TIMEBASE 8
#define APCI035_TCW_PROG 12
#define APCI035_TCW_TRIG_STATUS 16
#define APCI035_TCW_IRQ 20
#define APCI035_TCW_WARN_TIMEVAL 24
#define APCI035_TCW_WARN_TIMEBASE 28
#define ADDIDATA_TIMER 0
/* #define ADDIDATA_WATCHDOG 1 */
#define APCI035_TW1 0
#define APCI035_TW2 32
#define APCI035_TW3 64
#define APCI035_TW4 96
#define APCI035_AI_OFFSET 0
#define APCI035_TEMP 128
#define APCI035_ALR_SEQ 4
#define APCI035_START_STOP_INDEX 8
#define APCI035_ALR_START_STOP 12
#define APCI035_ALR_IRQ 16
#define APCI035_EOS 20
#define APCI035_CHAN_NO 24
#define APCI035_CHAN_VAL 28
#define APCI035_CONV_TIME_TIME_BASE 36
#define APCI035_RELOAD_CONV_TIME_VAL 32
#define APCI035_DELAY_TIME_TIME_BASE 44
#define APCI035_RELOAD_DELAY_TIME_VAL 40
#define ENABLE_EXT_TRIG 1
#define ENABLE_EXT_GATE 2
#define ENABLE_EXT_TRIG_GATE 3
#define ANALOG_INPUT 0
#define TEMPERATURE 1
#define RESISTANCE 2
#define ADDIDATA_GREATER_THAN_TEST 0
#define ADDIDATA_LESS_THAN_TEST 1
#define APCI035_MAXVOLT 2.5
#define ADDIDATA_UNIPOLAR 1
#define ADDIDATA_BIPOLAR 2
/* ADDIDATA Enable Disable */
#define ADDIDATA_ENABLE 1
#define ADDIDATA_DISABLE 0
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