drm/amdgpu: rename amdgpu_program_register_sequence

add device for consistency with other functions in this file.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu.h

@@ -1913,7 +1913,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
 int amdgpu_ttm_init(struct amdgpu_device *adev);
 void amdgpu_ttm_fini(struct amdgpu_device *adev);
-void amdgpu_program_register_sequence(struct amdgpu_device *adev,
+void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 					     const u32 *registers,
 					     const u32 array_size);
 

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

@@ -342,7 +342,7 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 }
 
 /**
- * amdgpu_program_register_sequence - program an array of registers.
+ * amdgpu_device_program_register_sequence - program an array of registers.
  *
  * @adev: amdgpu_device pointer
  * @registers: pointer to the register array
@@ -351,7 +351,7 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
  * Programs an array or registers with and and or masks.
  * This is a helper for setting golden registers.
  */
-void amdgpu_program_register_sequence(struct amdgpu_device *adev,
+void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 					     const u32 *registers,
 					     const u32 array_size)
 {

drivers/gpu/drm/amd/amdgpu/cik.c

@@ -755,72 +755,72 @@ static void cik_init_golden_registers(struct amdgpu_device *adev)
 
 	switch (adev->asic_type) {
 	case CHIP_BONAIRE:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							bonaire_mgcg_cgcg_init,
 							ARRAY_SIZE(bonaire_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							bonaire_golden_registers,
 							ARRAY_SIZE(bonaire_golden_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							bonaire_golden_common_registers,
 							ARRAY_SIZE(bonaire_golden_common_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							bonaire_golden_spm_registers,
 							ARRAY_SIZE(bonaire_golden_spm_registers));
 		break;
 	case CHIP_KABINI:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							kalindi_mgcg_cgcg_init,
 							ARRAY_SIZE(kalindi_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							kalindi_golden_registers,
 							ARRAY_SIZE(kalindi_golden_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							kalindi_golden_common_registers,
 							ARRAY_SIZE(kalindi_golden_common_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							kalindi_golden_spm_registers,
 							ARRAY_SIZE(kalindi_golden_spm_registers));
 		break;
 	case CHIP_MULLINS:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							kalindi_mgcg_cgcg_init,
 							ARRAY_SIZE(kalindi_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							godavari_golden_registers,
 							ARRAY_SIZE(godavari_golden_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							kalindi_golden_common_registers,
 							ARRAY_SIZE(kalindi_golden_common_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							kalindi_golden_spm_registers,
 							ARRAY_SIZE(kalindi_golden_spm_registers));
 		break;
 	case CHIP_KAVERI:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							spectre_mgcg_cgcg_init,
 							ARRAY_SIZE(spectre_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							spectre_golden_registers,
 							ARRAY_SIZE(spectre_golden_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							spectre_golden_common_registers,
 							ARRAY_SIZE(spectre_golden_common_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							spectre_golden_spm_registers,
 							ARRAY_SIZE(spectre_golden_spm_registers));
 		break;
 	case CHIP_HAWAII:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							hawaii_mgcg_cgcg_init,
 							ARRAY_SIZE(hawaii_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							hawaii_golden_registers,
 							ARRAY_SIZE(hawaii_golden_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							hawaii_golden_common_registers,
 							ARRAY_SIZE(hawaii_golden_common_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							hawaii_golden_spm_registers,
 							ARRAY_SIZE(hawaii_golden_spm_registers));
 		break;

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

@@ -145,18 +145,18 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_FIJI:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							fiji_mgcg_cgcg_init,
 							ARRAY_SIZE(fiji_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_fiji_a10,
 							ARRAY_SIZE(golden_settings_fiji_a10));
 		break;
 	case CHIP_TONGA:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							tonga_mgcg_cgcg_init,
 							ARRAY_SIZE(tonga_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_tonga_a11,
 							ARRAY_SIZE(golden_settings_tonga_a11));
 		break;

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

@@ -154,26 +154,26 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_CARRIZO:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							cz_mgcg_cgcg_init,
 							ARRAY_SIZE(cz_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							cz_golden_settings_a11,
 							ARRAY_SIZE(cz_golden_settings_a11));
 		break;
 	case CHIP_STONEY:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							stoney_golden_settings_a11,
 							ARRAY_SIZE(stoney_golden_settings_a11));
 		break;
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							polaris11_golden_settings_a11,
 							ARRAY_SIZE(polaris11_golden_settings_a11));
 		break;
 	case CHIP_POLARIS10:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							polaris10_golden_settings_a11,
 							ARRAY_SIZE(polaris10_golden_settings_a11));
 		break;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

@@ -679,53 +679,53 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_TOPAZ:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							iceland_mgcg_cgcg_init,
 							ARRAY_SIZE(iceland_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_iceland_a11,
 							ARRAY_SIZE(golden_settings_iceland_a11));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							iceland_golden_common_all,
 							ARRAY_SIZE(iceland_golden_common_all));
 		break;
 	case CHIP_FIJI:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							fiji_mgcg_cgcg_init,
 							ARRAY_SIZE(fiji_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_fiji_a10,
 							ARRAY_SIZE(golden_settings_fiji_a10));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							fiji_golden_common_all,
 							ARRAY_SIZE(fiji_golden_common_all));
 		break;
 
 	case CHIP_TONGA:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							tonga_mgcg_cgcg_init,
 							ARRAY_SIZE(tonga_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_tonga_a11,
 							ARRAY_SIZE(golden_settings_tonga_a11));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							tonga_golden_common_all,
 							ARRAY_SIZE(tonga_golden_common_all));
 		break;
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_polaris11_a11,
 							ARRAY_SIZE(golden_settings_polaris11_a11));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							polaris11_golden_common_all,
 							ARRAY_SIZE(polaris11_golden_common_all));
 		break;
 	case CHIP_POLARIS10:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_polaris10_a11,
 							ARRAY_SIZE(golden_settings_polaris10_a11));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							polaris10_golden_common_all,
 							ARRAY_SIZE(polaris10_golden_common_all));
 		WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
@@ -738,24 +738,24 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 		}
 		break;
 	case CHIP_CARRIZO:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							cz_mgcg_cgcg_init,
 							ARRAY_SIZE(cz_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							cz_golden_settings_a11,
 							ARRAY_SIZE(cz_golden_settings_a11));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							cz_golden_common_all,
 							ARRAY_SIZE(cz_golden_common_all));
 		break;
 	case CHIP_STONEY:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							stoney_mgcg_cgcg_init,
 							ARRAY_SIZE(stoney_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							stoney_golden_settings_a11,
 							ARRAY_SIZE(stoney_golden_settings_a11));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							stoney_golden_common_all,
 							ARRAY_SIZE(stoney_golden_common_all));
 		break;

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

@@ -67,10 +67,10 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_TOPAZ:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							iceland_mgcg_cgcg_init,
 							ARRAY_SIZE(iceland_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_iceland_a11,
 							ARRAY_SIZE(golden_settings_iceland_a11));
 		break;

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

@@ -120,42 +120,42 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_FIJI:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							fiji_mgcg_cgcg_init,
 							ARRAY_SIZE(fiji_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_fiji_a10,
 							ARRAY_SIZE(golden_settings_fiji_a10));
 		break;
 	case CHIP_TONGA:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							tonga_mgcg_cgcg_init,
 							ARRAY_SIZE(tonga_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_tonga_a11,
 							ARRAY_SIZE(golden_settings_tonga_a11));
 		break;
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_polaris11_a11,
 							ARRAY_SIZE(golden_settings_polaris11_a11));
 		break;
 	case CHIP_POLARIS10:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_polaris10_a11,
 							ARRAY_SIZE(golden_settings_polaris10_a11));
 		break;
 	case CHIP_CARRIZO:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							cz_mgcg_cgcg_init,
 							ARRAY_SIZE(cz_mgcg_cgcg_init));
 		break;
 	case CHIP_STONEY:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							stoney_mgcg_cgcg_init,
 							ARRAY_SIZE(stoney_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_stoney_common,
 							ARRAY_SIZE(golden_settings_stoney_common));
 		break;

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

@@ -918,7 +918,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 	bool value;
 	u32 tmp;
 
-	amdgpu_program_register_sequence(adev,
+	amdgpu_device_program_register_sequence(adev,
 						golden_settings_vega10_hdp,
 						ARRAY_SIZE(golden_settings_vega10_hdp));
 

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

@@ -279,29 +279,29 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_FIJI:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							xgpu_fiji_mgcg_cgcg_init,
 							ARRAY_SIZE(
 								xgpu_fiji_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							xgpu_fiji_golden_settings_a10,
 							ARRAY_SIZE(
 								xgpu_fiji_golden_settings_a10));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							xgpu_fiji_golden_common_all,
 							ARRAY_SIZE(
 								xgpu_fiji_golden_common_all));
 		break;
 	case CHIP_TONGA:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							xgpu_tonga_mgcg_cgcg_init,
 							ARRAY_SIZE(
 								xgpu_tonga_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							xgpu_tonga_golden_settings_a11,
 							ARRAY_SIZE(
 								xgpu_tonga_golden_settings_a11));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							xgpu_tonga_golden_common_all,
 							ARRAY_SIZE(
 								xgpu_tonga_golden_common_all));

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

@@ -93,10 +93,10 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_TOPAZ:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							iceland_mgcg_cgcg_init,
 							ARRAY_SIZE(iceland_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_iceland_a11,
 							ARRAY_SIZE(golden_settings_iceland_a11));
 		break;

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

@@ -192,45 +192,45 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_FIJI:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							fiji_mgcg_cgcg_init,
 							ARRAY_SIZE(fiji_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_fiji_a10,
 							ARRAY_SIZE(golden_settings_fiji_a10));
 		break;
 	case CHIP_TONGA:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							tonga_mgcg_cgcg_init,
 							ARRAY_SIZE(tonga_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_tonga_a11,
 							ARRAY_SIZE(golden_settings_tonga_a11));
 		break;
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_polaris11_a11,
 							ARRAY_SIZE(golden_settings_polaris11_a11));
 		break;
 	case CHIP_POLARIS10:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							golden_settings_polaris10_a11,
 							ARRAY_SIZE(golden_settings_polaris10_a11));
 		break;
 	case CHIP_CARRIZO:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							cz_mgcg_cgcg_init,
 							ARRAY_SIZE(cz_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							cz_golden_settings_a11,
 							ARRAY_SIZE(cz_golden_settings_a11));
 		break;
 	case CHIP_STONEY:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							stoney_mgcg_cgcg_init,
 							ARRAY_SIZE(stoney_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							stoney_golden_settings_a11,
 							ARRAY_SIZE(stoney_golden_settings_a11));
 		break;

drivers/gpu/drm/amd/amdgpu/si.c

@@ -1390,63 +1390,63 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_TAHITI:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							tahiti_golden_registers,
 							ARRAY_SIZE(tahiti_golden_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							tahiti_golden_rlc_registers,
 							ARRAY_SIZE(tahiti_golden_rlc_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							tahiti_mgcg_cgcg_init,
 							ARRAY_SIZE(tahiti_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							tahiti_golden_registers2,
 							ARRAY_SIZE(tahiti_golden_registers2));
 		break;
 	case CHIP_PITCAIRN:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							pitcairn_golden_registers,
 							ARRAY_SIZE(pitcairn_golden_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							pitcairn_golden_rlc_registers,
 							ARRAY_SIZE(pitcairn_golden_rlc_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							pitcairn_mgcg_cgcg_init,
 							ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
 		break;
 	case CHIP_VERDE:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							verde_golden_registers,
 							ARRAY_SIZE(verde_golden_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							verde_golden_rlc_registers,
 							ARRAY_SIZE(verde_golden_rlc_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							verde_mgcg_cgcg_init,
 							ARRAY_SIZE(verde_mgcg_cgcg_init));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							verde_pg_init,
 							ARRAY_SIZE(verde_pg_init));
 		break;
 	case CHIP_OLAND:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							oland_golden_registers,
 							ARRAY_SIZE(oland_golden_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							oland_golden_rlc_registers,
 							ARRAY_SIZE(oland_golden_rlc_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							oland_mgcg_cgcg_init,
 							ARRAY_SIZE(oland_mgcg_cgcg_init));
 		break;
 	case CHIP_HAINAN:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							hainan_golden_registers,
 							ARRAY_SIZE(hainan_golden_registers));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							hainan_golden_registers2,
 							ARRAY_SIZE(hainan_golden_registers2));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							hainan_mgcg_cgcg_init,
 							ARRAY_SIZE(hainan_mgcg_cgcg_init));
 		break;

drivers/gpu/drm/amd/amdgpu/vi.c

@@ -282,27 +282,27 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
 
 	switch (adev->asic_type) {
 	case CHIP_TOPAZ:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							iceland_mgcg_cgcg_init,
 							ARRAY_SIZE(iceland_mgcg_cgcg_init));
 		break;
 	case CHIP_FIJI:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							fiji_mgcg_cgcg_init,
 							ARRAY_SIZE(fiji_mgcg_cgcg_init));
 		break;
 	case CHIP_TONGA:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							tonga_mgcg_cgcg_init,
 							ARRAY_SIZE(tonga_mgcg_cgcg_init));
 		break;
 	case CHIP_CARRIZO:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							cz_mgcg_cgcg_init,
 							ARRAY_SIZE(cz_mgcg_cgcg_init));
 		break;
 	case CHIP_STONEY:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_device_program_register_sequence(adev,
 							stoney_mgcg_cgcg_init,
 							ARRAY_SIZE(stoney_mgcg_cgcg_init));
 		break;