Commit 9ca03a21 authored by Russell King's avatar Russell King

ARM: Factor out common code from cpu_proc_fin()

All implementations of cpu_proc_fin() start by disabling interrupts
and then flush caches.  Rather than have every processors proc_fin()
implementation do this, move it out into generic code - and move the
cache flush past setup_mm_for_reboot() (so it can benefit from having
caches still enabled.)

This allows cpu_proc_fin() to become independent of the L1/L2 cache
types, and eventually move the L2 cache flushing into the L2 support
code.
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b8ab5397
...@@ -74,7 +74,11 @@ void machine_kexec(struct kimage *image) ...@@ -74,7 +74,11 @@ void machine_kexec(struct kimage *image)
(unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
printk(KERN_INFO "Bye!\n"); printk(KERN_INFO "Bye!\n");
cpu_proc_fin(); local_irq_disable();
local_fiq_disable();
setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
flush_cache_all();
cpu_proc_fin();
flush_cache_all();
cpu_reset(reboot_code_buffer_phys); cpu_reset(reboot_code_buffer_phys);
} }
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#include <linux/utsname.h> #include <linux/utsname.h>
#include <linux/uaccess.h> #include <linux/uaccess.h>
#include <asm/cacheflush.h>
#include <asm/leds.h> #include <asm/leds.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/system.h> #include <asm/system.h>
...@@ -84,10 +85,9 @@ __setup("hlt", hlt_setup); ...@@ -84,10 +85,9 @@ __setup("hlt", hlt_setup);
void arm_machine_restart(char mode, const char *cmd) void arm_machine_restart(char mode, const char *cmd)
{ {
/* /* Disable interrupts first */
* Clean and disable cache, and turn off interrupts local_irq_disable();
*/ local_fiq_disable();
cpu_proc_fin();
/* /*
* Tell the mm system that we are going to reboot - * Tell the mm system that we are going to reboot -
...@@ -96,6 +96,15 @@ void arm_machine_restart(char mode, const char *cmd) ...@@ -96,6 +96,15 @@ void arm_machine_restart(char mode, const char *cmd)
*/ */
setup_mm_for_reboot(mode); setup_mm_for_reboot(mode);
/* Clean and invalidate caches */
flush_cache_all();
/* Turn off caching */
cpu_proc_fin();
/* Push out any further dirty data, and ensure cache is empty */
flush_cache_all();
/* /*
* Now call the architecture specific reboot code. * Now call the architecture specific reboot code.
*/ */
......
...@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020_proc_init) ...@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020_proc_init)
* cpu_arm1020_proc_fin() * cpu_arm1020_proc_fin()
*/ */
ENTRY(cpu_arm1020_proc_fin) ENTRY(cpu_arm1020_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl arm1020_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_arm1020_reset(loc) * cpu_arm1020_reset(loc)
......
...@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020e_proc_init) ...@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020e_proc_init)
* cpu_arm1020e_proc_fin() * cpu_arm1020e_proc_fin()
*/ */
ENTRY(cpu_arm1020e_proc_fin) ENTRY(cpu_arm1020e_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl arm1020e_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_arm1020e_reset(loc) * cpu_arm1020e_reset(loc)
......
...@@ -68,15 +68,11 @@ ENTRY(cpu_arm1022_proc_init) ...@@ -68,15 +68,11 @@ ENTRY(cpu_arm1022_proc_init)
* cpu_arm1022_proc_fin() * cpu_arm1022_proc_fin()
*/ */
ENTRY(cpu_arm1022_proc_fin) ENTRY(cpu_arm1022_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl arm1022_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_arm1022_reset(loc) * cpu_arm1022_reset(loc)
......
...@@ -68,15 +68,11 @@ ENTRY(cpu_arm1026_proc_init) ...@@ -68,15 +68,11 @@ ENTRY(cpu_arm1026_proc_init)
* cpu_arm1026_proc_fin() * cpu_arm1026_proc_fin()
*/ */
ENTRY(cpu_arm1026_proc_fin) ENTRY(cpu_arm1026_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl arm1026_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_arm1026_reset(loc) * cpu_arm1026_reset(loc)
......
...@@ -184,8 +184,6 @@ ENTRY(cpu_arm7_proc_init) ...@@ -184,8 +184,6 @@ ENTRY(cpu_arm7_proc_init)
ENTRY(cpu_arm6_proc_fin) ENTRY(cpu_arm6_proc_fin)
ENTRY(cpu_arm7_proc_fin) ENTRY(cpu_arm7_proc_fin)
mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, r0
mov r0, #0x31 @ ....S..DP...M mov r0, #0x31 @ ....S..DP...M
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
mov pc, lr mov pc, lr
......
...@@ -54,15 +54,11 @@ ENTRY(cpu_arm720_proc_init) ...@@ -54,15 +54,11 @@ ENTRY(cpu_arm720_proc_init)
mov pc, lr mov pc, lr
ENTRY(cpu_arm720_proc_fin) ENTRY(cpu_arm720_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
mrc p15, 0, r0, c1, c0, 0 mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
mcr p15, 0, r1, c7, c7, 0 @ invalidate cache mov pc, lr
ldmfd sp!, {pc}
/* /*
* Function: arm720_proc_do_idle(void) * Function: arm720_proc_do_idle(void)
......
...@@ -36,15 +36,11 @@ ENTRY(cpu_arm740_switch_mm) ...@@ -36,15 +36,11 @@ ENTRY(cpu_arm740_switch_mm)
* cpu_arm740_proc_fin() * cpu_arm740_proc_fin()
*/ */
ENTRY(cpu_arm740_proc_fin) ENTRY(cpu_arm740_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
mrc p15, 0, r0, c1, c0, 0 mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x3f000000 @ bank/f/lock/s bic r0, r0, #0x3f000000 @ bank/f/lock/s
bic r0, r0, #0x0000000c @ w-buffer/cache bic r0, r0, #0x0000000c @ w-buffer/cache
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
mcr p15, 0, r0, c7, c0, 0 @ invalidate cache mov pc, lr
ldmfd sp!, {pc}
/* /*
* cpu_arm740_reset(loc) * cpu_arm740_reset(loc)
......
...@@ -36,8 +36,6 @@ ENTRY(cpu_arm7tdmi_switch_mm) ...@@ -36,8 +36,6 @@ ENTRY(cpu_arm7tdmi_switch_mm)
* cpu_arm7tdmi_proc_fin() * cpu_arm7tdmi_proc_fin()
*/ */
ENTRY(cpu_arm7tdmi_proc_fin) ENTRY(cpu_arm7tdmi_proc_fin)
mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, r0
mov pc, lr mov pc, lr
/* /*
......
...@@ -69,19 +69,11 @@ ENTRY(cpu_arm920_proc_init) ...@@ -69,19 +69,11 @@ ENTRY(cpu_arm920_proc_init)
* cpu_arm920_proc_fin() * cpu_arm920_proc_fin()
*/ */
ENTRY(cpu_arm920_proc_fin) ENTRY(cpu_arm920_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
bl arm920_flush_kern_cache_all
#else
bl v4wt_flush_kern_cache_all
#endif
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_arm920_reset(loc) * cpu_arm920_reset(loc)
......
...@@ -71,19 +71,11 @@ ENTRY(cpu_arm922_proc_init) ...@@ -71,19 +71,11 @@ ENTRY(cpu_arm922_proc_init)
* cpu_arm922_proc_fin() * cpu_arm922_proc_fin()
*/ */
ENTRY(cpu_arm922_proc_fin) ENTRY(cpu_arm922_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
bl arm922_flush_kern_cache_all
#else
bl v4wt_flush_kern_cache_all
#endif
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_arm922_reset(loc) * cpu_arm922_reset(loc)
......
...@@ -92,15 +92,11 @@ ENTRY(cpu_arm925_proc_init) ...@@ -92,15 +92,11 @@ ENTRY(cpu_arm925_proc_init)
* cpu_arm925_proc_fin() * cpu_arm925_proc_fin()
*/ */
ENTRY(cpu_arm925_proc_fin) ENTRY(cpu_arm925_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl arm925_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_arm925_reset(loc) * cpu_arm925_reset(loc)
......
...@@ -61,15 +61,11 @@ ENTRY(cpu_arm926_proc_init) ...@@ -61,15 +61,11 @@ ENTRY(cpu_arm926_proc_init)
* cpu_arm926_proc_fin() * cpu_arm926_proc_fin()
*/ */
ENTRY(cpu_arm926_proc_fin) ENTRY(cpu_arm926_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl arm926_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_arm926_reset(loc) * cpu_arm926_reset(loc)
......
...@@ -37,15 +37,11 @@ ENTRY(cpu_arm940_switch_mm) ...@@ -37,15 +37,11 @@ ENTRY(cpu_arm940_switch_mm)
* cpu_arm940_proc_fin() * cpu_arm940_proc_fin()
*/ */
ENTRY(cpu_arm940_proc_fin) ENTRY(cpu_arm940_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl arm940_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x00001000 @ i-cache bic r0, r0, #0x00001000 @ i-cache
bic r0, r0, #0x00000004 @ d-cache bic r0, r0, #0x00000004 @ d-cache
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_arm940_reset(loc) * cpu_arm940_reset(loc)
......
...@@ -44,15 +44,11 @@ ENTRY(cpu_arm946_switch_mm) ...@@ -44,15 +44,11 @@ ENTRY(cpu_arm946_switch_mm)
* cpu_arm946_proc_fin() * cpu_arm946_proc_fin()
*/ */
ENTRY(cpu_arm946_proc_fin) ENTRY(cpu_arm946_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl arm946_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x00001000 @ i-cache bic r0, r0, #0x00001000 @ i-cache
bic r0, r0, #0x00000004 @ d-cache bic r0, r0, #0x00000004 @ d-cache
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_arm946_reset(loc) * cpu_arm946_reset(loc)
......
...@@ -36,8 +36,6 @@ ENTRY(cpu_arm9tdmi_switch_mm) ...@@ -36,8 +36,6 @@ ENTRY(cpu_arm9tdmi_switch_mm)
* cpu_arm9tdmi_proc_fin() * cpu_arm9tdmi_proc_fin()
*/ */
ENTRY(cpu_arm9tdmi_proc_fin) ENTRY(cpu_arm9tdmi_proc_fin)
mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, r0
mov pc, lr mov pc, lr
/* /*
......
...@@ -39,17 +39,13 @@ ENTRY(cpu_fa526_proc_init) ...@@ -39,17 +39,13 @@ ENTRY(cpu_fa526_proc_init)
* cpu_fa526_proc_fin() * cpu_fa526_proc_fin()
*/ */
ENTRY(cpu_fa526_proc_fin) ENTRY(cpu_fa526_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl fa_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
nop nop
nop nop
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_fa526_reset(loc) * cpu_fa526_reset(loc)
......
...@@ -75,11 +75,6 @@ ENTRY(cpu_feroceon_proc_init) ...@@ -75,11 +75,6 @@ ENTRY(cpu_feroceon_proc_init)
* cpu_feroceon_proc_fin() * cpu_feroceon_proc_fin()
*/ */
ENTRY(cpu_feroceon_proc_fin) ENTRY(cpu_feroceon_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl feroceon_flush_kern_cache_all
#if defined(CONFIG_CACHE_FEROCEON_L2) && \ #if defined(CONFIG_CACHE_FEROCEON_L2) && \
!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
mov r0, #0 mov r0, #0
...@@ -91,7 +86,7 @@ ENTRY(cpu_feroceon_proc_fin) ...@@ -91,7 +86,7 @@ ENTRY(cpu_feroceon_proc_fin)
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_feroceon_reset(loc) * cpu_feroceon_reset(loc)
......
...@@ -51,15 +51,11 @@ ENTRY(cpu_mohawk_proc_init) ...@@ -51,15 +51,11 @@ ENTRY(cpu_mohawk_proc_init)
* cpu_mohawk_proc_fin() * cpu_mohawk_proc_fin()
*/ */
ENTRY(cpu_mohawk_proc_fin) ENTRY(cpu_mohawk_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl mohawk_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1800 @ ...iz........... bic r0, r0, #0x1800 @ ...iz...........
bic r0, r0, #0x0006 @ .............ca. bic r0, r0, #0x0006 @ .............ca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_mohawk_reset(loc) * cpu_mohawk_reset(loc)
......
...@@ -44,17 +44,13 @@ ENTRY(cpu_sa110_proc_init) ...@@ -44,17 +44,13 @@ ENTRY(cpu_sa110_proc_init)
* cpu_sa110_proc_fin() * cpu_sa110_proc_fin()
*/ */
ENTRY(cpu_sa110_proc_fin) ENTRY(cpu_sa110_proc_fin)
stmfd sp!, {lr} mov r0, #0
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl v4wb_flush_kern_cache_all @ clean caches
1: mov r0, #0
mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_sa110_reset(loc) * cpu_sa110_reset(loc)
......
...@@ -55,16 +55,12 @@ ENTRY(cpu_sa1100_proc_init) ...@@ -55,16 +55,12 @@ ENTRY(cpu_sa1100_proc_init)
* - Clean and turn off caches. * - Clean and turn off caches.
*/ */
ENTRY(cpu_sa1100_proc_fin) ENTRY(cpu_sa1100_proc_fin)
stmfd sp!, {lr}
mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, ip
bl v4wb_flush_kern_cache_all
mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca. bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_sa1100_reset(loc) * cpu_sa1100_reset(loc)
......
...@@ -42,14 +42,11 @@ ENTRY(cpu_v6_proc_init) ...@@ -42,14 +42,11 @@ ENTRY(cpu_v6_proc_init)
mov pc, lr mov pc, lr
ENTRY(cpu_v6_proc_fin) ENTRY(cpu_v6_proc_fin)
stmfd sp!, {lr}
cpsid if @ disable interrupts
bl v6_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x0006 @ .............ca. bic r0, r0, #0x0006 @ .............ca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
/* /*
* cpu_v6_reset(loc) * cpu_v6_reset(loc)
......
...@@ -45,14 +45,11 @@ ENTRY(cpu_v7_proc_init) ...@@ -45,14 +45,11 @@ ENTRY(cpu_v7_proc_init)
ENDPROC(cpu_v7_proc_init) ENDPROC(cpu_v7_proc_init)
ENTRY(cpu_v7_proc_fin) ENTRY(cpu_v7_proc_fin)
stmfd sp!, {lr}
cpsid if @ disable interrupts
bl v7_flush_kern_cache_all
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x0006 @ .............ca. bic r0, r0, #0x0006 @ .............ca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldmfd sp!, {pc} mov pc, lr
ENDPROC(cpu_v7_proc_fin) ENDPROC(cpu_v7_proc_fin)
/* /*
......
...@@ -90,15 +90,11 @@ ENTRY(cpu_xsc3_proc_init) ...@@ -90,15 +90,11 @@ ENTRY(cpu_xsc3_proc_init)
* cpu_xsc3_proc_fin() * cpu_xsc3_proc_fin()
*/ */
ENTRY(cpu_xsc3_proc_fin) ENTRY(cpu_xsc3_proc_fin)
str lr, [sp, #-4]!
mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
msr cpsr_c, r0
bl xsc3_flush_kern_cache_all @ clean caches
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1800 @ ...IZ........... bic r0, r0, #0x1800 @ ...IZ...........
bic r0, r0, #0x0006 @ .............CA. bic r0, r0, #0x0006 @ .............CA.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldr pc, [sp], #4 mov pc, lr
/* /*
* cpu_xsc3_reset(loc) * cpu_xsc3_reset(loc)
......
...@@ -124,15 +124,11 @@ ENTRY(cpu_xscale_proc_init) ...@@ -124,15 +124,11 @@ ENTRY(cpu_xscale_proc_init)
* cpu_xscale_proc_fin() * cpu_xscale_proc_fin()
*/ */
ENTRY(cpu_xscale_proc_fin) ENTRY(cpu_xscale_proc_fin)
str lr, [sp, #-4]!
mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
msr cpsr_c, r0
bl xscale_flush_kern_cache_all @ clean caches
mrc p15, 0, r0, c1, c0, 0 @ ctrl register mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1800 @ ...IZ........... bic r0, r0, #0x1800 @ ...IZ...........
bic r0, r0, #0x0006 @ .............CA. bic r0, r0, #0x0006 @ .............CA.
mcr p15, 0, r0, c1, c0, 0 @ disable caches mcr p15, 0, r0, c1, c0, 0 @ disable caches
ldr pc, [sp], #4 mov pc, lr
/* /*
* cpu_xscale_reset(loc) * cpu_xscale_reset(loc)
......
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