From a06a1a1b1da7d4ad212ae28623621363d1b97253 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: Fri, 13 Feb 2004 12:57:25 +1100 Subject: [PATCH] ppc64: Add some definitions relative to the G5 CPU and POWERMAC platform --- arch/ppc64/kernel/smp.c | 7 ------- include/asm-ppc64/processor.h | 20 +++++++++++++++++++- include/asm-ppc64/sections.h | 12 ++++++++++++ include/asm-ppc64/systemcfg.h | 6 ++++++ 4 files changed, 37 insertions(+), 8 deletions(-) diff --git a/arch/ppc64/kernel/smp.c b/arch/ppc64/kernel/smp.c index 2b2d286fec65..101441d0adc7 100644 --- a/arch/ppc64/kernel/smp.c +++ b/arch/ppc64/kernel/smp.c @@ -76,13 +76,6 @@ extern long register_vpa(unsigned long flags, unsigned long proc, #define smp_message_pass(t,m,d,w) smp_ops->message_pass((t),(m),(d),(w)) -static inline void set_tb(unsigned int upper, unsigned int lower) -{ - mttbl(0); - mttbu(upper); - mttbl(lower); -} - #ifdef CONFIG_PPC_ISERIES static unsigned long iSeries_smp_message[NR_CPUS]; diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h index ffb684f7ab71..1bde268f4d85 100644 --- a/include/asm-ppc64/processor.h +++ b/include/asm-ppc64/processor.h @@ -216,8 +216,11 @@ #define HID0_BHTE (1<<2) /* Branch History Table Enable */ #define HID0_BTCD (1<<1) /* Branch target cache disable */ #define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */ +#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #define SPRN_NIADORM 0x3F3 /* Hardware Implementation Register 2 */ +#define SPRN_HID4 0x3F4 /* 970 HID4 */ +#define SPRN_HID5 0x3F6 /* 970 HID5 */ #define SPRN_TSC 0x3FD /* Thread switch control */ #define SPRN_TST 0x3FC /* Thread switch timeout */ #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ @@ -263,6 +266,7 @@ #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */ #define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */ +#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ #define SPRN_TCR 0x3DA /* Timer Control Register */ #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ #define WP_2_17 0 /* 2^17 clocks */ @@ -373,6 +377,7 @@ #define PV_ICESTAR 0x0036 #define PV_SSTAR 0x0037 #define PV_POWER4p 0x0038 +#define PV_GPUL 0x0039 #define PV_POWER5 0x003A #define PV_630 0x0040 #define PV_630p 0x0041 @@ -382,7 +387,12 @@ #define PLATFORM_PSERIES_LPAR 0x0101 #define PLATFORM_ISERIES_LPAR 0x0201 #define PLATFORM_LPAR 0x0001 - +#define PLATFORM_POWERMAC 0x0400 + +/* Compatibility with drivers coming from PPC32 world */ +#define _machine (systemcfg->platform) +#define _MACH_Pmac PLATFORM_POWERMAC + /* * List of interrupt controllers. */ @@ -457,6 +467,14 @@ GLUE(.,name): asm volatile("mfasr %0" : "=r" (rval)); rval;}) #ifndef __ASSEMBLY__ + +static inline void set_tb(unsigned int upper, unsigned int lower) +{ + mttbl(0); + mttbu(upper); + mttbl(lower); +} + extern unsigned long *_get_SP(void); extern int have_of; diff --git a/include/asm-ppc64/sections.h b/include/asm-ppc64/sections.h index b74722491931..95bac41d79b8 100644 --- a/include/asm-ppc64/sections.h +++ b/include/asm-ppc64/sections.h @@ -5,4 +5,16 @@ extern char _end[]; #include <asm-generic/sections.h> +#define __pmac +#define __pmacdata + +#define __prep +#define __prepdata + +#define __chrp +#define __chrpdata + +#define __openfirmware +#define __openfirmwaredata + #endif diff --git a/include/asm-ppc64/systemcfg.h b/include/asm-ppc64/systemcfg.h index b78c5a2828ca..72b5adba9325 100644 --- a/include/asm-ppc64/systemcfg.h +++ b/include/asm-ppc64/systemcfg.h @@ -72,6 +72,7 @@ extern struct systemcfg *systemcfg; #define PV_ICESTAR 0x0036 #define PV_SSTAR 0x0037 #define PV_POWER4p 0x0038 +#define PV_GPUL 0x0039 #define PV_630 0x0040 #define PV_630p 0x0041 @@ -79,6 +80,11 @@ extern struct systemcfg *systemcfg; #define PLATFORM_PSERIES 0x0100 #define PLATFORM_PSERIES_LPAR 0x0101 #define PLATFORM_ISERIES_LPAR 0x0201 +#define PLATFORM_POWERMAC 0x0400 + +/* Compatibility with drivers coming from PPC32 world */ +#define _machine (systemcfg->platform) +#define _MACH_Pmac PLATFORM_POWERMAC static inline volatile struct systemcfg *systemcfg_init(void) -- 2.30.9