Skip to content

L
linux
Commit a1606a95 authored by Ben Skeggs's avatar Ben Skeggs
Browse files
Options

drm/nouveau: new gem pushbuf interface, bump to 0.0.16 

This commit breaks the userspace interface, and requires a new libdrm for
nouveau to operate again.

The multiple GEM_PUSHBUF ioctls that were present in 0.0.15 for
compatibility purposes are now gone, and replaced with the new ioctl which
allows for multiple push buffers to be submitted (necessary for hw index
buffers in the nv50 3d driver) and relocations to be applied on any buffer.

A number of other ioctls (CARD_INIT, GEM_PIN, GEM_UNPIN) that were needed
for userspace modesetting have also been removed.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Signed-off-by: default avatarFrancisco Jerez <currojerez@riseup.net>
parent d87897d4
Expand all Show whitespace changes
Inline Side-by-side
Showing with 208 additions and 404 deletions
drivers/gpu/drm/nouveau/nouveau_channel.c
View file @ a1606a95
...@@ -385,6 +385,14 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, ...@@ -385,6 +385,14 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
return ret; return ret;
init->channel = chan->id; init->channel = chan->id;
if (chan->dma.ib_max)
init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
NOUVEAU_GEM_DOMAIN_GART;
else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
else
init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
init->subchan[0].handle = NvM2MF; init->subchan[0].handle = NvM2MF;
if (dev_priv->card_type < NV_50) if (dev_priv->card_type < NV_50)
init->subchan[0].grclass = 0x0039; init->subchan[0].grclass = 0x0039;
...@@ -424,7 +432,6 @@ nouveau_ioctl_fifo_free(struct drm_device *dev, void *data, ...@@ -424,7 +432,6 @@ nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
***********************************/ ***********************************/
struct drm_ioctl_desc nouveau_ioctls[] = { struct drm_ioctl_desc nouveau_ioctls[] = {
DRM_IOCTL_DEF(DRM_NOUVEAU_CARD_INIT, nouveau_ioctl_card_init, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
...@@ -434,13 +441,9 @@ struct drm_ioctl_desc nouveau_ioctls[] = { ...@@ -434,13 +441,9 @@ struct drm_ioctl_desc nouveau_ioctls[] = {
DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF_CALL, nouveau_gem_ioctl_pushbuf_call, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PIN, nouveau_gem_ioctl_pin, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_UNPIN, nouveau_gem_ioctl_unpin, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF_CALL2, nouveau_gem_ioctl_pushbuf_call2, DRM_AUTH),
}; };
int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls); int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
drivers/gpu/drm/nouveau/nouveau_dma.c
View file @ a1606a95
...@@ -179,7 +179,7 @@ READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout) ...@@ -179,7 +179,7 @@ READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
void void
nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
int delta, int dwords) int delta, int length)
{ {
struct nouveau_bo *pb = chan->pushbuf_bo; struct nouveau_bo *pb = chan->pushbuf_bo;
uint64_t offset = bo->bo.offset + delta; uint64_t offset = bo->bo.offset + delta;
...@@ -187,7 +187,7 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, ...@@ -187,7 +187,7 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
BUG_ON(chan->dma.ib_free < 1); BUG_ON(chan->dma.ib_free < 1);
nouveau_bo_wr32(pb, ip++, lower_32_bits(offset)); nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | dwords << 10); nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max; chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
nvchan_wr32(chan, 0x8c, chan->dma.ib_put); nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
......
drivers/gpu/drm/nouveau/nouveau_dma.h
View file @ a1606a95
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#endif #endif
void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *, void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *,
int delta, int dwords); int delta, int length);
/* /*
* There's a hw race condition where you can't jump to your PUT offset, * There's a hw race condition where you can't jump to your PUT offset,
...@@ -149,7 +149,7 @@ FIRE_RING(struct nouveau_channel *chan) ...@@ -149,7 +149,7 @@ FIRE_RING(struct nouveau_channel *chan)
if (chan->dma.ib_max) { if (chan->dma.ib_max) {
nv50_dma_push(chan, chan->pushbuf_bo, chan->dma.put << 2, nv50_dma_push(chan, chan->pushbuf_bo, chan->dma.put << 2,
chan->dma.cur - chan->dma.put); (chan->dma.cur - chan->dma.put) << 2);
} else { } else {
WRITE_PUT(chan->dma.cur); WRITE_PUT(chan->dma.cur);
} }
......
drivers/gpu/drm/nouveau/nouveau_drv.h
View file @ a1606a95
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
#define DRIVER_MAJOR 0 #define DRIVER_MAJOR 0
#define DRIVER_MINOR 0 #define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 15 #define DRIVER_PATCHLEVEL 16
#define NOUVEAU_FAMILY 0x0000FFFF #define NOUVEAU_FAMILY 0x0000FFFF
#define NOUVEAU_FLAGS 0xFFFF0000 #define NOUVEAU_FLAGS 0xFFFF0000
...@@ -83,6 +83,7 @@ struct nouveau_bo { ...@@ -83,6 +83,7 @@ struct nouveau_bo {
struct drm_file *reserved_by; struct drm_file *reserved_by;
struct list_head entry; struct list_head entry;
int pbbo_index; int pbbo_index;
bool validate_mapped;
struct nouveau_channel *channel; struct nouveau_channel *channel;
...@@ -704,12 +705,6 @@ extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, ...@@ -704,12 +705,6 @@ extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
uint32_t reg, uint32_t mask, uint32_t val); uint32_t reg, uint32_t mask, uint32_t val);
extern bool nouveau_wait_for_idle(struct drm_device *); extern bool nouveau_wait_for_idle(struct drm_device *);
extern int nouveau_card_init(struct drm_device *); extern int nouveau_card_init(struct drm_device *);
extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
struct drm_file *);
extern int nouveau_ioctl_suspend(struct drm_device *, void *data,
struct drm_file *);
extern int nouveau_ioctl_resume(struct drm_device *, void *data,
struct drm_file *);
/* nouveau_mem.c */ /* nouveau_mem.c */
extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start, extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
...@@ -1160,16 +1155,6 @@ extern int nouveau_gem_ioctl_new(struct drm_device *, void *, ...@@ -1160,16 +1155,6 @@ extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
struct drm_file *); struct drm_file *);
extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
struct drm_file *); struct drm_file *);
extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *,
struct drm_file *);
extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *,
struct drm_file *);
extern int nouveau_gem_ioctl_pin(struct drm_device *, void *,
struct drm_file *);
extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *,
struct drm_file *);
extern int nouveau_gem_ioctl_tile(struct drm_device *, void *,
struct drm_file *);
extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
struct drm_file *); struct drm_file *);
extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
......
drivers/gpu/drm/nouveau/nouveau_gem.c
View file @ a1606a95
This diff is collapsed.
drivers/gpu/drm/nouveau/nouveau_state.c
View file @ a1606a95
...@@ -777,13 +777,6 @@ int nouveau_unload(struct drm_device *dev) ...@@ -777,13 +777,6 @@ int nouveau_unload(struct drm_device *dev)
return 0; return 0;
} }
int
nouveau_ioctl_card_init(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
return nouveau_card_init(dev);
}
int nouveau_ioctl_getparam(struct drm_device *dev, void *data, int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
struct drm_file *file_priv) struct drm_file *file_priv)
{ {
......
include/drm/nouveau_drm.h
View file @ a1606a95
...@@ -25,13 +25,14 @@ ...@@ -25,13 +25,14 @@
#ifndef __NOUVEAU_DRM_H__ #ifndef __NOUVEAU_DRM_H__
#define __NOUVEAU_DRM_H__ #define __NOUVEAU_DRM_H__
#define NOUVEAU_DRM_HEADER_PATCHLEVEL 15 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
struct drm_nouveau_channel_alloc { struct drm_nouveau_channel_alloc {
uint32_t fb_ctxdma_handle; uint32_t fb_ctxdma_handle;
uint32_t tt_ctxdma_handle; uint32_t tt_ctxdma_handle;
int channel; int channel;
uint32_t pushbuf_domains;
/* Notifier memory */ /* Notifier memory */
uint32_t notifier_handle; uint32_t notifier_handle;
...@@ -109,68 +110,58 @@ struct drm_nouveau_gem_new { ...@@ -109,68 +110,58 @@ struct drm_nouveau_gem_new {
uint32_t align; uint32_t align;
}; };
#define NOUVEAU_GEM_MAX_BUFFERS 1024
struct drm_nouveau_gem_pushbuf_bo_presumed {
uint32_t valid;
uint32_t domain;
uint64_t offset;
};
struct drm_nouveau_gem_pushbuf_bo { struct drm_nouveau_gem_pushbuf_bo {
uint64_t user_priv; uint64_t user_priv;
uint32_t handle; uint32_t handle;
uint32_t read_domains; uint32_t read_domains;
uint32_t write_domains; uint32_t write_domains;
uint32_t valid_domains; uint32_t valid_domains;
uint32_t presumed_ok; struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
uint32_t presumed_domain;
uint64_t presumed_offset;
}; };
#define NOUVEAU_GEM_RELOC_LOW (1 << 0) #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
#define NOUVEAU_GEM_RELOC_HIGH (1 << 1) #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
#define NOUVEAU_GEM_RELOC_OR (1 << 2) #define NOUVEAU_GEM_RELOC_OR (1 << 2)
#define NOUVEAU_GEM_MAX_RELOCS 1024
struct drm_nouveau_gem_pushbuf_reloc { struct drm_nouveau_gem_pushbuf_reloc {
uint32_t reloc_bo_index;
uint32_t reloc_bo_offset;
uint32_t bo_index; uint32_t bo_index;
uint32_t reloc_index;
uint32_t flags; uint32_t flags;
uint32_t data; uint32_t data;
uint32_t vor; uint32_t vor;
uint32_t tor; uint32_t tor;
}; };
#define NOUVEAU_GEM_MAX_BUFFERS 1024 #define NOUVEAU_GEM_MAX_PUSH 512
#define NOUVEAU_GEM_MAX_RELOCS 1024 struct drm_nouveau_gem_pushbuf_push {
uint32_t bo_index;
uint32_t pad;
uint64_t offset;
uint64_t length;
};
struct drm_nouveau_gem_pushbuf { struct drm_nouveau_gem_pushbuf {
uint32_t channel; uint32_t channel;
uint32_t nr_dwords;
uint32_t nr_buffers; uint32_t nr_buffers;
uint32_t nr_relocs;
uint64_t dwords;
uint64_t buffers; uint64_t buffers;
uint64_t relocs;
};
struct drm_nouveau_gem_pushbuf_call {
uint32_t channel;
uint32_t handle;
uint32_t offset;
uint32_t nr_buffers;
uint32_t nr_relocs; uint32_t nr_relocs;
uint32_t nr_dwords; uint32_t nr_push;
uint64_t buffers;
uint64_t relocs; uint64_t relocs;
uint64_t push;
uint32_t suffix0; uint32_t suffix0;
uint32_t suffix1; uint32_t suffix1;
/* below only accessed for CALL2 */
uint64_t vram_available; uint64_t vram_available;
uint64_t gart_available; uint64_t gart_available;
}; };
struct drm_nouveau_gem_pin {
uint32_t handle;
uint32_t domain;
uint64_t offset;
};
struct drm_nouveau_gem_unpin {
uint32_t handle;
};
#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 #define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
...@@ -183,14 +174,6 @@ struct drm_nouveau_gem_cpu_fini { ...@@ -183,14 +174,6 @@ struct drm_nouveau_gem_cpu_fini {
uint32_t handle; uint32_t handle;
}; };
struct drm_nouveau_gem_tile {
uint32_t handle;
uint32_t offset;
uint32_t size;
uint32_t tile_mode;
uint32_t tile_flags;
};
enum nouveau_bus_type { enum nouveau_bus_type {
NV_AGP = 0, NV_AGP = 0,
NV_PCI = 1, NV_PCI = 1,
...@@ -200,22 +183,17 @@ enum nouveau_bus_type { ...@@ -200,22 +183,17 @@ enum nouveau_bus_type {
struct drm_nouveau_sarea { struct drm_nouveau_sarea {
}; };
#define DRM_NOUVEAU_CARD_INIT 0x00 #define DRM_NOUVEAU_GETPARAM 0x00
#define DRM_NOUVEAU_GETPARAM 0x01 #define DRM_NOUVEAU_SETPARAM 0x01
#define DRM_NOUVEAU_SETPARAM 0x02 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03 #define DRM_NOUVEAU_CHANNEL_FREE 0x03
#define DRM_NOUVEAU_CHANNEL_FREE 0x04 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04
#define DRM_NOUVEAU_GROBJ_ALLOC 0x05 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06
#define DRM_NOUVEAU_GPUOBJ_FREE 0x07
#define DRM_NOUVEAU_GEM_NEW 0x40 #define DRM_NOUVEAU_GEM_NEW 0x40
#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
#define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42
#define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */ #define DRM_NOUVEAU_GEM_CPU_FINI 0x43
#define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */ #define DRM_NOUVEAU_GEM_INFO 0x44
#define DRM_NOUVEAU_GEM_CPU_PREP 0x45
#define DRM_NOUVEAU_GEM_CPU_FINI 0x46
#define DRM_NOUVEAU_GEM_INFO 0x47
#define DRM_NOUVEAU_GEM_PUSHBUF_CALL2 0x48
#endif /* __NOUVEAU_DRM_H__ */ #endif /* __NOUVEAU_DRM_H__ */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7