[SPARC64]: Fix bad performance side effect of strbuf timeout changes.

The recent change to add a timeout to strbuf flushing had
a negative performance impact.  The udelay()'s are too long,
and they were done in the wrong order wrt. the register read
checks.  Fix both, and things are happy again.

There are more possible improvements in this area.  In fact,
PCI streaming buffer flushing seems to be part of the bottleneck
in network receive performance on my SunBlade1000 box.
Signed-off-by: David S. Miller <davem@davemloft.net>

arch/sparc64/kernel/pci_iommu.c

@@ -392,14 +392,16 @@ static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu,
 		flushreg = strbuf->strbuf_ctxflush;
 		matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
 
-		limit = 10000;
-		do {
+		limit = 100000;
 		pci_iommu_write(flushreg, ctx);
-			udelay(10);
+		for(;;) {
+			if (((long)pci_iommu_read(matchreg)) >= 0L)
+				break;
 			limit--;
 			if (!limit)
 				break;
-		} while(((long)pci_iommu_read(matchreg)) < 0L);
+			udelay(1);
+		}
 		if (!limit)
 			printk(KERN_WARNING "pci_strbuf_flush: ctx flush "
 			       "timeout vaddr[%08x] ctx[%lx]\n",
@@ -414,12 +416,12 @@ static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu,
 	pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
 	(void) pci_iommu_read(iommu->write_complete_reg);
 
-	limit = 10000;
+	limit = 100000;
 	while (!PCI_STC_FLUSHFLAG_SET(strbuf)) {
 		limit--;
 		if (!limit)
 			break;
-		udelay(10);
+		udelay(1);
 		membar("#LoadLoad");
 	}
 	if (!limit)

arch/sparc64/kernel/sbus.c

@@ -133,12 +133,12 @@ static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long
 		   iommu->strbuf_regs + STRBUF_FSYNC);
 	upa_readq(iommu->sbus_control_reg);
 
-	limit = 10000;
+	limit = 100000;
 	while (iommu->strbuf_flushflag == 0UL) {
 		limit--;
 		if (!limit)
 			break;
-		udelay(10);
+		udelay(1);
 		membar("#LoadLoad");
 	}
 	if (!limit)