Commit a5760db2 authored by Randy Dunlap's avatar Randy Dunlap Committed by Vineet Gupta

ARC: fix some Kconfig typos

Fix language typos in arch/arc/Kconfig.

Cc: linux-snps-arc@lists.infradead.org
Signed-off-by: default avatarRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent d560bb42
...@@ -154,7 +154,7 @@ config ARC_CPU_HS ...@@ -154,7 +154,7 @@ config ARC_CPU_HS
help help
Support for ARC HS38x Cores based on ARCv2 ISA Support for ARC HS38x Cores based on ARCv2 ISA
The notable features are: The notable features are:
- SMP configurations of upto 4 core with coherency - SMP configurations of up to 4 cores with coherency
- Optional L2 Cache and IO-Coherency - Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks, - Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore) auto stack switch, auto regfile save/restore)
...@@ -192,7 +192,7 @@ config ARC_SMP_HALT_ON_RESET ...@@ -192,7 +192,7 @@ config ARC_SMP_HALT_ON_RESET
help help
In SMP configuration cores can be configured as Halt-on-reset In SMP configuration cores can be configured as Halt-on-reset
or they could all start at same time. For Halt-on-reset, non or they could all start at same time. For Halt-on-reset, non
masters are parked until Master kicks them so they can start of masters are parked until Master kicks them so they can start off
at designated entry point. For other case, all jump to common at designated entry point. For other case, all jump to common
entry point and spin wait for Master's signal. entry point and spin wait for Master's signal.
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment