Commit a747c9ce authored by James Smart's avatar James Smart Committed by James Bottomley

[SCSI] lpfc 8.3.6 : Hardware related fixes and changes

Hardware related Fixes and Changes.
 - Added new Adapter IDs and update default Adapter names.
 - Added PCI read after EQarm doorbell PCI write to flush the write
   and avoid spurrious interrupts when in INTx mode.
 - Phase out use of ONLINE registers.
 - Fix for lost MSI interrupt
Signed-off-by: default avatarJames Smart <james.smart@emulex.com>
Signed-off-by: default avatarJames Bottomley <James.Bottomley@suse.de>
parent 1c6f4ef5
......@@ -1168,7 +1168,8 @@ typedef struct {
#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
#define PCI_VENDOR_ID_SERVERENGINE 0x19a2
#define PCI_DEVICE_ID_TIGERSHARK 0x0704
#define PCI_DEVICE_ID_TS_BE3 0x0714
#define PCI_DEVICE_ID_TOMCAT 0x0714
#define PCI_DEVICE_ID_FALCON 0xf180
#define JEDEC_ID_ADDRESS 0x0080001c
#define FIREFLY_JEDEC_ID 0x1ACC
......
......@@ -514,8 +514,8 @@ struct lpfc_register {
#define LPFC_UERR_STATUS_HI 0x00A4
#define LPFC_UERR_STATUS_LO 0x00A0
#define LPFC_ONLINE0 0x00B0
#define LPFC_ONLINE1 0x00B4
#define LPFC_UE_MASK_HI 0x00AC
#define LPFC_UE_MASK_LO 0x00A8
#define LPFC_SCRATCHPAD 0x0058
/* BAR0 Registers */
......
This diff is collapsed.
......@@ -263,6 +263,9 @@ lpfc_sli4_eq_release(struct lpfc_queue *q, bool arm)
bf_set(lpfc_eqcq_doorbell_qt, &doorbell, LPFC_QUEUE_TYPE_EVENT);
bf_set(lpfc_eqcq_doorbell_eqid, &doorbell, q->queue_id);
writel(doorbell.word0, q->phba->sli4_hba.EQCQDBregaddr);
/* PCI read to flush PCI pipeline on re-arming for INTx mode */
if ((q->phba->intr_type == INTx) && (arm == LPFC_QUEUE_REARM))
readl(q->phba->sli4_hba.EQCQDBregaddr);
return released;
}
......@@ -7686,23 +7689,21 @@ static int
lpfc_sli4_eratt_read(struct lpfc_hba *phba)
{
uint32_t uerr_sta_hi, uerr_sta_lo;
uint32_t onlnreg0, onlnreg1;
/* For now, use the SLI4 device internal unrecoverable error
* registers for error attention. This can be changed later.
*/
onlnreg0 = readl(phba->sli4_hba.ONLINE0regaddr);
onlnreg1 = readl(phba->sli4_hba.ONLINE1regaddr);
if ((onlnreg0 != LPFC_ONLINE_NERR) || (onlnreg1 != LPFC_ONLINE_NERR)) {
uerr_sta_lo = readl(phba->sli4_hba.UERRLOregaddr);
uerr_sta_hi = readl(phba->sli4_hba.UERRHIregaddr);
if (uerr_sta_lo || uerr_sta_hi) {
if ((~phba->sli4_hba.ue_mask_lo & uerr_sta_lo) ||
(~phba->sli4_hba.ue_mask_hi & uerr_sta_hi)) {
lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
"1423 HBA Unrecoverable error: "
"uerr_lo_reg=0x%x, uerr_hi_reg=0x%x, "
"online0_reg=0x%x, online1_reg=0x%x\n",
"ue_mask_lo_reg=0x%x, ue_mask_hi_reg=0x%x\n",
uerr_sta_lo, uerr_sta_hi,
onlnreg0, onlnreg1);
phba->sli4_hba.ue_mask_lo,
phba->sli4_hba.ue_mask_hi);
phba->work_status[0] = uerr_sta_lo;
phba->work_status[1] = uerr_sta_hi;
/* Set the driver HA work bitmap */
......@@ -7711,7 +7712,6 @@ lpfc_sli4_eratt_read(struct lpfc_hba *phba)
phba->hba_flag |= HBA_ERATT_HANDLED;
return 1;
}
}
return 0;
}
......@@ -7833,7 +7833,7 @@ irqreturn_t
lpfc_sli_sp_intr_handler(int irq, void *dev_id)
{
struct lpfc_hba *phba;
uint32_t ha_copy;
uint32_t ha_copy, hc_copy;
uint32_t work_ha_copy;
unsigned long status;
unsigned long iflag;
......@@ -7891,8 +7891,13 @@ lpfc_sli_sp_intr_handler(int irq, void *dev_id)
}
/* Clear up only attention source related to slow-path */
hc_copy = readl(phba->HCregaddr);
writel(hc_copy & ~(HC_MBINT_ENA | HC_R2INT_ENA |
HC_LAINT_ENA | HC_ERINT_ENA),
phba->HCregaddr);
writel((ha_copy & (HA_MBATT | HA_R2_CLR_MSK)),
phba->HAregaddr);
writel(hc_copy, phba->HCregaddr);
readl(phba->HAregaddr); /* flush */
spin_unlock_irqrestore(&phba->hbalock, iflag);
} else
......@@ -8202,6 +8207,7 @@ lpfc_sli_intr_handler(int irq, void *dev_id)
struct lpfc_hba *phba;
irqreturn_t sp_irq_rc, fp_irq_rc;
unsigned long status1, status2;
uint32_t hc_copy;
/*
* Get the driver's phba structure from the dev_id and
......@@ -8239,7 +8245,12 @@ lpfc_sli_intr_handler(int irq, void *dev_id)
}
/* Clear attention sources except link and error attentions */
hc_copy = readl(phba->HCregaddr);
writel(hc_copy & ~(HC_MBINT_ENA | HC_R0INT_ENA | HC_R1INT_ENA
| HC_R2INT_ENA | HC_LAINT_ENA | HC_ERINT_ENA),
phba->HCregaddr);
writel((phba->ha_copy & ~(HA_LATT | HA_ERATT)), phba->HAregaddr);
writel(hc_copy, phba->HCregaddr);
readl(phba->HAregaddr); /* flush */
spin_unlock(&phba->hbalock);
......
......@@ -293,9 +293,8 @@ struct lpfc_sli4_hba {
/* BAR0 PCI config space register memory map */
void __iomem *UERRLOregaddr; /* Address to UERR_STATUS_LO register */
void __iomem *UERRHIregaddr; /* Address to UERR_STATUS_HI register */
void __iomem *ONLINE0regaddr; /* Address to components of internal UE */
void __iomem *ONLINE1regaddr; /* Address to components of internal UE */
#define LPFC_ONLINE_NERR 0xFFFFFFFF
void __iomem *UEMASKLOregaddr; /* Address to UE_MASK_LO register */
void __iomem *UEMASKHIregaddr; /* Address to UE_MASK_HI register */
void __iomem *SCRATCHPADregaddr; /* Address to scratchpad register */
/* BAR1 FCoE function CSR register memory map */
void __iomem *STAregaddr; /* Address to HST_STATE register */
......@@ -309,6 +308,8 @@ struct lpfc_sli4_hba {
void __iomem *MQDBregaddr; /* Address to MQ_DOORBELL register */
void __iomem *BMBXregaddr; /* Address to BootStrap MBX register */
uint32_t ue_mask_lo;
uint32_t ue_mask_hi;
struct msix_entry *msix_entries;
uint32_t cfg_eqn;
struct lpfc_fcp_eq_hdl *fcp_eq_hdl; /* FCP per-WQ handle */
......
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