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Commit b0925249 authored by James Simmons's avatar James Simmons
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Updates to the NVIDIA driver. We now support more cards. I still have more hacking to do.

parent 8d7c2813
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drivers/video/i810/Makefile 0 → 100644
View file @ b0925249
#
# Makefile for the Intel 810/815 framebuffer driver
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
# Note 2! The CFLAGS definitions are now in the main makefile...
obj-$(CONFIG_FB_I810) += i810fb.o
i810fb-objs := i810_main.o i810_accel.o
ifdef CONFIG_FB_I810_GTF
i810fb-objs += i810_gtf.o
else
i810fb-objs += i810_dvt.o
endif
include $(TOPDIR)/Rules.make
drivers/video/riva/fbdev.c
View file @ b0925249
This diff is collapsed.
drivers/video/riva/nv_type.h 0 → 100644
View file @ b0925249
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.35 2002/08/05 20:47:06 mvojkovi Exp $ */
#ifndef __NV_STRUCT_H__
#define __NV_STRUCT_H__
#define NV_CHIP_RIVA_128 ((PCI_VENDOR_ID_NVIDIA_SGS << 16)| PCI_DEVICE_ID_NVIDIA_RIVA128)
#define NV_CHIP_TNT ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT)
#define NV_CHIP_TNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT2)
#define NV_CHIP_UTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UTNT2)
#define NV_CHIP_VTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_VTNT2)
#define NV_CHIP_UVTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UVTNT2)
#define NV_CHIP_ITNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_ITNT2)
#define NV_CHIP_GEFORCE_256 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_256)
#define NV_CHIP_GEFORCE_DDR ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR)
#define NV_CHIP_QUADRO ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_QUADRO)
#define NV_CHIP_GEFORCE2_MX ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX)
#define NV_CHIP_GEFORCE2_MX_100 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX_100)
#define NV_CHIP_QUADRO2_MXR ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR)
#define NV_CHIP_GEFORCE2_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO)
#define NV_CHIP_GEFORCE2_GTS ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS)
#define NV_CHIP_GEFORCE2_TI ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_TI)
#define NV_CHIP_GEFORCE2_ULTRA ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA)
#define NV_CHIP_QUADRO2_PRO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO)
#define NV_CHIP_GEFORCE4_MX_460 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460)
#define NV_CHIP_GEFORCE4_MX_440 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440)
#define NV_CHIP_GEFORCE4_MX_420 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420)
#define NV_CHIP_GEFORCE4_440_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO)
#define NV_CHIP_GEFORCE4_420_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO)
#define NV_CHIP_GEFORCE4_420_GO_M32 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32)
#define NV_CHIP_QUADRO4_500XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL)
#define NV_CHIP_GEFORCE4_440_GO_M64 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64)
#define NV_CHIP_QUADRO4_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_200)
#define NV_CHIP_QUADRO4_550XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL)
#define NV_CHIP_QUADRO4_500_GOGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL)
#define NV_CHIP_0x0180 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0180)
#define NV_CHIP_0x0181 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0181)
#define NV_CHIP_0x0182 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0182)
#define NV_CHIP_0x0188 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0188)
#define NV_CHIP_0x018A ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018A)
#define NV_CHIP_0x018B ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018B)
#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_IGEFORCE2)
#define NV_CHIP_0x01F0 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x01F0)
#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3)
#define NV_CHIP_GEFORCE3_TI_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_200)
#define NV_CHIP_GEFORCE3_TI_500 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_500)
#define NV_CHIP_QUADRO_DCC ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO_DCC)
#define NV_CHIP_GEFORCE4_TI_4600 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600)
#define NV_CHIP_GEFORCE4_TI_4400 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400)
#define NV_CHIP_GEFORCE4_TI_4200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200)
#define NV_CHIP_QUADRO4_900XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL)
#define NV_CHIP_QUADRO4_750XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL)
#define NV_CHIP_QUADRO4_700XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL)
#define NV_CHIP_0x0280 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0280)
#define NV_CHIP_0x0281 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0281)
#define NV_CHIP_0x0288 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0288)
#define NV_CHIP_0x0289 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0289)
#endif /* __NV_STRUCT_H__ */
drivers/video/riva/riva_hw.c
View file @ b0925249
......@@ -46,8 +46,12 @@
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.8 2000/02/08 17:19:11 dawes Exp $ */
#include <linux/pci_ids.h>
#include <linux/pci.h>
#include "riva_hw.h"
#include "riva_tbl.h"
#include "nv_type.h"
/*
* This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
* operate identically (except TNT has more memory and better 3D quality.
......@@ -76,29 +80,29 @@ static int nv10Busy
static void nv3LockUnlock
(
RIVA_HW_INST *chip,
int LockUnlock
int Lock
)
{
VGA_WR08(chip->PVIO, 0x3C4, 0x06);
VGA_WR08(chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57);
VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
}
static void nv4LockUnlock
(
RIVA_HW_INST *chip,
int LockUnlock
int Lock
)
{
VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57);
VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
}
static void nv10LockUnlock
(
RIVA_HW_INST *chip,
int LockUnlock
int Lock
)
{
VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57);
VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
}
static int ShowHideCursor
......@@ -107,13 +111,13 @@ static int ShowHideCursor
int ShowHide
)
{
int current;
current = chip->CurrentState->cursor1;
int cursor;
cursor = chip->CurrentState->cursor1;
chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
(ShowHide & 0x01);
VGA_WR08(chip->PCIO, 0x3D4, 0x31);
VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
return (current & 0x01);
return (cursor & 0x01);
}
/****************************************************************************\
......@@ -1285,6 +1289,7 @@ static void UpdateFifoState
chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
break;
case NV_ARCH_10:
case NV_ARCH_20:
/*
* Initialize state for the RivaTriangle3D05 routines.
*/
......
drivers/video/riva/riva_hw.h
View file @ b0925249
......@@ -49,6 +49,20 @@
#define __RIVA_HW_H__
#define RIVA_SW_VERSION 0x00010003
#ifndef Bool
typedef int Bool;
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
/*
* Typedefs to force certain sized values.
*/
......@@ -59,8 +73,14 @@ typedef unsigned int U032;
/*
* HW access macros.
*/
#if defined(__powerpc__)
#include <asm/io.h>
#define NV_WR08(p,i,d) out_8(p+i, d)
#define NV_RD08(p,i) in_8(p+i)
#else
#define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d))
#define NV_RD08(p,i) (((U008 *)(p))[i])
#endif
#define NV_WR16(p,i,d) (((U016 *)(p))[(i)/2]=(d))
#define NV_RD16(p,i) (((U016 *)(p))[(i)/2])
#define NV_WR32(p,i,d) (((U032 *)(p))[(i)/4]=(d))
......@@ -75,6 +95,7 @@ typedef unsigned int U032;
#define NV_ARCH_04 0x04
#define NV_ARCH_10 0x10
#define NV_ARCH_20 0x20
/***************************************************************************\
* *
* FIFO registers. *
......@@ -87,8 +108,12 @@ typedef unsigned int U032;
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 Rop3;
} RivaRop;
......@@ -98,8 +123,12 @@ typedef volatile struct
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BD];
U032 Shape;
U032 reserved03[0x001];
......@@ -113,8 +142,12 @@ typedef volatile struct
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 TopLeft;
U032 WidthHeight;
......@@ -125,8 +158,12 @@ typedef volatile struct
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop[1];
#endif
U032 reserved01[0x0BC];
U032 Color;
U032 reserved03[0x03E];
......@@ -139,8 +176,12 @@ typedef volatile struct
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 TopLeftSrc;
U032 TopLeftDst;
......@@ -152,8 +193,12 @@ typedef volatile struct
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop[1];
#endif
U032 reserved01[0x0BC];
U032 TopLeft;
U032 WidthHeight;
......@@ -167,8 +212,12 @@ typedef volatile struct
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 reserved03[(0x040)-1];
U032 Color1A;
......@@ -229,8 +278,12 @@ typedef volatile struct
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BC];
U032 TextureOffset;
U032 TextureFormat;
......@@ -255,8 +308,12 @@ typedef volatile struct
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 ColorKey;
U032 TextureOffset;
......@@ -289,8 +346,12 @@ typedef volatile struct
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop[1];
#endif
U032 reserved01[0x0BC];
U032 Color; /* source color 0304-0307*/
U032 Reserved02[0x03e];
......@@ -320,16 +381,24 @@ typedef volatile struct
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BE];
U032 Offset;
} RivaSurface;
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BD];
U032 Pitch;
U032 RenderBufferOffset;
......@@ -342,6 +411,9 @@ typedef volatile struct
* *
\***************************************************************************/
#define FP_ENABLE 1
#define FP_DITHER 2
struct _riva_hw_inst;
struct _riva_hw_state;
/*
......@@ -354,6 +426,7 @@ typedef struct _riva_hw_inst
*/
U032 Architecture;
U032 Version;
U032 Chipset;
U032 CrystalFreqKHz;
U032 RamAmountKBytes;
U032 MaxVClockFreqKHz;
......@@ -363,11 +436,15 @@ typedef struct _riva_hw_inst
U032 VBlankBit;
U032 FifoFreeCount;
U032 FifoEmptyCount;
U032 CursorStart;
U032 flatPanel;
Bool twoHeads;
/*
* Non-FIFO registers.
*/
volatile U032 *PCRTC0;
volatile U032 *PCRTC;
volatile U032 *PRAMDAC;
volatile U032 *PRAMDAC0;
volatile U032 *PFB;
volatile U032 *PFIFO;
volatile U032 *PGRAPH;
......@@ -380,9 +457,12 @@ typedef struct _riva_hw_inst
volatile U032 *CURSORPOS;
volatile U032 *VBLANKENABLE;
volatile U032 *VBLANK;
volatile U008 *PCIO0;
volatile U008 *PCIO;
volatile U008 *PVIO;
volatile U008 *PDIO0;
volatile U008 *PDIO;
volatile U032 *PRAMDAC;
/*
* Common chip functions.
*/
......@@ -420,17 +500,26 @@ typedef struct _riva_hw_state
U032 bpp;
U032 width;
U032 height;
U032 interlace;
U032 repaint0;
U032 repaint1;
U032 screen;
U032 scale;
U032 dither;
U032 extra;
U032 pixel;
U032 horiz;
U032 arbitration0;
U032 arbitration1;
U032 vpll;
U032 vpll2;
U032 pllsel;
U032 general;
U032 crtcOwner;
U032 head;
U032 head2;
U032 config;
U032 cursorConfig;
U032 cursor0;
U032 cursor1;
U032 cursor2;
......
drivers/video/riva/riva_tbl.h
View file @ b0925249
......@@ -44,7 +44,9 @@
* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
*/
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.5 2000/02/08 17:19:12 dawes Exp $ */
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.9 2002/01/30 01:35:03 mvojkovi Exp $ */
/*
* RIVA Fixed Functionality Init Tables.
*/
......@@ -69,6 +71,7 @@ static unsigned RivaTableFIFO[][2] =
{0x00001800, 0x80000010},
{0x00002000, 0x80000011},
{0x00002800, 0x80000012},
{0x00003000, 0x80000016},
{0x00003800, 0x80000013}
};
static unsigned nv3TablePFIFO[][2] =
......@@ -174,6 +177,8 @@ static unsigned nv3TablePRAMIN[][2] =
{0x00000249, 0x00CC0346},
{0x0000024C, 0x80000013},
{0x0000024D, 0x00D70347},
{0x00000258, 0x80000016},
{0x00000259, 0x00CA034C},
{0x00000D05, 0x00000000},
{0x00000D06, 0x00000000},
{0x00000D07, 0x00000000},
......@@ -210,7 +215,10 @@ static unsigned nv3TablePRAMIN[][2] =
{0x00000D2C, 0x10830200},
{0x00000D2D, 0x00000000},
{0x00000D2E, 0x00000000},
{0x00000D2F, 0x00000000}
{0x00000D2F, 0x00000000},
{0x00000D31, 0x00000000},
{0x00000D32, 0x00000000},
{0x00000D33, 0x00000000}
};
static unsigned nv3TablePRAMIN_8BPP[][2] =
{
......@@ -222,7 +230,8 @@ static unsigned nv3TablePRAMIN_8BPP[][2] =
{0x00000D10, 0x10118203},
{0x00000D14, 0x10110203},
{0x00000D18, 0x10110203},
{0x00000D1C, 0x10419208}
{0x00000D1C, 0x10419208},
{0x00000D30, 0x10118203}
};
static unsigned nv3TablePRAMIN_15BPP[][2] =
{
......@@ -234,7 +243,8 @@ static unsigned nv3TablePRAMIN_15BPP[][2] =
{0x00000D10, 0x10118200},
{0x00000D14, 0x10110200},
{0x00000D18, 0x10110200},
{0x00000D1C, 0x10419208}
{0x00000D1C, 0x10419208},
{0x00000D30, 0x10118200}
};
static unsigned nv3TablePRAMIN_32BPP[][2] =
{
......@@ -246,7 +256,8 @@ static unsigned nv3TablePRAMIN_32BPP[][2] =
{0x00000D10, 0x10118201},
{0x00000D14, 0x10110201},
{0x00000D18, 0x10110201},
{0x00000D1C, 0x10419208}
{0x00000D1C, 0x10419208},
{0x00000D30, 0x10118201}
};
static unsigned nv4TableFIFO[][2] =
{
......@@ -370,6 +381,8 @@ static unsigned nv4TablePRAMIN[][2] =
{0x00000009, 0x80011149},
{0x0000000A, 0x80000015},
{0x0000000B, 0x8001114A},
{0x0000000C, 0x80000016},
{0x0000000D, 0x8001114F},
{0x00000020, 0x80000000},
{0x00000021, 0x80011142},
{0x00000022, 0x80000001},
......@@ -437,7 +450,10 @@ static unsigned nv4TablePRAMIN[][2] =
{0x00000537, 0x00000000},
{0x00000538, 0x0000005B},
{0x0000053A, 0x11401140},
{0x0000053B, 0x00000000}
{0x0000053B, 0x00000000},
{0x0000053C, 0x0300A01C},
{0x0000053E, 0x11401140},
{0x0000053F, 0x00000000}
};
static unsigned nv4TablePRAMIN_8BPP[][2] =
{
......@@ -452,7 +468,8 @@ static unsigned nv4TablePRAMIN_8BPP[][2] =
{0x0000052D, 0x00000302},
{0x0000052E, 0x00000302},
{0x00000535, 0x00000000},
{0x00000539, 0x00000000}
{0x00000539, 0x00000000},
{0x0000053D, 0x00000302}
};
static unsigned nv4TablePRAMIN_15BPP[][2] =
{
......@@ -467,7 +484,8 @@ static unsigned nv4TablePRAMIN_15BPP[][2] =
{0x0000052D, 0x00000902},
{0x0000052E, 0x00000902},
{0x00000535, 0x00000702},
{0x00000539, 0x00000702}
{0x00000539, 0x00000702},
{0x0000053D, 0x00000902}
};
static unsigned nv4TablePRAMIN_16BPP[][2] =
{
......@@ -482,7 +500,8 @@ static unsigned nv4TablePRAMIN_16BPP[][2] =
{0x0000052D, 0x00000C02},
{0x0000052E, 0x00000C02},
{0x00000535, 0x00000702},
{0x00000539, 0x00000702}
{0x00000539, 0x00000702},
{0x0000053D, 0x00000C02}
};
static unsigned nv4TablePRAMIN_32BPP[][2] =
{
......@@ -497,7 +516,8 @@ static unsigned nv4TablePRAMIN_32BPP[][2] =
{0x0000052D, 0x00000E02},
{0x0000052E, 0x00000E02},
{0x00000535, 0x00000E02},
{0x00000539, 0x00000E02}
{0x00000539, 0x00000E02},
{0x0000053D, 0x00000E02}
};
static unsigned nv10TableFIFO[][2] =
{
......@@ -810,6 +830,8 @@ static unsigned nv10TablePRAMIN[][2] =
{0x00000009, 0x80011149},
{0x0000000A, 0x80000015},
{0x0000000B, 0x8001114A},
{0x0000000C, 0x80000016},
{0x0000000D, 0x80011150},
{0x00000020, 0x80000000},
{0x00000021, 0x80011142},
{0x00000022, 0x80000001},
......@@ -830,29 +852,45 @@ static unsigned nv10TablePRAMIN[][2] =
{0x00000501, 0x01FFFFFF},
{0x00000502, 0x00000002},
{0x00000503, 0x00000002},
#ifdef __BIG_ENDIAN
{0x00000508, 0x01088043},
#else
{0x00000508, 0x01008043},
#endif
{0x0000050A, 0x00000000},
{0x0000050B, 0x00000000},
#ifdef __BIG_ENDIAN
{0x0000050C, 0x01088019},
#else
{0x0000050C, 0x01008019},
#endif
{0x0000050E, 0x00000000},
{0x0000050F, 0x00000000},
#if 1
{0x00000510, 0x01008018},
#ifdef __BIG_ENDIAN
{0x00000510, 0x01088018},
#else
{0x00000510, 0x01008044},
{0x00000510, 0x01008018},
#endif
{0x00000512, 0x00000000},
{0x00000513, 0x00000000},
#ifdef __BIG_ENDIAN
{0x00000514, 0x01088021},
#else
{0x00000514, 0x01008021},
#endif
{0x00000516, 0x00000000},
{0x00000517, 0x00000000},
#ifdef __BIG_ENDIAN
{0x00000518, 0x0108805F},
#else
{0x00000518, 0x0100805F},
#endif
{0x0000051A, 0x00000000},
{0x0000051B, 0x00000000},
#if 1
{0x0000051C, 0x0100804B},
#ifdef __BIG_ENDIAN
{0x0000051C, 0x0108804B},
#else
{0x0000051C, 0x0100804A},
{0x0000051C, 0x0100804B},
#endif
{0x0000051E, 0x00000000},
{0x0000051F, 0x00000000},
......@@ -868,10 +906,18 @@ static unsigned nv10TablePRAMIN[][2] =
{0x00000529, 0x00000D01},
{0x0000052A, 0x11401140},
{0x0000052B, 0x00000000},
#ifdef __BIG_ENDIAN
{0x0000052C, 0x00080058},
#else
{0x0000052C, 0x00000058},
#endif
{0x0000052E, 0x11401140},
{0x0000052F, 0x00000000},
#ifdef __BIG_ENDIAN
{0x00000530, 0x00080059},
#else
{0x00000530, 0x00000059},
#endif
{0x00000532, 0x11401140},
{0x00000533, 0x00000000},
{0x00000534, 0x0000005A},
......@@ -882,7 +928,14 @@ static unsigned nv10TablePRAMIN[][2] =
{0x0000053B, 0x00000000},
{0x0000053C, 0x00000093},
{0x0000053E, 0x11401140},
{0x0000053F, 0x00000000}
{0x0000053F, 0x00000000},
#ifdef __BIG_ENDIAN
{0x00000540, 0x0308A01C},
#else
{0x00000540, 0x0300A01C},
#endif
{0x00000542, 0x11401140},
{0x00000543, 0x00000000}
};
static unsigned nv10TablePRAMIN_8BPP[][2] =
{
......@@ -898,7 +951,8 @@ static unsigned nv10TablePRAMIN_8BPP[][2] =
{0x0000052E, 0x00000302},
{0x00000535, 0x00000000},
{0x00000539, 0x00000000},
{0x0000053D, 0x00000000}
{0x0000053D, 0x00000000},
{0x00000541, 0x00000302}
};
static unsigned nv10TablePRAMIN_15BPP[][2] =
{
......@@ -914,7 +968,8 @@ static unsigned nv10TablePRAMIN_15BPP[][2] =
{0x0000052E, 0x00000902},
{0x00000535, 0x00000902},
{0x00000539, 0x00000902},
{0x0000053D, 0x00000902}
{0x0000053D, 0x00000902},
{0x00000541, 0x00000902}
};
static unsigned nv10TablePRAMIN_16BPP[][2] =
{
......@@ -930,7 +985,8 @@ static unsigned nv10TablePRAMIN_16BPP[][2] =
{0x0000052E, 0x00000C02},
{0x00000535, 0x00000C02},
{0x00000539, 0x00000C02},
{0x0000053D, 0x00000C02}
{0x0000053D, 0x00000C02},
{0x00000541, 0x00000C02}
};
static unsigned nv10TablePRAMIN_32BPP[][2] =
{
......@@ -946,6 +1002,7 @@ static unsigned nv10TablePRAMIN_32BPP[][2] =
{0x0000052E, 0x00000E02},
{0x00000535, 0x00000E02},
{0x00000539, 0x00000E02},
{0x0000053D, 0x00000E02}
{0x0000053D, 0x00000E02},
{0x00000541, 0x00000E02}
};
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