drm/nouveau/nvfw: firmware structures should begin with nvfw_

Rename all structures that are used directly by firmware to have a nvfw_
prefix.

This makes it easier to identify structures that have a fixed, specific
layout.  A future patch will define several more such structures, so it's
important to be consistent now.
Signed-off-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvfw/pmu.h

@@ -25,7 +25,7 @@ struct nv_pmu_args {
 #define NV_PMU_UNIT_ACR                                                    0x0a
 
 struct nv_pmu_init_msg {
-	struct nv_falcon_msg hdr;
+	struct nvfw_falcon_msg hdr;
 #define NV_PMU_INIT_MSG_INIT                                               0x00
 	u8 msg_type;
 
@@ -44,7 +44,7 @@ struct nv_pmu_init_msg {
 };
 
 struct nv_pmu_acr_cmd {
-	struct nv_falcon_cmd hdr;
+	struct nvfw_falcon_cmd hdr;
 #define NV_PMU_ACR_CMD_INIT_WPR_REGION                                     0x00
 #define NV_PMU_ACR_CMD_BOOTSTRAP_FALCON                                    0x01
 #define NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS                          0x03
@@ -52,7 +52,7 @@ struct nv_pmu_acr_cmd {
 };
 
 struct nv_pmu_acr_msg {
-	struct nv_falcon_cmd hdr;
+	struct nvfw_falcon_cmd hdr;
 	u8 msg_type;
 };
 

drivers/gpu/drm/nouveau/include/nvfw/sec2.h

@@ -13,7 +13,7 @@ struct nv_sec2_args {
 #define NV_SEC2_UNIT_ACR                                                   0x08
 
 struct nv_sec2_init_msg {
-	struct nv_falcon_msg hdr;
+	struct nvfw_falcon_msg hdr;
 #define NV_SEC2_INIT_MSG_INIT                                              0x00
 	u8 msg_type;
 
@@ -34,13 +34,13 @@ struct nv_sec2_init_msg {
 };
 
 struct nv_sec2_acr_cmd {
-	struct nv_falcon_cmd hdr;
+	struct nvfw_falcon_cmd hdr;
 #define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON                                   0x00
 	u8 cmd_type;
 };
 
 struct nv_sec2_acr_msg {
-	struct nv_falcon_cmd hdr;
+	struct nvfw_falcon_cmd hdr;
 	u8 msg_type;
 };
 

drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h

@@ -31,21 +31,21 @@ int gp102_sec2_flcn_enable(struct nvkm_falcon *);
 #define FLCN_ERR(f,fmt,a...) FLCN_PRINTK(error, (f), fmt, ##a)
 
 /**
- * struct nv_falcon_msg - header for all messages
+ * struct nvfw_falcon_msg - header for all messages
  *
  * @unit_id:	id of firmware process that sent the message
  * @size:	total size of message
  * @ctrl_flags:	control flags
  * @seq_id:	used to match a message from its corresponding command
  */
-struct nv_falcon_msg {
+struct nvfw_falcon_msg {
 	u8 unit_id;
 	u8 size;
 	u8 ctrl_flags;
 	u8 seq_id;
 };
 
-#define nv_falcon_cmd nv_falcon_msg
+#define nvfw_falcon_cmd nvfw_falcon_msg
 #define NV_FALCON_CMD_UNIT_ID_REWIND                                       0x00
 
 struct nvkm_falcon_qmgr;
@@ -53,7 +53,7 @@ int nvkm_falcon_qmgr_new(struct nvkm_falcon *, struct nvkm_falcon_qmgr **);
 void nvkm_falcon_qmgr_del(struct nvkm_falcon_qmgr **);
 
 typedef int
-(*nvkm_falcon_qmgr_callback)(void *priv, struct nv_falcon_msg *);
+(*nvkm_falcon_qmgr_callback)(void *priv, struct nvfw_falcon_msg *);
 
 struct nvkm_falcon_cmdq;
 int nvkm_falcon_cmdq_new(struct nvkm_falcon_qmgr *, const char *name,
@@ -62,7 +62,7 @@ void nvkm_falcon_cmdq_del(struct nvkm_falcon_cmdq **);
 void nvkm_falcon_cmdq_init(struct nvkm_falcon_cmdq *,
 			   u32 index, u32 offset, u32 size);
 void nvkm_falcon_cmdq_fini(struct nvkm_falcon_cmdq *);
-int nvkm_falcon_cmdq_send(struct nvkm_falcon_cmdq *, struct nv_falcon_cmd *,
+int nvkm_falcon_cmdq_send(struct nvkm_falcon_cmdq *, struct nvfw_falcon_cmd *,
 			  nvkm_falcon_qmgr_callback, void *priv,
 			  unsigned long timeout_jiffies);
 

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

@@ -29,7 +29,7 @@
 #include <nvfw/sec2.h>
 
 static int
-gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nv_falcon_msg *hdr)
+gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr)
 {
 	struct nv_sec2_acr_bootstrap_falcon_msg *msg =
 		container_of(hdr, typeof(*msg), msg.hdr);

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

@@ -58,7 +58,7 @@ nvkm_falcon_cmdq_push(struct nvkm_falcon_cmdq *cmdq, void *data, u32 size)
 static void
 nvkm_falcon_cmdq_rewind(struct nvkm_falcon_cmdq *cmdq)
 {
-	struct nv_falcon_cmd cmd;
+	struct nvfw_falcon_cmd cmd;
 
 	cmd.unit_id = NV_FALCON_CMD_UNIT_ID_REWIND;
 	cmd.size = sizeof(cmd);
@@ -97,7 +97,7 @@ nvkm_falcon_cmdq_close(struct nvkm_falcon_cmdq *cmdq)
 }
 
 static int
-nvkm_falcon_cmdq_write(struct nvkm_falcon_cmdq *cmdq, struct nv_falcon_cmd *cmd)
+nvkm_falcon_cmdq_write(struct nvkm_falcon_cmdq *cmdq, struct nvfw_falcon_cmd *cmd)
 {
 	static unsigned timeout = 2000;
 	unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
@@ -121,7 +121,7 @@ nvkm_falcon_cmdq_write(struct nvkm_falcon_cmdq *cmdq, struct nv_falcon_cmd *cmd)
 #define CMD_FLAGS_INTR BIT(1)
 
 int
-nvkm_falcon_cmdq_send(struct nvkm_falcon_cmdq *cmdq, struct nv_falcon_cmd *cmd,
+nvkm_falcon_cmdq_send(struct nvkm_falcon_cmdq *cmdq, struct nvfw_falcon_cmd *cmd,
 		      nvkm_falcon_qmgr_callback cb, void *priv,
 		      unsigned long timeout)
 {

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

@@ -74,7 +74,7 @@ nvkm_falcon_msgq_pop(struct nvkm_falcon_msgq *msgq, void *data, u32 size)
 }
 
 static int
-nvkm_falcon_msgq_read(struct nvkm_falcon_msgq *msgq, struct nv_falcon_msg *hdr)
+nvkm_falcon_msgq_read(struct nvkm_falcon_msgq *msgq, struct nvfw_falcon_msg *hdr)
 {
 	int ret = 0;
 
@@ -112,7 +112,7 @@ nvkm_falcon_msgq_read(struct nvkm_falcon_msgq *msgq, struct nv_falcon_msg *hdr)
 }
 
 static int
-nvkm_falcon_msgq_exec(struct nvkm_falcon_msgq *msgq, struct nv_falcon_msg *hdr)
+nvkm_falcon_msgq_exec(struct nvkm_falcon_msgq *msgq, struct nvfw_falcon_msg *hdr)
 {
 	struct nvkm_falcon_qmgr_seq *seq;
 
@@ -144,7 +144,7 @@ nvkm_falcon_msgq_recv(struct nvkm_falcon_msgq *msgq)
 	 * stack space to work with.
 	 */
 	u8 msg_buffer[MSG_BUF_SIZE];
-	struct nv_falcon_msg *hdr = (void *)msg_buffer;
+	struct nvfw_falcon_msg *hdr = (void *)msg_buffer;
 
 	while (nvkm_falcon_msgq_read(msgq, hdr) > 0)
 		nvkm_falcon_msgq_exec(msgq, hdr);
@@ -155,7 +155,7 @@ nvkm_falcon_msgq_recv_initmsg(struct nvkm_falcon_msgq *msgq,
 			      void *data, u32 size)
 {
 	struct nvkm_falcon *falcon = msgq->qmgr->falcon;
-	struct nv_falcon_msg *hdr = data;
+	struct nvfw_falcon_msg *hdr = data;
 	int ret;
 
 	msgq->head_reg = falcon->func->msgq.head;

drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h

@@ -3,7 +3,7 @@
 #define __NVKM_FALCON_QMGR_H__
 #include <core/falcon.h>
 
-#define HDR_SIZE sizeof(struct nv_falcon_msg)
+#define HDR_SIZE sizeof(struct nvfw_falcon_msg)
 #define QUEUE_ALIGNMENT 4
 /* max size of the messages we can receive */
 #define MSG_BUF_SIZE 128

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

@@ -28,7 +28,7 @@
 #include <nvfw/pmu.h>
 
 static int
-gm20b_pmu_acr_bootstrap_falcon_cb(void *priv, struct nv_falcon_msg *hdr)
+gm20b_pmu_acr_bootstrap_falcon_cb(void *priv, struct nvfw_falcon_msg *hdr)
 {
 	struct nv_pmu_acr_bootstrap_falcon_msg *msg =
 		container_of(hdr, typeof(*msg), msg.hdr);
@@ -130,7 +130,7 @@ gm20b_pmu_acr = {
 };
 
 static int
-gm20b_pmu_acr_init_wpr_callback(void *priv, struct nv_falcon_msg *hdr)
+gm20b_pmu_acr_init_wpr_callback(void *priv, struct nvfw_falcon_msg *hdr)
 {
 	struct nv_pmu_acr_init_wpr_region_msg *msg =
 		container_of(hdr, typeof(*msg), msg.hdr);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c

@@ -28,7 +28,7 @@
 
 static int
 gp10b_pmu_acr_bootstrap_multiple_falcons_cb(void *priv,
-					    struct nv_falcon_msg *hdr)
+					    struct nvfw_falcon_msg *hdr)
 {
 	struct nv_pmu_acr_bootstrap_multiple_falcons_msg *msg =
 		container_of(hdr, typeof(*msg), msg.hdr);