Commit b5163dbb authored by Chris Wilson's avatar Chris Wilson

drm/i915: Fix nesting of rps.mutex and struct_mutex during powersave init

During intel_gt_powersave_init() we take the RPS mutex to ensure that
all locking requirements are met as we talk to the punit, but we also
require the struct_mutex for allocating a slice of the global GTT for a
power context on Valleyview. struct_mutex must be the outer lock here,
as we nest rps.mutex inside later on.
Reported-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Fixes: 773ea9a8 ("drm/i915: Perform static RPS frequency setup before...")
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470833904-29886-1-git-send-email-chris@chris-wilson.co.ukReviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
parent eebb40e0
...@@ -5675,8 +5675,6 @@ static void valleyview_setup_pctx(struct drm_i915_private *dev_priv) ...@@ -5675,8 +5675,6 @@ static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
u32 pcbr; u32 pcbr;
int pctx_size = 24*1024; int pctx_size = 24*1024;
mutex_lock(&dev_priv->drm.struct_mutex);
pcbr = I915_READ(VLV_PCBR); pcbr = I915_READ(VLV_PCBR);
if (pcbr) { if (pcbr) {
/* BIOS set it up already, grab the pre-alloc'd space */ /* BIOS set it up already, grab the pre-alloc'd space */
...@@ -5712,7 +5710,6 @@ static void valleyview_setup_pctx(struct drm_i915_private *dev_priv) ...@@ -5712,7 +5710,6 @@ static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
out: out:
DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
dev_priv->vlv_pctx = pctx; dev_priv->vlv_pctx = pctx;
mutex_unlock(&dev_priv->drm.struct_mutex);
} }
static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv) static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
...@@ -6488,6 +6485,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv) ...@@ -6488,6 +6485,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
intel_runtime_pm_get(dev_priv); intel_runtime_pm_get(dev_priv);
} }
mutex_lock(&dev_priv->drm.struct_mutex);
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->rps.hw_lock);
/* Initialize RPS limits (for userspace) */ /* Initialize RPS limits (for userspace) */
...@@ -6529,6 +6527,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv) ...@@ -6529,6 +6527,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
dev_priv->rps.boost_freq = dev_priv->rps.max_freq; dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->rps.hw_lock);
mutex_unlock(&dev_priv->drm.struct_mutex);
intel_autoenable_gt_powersave(dev_priv); intel_autoenable_gt_powersave(dev_priv);
} }
......
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