Commit b76db38c authored by Mugunthan V N's avatar Mugunthan V N Committed by David S. Miller

ARM: dts: dra72-evm-revc: add phy impedance settings

The default impedance settings of the phy is not the optimal
value, due to this the second ethernet is not working. Fix it
with correct values which makes the second ethernet port to work.
Signed-off-by: default avatarMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ed838fe9
...@@ -62,6 +62,7 @@ dp83867_0: ethernet-phy@2 { ...@@ -62,6 +62,7 @@ dp83867_0: ethernet-phy@2 {
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
}; };
dp83867_1: ethernet-phy@3 { dp83867_1: ethernet-phy@3 {
...@@ -69,5 +70,6 @@ dp83867_1: ethernet-phy@3 { ...@@ -69,5 +70,6 @@ dp83867_1: ethernet-phy@3 {
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-imepdance;
}; };
}; };
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