Commit b7825ca0 authored by Ryder Lee's avatar Ryder Lee Committed by Felix Fietkau

mt76: mt7615: cleanup mib related defines and structs

Simplify mib macros and use proper type for related counters.
Signed-off-by: default avatarRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent b473fdbb
...@@ -1535,8 +1535,8 @@ void mt7615_mac_set_scs(struct mt7615_dev *dev, bool enable) ...@@ -1535,8 +1535,8 @@ void mt7615_mac_set_scs(struct mt7615_dev *dev, bool enable)
mt76_set(dev, MT_WF_PHY_MIN_PRI_PWR(1), mt76_set(dev, MT_WF_PHY_MIN_PRI_PWR(1),
MT_WF_PHY_PD_BLK(1)); MT_WF_PHY_PD_BLK(1));
if (is_mt7622(&dev->mt76)) { if (is_mt7622(&dev->mt76)) {
mt76_set(dev, MT_MIB_M0_MISC_CR, 0x7 << 8); mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8);
mt76_set(dev, MT_MIB_M0_MISC_CR, 0x7); mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7);
} }
} else { } else {
mt76_clear(dev, MT_WF_PHY_MIN_PRI_PWR(0), mt76_clear(dev, MT_WF_PHY_MIN_PRI_PWR(0),
...@@ -1762,18 +1762,18 @@ mt7615_mac_update_mib_stats(struct mt7615_phy *phy) ...@@ -1762,18 +1762,18 @@ mt7615_mac_update_mib_stats(struct mt7615_phy *phy)
aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
u32 data, val, val2; u32 val, val2;
val = mt76_get_field(dev, MT_MIB_MB_SDR1(ext_phy, i), val = mt76_get_field(dev, MT_MIB_MB_SDR1(ext_phy, i),
MT_MIB_ACK_FAIL_COUNT_MASK); MT_MIB_ACK_FAIL_COUNT_MASK);
if (val > mib->ack_fail_cnt) if (val > mib->ack_fail_cnt)
mib->ack_fail_cnt = val; mib->ack_fail_cnt = val;
val2 = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
data = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val2); val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
if (data > mib->rts_retries_cnt) { if (val2 > mib->rts_retries_cnt) {
mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val2); mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
mib->rts_retries_cnt = data; mib->rts_retries_cnt = val2;
} }
val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
......
...@@ -113,10 +113,10 @@ struct mt7615_vif { ...@@ -113,10 +113,10 @@ struct mt7615_vif {
}; };
struct mib_stats { struct mib_stats {
u32 ack_fail_cnt; u16 ack_fail_cnt;
u32 fcs_err_cnt; u16 fcs_err_cnt;
u32 rts_cnt; u16 rts_cnt;
u32 rts_retries_cnt; u16 rts_retries_cnt;
}; };
struct mt7615_phy { struct mt7615_phy {
......
...@@ -379,35 +379,32 @@ enum mt7615_reg_base { ...@@ -379,35 +379,32 @@ enum mt7615_reg_base {
#define MT_LPON_UTTR1 MT_LPON(0x01c) #define MT_LPON_UTTR1 MT_LPON(0x01c)
#define MT_WF_MIB_BASE (dev->reg_map[MT_MIB_BASE]) #define MT_WF_MIB_BASE (dev->reg_map[MT_MIB_BASE])
#define MT_WF_MIB(ofs) (MT_WF_MIB_BASE + (ofs)) #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE + (ofs) + (_band) * 0x200)
#define MT_MIB_M0_MISC_CR MT_WF_MIB(0x00c) #define MT_MIB_M0_MISC_CR(_band) MT_WF_MIB(_band, 0x00c)
#define MT_MIB_SDR3(n) MT_WF_MIB(0x014 + ((n) << 9)) #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014)
#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0) #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
#define MT_MIB_SDR9(n) MT_WF_MIB(0x02c + ((n) << 9)) #define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c)
#define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0) #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)
#define MT_MIB_SDR16(n) MT_WF_MIB(0x048 + ((n) << 9)) #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048)
#define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0) #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)
#define MT_MIB_SDR36(n) MT_WF_MIB(0x098 + ((n) << 9)) #define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x098)
#define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0) #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)
#define MT_MIB_SDR37(n) MT_WF_MIB(0x09c + ((n) << 9)) #define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x09c)
#define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0) #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)
#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(0x100 + ((_band) << 9) + \ #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4))
((n) << 4))
#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(0x104 + ((_band) << 9) + \ #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4))
((n) << 4))
#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(0xa8 + ((_band) << 9) + \ #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0xa8 + ((n) << 2))
((n) << 2))
#define MT_DMA_SHDL(ofs) (dev->reg_map[MT_DMA_SHDL_BASE] + (ofs)) #define MT_DMA_SHDL(ofs) (dev->reg_map[MT_DMA_SHDL_BASE] + (ofs))
......
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