Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
nexedi
linux
Commits
bc19f597
Commit
bc19f597
authored
Jun 07, 2013
by
Alex Deucher
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
drm/radeon: update power state parsing for CI
Signed-off-by:
Alex Deucher
<
alexander.deucher@amd.com
>
parent
51150207
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
10 additions
and
0 deletions
+10
-0
drivers/gpu/drm/radeon/radeon_atombios.c
drivers/gpu/drm/radeon/radeon_atombios.c
+10
-0
No files found.
drivers/gpu/drm/radeon/radeon_atombios.c
View file @
bc19f597
...
@@ -1945,6 +1945,7 @@ union pplib_clock_info {
...
@@ -1945,6 +1945,7 @@ union pplib_clock_info {
struct
_ATOM_PPLIB_EVERGREEN_CLOCK_INFO
evergreen
;
struct
_ATOM_PPLIB_EVERGREEN_CLOCK_INFO
evergreen
;
struct
_ATOM_PPLIB_SUMO_CLOCK_INFO
sumo
;
struct
_ATOM_PPLIB_SUMO_CLOCK_INFO
sumo
;
struct
_ATOM_PPLIB_SI_CLOCK_INFO
si
;
struct
_ATOM_PPLIB_SI_CLOCK_INFO
si
;
struct
_ATOM_PPLIB_CI_CLOCK_INFO
ci
;
};
};
union
pplib_power_state
{
union
pplib_power_state
{
...
@@ -2353,6 +2354,15 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
...
@@ -2353,6 +2354,15 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
sclk
|=
clock_info
->
rs780
.
ucLowEngineClockHigh
<<
16
;
sclk
|=
clock_info
->
rs780
.
ucLowEngineClockHigh
<<
16
;
rdev
->
pm
.
power_state
[
state_index
].
clock_info
[
mode_index
].
sclk
=
sclk
;
rdev
->
pm
.
power_state
[
state_index
].
clock_info
[
mode_index
].
sclk
=
sclk
;
}
}
}
else
if
(
rdev
->
family
>=
CHIP_BONAIRE
)
{
sclk
=
le16_to_cpu
(
clock_info
->
ci
.
usEngineClockLow
);
sclk
|=
clock_info
->
ci
.
ucEngineClockHigh
<<
16
;
mclk
=
le16_to_cpu
(
clock_info
->
ci
.
usMemoryClockLow
);
mclk
|=
clock_info
->
ci
.
ucMemoryClockHigh
<<
16
;
rdev
->
pm
.
power_state
[
state_index
].
clock_info
[
mode_index
].
mclk
=
mclk
;
rdev
->
pm
.
power_state
[
state_index
].
clock_info
[
mode_index
].
sclk
=
sclk
;
rdev
->
pm
.
power_state
[
state_index
].
clock_info
[
mode_index
].
voltage
.
type
=
VOLTAGE_NONE
;
}
else
if
(
rdev
->
family
>=
CHIP_TAHITI
)
{
}
else
if
(
rdev
->
family
>=
CHIP_TAHITI
)
{
sclk
=
le16_to_cpu
(
clock_info
->
si
.
usEngineClockLow
);
sclk
=
le16_to_cpu
(
clock_info
->
si
.
usEngineClockLow
);
sclk
|=
clock_info
->
si
.
ucEngineClockHigh
<<
16
;
sclk
|=
clock_info
->
si
.
ucEngineClockHigh
<<
16
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment