Commit bd80ef5e authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman

ARM64: dts: meson: meson-gx: add the SAR ADC

Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL and GXM provide a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on one of the ADC
channels to indicate the board revision.
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarAndreas Färber <afaerber@suse.de>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 249a2243
...@@ -237,6 +237,14 @@ pwm_cd: pwm@8650 { ...@@ -237,6 +237,14 @@ pwm_cd: pwm@8650 {
status = "disabled"; status = "disabled";
}; };
saradc: adc@8680 {
compatible = "amlogic,meson-saradc";
reg = <0x0 0x8680 0x0 0x34>;
#io-channel-cells = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
pwm_ef: pwm@86c0 { pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>; reg = <0x0 0x086c0 0x0 0x10>;
......
...@@ -490,6 +490,16 @@ &i2c_C { ...@@ -490,6 +490,16 @@ &i2c_C {
clocks = <&clkc CLKID_I2C>; clocks = <&clkc CLKID_I2C>;
}; };
&saradc {
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
<&clkc CLKID_SAR_ADC>,
<&clkc CLKID_SANA>,
<&clkc CLKID_SAR_ADC_CLK>,
<&clkc CLKID_SAR_ADC_SEL>;
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
};
&sd_emmc_a { &sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>, clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>, <&xtal>,
......
...@@ -347,6 +347,16 @@ &i2c_C { ...@@ -347,6 +347,16 @@ &i2c_C {
clocks = <&clkc CLKID_I2C>; clocks = <&clkc CLKID_I2C>;
}; };
&saradc {
compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
<&clkc CLKID_SAR_ADC>,
<&clkc CLKID_SANA>,
<&clkc CLKID_SAR_ADC_CLK>,
<&clkc CLKID_SAR_ADC_SEL>;
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
};
&sd_emmc_a { &sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>, clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>, <&xtal>,
......
...@@ -117,6 +117,10 @@ cpu7: cpu@103 { ...@@ -117,6 +117,10 @@ cpu7: cpu@103 {
}; };
}; };
&saradc {
compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
};
&scpi_dvfs { &scpi_dvfs {
clock-indices = <0 1>; clock-indices = <0 1>;
clock-output-names = "vbig", "vlittle"; clock-output-names = "vbig", "vlittle";
......
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