Commit bfb7bfef authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Ingo Molnar:
 "Mostly irqchip driver fixes, plus a symbol export"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  kernel/irq: Export irq_set_parent()
  irqchip/gic: Add missing \n to CPU IF adjustment message
  irqchip/jcore: Don't show Kconfig menu item for driver
  irqchip/eznps: Drop pointless static qualifier in nps400_of_init()
  irqchip/gic-v3-its: Fix entry size mask for GITS_BASER
  irqchip/gic-v3-its: Fix 64bit GIC{R,ITS}_TYPER accesses
parents 90e01058 a442950d
...@@ -158,8 +158,8 @@ config PIC32_EVIC ...@@ -158,8 +158,8 @@ config PIC32_EVIC
select IRQ_DOMAIN select IRQ_DOMAIN
config JCORE_AIC config JCORE_AIC
bool "J-Core integrated AIC" bool "J-Core integrated AIC" if COMPILE_TEST
depends on OF && (SUPERH || COMPILE_TEST) depends on OF
select IRQ_DOMAIN select IRQ_DOMAIN
help help
Support for the J-Core integrated AIC. Support for the J-Core integrated AIC.
......
...@@ -135,7 +135,7 @@ static const struct irq_domain_ops nps400_irq_ops = { ...@@ -135,7 +135,7 @@ static const struct irq_domain_ops nps400_irq_ops = {
static int __init nps400_of_init(struct device_node *node, static int __init nps400_of_init(struct device_node *node,
struct device_node *parent) struct device_node *parent)
{ {
static struct irq_domain *nps400_root_domain; struct irq_domain *nps400_root_domain;
if (parent) { if (parent) {
pr_err("DeviceTree incore ic not a root irq controller\n"); pr_err("DeviceTree incore ic not a root irq controller\n");
......
...@@ -1023,7 +1023,7 @@ static void its_free_tables(struct its_node *its) ...@@ -1023,7 +1023,7 @@ static void its_free_tables(struct its_node *its)
static int its_alloc_tables(struct its_node *its) static int its_alloc_tables(struct its_node *its)
{ {
u64 typer = readq_relaxed(its->base + GITS_TYPER); u64 typer = gic_read_typer(its->base + GITS_TYPER);
u32 ids = GITS_TYPER_DEVBITS(typer); u32 ids = GITS_TYPER_DEVBITS(typer);
u64 shr = GITS_BASER_InnerShareable; u64 shr = GITS_BASER_InnerShareable;
u64 cache = GITS_BASER_WaWb; u64 cache = GITS_BASER_WaWb;
...@@ -1198,7 +1198,7 @@ static void its_cpu_init_collection(void) ...@@ -1198,7 +1198,7 @@ static void its_cpu_init_collection(void)
* We now have to bind each collection to its target * We now have to bind each collection to its target
* redistributor. * redistributor.
*/ */
if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) { if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
/* /*
* This ITS wants the physical address of the * This ITS wants the physical address of the
* redistributor. * redistributor.
...@@ -1208,7 +1208,7 @@ static void its_cpu_init_collection(void) ...@@ -1208,7 +1208,7 @@ static void its_cpu_init_collection(void)
/* /*
* This ITS wants a linear CPU number. * This ITS wants a linear CPU number.
*/ */
target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER); target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
target = GICR_TYPER_CPU_NUMBER(target) << 16; target = GICR_TYPER_CPU_NUMBER(target) << 16;
} }
...@@ -1691,7 +1691,7 @@ static int __init its_probe_one(struct resource *res, ...@@ -1691,7 +1691,7 @@ static int __init its_probe_one(struct resource *res,
INIT_LIST_HEAD(&its->its_device_list); INIT_LIST_HEAD(&its->its_device_list);
its->base = its_base; its->base = its_base;
its->phys_base = res->start; its->phys_base = res->start;
its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1; its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
its->numa_node = numa_node; its->numa_node = numa_node;
its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL); its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
...@@ -1763,7 +1763,7 @@ static int __init its_probe_one(struct resource *res, ...@@ -1763,7 +1763,7 @@ static int __init its_probe_one(struct resource *res,
static bool gic_rdists_supports_plpis(void) static bool gic_rdists_supports_plpis(void)
{ {
return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
} }
int its_cpu_init(void) int its_cpu_init(void)
......
...@@ -1279,7 +1279,7 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base) ...@@ -1279,7 +1279,7 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
*/ */
*base += 0xf000; *base += 0xf000;
cpuif_res.start += 0xf000; cpuif_res.start += 0xf000;
pr_warn("GIC: Adjusting CPU interface base to %pa", pr_warn("GIC: Adjusting CPU interface base to %pa\n",
&cpuif_res.start); &cpuif_res.start);
} }
......
...@@ -290,7 +290,7 @@ ...@@ -290,7 +290,7 @@
#define GITS_BASER_TYPE_SHIFT (56) #define GITS_BASER_TYPE_SHIFT (56)
#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
#define GITS_BASER_ENTRY_SIZE_SHIFT (48) #define GITS_BASER_ENTRY_SIZE_SHIFT (48)
#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1) #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
#define GITS_BASER_SHAREABILITY_SHIFT (10) #define GITS_BASER_SHAREABILITY_SHIFT (10)
#define GITS_BASER_InnerShareable \ #define GITS_BASER_InnerShareable \
GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
......
...@@ -721,6 +721,7 @@ int irq_set_parent(int irq, int parent_irq) ...@@ -721,6 +721,7 @@ int irq_set_parent(int irq, int parent_irq)
irq_put_desc_unlock(desc, flags); irq_put_desc_unlock(desc, flags);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(irq_set_parent);
#endif #endif
/* /*
......
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