Commit c11d7162 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Kevin Hilman:
 "A relatively small setup of cleanups this time around, and similar to
  last time the bulk of it is removal of legacy board support:

   - OMAP: removal of legacy (non-DT) booting for several platforms

   - i.MX: remove some legacy board files"

* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (36 commits)
  ARM: fix EFM32 build breakage caused by cpu_resume_arm
  ARM: 8389/1: Add cpu_resume_arm() for firmwares that resume in ARM state
  ARM: v7 setup function should invalidate L1 cache
  mach-omap2: Remove use of deprecated marco, PTR_RET in devices.c
  ARM: OMAP2+: Remove calls to deprecacted marco,PTR_RET in the files,fb.c and pmu.c
  ARM: OMAP2+: Constify irq_domain_ops
  ARM: OMAP2+: use symbolic defines for console loglevels instead of numbers
  ARM: at91: remove useless Makefile.boot
  ARM: at91: remove at91rm9200_sdramc.h
  ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h
  ARM: at91/pm: use the atmel-mc syscon defines
  pcmcia: at91_cf: Use syscon to configure the MC/smc
  ARM: at91: declare the at91rm9200 memory controller as a syscon
  mfd: syscon: Add Atmel MC (Memory Controller) registers definition
  ARM: at91: drop sam9_smc.c
  ata: at91: use syscon to configure the smc
  ARM: ux500: delete static resource defines
  ARM: ux500: rename ux500_map_io
  ARM: ux500: look up PRCMU resource from DT
  ARM: ux500: kill off L2CC static map
  ...
parents 47a46942 e75ea456
...@@ -98,7 +98,7 @@ Example: ...@@ -98,7 +98,7 @@ Example:
}; };
RAMC SDRAM/DDR Controller required properties: RAMC SDRAM/DDR Controller required properties:
- compatible: Should be "atmel,at91rm9200-sdramc", - compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
"atmel,at91sam9260-sdramc", "atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc", "atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc", "atmel,sama5d3-ddramc",
......
...@@ -29,7 +29,7 @@ Example: ...@@ -29,7 +29,7 @@ Example:
fuse@7000f800 { fuse@7000f800 {
compatible = "nvidia,tegra20-efuse"; compatible = "nvidia,tegra20-efuse";
reg = <0x7000F800 0x400>, reg = <0x7000f800 0x400>,
<0x70000000 0x400>; <0x70000000 0x400>;
clocks = <&tegra_car TEGRA20_CLK_FUSE>; clocks = <&tegra_car TEGRA20_CLK_FUSE>;
clock-names = "fuse"; clock-names = "fuse";
......
...@@ -92,7 +92,7 @@ aic: interrupt-controller@fffff000 { ...@@ -92,7 +92,7 @@ aic: interrupt-controller@fffff000 {
}; };
ramc0: ramc@ffffff00 { ramc0: ramc@ffffff00 {
compatible = "atmel,at91rm9200-sdramc"; compatible = "atmel,at91rm9200-sdramc", "syscon";
reg = <0xffffff00 0x100>; reg = <0xffffff00 0x100>;
}; };
......
...@@ -70,7 +70,7 @@ &mmc_0 { ...@@ -70,7 +70,7 @@ &mmc_0 {
broken-cd; broken-cd;
bypass-smu; bypass-smu;
cap-mmc-highspeed; cap-mmc-highspeed;
supports-hs200-mode; /* 200 Mhz */ supports-hs200-mode; /* 200 MHz */
card-detect-delay = <200>; card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-sdr-timing = <0 4>;
......
...@@ -66,7 +66,7 @@ OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ ...@@ -66,7 +66,7 @@ OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */
otg_drv_vbus: pinmux_otg_drv_vbus { otg_drv_vbus: pinmux_otg_drv_vbus {
pinctrl-single,pins = < pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50Mhz_clk.usb0_drvvbus */ OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */
>; >;
}; };
......
...@@ -300,7 +300,7 @@ apbdma: dma@0,60020000 { ...@@ -300,7 +300,7 @@ apbdma: dma@0,60020000 {
apbmisc@0,70000800 { apbmisc@0,70000800 {
compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
<0x0 0x7000E864 0x0 0x04>; /* Strapping options */ <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
}; };
pinmux: pinmux@0,70000868 { pinmux: pinmux@0,70000868 {
......
...@@ -563,7 +563,7 @@ memory-controller@7000f400 { ...@@ -563,7 +563,7 @@ memory-controller@7000f400 {
fuse@7000f800 { fuse@7000f800 {
compatible = "nvidia,tegra20-efuse"; compatible = "nvidia,tegra20-efuse";
reg = <0x7000F800 0x400>; reg = <0x7000f800 0x400>;
clocks = <&tegra_car TEGRA20_CLK_FUSE>; clocks = <&tegra_car TEGRA20_CLK_FUSE>;
clock-names = "fuse"; clock-names = "fuse";
resets = <&tegra_car 39>; resets = <&tegra_car 39>;
......
...@@ -7,6 +7,7 @@ struct sleep_save_sp { ...@@ -7,6 +7,7 @@ struct sleep_save_sp {
}; };
extern void cpu_resume(void); extern void cpu_resume(void);
extern void cpu_resume_arm(void);
extern int cpu_suspend(unsigned long, int (*)(unsigned long)); extern int cpu_suspend(unsigned long, int (*)(unsigned long));
#endif #endif
...@@ -118,6 +118,16 @@ ENDPROC(cpu_resume_after_mmu) ...@@ -118,6 +118,16 @@ ENDPROC(cpu_resume_after_mmu)
.text .text
.align .align
#ifdef CONFIG_MMU
.arm
ENTRY(cpu_resume_arm)
THUMB( adr r9, BSYM(1f) ) @ Kernel is entered in ARM.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
THUMB(1: )
#endif
ENTRY(cpu_resume) ENTRY(cpu_resume)
ARM_BE8(setend be) @ ensure we are in BE mode ARM_BE8(setend be) @ ensure we are in BE mode
#ifdef CONFIG_ARM_VIRT_EXT #ifdef CONFIG_ARM_VIRT_EXT
...@@ -150,6 +160,10 @@ THUMB( mov sp, r2 ) ...@@ -150,6 +160,10 @@ THUMB( mov sp, r2 )
THUMB( bx r3 ) THUMB( bx r3 )
ENDPROC(cpu_resume) ENDPROC(cpu_resume)
#ifdef CONFIG_MMU
ENDPROC(cpu_resume_arm)
#endif
.align 2 .align 2
_sleep_save_sp: _sleep_save_sp:
.long sleep_save_sp - . .long sleep_save_sp - .
......
# #
# Makefile for the linux kernel. # Makefile for the linux kernel.
# #
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
obj-y := soc.o obj-y := soc.o
obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
# CPU-specific support # CPU-specific support
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
......
# Note: the following conditions must always be true:
# ZRELADDR == virt_to_phys(TEXTADDR)
# PARAMS_PHYS must be within 4MB of ZRELADDR
# INITRD_PHYS must be in RAM
zreladdr-y += 0x20008000
params_phys-y := 0x20000100
initrd_phys-y := 0x20410000
/*
* Header file for the Atmel RAM Controller
*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2 only
*/
#ifndef __AT91_RAMC_H__
#define __AT91_RAMC_H__
#ifndef __ASSEMBLY__
extern void __iomem *at91_ramc_base[];
#define at91_ramc_read(id, field) \
__raw_readl(at91_ramc_base[id] + field)
#define at91_ramc_write(id, field, value) \
__raw_writel(value, at91_ramc_base[id] + field)
#else
.extern at91_ramc_base
#endif
#include <soc/at91/at91rm9200_sdramc.h>
#include <soc/at91/at91sam9_ddrsdr.h>
#include <soc/at91/at91sam9_sdramc.h>
#endif /* __AT91_RAMC_H__ */
/*
* arch/arm/mach-at91/include/mach/at91rm9200_mc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_MC_H
#define AT91RM9200_MC_H
/* Memory Controller */
#define AT91_MC_RCR 0x00 /* MC Remap Control Register */
#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
#define AT91_MC_ASR 0x04 /* MC Abort Status Register */
#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
#define AT91_MC_ABTSZ_BYTE (0 << 8)
#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
#define AT91_MC_ABTSZ_WORD (2 << 8)
#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
#define AT91_MC_ABTTYP_FETCH (2 << 10)
#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
#define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */
#define AT91_MC_MPR 0x0c /* MC Master Priority Register */
#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
/* External Bus Interface (EBI) registers */
#define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */
#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
#define AT91_EBI_CS0A_SMC (0 << 0)
#define AT91_EBI_CS0A_BFC (1 << 0)
#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_EBI_CS1A_SMC (0 << 1)
#define AT91_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
#define AT91_EBI_CS3A_SMC (0 << 3)
#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
#define AT91_EBI_CS4A_SMC (0 << 4)
#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
/* Static Memory Controller (SMC) registers */
#define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */
#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
#define AT91_SMC_NWS_(x) ((x) << 0)
#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
#define AT91_SMC_TDF_(x) ((x) << 8)
#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
#define AT91_SMC_DBW_16 (1 << 13)
#define AT91_SMC_DBW_8 (2 << 13)
#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
#define AT91_SMC_ACSS_STD (0 << 16)
#define AT91_SMC_ACSS_1 (1 << 16)
#define AT91_SMC_ACSS_2 (2 << 16)
#define AT91_SMC_ACSS_3 (3 << 16)
#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
#define AT91_SMC_RWSETUP_(x) ((x) << 24)
#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
#define AT91_SMC_RWHOLD_(x) ((x) << 28)
/* Burst Flash Controller register */
#define AT91_BFC_MR 0xc0 /* Mode Register */
#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
#define AT91_BFC_BFCOM_DISABLED (0 << 0)
#define AT91_BFC_BFCOM_ASYNC (1 << 0)
#define AT91_BFC_BFCOM_BURST (2 << 0)
#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
#define AT91_BFC_BFCC_MCK (1 << 2)
#define AT91_BFC_BFCC_DIV2 (2 << 2)
#define AT91_BFC_BFCC_DIV4 (3 << 2)
#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
#define AT91_BFC_PAGES (7 << 8) /* Page Size */
#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
#define AT91_BFC_PAGES_16 (1 << 8)
#define AT91_BFC_PAGES_32 (2 << 8)
#define AT91_BFC_PAGES_64 (3 << 8)
#define AT91_BFC_PAGES_128 (4 << 8)
#define AT91_BFC_PAGES_256 (5 << 8)
#define AT91_BFC_PAGES_512 (6 << 8)
#define AT91_BFC_PAGES_1024 (7 << 8)
#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
#endif
/*
* arch/arm/mach-at91/include/mach/at91sam9_smc.h
*
* Copyright (C) 2007 Andrew Victor
* Copyright (C) 2007 Atmel Corporation.
*
* Static Memory Controllers (SMC) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9_SMC_H
#define AT91SAM9_SMC_H
#ifndef __ASSEMBLY__
struct sam9_smc_config {
/* Setup register */
u8 ncs_read_setup;
u8 nrd_setup;
u8 ncs_write_setup;
u8 nwe_setup;
/* Pulse register */
u8 ncs_read_pulse;
u8 nrd_pulse;
u8 ncs_write_pulse;
u8 nwe_pulse;
/* Cycle register */
u16 read_cycle;
u16 write_cycle;
/* Mode register */
u32 mode;
u8 tdf_cycles:4;
};
extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
#endif
#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
#define AT91_SMC_EXNWMODE_READY (3 << 4)
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
#define AT91_SMC_BAT_SELECT (0 << 8)
#define AT91_SMC_BAT_WRITE (1 << 8)
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
#define AT91_SMC_DBW_8 (0 << 12)
#define AT91_SMC_DBW_16 (1 << 12)
#define AT91_SMC_DBW_32 (2 << 12)
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
#define AT91_SMC_TDF_(x) ((x) << 16)
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
#define AT91_SMC_PS (3 << 28) /* Page Size */
#define AT91_SMC_PS_4 (0 << 28)
#define AT91_SMC_PS_8 (1 << 28)
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
#endif
...@@ -233,7 +233,7 @@ static void at91_pm_set_standby(void (*at91_standby)(void)) ...@@ -233,7 +233,7 @@ static void at91_pm_set_standby(void (*at91_standby)(void))
*/ */
static void at91rm9200_standby(void) static void at91rm9200_standby(void)
{ {
u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
asm volatile( asm volatile(
"b 1f\n\t" "b 1f\n\t"
...@@ -244,8 +244,8 @@ static void at91rm9200_standby(void) ...@@ -244,8 +244,8 @@ static void at91rm9200_standby(void)
" mcr p15, 0, %0, c7, c0, 4\n\t" " mcr p15, 0, %0, c7, c0, 4\n\t"
" str %5, [%1, %2]" " str %5, [%1, %2]"
: :
: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR), : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
"r" (1), "r" (AT91RM9200_SDRAMC_SRR), "r" (1), "r" (AT91_MC_SDRAMC_SRR),
"r" (lpr)); "r" (lpr));
} }
...@@ -414,7 +414,7 @@ void __init at91rm9200_pm_init(void) ...@@ -414,7 +414,7 @@ void __init at91rm9200_pm_init(void)
/* /*
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
*/ */
at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
at91_pm_data.memctrl = AT91_MEMCTRL_MC; at91_pm_data.memctrl = AT91_MEMCTRL_MC;
......
...@@ -13,7 +13,19 @@ ...@@ -13,7 +13,19 @@
#include <asm/proc-fns.h> #include <asm/proc-fns.h>
#include <mach/at91_ramc.h> #include <linux/mfd/syscon/atmel-mc.h>
#include <soc/at91/at91sam9_ddrsdr.h>
#include <soc/at91/at91sam9_sdramc.h>
#ifndef __ASSEMBLY__
extern void __iomem *at91_ramc_base[];
#define at91_ramc_read(id, field) \
__raw_readl(at91_ramc_base[id] + field)
#define at91_ramc_write(id, field, value) \
__raw_writel(value, at91_ramc_base[id] + field)
#endif
#define AT91_MEMCTRL_MC 0 #define AT91_MEMCTRL_MC 0
#define AT91_MEMCTRL_SDRAMC 1 #define AT91_MEMCTRL_SDRAMC 1
......
...@@ -13,7 +13,6 @@ ...@@ -13,7 +13,6 @@
*/ */
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/clk/at91_pmc.h> #include <linux/clk/at91_pmc.h>
#include <mach/at91_ramc.h>
#include "pm.h" #include "pm.h"
#define SRAMC_SELF_FRESH_ACTIVE 0x01 #define SRAMC_SELF_FRESH_ACTIVE 0x01
...@@ -216,7 +215,7 @@ ENTRY(at91_sramc_self_refresh) ...@@ -216,7 +215,7 @@ ENTRY(at91_sramc_self_refresh)
/* Active SDRAM self-refresh mode */ /* Active SDRAM self-refresh mode */
mov r3, #1 mov r3, #1
str r3, [r2, #AT91RM9200_SDRAMC_SRR] str r3, [r2, #AT91_MC_SDRAMC_SRR]
b exit_sramc_sf b exit_sramc_sf
ddrc_sf: ddrc_sf:
......
/*
* linux/arch/arm/mach-at91/sam9_smc.c
*
* Copyright (C) 2008 Andrew Victor
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <mach/at91sam9_smc.h>
#include "sam9_smc.h"
#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10))
static void __iomem *smc_base_addr[2];
static void sam9_smc_cs_write_mode(void __iomem *base,
struct sam9_smc_config *config)
{
__raw_writel(config->mode
| AT91_SMC_TDF_(config->tdf_cycles),
base + AT91_SMC_MODE);
}
void sam9_smc_write_mode(int id, int cs,
struct sam9_smc_config *config)
{
sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
}
EXPORT_SYMBOL_GPL(sam9_smc_write_mode);
static void sam9_smc_cs_configure(void __iomem *base,
struct sam9_smc_config *config)
{
/* Setup register */
__raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
| AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
| AT91_SMC_NRDSETUP_(config->nrd_setup)
| AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
base + AT91_SMC_SETUP);
/* Pulse register */
__raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
| AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
| AT91_SMC_NRDPULSE_(config->nrd_pulse)
| AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
base + AT91_SMC_PULSE);
/* Cycle register */
__raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
| AT91_SMC_NRDCYCLE_(config->read_cycle),
base + AT91_SMC_CYCLE);
/* Mode register */
sam9_smc_cs_write_mode(base, config);
}
void sam9_smc_configure(int id, int cs,
struct sam9_smc_config *config)
{
sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
}
EXPORT_SYMBOL_GPL(sam9_smc_configure);
static void sam9_smc_cs_read_mode(void __iomem *base,
struct sam9_smc_config *config)
{
u32 val = __raw_readl(base + AT91_SMC_MODE);
config->mode = (val & ~AT91_SMC_NWECYCLE);
config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
}
void sam9_smc_read_mode(int id, int cs,
struct sam9_smc_config *config)
{
sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
}
EXPORT_SYMBOL_GPL(sam9_smc_read_mode);
static void sam9_smc_cs_read(void __iomem *base,
struct sam9_smc_config *config)
{
u32 val;
/* Setup register */
val = __raw_readl(base + AT91_SMC_SETUP);
config->nwe_setup = val & AT91_SMC_NWESETUP;
config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
/* Pulse register */
val = __raw_readl(base + AT91_SMC_PULSE);
config->nwe_pulse = val & AT91_SMC_NWEPULSE;
config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
/* Cycle register */
val = __raw_readl(base + AT91_SMC_CYCLE);
config->write_cycle = val & AT91_SMC_NWECYCLE;
config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
/* Mode register */
sam9_smc_cs_read_mode(base, config);
}
void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
{
sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
}
void __init at91sam9_ioremap_smc(int id, u32 addr)
{
if (id > 1) {
pr_warn("%s: id > 2\n", __func__);
return;
}
smc_base_addr[id] = ioremap(addr, 512);
if (!smc_base_addr[id])
pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr);
}
/*
* linux/arch/arm/mach-at91/sam9_smc.
*
* Copyright (C) 2008 Andrew Victor
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
extern void __init at91sam9_ioremap_smc(int id, u32 addr);
...@@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o ...@@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
ifeq ($(CONFIG_ARCH_BRCMSTB),y) ifeq ($(CONFIG_ARCH_BRCMSTB),y)
CFLAGS_platsmp-brcmstb.o += -march=armv7-a CFLAGS_platsmp-brcmstb.o += -march=armv7-a
obj-y += brcmstb.o obj-y += brcmstb.o
obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o obj-$(CONFIG_SMP) += platsmp-brcmstb.o
endif endif
/*
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __BRCMSTB_H__
#define __BRCMSTB_H__
void brcmstb_secondary_startup(void);
#endif /* __BRCMSTB_H__ */
/*
* SMP boot code for secondary CPUs
* Based on arch/arm/mach-tegra/headsmp.S
*
* Copyright (C) 2010 NVIDIA, Inc.
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <asm/assembler.h>
#include <linux/linkage.h>
#include <linux/init.h>
.section ".text.head", "ax"
ENTRY(brcmstb_secondary_startup)
/*
* Ensure CPU is in a sane state by disabling all IRQs and switching
* into SVC mode.
*/
setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
bl v7_invalidate_l1
b secondary_startup
ENDPROC(brcmstb_secondary_startup)
...@@ -30,8 +30,6 @@ ...@@ -30,8 +30,6 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
#include "brcmstb.h"
enum { enum {
ZONE_MAN_CLKEN_MASK = BIT(0), ZONE_MAN_CLKEN_MASK = BIT(0),
ZONE_MAN_RESET_CNTL_MASK = BIT(1), ZONE_MAN_RESET_CNTL_MASK = BIT(1),
...@@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu) ...@@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
* Set the reset vector to point to the secondary_startup * Set the reset vector to point to the secondary_startup
* routine * routine
*/ */
cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup)); cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
/* Unhalt the cpu */ /* Unhalt the cpu */
cpu_rst_cfg_set(cpu, 0); cpu_rst_cfg_set(cpu, 0);
......
...@@ -12,12 +12,6 @@ ...@@ -12,12 +12,6 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/assembler.h> #include <asm/assembler.h>
ENTRY(berlin_secondary_startup)
ARM_BE8(setend be)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(berlin_secondary_startup)
/* /*
* If the following instruction is set in the reset exception vector, CPUs * If the following instruction is set in the reset exception vector, CPUs
* will fetch the value of the software reset address vector when being * will fetch the value of the software reset address vector when being
......
...@@ -22,7 +22,6 @@ ...@@ -22,7 +22,6 @@
#define RESET_VECT 0x00 #define RESET_VECT 0x00
#define SW_RESET_ADDR 0x94 #define SW_RESET_ADDR 0x94
extern void berlin_secondary_startup(void);
extern u32 boot_inst; extern u32 boot_inst;
static void __iomem *cpu_ctrl; static void __iomem *cpu_ctrl;
...@@ -85,7 +84,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus) ...@@ -85,7 +84,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
* Write the secondary startup address into the SW reset address * Write the secondary startup address into the SW reset address
* vector. This is used by boot_inst. * vector. This is used by boot_inst.
*/ */
writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR); writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
iounmap(vectors_base); iounmap(vectors_base);
unmap_scu: unmap_scu:
......
...@@ -36,7 +36,7 @@ extern void __iomem *da8xx_syscfg1_base; ...@@ -36,7 +36,7 @@ extern void __iomem *da8xx_syscfg1_base;
/* /*
* If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
* (than the regular 300Mhz variant), the board code should set this up * (than the regular 300MHz variant), the board code should set this up
* with the supported speed before calling da850_register_cpufreq(). * with the supported speed before calling da850_register_cpufreq().
*/ */
extern unsigned int da850_max_speed; extern unsigned int da850_max_speed;
......
...@@ -6,4 +6,4 @@ CFLAGS_platmcpm.o := -march=armv7-a ...@@ -6,4 +6,4 @@ CFLAGS_platmcpm.o := -march=armv7-a
obj-y += hisilicon.o obj-y += hisilicon.o
obj-$(CONFIG_MCPM) += platmcpm.o obj-$(CONFIG_MCPM) += platmcpm.o
obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o hotplug.o
...@@ -12,7 +12,6 @@ extern void hi3xxx_cpu_die(unsigned int cpu); ...@@ -12,7 +12,6 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
extern int hi3xxx_cpu_kill(unsigned int cpu); extern int hi3xxx_cpu_kill(unsigned int cpu);
extern void hi3xxx_set_cpu(int cpu, bool enable); extern void hi3xxx_set_cpu(int cpu, bool enable);
extern void hisi_secondary_startup(void);
extern struct smp_operations hix5hd2_smp_ops; extern struct smp_operations hix5hd2_smp_ops;
extern void hix5hd2_set_cpu(int cpu, bool enable); extern void hix5hd2_set_cpu(int cpu, bool enable);
extern void hix5hd2_cpu_die(unsigned int cpu); extern void hix5hd2_cpu_die(unsigned int cpu);
......
/*
* Copyright (c) 2014 Hisilicon Limited.
* Copyright (c) 2014 Linaro Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
ENTRY(hisi_secondary_startup)
bl v7_invalidate_l1
b secondary_startup
...@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{ {
phys_addr_t jumpaddr; phys_addr_t jumpaddr;
jumpaddr = virt_to_phys(hisi_secondary_startup); jumpaddr = virt_to_phys(secondary_startup);
hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr); hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
hix5hd2_set_cpu(cpu, true); hix5hd2_set_cpu(cpu, true);
arch_send_wakeup_ipi_mask(cpumask_of(cpu)); arch_send_wakeup_ipi_mask(cpumask_of(cpu));
...@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
struct device_node *node; struct device_node *node;
jumpaddr = virt_to_phys(hisi_secondary_startup); jumpaddr = virt_to_phys(secondary_startup);
hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr); hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl"); node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
......
...@@ -444,40 +444,6 @@ config MACH_MX35_3DS ...@@ -444,40 +444,6 @@ config MACH_MX35_3DS
Include support for MX35PDK platform. This includes specific Include support for MX35PDK platform. This includes specific
configurations for the board and its peripherals. configurations for the board and its peripherals.
config MACH_EUKREA_CPUIMX35SD
bool "Support Eukrea CPUIMX35 Platform"
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select USB_ULPI_VIEWPORT if USB_ULPI
select SOC_IMX35
help
Include support for Eukrea CPUIMX35 platform. This includes
specific configurations for the board and its peripherals.
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX35SD
default MACH_EUKREA_MBIMXSD35_BASEBOARD
config MACH_EUKREA_MBIMXSD35_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_SPI_IMX
select LEDS_GPIO_REGISTER
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
config MACH_VPR200 config MACH_VPR200
bool "Support VPR200 platform" bool "Support VPR200 platform"
select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_FSL_USB2_UDC
......
...@@ -73,8 +73,6 @@ obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o ...@@ -73,8 +73,6 @@ obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o
# i.MX35 based machines # i.MX35 based machines
obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
......
...@@ -216,7 +216,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) ...@@ -216,7 +216,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
/* FIXME 100Mhz is used for pcie ref for all imx6 pcie, excepted imx6q */ /* FIXME 100MHz is used for pcie ref for all imx6 pcie, excepted imx6q */
clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5); clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
...@@ -520,7 +520,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) ...@@ -520,7 +520,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
pr_err("Failed to set pcie parent clk.\n"); pr_err("Failed to set pcie parent clk.\n");
/* /*
* Init enet system AHB clock, set to 200Mhz * Init enet system AHB clock, set to 200MHz
* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
*/ */
clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
......
/*
* Copyright (C) 2010 Eric Benard - eric@eukrea.com
*
* Based on pcm970-baseboard.c which is :
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <video/platform_lcd.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include "common.h"
#include "devices-imx35.h"
#include "hardware.h"
#include "iomux-mx35.h"
static const struct fb_videomode fb_modedb[] = {
{
.name = "CMO-QVGA",
.refresh = 60,
.xres = 320,
.yres = 240,
.pixclock = KHZ2PICOS(6500),
.left_margin = 68,
.right_margin = 20,
.upper_margin = 15,
.lower_margin = 4,
.hsync_len = 30,
.vsync_len = 3,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
{
.name = "DVI-VGA",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 32000,
.left_margin = 100,
.right_margin = 100,
.upper_margin = 7,
.lower_margin = 100,
.hsync_len = 7,
.vsync_len = 7,
.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
{
.name = "DVI-SVGA",
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 25000,
.left_margin = 75,
.right_margin = 75,
.upper_margin = 7,
.lower_margin = 75,
.hsync_len = 7,
.vsync_len = 7,
.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
};
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "CMO-QVGA",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
};
static const iomux_v3_cfg_t eukrea_mbimxsd_pads[] __initconst = {
/* LCD */
MX35_PAD_LD0__IPU_DISPB_DAT_0,
MX35_PAD_LD1__IPU_DISPB_DAT_1,
MX35_PAD_LD2__IPU_DISPB_DAT_2,
MX35_PAD_LD3__IPU_DISPB_DAT_3,
MX35_PAD_LD4__IPU_DISPB_DAT_4,
MX35_PAD_LD5__IPU_DISPB_DAT_5,
MX35_PAD_LD6__IPU_DISPB_DAT_6,
MX35_PAD_LD7__IPU_DISPB_DAT_7,
MX35_PAD_LD8__IPU_DISPB_DAT_8,
MX35_PAD_LD9__IPU_DISPB_DAT_9,
MX35_PAD_LD10__IPU_DISPB_DAT_10,
MX35_PAD_LD11__IPU_DISPB_DAT_11,
MX35_PAD_LD12__IPU_DISPB_DAT_12,
MX35_PAD_LD13__IPU_DISPB_DAT_13,
MX35_PAD_LD14__IPU_DISPB_DAT_14,
MX35_PAD_LD15__IPU_DISPB_DAT_15,
MX35_PAD_LD16__IPU_DISPB_DAT_16,
MX35_PAD_LD17__IPU_DISPB_DAT_17,
MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
/* Backlight */
MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
/* LCD_PWR */
MX35_PAD_D3_CLS__GPIO1_4,
/* LED */
MX35_PAD_LD23__GPIO3_29,
/* SWITCH */
MX35_PAD_LD19__GPIO3_25,
/* UART2 */
MX35_PAD_CTS2__UART2_CTS,
MX35_PAD_RTS2__UART2_RTS,
MX35_PAD_TXD2__UART2_TXD_MUX,
MX35_PAD_RXD2__UART2_RXD_MUX,
/* I2S */
MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
/* CAN2 */
MX35_PAD_TX5_RX0__CAN2_TXCAN,
MX35_PAD_TX4_RX1__CAN2_RXCAN,
/* SDCARD */
MX35_PAD_SD1_CMD__ESDHC1_CMD,
MX35_PAD_SD1_CLK__ESDHC1_CLK,
MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
/* SD1 CD */
MX35_PAD_LD18__GPIO3_24,
/* SPI */
MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
MX35_PAD_CSPI1_MISO__CSPI1_MISO,
MX35_PAD_CSPI1_SS0__GPIO1_18,
MX35_PAD_CSPI1_SS1__GPIO1_19,
MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
MX35_PAD_CSPI1_SPI_RDY__GPIO3_5,
};
#define GPIO_LED1 IMX_GPIO_NR(3, 29)
#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25)
#define GPIO_LCDPWR IMX_GPIO_NR(1, 4)
#define GPIO_SD1CD IMX_GPIO_NR(3, 24)
#define GPIO_SPI1_SS0 IMX_GPIO_NR(1, 18)
#define GPIO_SPI1_SS1 IMX_GPIO_NR(1, 19)
#define GPIO_SPI1_IRQ IMX_GPIO_NR(3, 5)
static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power)
gpio_direction_output(GPIO_LCDPWR, 1);
else
gpio_direction_output(GPIO_LCDPWR, 0);
}
static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
.set_power = eukrea_mbimxsd_lcd_power_set,
};
static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
.name = "platform-lcd",
.dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
};
static struct gpio_led eukrea_mbimxsd_leds[] = {
{
.name = "led1",
.default_trigger = "heartbeat",
.active_low = 1,
.gpio = GPIO_LED1,
},
};
static const struct gpio_led_platform_data
eukrea_mbimxsd_led_info __initconst = {
.leds = eukrea_mbimxsd_leds,
.num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
};
static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
{
.gpio = GPIO_SWITCH1,
.code = BTN_0,
.desc = "BP1",
.active_low = 1,
.wakeup = 1,
},
};
static const struct gpio_keys_platform_data
eukrea_mbimxsd_button_data __initconst = {
.buttons = eukrea_mbimxsd_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
static struct platform_device *platform_devices[] __initdata = {
&eukrea_mbimxsd_lcd_powerdev,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
{
I2C_BOARD_INFO("tlv320aic23", 0x1a),
},
};
static const
struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
.flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
};
static struct esdhc_platform_data sd1_pdata = {
.cd_gpio = GPIO_SD1CD,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_NONE,
};
static struct spi_board_info eukrea_mbimxsd35_spi_board_info[] __initdata = {
{
.modalias = "spidev",
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
},
{
.modalias = "spidev",
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 1,
.mode = SPI_MODE_0,
},
};
static int eukrea_mbimxsd35_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
static const struct spi_imx_master eukrea_mbimxsd35_spi0_data __initconst = {
.chipselect = eukrea_mbimxsd35_spi_cs,
.num_chipselect = ARRAY_SIZE(eukrea_mbimxsd35_spi_cs),
};
/*
* system init for baseboard usage. Will be called by cpuimx35 init.
*
* Add platform devices present on this baseboard and init
* them from CPU side as far as required to use them later on
*/
void __init eukrea_mbimxsd35_baseboard_init(void)
{
if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
ARRAY_SIZE(eukrea_mbimxsd_pads)))
printk(KERN_ERR "error setting mbimxsd pads !\n");
imx35_add_imx_uart1(&uart_pdata);
imx35_add_ipu_core();
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
imx35_add_flexcan1();
imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);
gpio_free(GPIO_LED1);
gpio_request(GPIO_SWITCH1, "SWITCH1");
gpio_direction_input(GPIO_SWITCH1);
gpio_free(GPIO_SWITCH1);
gpio_request(GPIO_LCDPWR, "LCDPWR");
gpio_direction_output(GPIO_LCDPWR, 1);
i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
gpio_direction_input(GPIO_SPI1_IRQ);
gpio_free(GPIO_SPI1_IRQ);
imx35_add_spi_imx0(&eukrea_mbimxsd35_spi0_data);
spi_register_board_info(eukrea_mbimxsd35_spi_board_info,
ARRAY_SIZE(eukrea_mbimxsd35_spi_board_info));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
}
...@@ -474,7 +474,6 @@ static const struct of_device_id imx_gpc_dt_ids[] = { ...@@ -474,7 +474,6 @@ static const struct of_device_id imx_gpc_dt_ids[] = {
static struct platform_driver imx_gpc_driver = { static struct platform_driver imx_gpc_driver = {
.driver = { .driver = {
.name = "imx-gpc", .name = "imx-gpc",
.owner = THIS_MODULE,
.of_match_table = imx_gpc_dt_ids, .of_match_table = imx_gpc_dt_ids,
}, },
.probe = imx_gpc_probe, .probe = imx_gpc_probe,
......
...@@ -25,7 +25,6 @@ diag_reg_offset: ...@@ -25,7 +25,6 @@ diag_reg_offset:
.endm .endm
ENTRY(v7_secondary_startup) ENTRY(v7_secondary_startup)
bl v7_invalidate_l1
set_diag_reg set_diag_reg
b secondary_startup b secondary_startup
ENDPROC(v7_secondary_startup) ENDPROC(v7_secondary_startup)
/*
* Copyright (C) 2010 Eric Benard - eric@eukrea.com
* Copyright (C) 2009 Sascha Hauer, Pengutronix
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/memory.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/i2c/tsc2007.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/i2c-gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include "common.h"
#include "devices-imx35.h"
#include "ehci.h"
#include "eukrea-baseboards.h"
#include "hardware.h"
#include "iomux-mx35.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static const struct imxi2c_platform_data
eukrea_cpuimx35_i2c0_data __initconst = {
.bitrate = 100000,
};
#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 2)
static int tsc2007_get_pendown_state(struct device *dev)
{
return !gpio_get_value(TSC2007_IRQGPIO);
}
static struct tsc2007_platform_data tsc2007_info = {
.model = 2007,
.x_plate_ohms = 180,
.get_pendown_state = tsc2007_get_pendown_state,
};
static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
{
I2C_BOARD_INFO("pcf8563", 0x51),
}, {
I2C_BOARD_INFO("tsc2007", 0x48),
.platform_data = &tsc2007_info,
/* irq number is run-time assigned */
},
};
static const iomux_v3_cfg_t eukrea_cpuimx35_pads[] __initconst = {
/* UART1 */
MX35_PAD_CTS1__UART1_CTS,
MX35_PAD_RTS1__UART1_RTS,
MX35_PAD_TXD1__UART1_TXD_MUX,
MX35_PAD_RXD1__UART1_RXD_MUX,
/* FEC */
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
MX35_PAD_FEC_RX_DV__FEC_RX_DV,
MX35_PAD_FEC_COL__FEC_COL,
MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
MX35_PAD_FEC_TX_EN__FEC_TX_EN,
MX35_PAD_FEC_MDC__FEC_MDC,
MX35_PAD_FEC_MDIO__FEC_MDIO,
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
MX35_PAD_FEC_CRS__FEC_CRS,
MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
/* I2C1 */
MX35_PAD_I2C1_CLK__I2C1_SCL,
MX35_PAD_I2C1_DAT__I2C1_SDA,
/* TSC2007 IRQ */
MX35_PAD_ATA_DA2__GPIO3_2,
};
static const struct mxc_nand_platform_data
eukrea_cpuimx35_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static int eukrea_cpuimx35_otg_init(struct platform_device *pdev)
{
return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
}
static const struct mxc_usbh_platform_data otg_pdata __initconst = {
.init = eukrea_cpuimx35_otg_init,
.portsc = MXC_EHCI_MODE_UTMI,
};
static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev)
{
return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
}
static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
.init = eukrea_cpuimx35_usbh1_init,
.portsc = MXC_EHCI_MODE_SERIAL,
};
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
.workaround = FLS_USB2_WORKAROUND_ENGCM09152,
};
static bool otg_mode_host __initdata;
static int __init eukrea_cpuimx35_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = true;
else if (!strcmp(options, "device"))
otg_mode_host = false;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 1;
}
__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
/*
* Board specific initialization.
*/
static void __init eukrea_cpuimx35_init(void)
{
imx35_soc_init();
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
ARRAY_SIZE(eukrea_cpuimx35_pads));
imx35_add_fec(NULL);
imx35_add_imx2_wdt();
imx35_add_imx_uart0(&uart_pdata);
imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
eukrea_cpuimx35_i2c_devices[1].irq = gpio_to_irq(TSC2007_IRQGPIO);
i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
if (otg_mode_host)
imx35_add_mxc_ehci_otg(&otg_pdata);
else
imx35_add_fsl_usb2_udc(&otg_device_pdata);
imx35_add_mxc_ehci_hs(&usbh1_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
eukrea_mbimxsd35_baseboard_init();
#endif
}
static void __init eukrea_cpuimx35_timer_init(void)
{
mx35_clocks_init();
}
MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
/* Maintainer: Eukrea Electromatique */
.atag_offset = 0x100,
.map_io = mx35_map_io,
.init_early = imx35_init_early,
.init_irq = mx35_init_irq,
.init_time = eukrea_cpuimx35_timer_init,
.init_machine = eukrea_cpuimx35_init,
.restart = mxc_restart,
MACHINE_END
...@@ -42,7 +42,7 @@ static inline unsigned long iop13xx_core_freq(void) ...@@ -42,7 +42,7 @@ static inline unsigned long iop13xx_core_freq(void)
case IOP13XX_CORE_FREQ_1200: case IOP13XX_CORE_FREQ_1200:
return 1200000000; return 1200000000;
default: default:
printk("%s: warning unknown frequency, defaulting to 800Mhz\n", printk("%s: warning unknown frequency, defaulting to 800MHz\n",
__func__); __func__);
} }
......
...@@ -74,7 +74,7 @@ extern unsigned long ixp4xx_exp_bus_size; ...@@ -74,7 +74,7 @@ extern unsigned long ixp4xx_exp_bus_size;
/* /*
* Clock Speed Definitions. * Clock Speed Definitions.
*/ */
#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ #define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66MHzi APB BUS */
#define IXP4XX_UART_XTAL 14745600 #define IXP4XX_UART_XTAL 14745600
/* /*
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
#include <asm/sizes.h> #include <asm/sizes.h>
/* /*
* Clocks are derived from MCLK, which is 25Mhz * Clocks are derived from MCLK, which is 25MHz
*/ */
#define KS8695_CLOCK_RATE 25000000 #define KS8695_CLOCK_RATE 25000000
......
...@@ -21,7 +21,6 @@ ...@@ -21,7 +21,6 @@
ENTRY(mvebu_cortex_a9_secondary_startup) ENTRY(mvebu_cortex_a9_secondary_startup)
ARM_BE8(setend be) ARM_BE8(setend be)
bl v7_invalidate_l1
bl armada_38x_scu_power_up bl armada_38x_scu_power_up
b secondary_startup b secondary_startup
ENDPROC(mvebu_cortex_a9_secondary_startup) ENDPROC(mvebu_cortex_a9_secondary_startup)
...@@ -171,12 +171,6 @@ config MACH_OMAP2_TUSB6010 ...@@ -171,12 +171,6 @@ config MACH_OMAP2_TUSB6010
depends on ARCH_OMAP2 && SOC_OMAP2420 depends on ARCH_OMAP2 && SOC_OMAP2420
default y if MACH_NOKIA_N8X0 default y if MACH_NOKIA_N8X0
config MACH_OMAP3_BEAGLE
bool "OMAP3 BEAGLE board"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
config MACH_OMAP_LDP config MACH_OMAP_LDP
bool "OMAP3 LDP board" bool "OMAP3 LDP board"
depends on ARCH_OMAP3 depends on ARCH_OMAP3
...@@ -203,12 +197,6 @@ config MACH_OMAP3_TORPEDO ...@@ -203,12 +197,6 @@ config MACH_OMAP3_TORPEDO
for full description please see the products webpage at for full description please see the products webpage at
http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
config MACH_OVERO
bool "Gumstix Overo board"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
config MACH_OMAP3517EVM config MACH_OMAP3517EVM
bool "OMAP3517/ AM3517 EVM board" bool "OMAP3517/ AM3517 EVM board"
depends on ARCH_OMAP3 depends on ARCH_OMAP3
...@@ -240,16 +228,6 @@ config MACH_NOKIA_RX51 ...@@ -240,16 +228,6 @@ config MACH_NOKIA_RX51
default y default y
select OMAP_PACKAGE_CBB select OMAP_PACKAGE_CBB
config MACH_CM_T35
bool "CompuLab CM-T35/CM-T3730 modules"
depends on ARCH_OMAP3
default y
select MACH_CM_T3730
select OMAP_PACKAGE_CUS
config MACH_CM_T3730
bool
config OMAP3_SDRC_AC_TIMING config OMAP3_SDRC_AC_TIMING
bool "Enable SDRC AC timing register changes" bool "Enable SDRC AC timing register changes"
depends on ARCH_OMAP3 depends on ARCH_OMAP3
......
...@@ -242,17 +242,14 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o ...@@ -242,17 +242,14 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o
# Specific board support # Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
obj-$(CONFIG_MACH_OVERO) += board-overo.o
obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o
obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o
obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
# Platform specific device init code # Platform specific device init code
......
/*
* CompuLab CM-T35/CM-T3730 modules support
*
* Copyright (C) 2009-2011 CompuLab, Ltd.
* Authors: Mike Rapoport <mike@compulab.co.il>
* Igor Grinberg <grinberg@compulab.co.il>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
*/
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/input/matrix_keypad.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/omap-gpmc.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/at24.h>
#include <linux/i2c/twl.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/mmc/host.h>
#include <linux/usb/phy.h>
#include <linux/spi/spi.h>
#include <linux/spi/tdo24m.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <linux/platform_data/mtd-nand-omap2.h>
#include <video/omapdss.h>
#include <video/omap-panel-data.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include "common.h"
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "hsmmc.h"
#include "common-board-devices.h"
#define CM_T35_GPIO_PENDOWN 57
#define SB_T35_USB_HUB_RESET_GPIO 167
#define CM_T35_SMSC911X_CS 5
#define CM_T35_SMSC911X_GPIO 163
#define SB_T35_SMSC911X_CS 4
#define SB_T35_SMSC911X_GPIO 65
#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
#include <linux/smsc911x.h>
#include "gpmc-smsc911x.h"
static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
.id = 0,
.cs = CM_T35_SMSC911X_CS,
.gpio_irq = CM_T35_SMSC911X_GPIO,
.gpio_reset = -EINVAL,
.flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
};
static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = {
.id = 1,
.cs = SB_T35_SMSC911X_CS,
.gpio_irq = SB_T35_SMSC911X_GPIO,
.gpio_reset = -EINVAL,
.flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
};
static struct regulator_consumer_supply cm_t35_smsc911x_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
};
static struct regulator_consumer_supply sb_t35_smsc911x_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x.1"),
REGULATOR_SUPPLY("vdd33a", "smsc911x.1"),
};
static void __init cm_t35_init_ethernet(void)
{
regulator_register_fixed(0, cm_t35_smsc911x_supplies,
ARRAY_SIZE(cm_t35_smsc911x_supplies));
regulator_register_fixed(1, sb_t35_smsc911x_supplies,
ARRAY_SIZE(sb_t35_smsc911x_supplies));
gpmc_smsc911x_init(&cm_t35_smsc911x_cfg);
gpmc_smsc911x_init(&sb_t35_smsc911x_cfg);
}
#else
static inline void __init cm_t35_init_ethernet(void) { return; }
#endif
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
#include <linux/leds.h>
static struct gpio_led cm_t35_leds[] = {
[0] = {
.gpio = 186,
.name = "cm-t35:green",
.default_trigger = "heartbeat",
.active_low = 0,
},
};
static struct gpio_led_platform_data cm_t35_led_pdata = {
.num_leds = ARRAY_SIZE(cm_t35_leds),
.leds = cm_t35_leds,
};
static struct platform_device cm_t35_led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &cm_t35_led_pdata,
},
};
static void __init cm_t35_init_led(void)
{
platform_device_register(&cm_t35_led_device);
}
#else
static inline void cm_t35_init_led(void) {}
#endif
#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
static struct mtd_partition cm_t35_nand_partitions[] = {
{
.name = "xloader",
.offset = 0, /* Offset = 0x00000 */
.size = 4 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE
},
{
.name = "uboot",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
.size = 15 * NAND_BLOCK_SIZE,
},
{
.name = "uboot environment",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
.size = 2 * NAND_BLOCK_SIZE,
},
{
.name = "linux",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */
.size = 32 * NAND_BLOCK_SIZE,
},
{
.name = "rootfs",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */
.size = MTDPART_SIZ_FULL,
},
};
static struct omap_nand_platform_data cm_t35_nand_data = {
.parts = cm_t35_nand_partitions,
.nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
.cs = 0,
};
static void __init cm_t35_init_nand(void)
{
if (gpmc_nand_init(&cm_t35_nand_data, NULL) < 0)
pr_err("CM-T35: Unable to register NAND device\n");
}
#else
static inline void cm_t35_init_nand(void) {}
#endif
#define CM_T35_LCD_EN_GPIO 157
#define CM_T35_LCD_BL_GPIO 58
#define CM_T35_DVI_EN_GPIO 54
static const struct display_timing cm_t35_lcd_videomode = {
.pixelclock = { 0, 26000000, 0 },
.hactive = { 0, 480, 0 },
.hfront_porch = { 0, 104, 0 },
.hback_porch = { 0, 8, 0 },
.hsync_len = { 0, 8, 0 },
.vactive = { 0, 640, 0 },
.vfront_porch = { 0, 4, 0 },
.vback_porch = { 0, 2, 0 },
.vsync_len = { 0, 2, 0 },
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE,
};
static struct panel_dpi_platform_data cm_t35_lcd_pdata = {
.name = "lcd",
.source = "dpi.0",
.data_lines = 18,
.display_timing = &cm_t35_lcd_videomode,
.enable_gpio = -1,
.backlight_gpio = CM_T35_LCD_BL_GPIO,
};
static struct platform_device cm_t35_lcd_device = {
.name = "panel-dpi",
.id = 0,
.dev.platform_data = &cm_t35_lcd_pdata,
};
static struct connector_dvi_platform_data cm_t35_dvi_connector_pdata = {
.name = "dvi",
.source = "tfp410.0",
.i2c_bus_num = -1,
};
static struct platform_device cm_t35_dvi_connector_device = {
.name = "connector-dvi",
.id = 0,
.dev.platform_data = &cm_t35_dvi_connector_pdata,
};
static struct encoder_tfp410_platform_data cm_t35_tfp410_pdata = {
.name = "tfp410.0",
.source = "dpi.0",
.data_lines = 24,
.power_down_gpio = CM_T35_DVI_EN_GPIO,
};
static struct platform_device cm_t35_tfp410_device = {
.name = "tfp410",
.id = 0,
.dev.platform_data = &cm_t35_tfp410_pdata,
};
static struct connector_atv_platform_data cm_t35_tv_pdata = {
.name = "tv",
.source = "venc.0",
.connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
.invert_polarity = false,
};
static struct platform_device cm_t35_tv_connector_device = {
.name = "connector-analog-tv",
.id = 0,
.dev.platform_data = &cm_t35_tv_pdata,
};
static struct omap_dss_board_info cm_t35_dss_data = {
.default_display_name = "dvi",
};
static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
.turbo_mode = 0,
};
static struct tdo24m_platform_data tdo24m_config = {
.model = TDO35S,
};
static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
{
.modalias = "tdo24m",
.bus_num = 4,
.chip_select = 0,
.max_speed_hz = 1000000,
.controller_data = &tdo24m_mcspi_config,
.platform_data = &tdo24m_config,
},
};
static void __init cm_t35_init_display(void)
{
int err;
spi_register_board_info(cm_t35_lcd_spi_board_info,
ARRAY_SIZE(cm_t35_lcd_spi_board_info));
err = gpio_request_one(CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW,
"lcd bl enable");
if (err) {
pr_err("CM-T35: failed to request LCD EN GPIO\n");
return;
}
msleep(50);
gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
err = omap_display_init(&cm_t35_dss_data);
if (err) {
pr_err("CM-T35: failed to register DSS device\n");
gpio_free(CM_T35_LCD_EN_GPIO);
}
platform_device_register(&cm_t35_tfp410_device);
platform_device_register(&cm_t35_dvi_connector_device);
platform_device_register(&cm_t35_lcd_device);
platform_device_register(&cm_t35_tv_connector_device);
}
static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
REGULATOR_SUPPLY("vcc", "spi1.0"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data cm_t35_vmmc1 = {
.constraints = {
.min_uV = 1850000,
.max_uV = 3150000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply),
.consumer_supplies = cm_t35_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
static struct regulator_init_data cm_t35_vsim = {
.constraints = {
.min_uV = 1800000,
.max_uV = 3000000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply),
.consumer_supplies = cm_t35_vsim_supply,
};
static struct regulator_init_data cm_t35_vio = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE,
},
.num_consumer_supplies = ARRAY_SIZE(cm_t35_vio_supplies),
.consumer_supplies = cm_t35_vio_supplies,
};
static uint32_t cm_t35_keymap[] = {
KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT),
KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN),
KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D),
};
static struct matrix_keymap_data cm_t35_keymap_data = {
.keymap = cm_t35_keymap,
.keymap_size = ARRAY_SIZE(cm_t35_keymap),
};
static struct twl4030_keypad_data cm_t35_kp_data = {
.keymap_data = &cm_t35_keymap_data,
.rows = 3,
.cols = 3,
.rep = 1,
};
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.deferred = true,
},
{
.mmc = 2,
.caps = MMC_CAP_4_BIT_DATA,
.transceiver = 1,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.ocr_mask = 0x00100000, /* 3.3V */
},
{} /* Terminator */
};
static struct usbhs_phy_data phy_data[] __initdata = {
{
.port = 1,
.reset_gpio = OMAP_MAX_GPIO_LINES + 6,
.vcc_gpio = -EINVAL,
},
{
.port = 2,
.reset_gpio = OMAP_MAX_GPIO_LINES + 7,
.vcc_gpio = -EINVAL,
},
};
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
};
static void __init cm_t35_init_usbh(void)
{
int err;
err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO,
GPIOF_OUT_INIT_LOW, "usb hub rst");
if (err) {
pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err);
} else {
udelay(10);
gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
msleep(1);
}
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
usbhs_init(&usbhs_bdata);
}
static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
unsigned ngpio)
{
int wlan_rst = gpio + 2;
if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) {
gpio_export(wlan_rst, 0);
udelay(10);
gpio_set_value_cansleep(wlan_rst, 0);
udelay(10);
gpio_set_value_cansleep(wlan_rst, 1);
} else {
pr_err("CM-T35: could not obtain gpio for WiFi reset\n");
}
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap_hsmmc_late_init(mmc);
return 0;
}
static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
.setup = cm_t35_twl_gpio_setup,
};
static struct twl4030_power_data cm_t35_power_data = {
.use_poweroff = true,
};
static struct twl4030_platform_data cm_t35_twldata = {
/* platform_data for children goes here */
.keypad = &cm_t35_kp_data,
.gpio = &cm_t35_gpio_data,
.vmmc1 = &cm_t35_vmmc1,
.vsim = &cm_t35_vsim,
.vio = &cm_t35_vio,
.power = &cm_t35_power_data,
};
#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
#include <media/omap3isp.h>
#include "devices.h"
static struct isp_platform_subdev cm_t35_isp_subdevs[] = {
{
.board_info = &(struct i2c_board_info){
I2C_BOARD_INFO("mt9t001", 0x5d)
},
.i2c_adapter_id = 3,
.bus = &(struct isp_bus_cfg){
.interface = ISP_INTERFACE_PARALLEL,
.bus = {
.parallel = {
.clk_pol = 1,
},
},
},
},
{
.board_info = &(struct i2c_board_info){
I2C_BOARD_INFO("tvp5150", 0x5c),
},
.i2c_adapter_id = 3,
.bus = &(struct isp_bus_cfg){
.interface = ISP_INTERFACE_PARALLEL,
.bus = {
.parallel = {
.clk_pol = 0,
},
},
},
},
{ 0 },
};
static struct isp_platform_data cm_t35_isp_pdata = {
.subdevs = cm_t35_isp_subdevs,
};
static struct regulator_consumer_supply cm_t35_camera_supplies[] = {
REGULATOR_SUPPLY("vaa", "3-005d"),
REGULATOR_SUPPLY("vdd", "3-005d"),
};
static void __init cm_t35_init_camera(void)
{
struct clk *clk;
clk = clk_register_fixed_rate(NULL, "mt9t001-clkin", NULL, CLK_IS_ROOT,
48000000);
clk_register_clkdev(clk, NULL, "3-005d");
regulator_register_fixed(2, cm_t35_camera_supplies,
ARRAY_SIZE(cm_t35_camera_supplies));
if (omap3_init_camera(&cm_t35_isp_pdata) < 0)
pr_warn("CM-T3x: Failed registering camera device!\n");
}
#else
static inline void cm_t35_init_camera(void) {}
#endif /* CONFIG_VIDEO_OMAP3 */
static void __init cm_t35_init_i2c(void)
{
omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
TWL_COMMON_REGULATOR_VDAC |
TWL_COMMON_PDATA_AUDIO);
omap3_pmic_init("tps65930", &cm_t35_twldata);
omap_register_i2c_bus(3, 400, NULL, 0);
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* nCS and IRQ for CM-T35 ethernet */
OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
/* nCS and IRQ for SB-T35 ethernet */
OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0),
OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
/* PENDOWN GPIO */
OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* mUSB */
OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* MMC 2 */
OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
/* McSPI 1 */
OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
/* McSPI 4 */
OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
/* McBSP 2 */
OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
/* serial ports */
OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* common DSS */
OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
/* Camera */
OMAP3_MUX(CAM_HS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_VS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_XCLKA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_FLD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_D0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_D1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_D2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_D3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_D4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_D5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_D6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_D7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_D8, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP3_MUX(CAM_D9, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP3_MUX(CAM_STROBE, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(CAM_D10, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN),
OMAP3_MUX(CAM_D11, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN),
/* display controls */
OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
/* TPS IRQ */
OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
OMAP_PIN_INPUT_PULLUP),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static void __init cm_t3x_common_dss_mux_init(int mux_mode)
{
omap_mux_init_signal("dss_data18", mux_mode);
omap_mux_init_signal("dss_data19", mux_mode);
omap_mux_init_signal("dss_data20", mux_mode);
omap_mux_init_signal("dss_data21", mux_mode);
omap_mux_init_signal("dss_data22", mux_mode);
omap_mux_init_signal("dss_data23", mux_mode);
}
static void __init cm_t35_init_mux(void)
{
int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT;
omap_mux_init_signal("dss_data0.dss_data0", mux_mode);
omap_mux_init_signal("dss_data1.dss_data1", mux_mode);
omap_mux_init_signal("dss_data2.dss_data2", mux_mode);
omap_mux_init_signal("dss_data3.dss_data3", mux_mode);
omap_mux_init_signal("dss_data4.dss_data4", mux_mode);
omap_mux_init_signal("dss_data5.dss_data5", mux_mode);
cm_t3x_common_dss_mux_init(mux_mode);
}
static void __init cm_t3730_init_mux(void)
{
int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT;
omap_mux_init_signal("sys_boot0", mux_mode);
omap_mux_init_signal("sys_boot1", mux_mode);
omap_mux_init_signal("sys_boot3", mux_mode);
omap_mux_init_signal("sys_boot4", mux_mode);
omap_mux_init_signal("sys_boot5", mux_mode);
omap_mux_init_signal("sys_boot6", mux_mode);
cm_t3x_common_dss_mux_init(mux_mode);
}
#else
static inline void cm_t35_init_mux(void) {}
static inline void cm_t3730_init_mux(void) {}
#endif
static void __init cm_t3x_common_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
omap_serial_init();
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_hsmmc_init(mmc);
cm_t35_init_i2c();
omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
cm_t35_init_ethernet();
cm_t35_init_led();
cm_t35_init_display();
omap_twl4030_audio_init("cm-t3x", NULL);
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
usb_musb_init(NULL);
cm_t35_init_usbh();
cm_t35_init_camera();
}
static void __init cm_t35_init(void)
{
cm_t3x_common_init();
cm_t35_init_mux();
cm_t35_init_nand();
}
static void __init cm_t3730_init(void)
{
cm_t3x_common_init();
cm_t3730_init_mux();
}
MACHINE_START(CM_T35, "Compulab CM-T35")
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
.init_machine = cm_t35_init,
.init_late = omap35xx_init_late,
.init_time = omap3_sync32k_timer_init,
.restart = omap3xxx_restart,
MACHINE_END
MACHINE_START(CM_T3730, "Compulab CM-T3730")
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3630_init_early,
.init_irq = omap3_init_irq,
.init_machine = cm_t3730_init,
.init_late = omap3630_init_late,
.init_time = omap3_sync32k_timer_init,
.restart = omap3xxx_restart,
MACHINE_END
/*
* linux/arch/arm/mach-omap2/board-omap3beagle.c
*
* Copyright (C) 2008 Texas Instruments
*
* Modified from mach-omap2/board-3430sdp.c
*
* Initial code: Syed Mohammed Khasim
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/leds.h>
#include <linux/pwm.h>
#include <linux/leds_pwm.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/pm_opp.h>
#include <linux/cpu.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand.h>
#include <linux/mmc/host.h>
#include <linux/usb/phy.h>
#include <linux/regulator/machine.h>
#include <linux/i2c/twl.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <video/omapdss.h>
#include <video/omap-panel-data.h>
#include <linux/platform_data/mtd-nand-omap2.h>
#include "common.h"
#include "omap_device.h"
#include "gpmc.h"
#include "soc.h"
#include "mux.h"
#include "hsmmc.h"
#include "pm.h"
#include "board-flash.h"
#include "common-board-devices.h"
#define NAND_CS 0
static struct pwm_lookup pwm_lookup[] = {
/* LEDB -> PMU_STAT */
PWM_LOOKUP("twl-pwmled", 1, "leds_pwm", "beagleboard::pmu_stat",
7812500, PWM_POLARITY_NORMAL),
};
static struct led_pwm pwm_leds[] = {
{
.name = "beagleboard::pmu_stat",
.max_brightness = 127,
.pwm_period_ns = 7812500,
},
};
static struct led_pwm_platform_data pwm_data = {
.num_leds = ARRAY_SIZE(pwm_leds),
.leds = pwm_leds,
};
static struct platform_device leds_pwm = {
.name = "leds_pwm",
.id = -1,
.dev = {
.platform_data = &pwm_data,
},
};
/*
* OMAP3 Beagle revision
* Run time detection of Beagle revision is done by reading GPIO.
* GPIO ID -
* AXBX = GPIO173, GPIO172, GPIO171: 1 1 1
* C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0
* C4 = GPIO173, GPIO172, GPIO171: 1 0 1
* XMA/XMB = GPIO173, GPIO172, GPIO171: 0 0 0
* XMC = GPIO173, GPIO172, GPIO171: 0 1 0
*/
enum {
OMAP3BEAGLE_BOARD_UNKN = 0,
OMAP3BEAGLE_BOARD_AXBX,
OMAP3BEAGLE_BOARD_C1_3,
OMAP3BEAGLE_BOARD_C4,
OMAP3BEAGLE_BOARD_XM,
OMAP3BEAGLE_BOARD_XMC,
};
static u8 omap3_beagle_version;
/*
* Board-specific configuration
* Defaults to BeagleBoard-xMC
*/
static struct {
int mmc1_gpio_wp;
bool usb_pwr_level; /* 0 - Active Low, 1 - Active High */
int dvi_pd_gpio;
int usr_button_gpio;
int mmc_caps;
} beagle_config = {
.mmc1_gpio_wp = -EINVAL,
.usb_pwr_level = 0,
.dvi_pd_gpio = -EINVAL,
.usr_button_gpio = 4,
.mmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
};
static struct gpio omap3_beagle_rev_gpios[] __initdata = {
{ 171, GPIOF_IN, "rev_id_0" },
{ 172, GPIOF_IN, "rev_id_1" },
{ 173, GPIOF_IN, "rev_id_2" },
};
static void __init omap3_beagle_init_rev(void)
{
int ret;
u16 beagle_rev = 0;
omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP);
omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP);
omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP);
ret = gpio_request_array(omap3_beagle_rev_gpios,
ARRAY_SIZE(omap3_beagle_rev_gpios));
if (ret < 0) {
printk(KERN_ERR "Unable to get revision detection GPIO pins\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
return;
}
beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1)
| (gpio_get_value(173) << 2);
gpio_free_array(omap3_beagle_rev_gpios,
ARRAY_SIZE(omap3_beagle_rev_gpios));
switch (beagle_rev) {
case 7:
printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX;
beagle_config.mmc1_gpio_wp = 29;
beagle_config.dvi_pd_gpio = 170;
beagle_config.usr_button_gpio = 7;
break;
case 6:
printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3;
beagle_config.mmc1_gpio_wp = 23;
beagle_config.dvi_pd_gpio = 170;
beagle_config.usr_button_gpio = 7;
break;
case 5:
printk(KERN_INFO "OMAP3 Beagle Rev: C4\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_C4;
beagle_config.mmc1_gpio_wp = 23;
beagle_config.dvi_pd_gpio = 170;
beagle_config.usr_button_gpio = 7;
break;
case 0:
printk(KERN_INFO "OMAP3 Beagle Rev: xM Ax/Bx\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
beagle_config.usb_pwr_level = 1;
beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
break;
case 2:
printk(KERN_INFO "OMAP3 Beagle Rev: xM C\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_XMC;
beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
break;
default:
printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
}
}
static struct mtd_partition omap3beagle_nand_partitions[] = {
/* All the partition sizes are listed in terms of NAND block size */
{
.name = "X-Loader",
.offset = 0,
.size = 4 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
{
.name = "U-Boot",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
.size = 15 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
{
.name = "U-Boot Env",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
.size = 1 * NAND_BLOCK_SIZE,
},
{
.name = "Kernel",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
.size = 32 * NAND_BLOCK_SIZE,
},
{
.name = "File System",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
.size = MTDPART_SIZ_FULL,
},
};
/* DSS */
static struct connector_dvi_platform_data beagle_dvi_connector_pdata = {
.name = "dvi",
.source = "tfp410.0",
.i2c_bus_num = 3,
};
static struct platform_device beagle_dvi_connector_device = {
.name = "connector-dvi",
.id = 0,
.dev.platform_data = &beagle_dvi_connector_pdata,
};
static struct encoder_tfp410_platform_data beagle_tfp410_pdata = {
.name = "tfp410.0",
.source = "dpi.0",
.data_lines = 24,
.power_down_gpio = -1,
};
static struct platform_device beagle_tfp410_device = {
.name = "tfp410",
.id = 0,
.dev.platform_data = &beagle_tfp410_pdata,
};
static struct connector_atv_platform_data beagle_tv_pdata = {
.name = "tv",
.source = "venc.0",
.connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
.invert_polarity = false,
};
static struct platform_device beagle_tv_connector_device = {
.name = "connector-analog-tv",
.id = 0,
.dev.platform_data = &beagle_tv_pdata,
};
static struct omap_dss_board_info beagle_dss_data = {
.default_display_name = "dvi",
};
#include "sdram-micron-mt46h32m32lf-6.h"
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_wp = -EINVAL,
.deferred = true,
},
{} /* Terminator */
};
static struct regulator_consumer_supply beagle_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply beagle_vsim_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
static struct gpio_led gpio_leds[];
static struct usbhs_phy_data phy_data[] = {
{
.port = 2,
.reset_gpio = 147,
.vcc_gpio = -1, /* updated in beagle_twl_gpio_setup */
.vcc_polarity = 1, /* updated in beagle_twl_gpio_setup */
},
};
static int beagle_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
int r;
mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap_hsmmc_late_init(mmc);
/*
* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
* high / others active low)
* DVI reset GPIO is different between beagle revisions
*/
/* Valid for all -xM revisions */
if (cpu_is_omap3630()) {
/*
* gpio + 1 on Xm controls the TFP410's enable line (active low)
* gpio + 2 control varies depending on the board rev as below:
* P7/P8 revisions(prototype): Camera EN
* A2+ revisions (production): LDO (DVI, serial, led blocks)
*/
r = gpio_request_one(gpio + 1, GPIOF_OUT_INIT_LOW,
"nDVI_PWR_EN");
if (r)
pr_err("%s: unable to configure nDVI_PWR_EN\n",
__func__);
beagle_config.dvi_pd_gpio = gpio + 2;
} else {
/*
* REVISIT: need ehci-omap hooks for external VBUS
* power switch and overcurrent detect
*/
if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
pr_err("%s: unable to configure EHCI_nOC\n", __func__);
}
beagle_tfp410_pdata.power_down_gpio = beagle_config.dvi_pd_gpio;
platform_device_register(&beagle_tfp410_device);
platform_device_register(&beagle_dvi_connector_device);
platform_device_register(&beagle_tv_connector_device);
/* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */
phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX;
phy_data[0].vcc_polarity = beagle_config.usb_pwr_level;
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
return 0;
}
static struct twl4030_gpio_platform_data beagle_gpio_data = {
.use_leds = true,
.pullups = BIT(1),
.pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
| BIT(15) | BIT(16) | BIT(17),
.setup = beagle_twl_gpio_setup,
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data beagle_vmmc1 = {
.constraints = {
.min_uV = 1850000,
.max_uV = 3150000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(beagle_vmmc1_supply),
.consumer_supplies = beagle_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
static struct regulator_init_data beagle_vsim = {
.constraints = {
.min_uV = 1800000,
.max_uV = 3000000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(beagle_vsim_supply),
.consumer_supplies = beagle_vsim_supply,
};
static struct twl4030_platform_data beagle_twldata = {
/* platform_data for children goes here */
.gpio = &beagle_gpio_data,
.vmmc1 = &beagle_vmmc1,
.vsim = &beagle_vsim,
};
static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
{
I2C_BOARD_INFO("eeprom", 0x50),
},
};
static int __init omap3_beagle_i2c_init(void)
{
omap3_pmic_get_config(&beagle_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
beagle_twldata.vpll2->constraints.name = "VDVI";
omap3_pmic_init("twl4030", &beagle_twldata);
/* Bus 3 is attached to the DVI port where devices like the pico DLP
* projector don't work reliably with 400kHz */
omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom));
return 0;
}
static struct gpio_led gpio_leds[] = {
{
.name = "beagleboard::usr0",
.default_trigger = "heartbeat",
.gpio = 150,
},
{
.name = "beagleboard::usr1",
.default_trigger = "mmc0",
.gpio = 149,
},
};
static struct gpio_led_platform_data gpio_led_info = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct platform_device leds_gpio = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &gpio_led_info,
},
};
static struct gpio_keys_button gpio_buttons[] = {
{
.code = BTN_EXTRA,
/* Dynamically assigned depending on board */
.gpio = -EINVAL,
.desc = "user",
.wakeup = 1,
},
};
static struct gpio_keys_platform_data gpio_key_info = {
.buttons = gpio_buttons,
.nbuttons = ARRAY_SIZE(gpio_buttons),
};
static struct platform_device keys_gpio = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &gpio_key_info,
},
};
static struct platform_device madc_hwmon = {
.name = "twl4030_madc_hwmon",
.id = -1,
};
static struct platform_device *omap3_beagle_devices[] __initdata = {
&leds_gpio,
&keys_gpio,
&madc_hwmon,
&leds_pwm,
};
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
static int __init beagle_opp_init(void)
{
int r = 0;
if (!machine_is_omap3_beagle())
return 0;
/* Initialize the omap3 opp table if not already created. */
r = omap3_opp_init();
if (r < 0 && (r != -EEXIST)) {
pr_err("%s: opp default init failed\n", __func__);
return r;
}
/* Custom OPP enabled for all xM versions */
if (cpu_is_omap3630()) {
struct device *mpu_dev, *iva_dev;
mpu_dev = get_cpu_device(0);
iva_dev = omap_device_get_by_hwmod_name("iva");
if (!mpu_dev || IS_ERR(iva_dev)) {
pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
__func__, mpu_dev, iva_dev);
return -ENODEV;
}
/* Enable MPU 1GHz and lower opps */
r = dev_pm_opp_enable(mpu_dev, 800000000);
/* TODO: MPU 1GHz needs SR and ABB */
/* Enable IVA 800MHz and lower opps */
r |= dev_pm_opp_enable(iva_dev, 660000000);
/* TODO: DSP 800MHz needs SR and ABB */
if (r) {
pr_err("%s: failed to enable higher opp %d\n",
__func__, r);
/*
* Cleanup - disable the higher freqs - we dont care
* about the results
*/
dev_pm_opp_disable(mpu_dev, 800000000);
dev_pm_opp_disable(iva_dev, 660000000);
}
}
return 0;
}
omap_device_initcall(beagle_opp_init);
static void __init omap3_beagle_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3_beagle_init_rev();
if (gpio_is_valid(beagle_config.mmc1_gpio_wp))
omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
mmc[0].caps = beagle_config.mmc_caps;
omap_hsmmc_init(mmc);
omap3_beagle_i2c_init();
gpio_buttons[0].gpio = beagle_config.usr_button_gpio;
platform_add_devices(omap3_beagle_devices,
ARRAY_SIZE(omap3_beagle_devices));
if (gpio_is_valid(beagle_config.dvi_pd_gpio))
omap_mux_init_gpio(beagle_config.dvi_pd_gpio, OMAP_PIN_OUTPUT);
omap_display_init(&beagle_dss_data);
omap_serial_init();
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
usb_musb_init(NULL);
usbhs_init(&usbhs_bdata);
board_nand_init(omap3beagle_nand_partitions,
ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
NAND_BUSWIDTH_16, NULL);
omap_twl4030_audio_init("omap3beagle", NULL);
/* Ensure msecure is mux'd to be able to set the RTC. */
omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup));
}
MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
/* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3_init_early,
.init_irq = omap3_init_irq,
.init_machine = omap3_beagle_init,
.init_late = omap3_init_late,
.init_time = omap3_secure_sync32k_timer_init,
.restart = omap3xxx_restart,
MACHINE_END
/*
* board-overo.c (Gumstix Overo)
*
* Initial code: Steve Sakoman <steve@sakoman.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/i2c/twl.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/spi/spi.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/mmc/host.h>
#include <linux/usb/phy.h>
#include <linux/platform_data/mtd-nand-omap2.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <video/omapdss.h>
#include <video/omap-panel-data.h>
#include "common.h"
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "gpmc.h"
#include "hsmmc.h"
#include "board-flash.h"
#include "common-board-devices.h"
#define NAND_CS 0
#define OVERO_GPIO_BT_XGATE 15
#define OVERO_GPIO_W2W_NRESET 16
#define OVERO_GPIO_PENDOWN 114
#define OVERO_GPIO_BT_NRESET 164
#define OVERO_GPIO_USBH_CPEN 168
#define OVERO_GPIO_USBH_NRESET 183
#define OVERO_SMSC911X_CS 5
#define OVERO_SMSC911X_GPIO 176
#define OVERO_SMSC911X_NRESET 64
#define OVERO_SMSC911X2_CS 4
#define OVERO_SMSC911X2_GPIO 65
/* whether to register LCD35 instead of LCD43 */
static bool overo_use_lcd35;
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
/* fixed regulator for ads7846 */
static struct regulator_consumer_supply ads7846_supply[] = {
REGULATOR_SUPPLY("vcc", "spi1.0"),
};
static struct regulator_init_data vads7846_regulator = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(ads7846_supply),
.consumer_supplies = ads7846_supply,
};
static struct fixed_voltage_config vads7846 = {
.supply_name = "vads7846",
.microvolts = 3300000, /* 3.3V */
.gpio = -EINVAL,
.startup_delay = 0,
.init_data = &vads7846_regulator,
};
static struct platform_device vads7846_device = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &vads7846,
},
};
static void __init overo_ads7846_init(void)
{
omap_ads7846_init(1, OVERO_GPIO_PENDOWN, 0, NULL);
platform_device_register(&vads7846_device);
}
#else
static inline void __init overo_ads7846_init(void) { return; }
#endif
#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
#include <linux/smsc911x.h>
#include "gpmc-smsc911x.h"
static struct omap_smsc911x_platform_data smsc911x_cfg = {
.id = 0,
.cs = OVERO_SMSC911X_CS,
.gpio_irq = OVERO_SMSC911X_GPIO,
.gpio_reset = OVERO_SMSC911X_NRESET,
.flags = SMSC911X_USE_32BIT,
};
static struct omap_smsc911x_platform_data smsc911x2_cfg = {
.id = 1,
.cs = OVERO_SMSC911X2_CS,
.gpio_irq = OVERO_SMSC911X2_GPIO,
.gpio_reset = -EINVAL,
.flags = SMSC911X_USE_32BIT,
};
static void __init overo_init_smsc911x(void)
{
gpmc_smsc911x_init(&smsc911x_cfg);
gpmc_smsc911x_init(&smsc911x2_cfg);
}
#else
static inline void __init overo_init_smsc911x(void) { return; }
#endif
/* DSS */
#define OVERO_GPIO_LCD_EN 144
#define OVERO_GPIO_LCD_BL 145
static struct connector_atv_platform_data overo_tv_pdata = {
.name = "tv",
.source = "venc.0",
.connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
.invert_polarity = false,
};
static struct platform_device overo_tv_connector_device = {
.name = "connector-analog-tv",
.id = 0,
.dev.platform_data = &overo_tv_pdata,
};
static const struct display_timing overo_lcd43_videomode = {
.pixelclock = { 0, 9200000, 0 },
.hactive = { 0, 480, 0 },
.hfront_porch = { 0, 8, 0 },
.hback_porch = { 0, 4, 0 },
.hsync_len = { 0, 41, 0 },
.vactive = { 0, 272, 0 },
.vfront_porch = { 0, 4, 0 },
.vback_porch = { 0, 2, 0 },
.vsync_len = { 0, 10, 0 },
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
};
static struct panel_dpi_platform_data overo_lcd43_pdata = {
.name = "lcd43",
.source = "dpi.0",
.data_lines = 24,
.display_timing = &overo_lcd43_videomode,
.enable_gpio = OVERO_GPIO_LCD_EN,
.backlight_gpio = OVERO_GPIO_LCD_BL,
};
static struct platform_device overo_lcd43_device = {
.name = "panel-dpi",
.id = 0,
.dev.platform_data = &overo_lcd43_pdata,
};
static struct connector_dvi_platform_data overo_dvi_connector_pdata = {
.name = "dvi",
.source = "tfp410.0",
.i2c_bus_num = 3,
};
static struct platform_device overo_dvi_connector_device = {
.name = "connector-dvi",
.id = 0,
.dev.platform_data = &overo_dvi_connector_pdata,
};
static struct encoder_tfp410_platform_data overo_tfp410_pdata = {
.name = "tfp410.0",
.source = "dpi.0",
.data_lines = 24,
.power_down_gpio = -1,
};
static struct platform_device overo_tfp410_device = {
.name = "tfp410",
.id = 0,
.dev.platform_data = &overo_tfp410_pdata,
};
static struct omap_dss_board_info overo_dss_data = {
.default_display_name = "lcd43",
};
static void __init overo_display_init(void)
{
omap_display_init(&overo_dss_data);
if (!overo_use_lcd35)
platform_device_register(&overo_lcd43_device);
platform_device_register(&overo_tfp410_device);
platform_device_register(&overo_dvi_connector_device);
platform_device_register(&overo_tv_connector_device);
}
static struct mtd_partition overo_nand_partitions[] = {
{
.name = "xloader",
.offset = 0, /* Offset = 0x00000 */
.size = 4 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE
},
{
.name = "uboot",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
.size = 14 * NAND_BLOCK_SIZE,
},
{
.name = "uboot environment",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x240000 */
.size = 2 * NAND_BLOCK_SIZE,
},
{
.name = "linux",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
.size = 32 * NAND_BLOCK_SIZE,
},
{
.name = "rootfs",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
.size = MTDPART_SIZ_FULL,
},
};
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
},
{
.mmc = 2,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.transceiver = true,
.ocr_mask = 0x00100000, /* 3.3V */
},
{} /* Terminator */
};
static struct regulator_consumer_supply overo_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
#include <linux/leds.h>
static struct gpio_led gpio_leds[] = {
{
.name = "overo:red:gpio21",
.default_trigger = "heartbeat",
.gpio = 21,
.active_low = true,
},
{
.name = "overo:blue:gpio22",
.default_trigger = "none",
.gpio = 22,
.active_low = true,
},
{
.name = "overo:blue:COM",
.default_trigger = "mmc0",
.gpio = -EINVAL, /* gets replaced */
.active_low = true,
},
};
static struct gpio_led_platform_data gpio_leds_pdata = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct platform_device gpio_leds_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &gpio_leds_pdata,
},
};
static void __init overo_init_led(void)
{
platform_device_register(&gpio_leds_device);
}
#else
static inline void __init overo_init_led(void) { return; }
#endif
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
#include <linux/input.h>
#include <linux/gpio_keys.h>
static struct gpio_keys_button gpio_buttons[] = {
{
.code = BTN_0,
.gpio = 23,
.desc = "button0",
.wakeup = 1,
},
{
.code = BTN_1,
.gpio = 14,
.desc = "button1",
.wakeup = 1,
},
};
static struct gpio_keys_platform_data gpio_keys_pdata = {
.buttons = gpio_buttons,
.nbuttons = ARRAY_SIZE(gpio_buttons),
};
static struct platform_device gpio_keys_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &gpio_keys_pdata,
},
};
static void __init overo_init_keys(void)
{
platform_device_register(&gpio_keys_device);
}
#else
static inline void __init overo_init_keys(void) { return; }
#endif
static int overo_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
#endif
return 0;
}
static struct twl4030_gpio_platform_data overo_gpio_data = {
.use_leds = true,
.setup = overo_twl_gpio_setup,
};
static struct regulator_init_data overo_vmmc1 = {
.constraints = {
.min_uV = 1850000,
.max_uV = 3150000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(overo_vmmc1_supply),
.consumer_supplies = overo_vmmc1_supply,
};
static struct twl4030_platform_data overo_twldata = {
.gpio = &overo_gpio_data,
.vmmc1 = &overo_vmmc1,
};
static int __init overo_i2c_init(void)
{
omap3_pmic_get_config(&overo_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
overo_twldata.vpll2->constraints.name = "VDVI";
omap3_pmic_init("tps65950", &overo_twldata);
/* i2c2 pins are used for gpio */
omap_register_i2c_bus(3, 400, NULL, 0);
return 0;
}
static struct panel_lb035q02_platform_data overo_lcd35_pdata = {
.name = "lcd35",
.source = "dpi.0",
.data_lines = 24,
.enable_gpio = OVERO_GPIO_LCD_EN,
.backlight_gpio = OVERO_GPIO_LCD_BL,
};
/*
* NOTE: We need to add either the lgphilips panel, or the lcd43 panel. The
* selection is done based on the overo_use_lcd35 field. If new SPI
* devices are added here, extra work is needed to make only the lgphilips panel
* affected by the overo_use_lcd35 field.
*/
static struct spi_board_info overo_spi_board_info[] __initdata = {
{
.modalias = "panel_lgphilips_lb035q02",
.bus_num = 1,
.chip_select = 1,
.max_speed_hz = 500000,
.mode = SPI_MODE_3,
.platform_data = &overo_lcd35_pdata,
},
};
static int __init overo_spi_init(void)
{
overo_ads7846_init();
if (overo_use_lcd35) {
spi_register_board_info(overo_spi_board_info,
ARRAY_SIZE(overo_spi_board_info));
}
return 0;
}
static struct usbhs_phy_data phy_data[] __initdata = {
{
.port = 2,
.reset_gpio = OVERO_GPIO_USBH_NRESET,
.vcc_gpio = -EINVAL,
},
};
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
static struct gpio overo_bt_gpios[] __initdata = {
{ OVERO_GPIO_BT_XGATE, GPIOF_OUT_INIT_LOW, "lcd enable" },
{ OVERO_GPIO_BT_NRESET, GPIOF_OUT_INIT_HIGH, "lcd bl enable" },
};
static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
REGULATOR_SUPPLY("vddvario", "smsc911x.1"),
REGULATOR_SUPPLY("vdd33a", "smsc911x.1"),
};
static void __init overo_init(void)
{
int ret;
if (strstr(boot_command_line, "omapdss.def_disp=lcd35"))
overo_use_lcd35 = true;
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
overo_i2c_init();
omap_hsmmc_init(mmc);
omap_serial_init();
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
board_nand_init(overo_nand_partitions,
ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
usb_musb_init(NULL);
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
usbhs_init(&usbhs_bdata);
overo_spi_init();
overo_init_smsc911x();
overo_init_led();
overo_init_keys();
omap_twl4030_audio_init("overo", NULL);
overo_display_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
ret = gpio_request_one(OVERO_GPIO_W2W_NRESET, GPIOF_OUT_INIT_HIGH,
"OVERO_GPIO_W2W_NRESET");
if (ret == 0) {
gpio_export(OVERO_GPIO_W2W_NRESET, 0);
gpio_set_value(OVERO_GPIO_W2W_NRESET, 0);
udelay(10);
gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
} else {
pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n");
}
ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
if (ret) {
pr_err("%s: could not obtain BT gpios\n", __func__);
} else {
gpio_export(OVERO_GPIO_BT_XGATE, 0);
gpio_export(OVERO_GPIO_BT_NRESET, 0);
gpio_set_value(OVERO_GPIO_BT_NRESET, 0);
mdelay(6);
gpio_set_value(OVERO_GPIO_BT_NRESET, 1);
}
ret = gpio_request_one(OVERO_GPIO_USBH_CPEN, GPIOF_OUT_INIT_HIGH,
"OVERO_GPIO_USBH_CPEN");
if (ret == 0)
gpio_export(OVERO_GPIO_USBH_CPEN, 0);
else
pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n");
}
MACHINE_START(OVERO, "Gumstix Overo")
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
.init_machine = overo_init,
.init_late = omap35xx_init_late,
.init_time = omap3_sync32k_timer_init,
.restart = omap3xxx_restart,
MACHINE_END
...@@ -63,7 +63,7 @@ static int __init omap3_l3_init(void) ...@@ -63,7 +63,7 @@ static int __init omap3_l3_init(void)
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
return PTR_RET(pdev); return PTR_ERR_OR_ZERO(pdev);
} }
omap_postcore_initcall(omap3_l3_init); omap_postcore_initcall(omap3_l3_init);
...@@ -333,6 +333,6 @@ static int __init omap_gpmc_init(void) ...@@ -333,6 +333,6 @@ static int __init omap_gpmc_init(void)
pdev = omap_device_build("omap-gpmc", -1, oh, NULL, 0); pdev = omap_device_build("omap-gpmc", -1, oh, NULL, 0);
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
return PTR_RET(pdev); return PTR_ERR_OR_ZERO(pdev);
} }
omap_postcore_initcall(omap_gpmc_init); omap_postcore_initcall(omap_gpmc_init);
...@@ -84,7 +84,7 @@ int __init omap_init_vrfb(void) ...@@ -84,7 +84,7 @@ int __init omap_init_vrfb(void)
pdev = platform_device_register_resndata(NULL, "omapvrfb", -1, pdev = platform_device_register_resndata(NULL, "omapvrfb", -1,
res, num_res, NULL, 0); res, num_res, NULL, 0);
return PTR_RET(pdev); return PTR_ERR_OR_ZERO(pdev);
} }
#else #else
int __init omap_init_vrfb(void) { return 0; } int __init omap_init_vrfb(void) { return 0; }
......
...@@ -216,11 +216,11 @@ static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t, ...@@ -216,11 +216,11 @@ static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
div = gpmc_calc_divider(min_gpmc_clk_period); div = gpmc_calc_divider(min_gpmc_clk_period);
gpmc_clk_ns = gpmc_ticks_to_ns(div); gpmc_clk_ns = gpmc_ticks_to_ns(div);
if (gpmc_clk_ns < 15) /* >66Mhz */ if (gpmc_clk_ns < 15) /* >66MHz */
onenand_flags |= ONENAND_FLAG_HF; onenand_flags |= ONENAND_FLAG_HF;
else else
onenand_flags &= ~ONENAND_FLAG_HF; onenand_flags &= ~ONENAND_FLAG_HF;
if (gpmc_clk_ns < 12) /* >83Mhz */ if (gpmc_clk_ns < 12) /* >83MHz */
onenand_flags |= ONENAND_FLAG_VHF; onenand_flags |= ONENAND_FLAG_VHF;
else else
onenand_flags &= ~ONENAND_FLAG_VHF; onenand_flags &= ~ONENAND_FLAG_VHF;
......
...@@ -70,7 +70,7 @@ static void omap_hsmmc1_before_set_reg(struct device *dev, ...@@ -70,7 +70,7 @@ static void omap_hsmmc1_before_set_reg(struct device *dev,
reg = omap_ctrl_readl(control_pbias_offset); reg = omap_ctrl_readl(control_pbias_offset);
if (cpu_is_omap3630()) { if (cpu_is_omap3630()) {
/* Set MMC I/O to 52Mhz */ /* Set MMC I/O to 52MHz */
prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
......
...@@ -444,7 +444,7 @@ static int wakeupgen_domain_alloc(struct irq_domain *domain, ...@@ -444,7 +444,7 @@ static int wakeupgen_domain_alloc(struct irq_domain *domain,
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args); return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args);
} }
static struct irq_domain_ops wakeupgen_domain_ops = { static const struct irq_domain_ops wakeupgen_domain_ops = {
.xlate = wakeupgen_domain_xlate, .xlate = wakeupgen_domain_xlate,
.alloc = wakeupgen_domain_alloc, .alloc = wakeupgen_domain_alloc,
.free = irq_domain_free_irqs_common, .free = irq_domain_free_irqs_common,
......
...@@ -116,7 +116,7 @@ const struct prcm_config omap2430_rate_table[] = { ...@@ -116,7 +116,7 @@ const struct prcm_config omap2430_rate_table[] = {
RATE_IN_243X}, RATE_IN_243X},
/* PRCM-boot/bypass */ /* PRCM-boot/bypass */
{S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13MHz */
RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
...@@ -124,7 +124,7 @@ const struct prcm_config omap2430_rate_table[] = { ...@@ -124,7 +124,7 @@ const struct prcm_config omap2430_rate_table[] = {
RATE_IN_243X}, RATE_IN_243X},
/* PRCM-boot/bypass */ /* PRCM-boot/bypass */
{S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12MHz */
RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
......
...@@ -55,7 +55,7 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[]) ...@@ -55,7 +55,7 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n", WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
dev_name); dev_name);
return PTR_RET(omap_pmu_dev); return PTR_ERR_OR_ZERO(omap_pmu_dev);
} }
static int __init omap_init_pmu(void) static int __init omap_init_pmu(void)
......
...@@ -164,6 +164,6 @@ void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode) ...@@ -164,6 +164,6 @@ void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
mem_timings.slow_dll_ctrl |= mem_timings.slow_dll_ctrl |=
((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2)); ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
/* 90 degree phase for anything below 133Mhz + disable DLL filter */ /* 90 degree phase for anything below 133MHz + disable DLL filter */
mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
} }
...@@ -203,7 +203,7 @@ static int __init omap_serial_early_init(void) ...@@ -203,7 +203,7 @@ static int __init omap_serial_early_init(void)
if (cmdline_find_option(uart_name)) { if (cmdline_find_option(uart_name)) {
console_uart_id = uart->num; console_uart_id = uart->num;
if (console_loglevel >= 10) { if (console_loglevel >= CONSOLE_LOGLEVEL_DEBUG) {
uart_debug = true; uart_debug = true;
pr_info("%s used as console in debug mode: uart%d clocks will not be gated", pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
uart_name, uart->num); uart_name, uart->num);
......
...@@ -64,7 +64,7 @@ ENTRY(omap242x_sram_ddr_init) ...@@ -64,7 +64,7 @@ ENTRY(omap242x_sram_ddr_init)
mvn r9, #0x4 @ mask to get clear bit2 mvn r9, #0x4 @ mask to get clear bit2
and r10, r10, r9 @ clear bit2 for lock mode. and r10, r10, r9 @ clear bit2 for lock mode.
orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
str r10, [r11] @ commit to DLLA_CTRL str r10, [r11] @ commit to DLLA_CTRL
bl i_dll_wait @ wait for dll to lock bl i_dll_wait @ wait for dll to lock
......
...@@ -64,7 +64,7 @@ ENTRY(omap243x_sram_ddr_init) ...@@ -64,7 +64,7 @@ ENTRY(omap243x_sram_ddr_init)
mvn r9, #0x4 @ mask to get clear bit2 mvn r9, #0x4 @ mask to get clear bit2
and r10, r10, r9 @ clear bit2 for lock mode. and r10, r10, r9 @ clear bit2 for lock mode.
orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
str r10, [r11] @ commit to DLLA_CTRL str r10, [r11] @ commit to DLLA_CTRL
bl i_dll_wait @ wait for dll to lock bl i_dll_wait @ wait for dll to lock
......
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
* ready for them to initialise. * ready for them to initialise.
*/ */
ENTRY(sirfsoc_secondary_startup) ENTRY(sirfsoc_secondary_startup)
bl v7_invalidate_l1
mrc p15, 0, r0, c0, c0, 5 mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15 and r0, r0, #15
adr r4, 1f adr r4, 1f
......
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
static void isp116x_pfm_delay(struct device *dev, int delay) static void isp116x_pfm_delay(struct device *dev, int delay)
{ {
/* 400Mhz PXA2 = 2.5ns / instruction */ /* 400MHz PXA2 = 2.5ns / instruction */
int cyc = delay / 10; int cyc = delay / 10;
......
...@@ -17,4 +17,3 @@ extern char rockchip_secondary_trampoline; ...@@ -17,4 +17,3 @@ extern char rockchip_secondary_trampoline;
extern char rockchip_secondary_trampoline_end; extern char rockchip_secondary_trampoline_end;
extern unsigned long rockchip_boot_fn; extern unsigned long rockchip_boot_fn;
extern void rockchip_secondary_startup(void);
...@@ -15,14 +15,6 @@ ...@@ -15,14 +15,6 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/init.h> #include <linux/init.h>
ENTRY(rockchip_secondary_startup)
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
ldr r1, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r1
beq v7_invalidate_l1
b secondary_startup
ENDPROC(rockchip_secondary_startup)
ENTRY(rockchip_secondary_trampoline) ENTRY(rockchip_secondary_trampoline)
ldr pc, 1f ldr pc, 1f
ENDPROC(rockchip_secondary_trampoline) ENDPROC(rockchip_secondary_trampoline)
......
...@@ -149,8 +149,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, ...@@ -149,8 +149,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
* sram_base_addr + 8: start address for pc * sram_base_addr + 8: start address for pc
* */ * */
udelay(10); udelay(10);
writel(virt_to_phys(rockchip_secondary_startup), writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4); writel(0xDEADBEAF, sram_base_addr + 4);
dsb_sev(); dsb_sev();
} }
...@@ -189,7 +188,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node) ...@@ -189,7 +188,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
} }
/* set the boot function for the sram code */ /* set the boot function for the sram code */
rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup); rockchip_boot_fn = virt_to_phys(secondary_startup);
/* copy the trampoline to sram, that runs during startup of the core */ /* copy the trampoline to sram, that runs during startup of the core */
memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz); memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
......
...@@ -14,7 +14,6 @@ extern void shmobile_smp_sleep(void); ...@@ -14,7 +14,6 @@ extern void shmobile_smp_sleep(void);
extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
unsigned long arg); unsigned long arg);
extern int shmobile_smp_cpu_disable(unsigned int cpu); extern int shmobile_smp_cpu_disable(unsigned int cpu);
extern void shmobile_invalidate_start(void);
extern void shmobile_boot_scu(void); extern void shmobile_boot_scu(void);
extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
extern void shmobile_smp_scu_cpu_die(unsigned int cpu); extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
......
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
* Boot code for secondary CPUs. * Boot code for secondary CPUs.
* *
* First we turn on L1 cache coherency for our CPU. Then we jump to * First we turn on L1 cache coherency for our CPU. Then we jump to
* shmobile_invalidate_start that invalidates the cache and hands over control * secondary_startup that invalidates the cache and hands over control
* to the common ARM startup code. * to the common ARM startup code.
*/ */
ENTRY(shmobile_boot_scu) ENTRY(shmobile_boot_scu)
...@@ -36,7 +36,7 @@ ENTRY(shmobile_boot_scu) ...@@ -36,7 +36,7 @@ ENTRY(shmobile_boot_scu)
bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
str r2, [r0, #8] @ write back str r2, [r0, #8] @ write back
b shmobile_invalidate_start b secondary_startup
ENDPROC(shmobile_boot_scu) ENDPROC(shmobile_boot_scu)
.text .text
......
...@@ -16,13 +16,6 @@ ...@@ -16,13 +16,6 @@
#include <asm/assembler.h> #include <asm/assembler.h>
#include <asm/memory.h> #include <asm/memory.h>
#ifdef CONFIG_SMP
ENTRY(shmobile_invalidate_start)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(shmobile_invalidate_start)
#endif
/* /*
* Reset vector for secondary CPUs. * Reset vector for secondary CPUs.
* This will be mapped at address 0 by SBAR register. * This will be mapped at address 0 by SBAR register.
......
...@@ -133,7 +133,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, ...@@ -133,7 +133,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
{ {
/* For this particular CPU register boot vector */ /* For this particular CPU register boot vector */
shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0); shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
return apmu_wrap(cpu, apmu_power_on); return apmu_wrap(cpu, apmu_power_on);
} }
......
...@@ -31,7 +31,6 @@ ...@@ -31,7 +31,6 @@
#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
extern void socfpga_secondary_startup(void);
extern void __iomem *socfpga_scu_base_addr; extern void __iomem *socfpga_scu_base_addr;
extern void socfpga_init_clocks(void); extern void socfpga_init_clocks(void);
......
...@@ -30,8 +30,3 @@ ENTRY(secondary_trampoline) ...@@ -30,8 +30,3 @@ ENTRY(secondary_trampoline)
1: .long . 1: .long .
.long socfpga_cpu1start_addr .long socfpga_cpu1start_addr
ENTRY(secondary_trampoline_end) ENTRY(secondary_trampoline_end)
ENTRY(socfpga_secondary_startup)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(socfpga_secondary_startup)
...@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
writel(virt_to_phys(socfpga_secondary_startup), writel(virt_to_phys(secondary_startup),
sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)); sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
flush_cache_all(); flush_cache_all();
......
...@@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o ...@@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
ifeq ($(CONFIG_CPU_IDLE),y) ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
endif endif
obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
......
#include <linux/linkage.h>
#include <linux/init.h>
#include "sleep.h"
.section ".text.head", "ax"
ENTRY(tegra_secondary_startup)
check_cpu_part_num 0xc09, r8, r9
bleq v7_invalidate_l1
b secondary_startup
ENDPROC(tegra_secondary_startup)
...@@ -94,7 +94,7 @@ void __init tegra_cpu_reset_handler_init(void) ...@@ -94,7 +94,7 @@ void __init tegra_cpu_reset_handler_init(void)
__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
*((u32 *)cpu_possible_mask); *((u32 *)cpu_possible_mask);
__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
virt_to_phys((void *)tegra_secondary_startup); virt_to_phys((void *)secondary_startup);
#endif #endif
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
......
...@@ -36,7 +36,6 @@ extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE]; ...@@ -36,7 +36,6 @@ extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
void __tegra_cpu_reset_handler_start(void); void __tegra_cpu_reset_handler_start(void);
void __tegra_cpu_reset_handler(void); void __tegra_cpu_reset_handler(void);
void __tegra_cpu_reset_handler_end(void); void __tegra_cpu_reset_handler_end(void);
void tegra_secondary_startup(void);
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
#define tegra_cpu_lp1_mask \ #define tegra_cpu_lp1_mask \
......
...@@ -223,7 +223,7 @@ wfe_war: ...@@ -223,7 +223,7 @@ wfe_war:
b __cpu_reset_again b __cpu_reset_again
/* /*
* 38 nop's, which fills reset of wfe cache line and * 38 nop's, which fills rest of wfe cache line and
* 4 more cachelines with nop * 4 more cachelines with nop
*/ */
.rept 38 .rept 38
......
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h>
#include <asm/hardware/cache-l2x0.h> #include <asm/hardware/cache-l2x0.h>
...@@ -15,7 +16,14 @@ ...@@ -15,7 +16,14 @@
static int __init ux500_l2x0_unlock(void) static int __init ux500_l2x0_unlock(void)
{ {
int i; int i;
void __iomem *l2x0_base = __io_address(U8500_L2CC_BASE); struct device_node *np;
void __iomem *l2x0_base;
np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
l2x0_base = of_iomap(np, 0);
of_node_put(np);
if (!l2x0_base)
return -ENODEV;
/* /*
* Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
...@@ -30,6 +38,7 @@ static int __init ux500_l2x0_unlock(void) ...@@ -30,6 +38,7 @@ static int __init ux500_l2x0_unlock(void)
writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
i * L2X0_LOCKDOWN_STRIDE); i * L2X0_LOCKDOWN_STRIDE);
} }
iounmap(l2x0_base);
return 0; return 0;
} }
......
...@@ -43,60 +43,10 @@ static struct prcmu_pdata db8500_prcmu_pdata = { ...@@ -43,60 +43,10 @@ static struct prcmu_pdata db8500_prcmu_pdata = {
.legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET,
}; };
/* minimum static i/o mapping required to boot U8500 platforms */
static struct map_desc u8500_uart_io_desc[] __initdata = {
__IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
__IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
};
/* U8500 and U9540 common io_desc */
static struct map_desc u8500_common_io_desc[] __initdata = {
/* SCU base also covers GIC CPU BASE and TWD with its 4K page */
__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
__IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
__IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
__IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
__IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
__IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
__IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
__IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
};
/* U8500 IO map specific description */
static struct map_desc u8500_io_desc[] __initdata = {
__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
};
/* U9540 IO map specific description */
static struct map_desc u9540_io_desc[] __initdata = {
__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K),
__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
};
static void __init u8500_map_io(void) static void __init u8500_map_io(void)
{ {
/* debug_ll_io_init();
* Map the UARTs early so that the DEBUG_LL stuff continues to work. ux500_setup_id();
*/
iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
ux500_map_io();
iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
if (cpu_is_ux540_family())
iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
else
iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
} }
/* /*
...@@ -125,14 +75,18 @@ static struct arm_pmu_platdata db8500_pmu_platdata = { ...@@ -125,14 +75,18 @@ static struct arm_pmu_platdata db8500_pmu_platdata = {
static const char *db8500_read_soc_id(void) static const char *db8500_read_soc_id(void)
{ {
void __iomem *uid = __io_address(U8500_BB_UID_BASE); void __iomem *uid;
uid = ioremap(U8500_BB_UID_BASE, 0x20);
if (!uid)
return NULL;
/* Throw these device-specific numbers into the entropy pool */ /* Throw these device-specific numbers into the entropy pool */
add_device_randomness(uid, 0x14); add_device_randomness(uid, 0x14);
return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x", return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
readl((u32 *)uid+0), readl((u32 *)uid+0),
readl((u32 *)uid+1), readl((u32 *)uid+2), readl((u32 *)uid+1), readl((u32 *)uid+2),
readl((u32 *)uid+3), readl((u32 *)uid+4)); readl((u32 *)uid+3), readl((u32 *)uid+4));
iounmap(uid);
} }
static struct device * __init db8500_soc_device_init(void) static struct device * __init db8500_soc_device_init(void)
......
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
#include <linux/stat.h> #include <linux/stat.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_irq.h> #include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/irqchip.h> #include <linux/irqchip.h>
#include <linux/irqchip/arm-gic.h> #include <linux/irqchip/arm-gic.h>
...@@ -52,31 +53,36 @@ void ux500_restart(enum reboot_mode mode, const char *cmd) ...@@ -52,31 +53,36 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
*/ */
void __init ux500_init_irq(void) void __init ux500_init_irq(void)
{ {
struct device_node *np;
struct resource r;
gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND); gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init(); irqchip_init();
np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
of_address_to_resource(np, 0, &r);
of_node_put(np);
if (!r.start) {
pr_err("could not find PRCMU base resource\n");
return;
}
prcmu_early_init(r.start, r.end-r.start);
ux500_pm_init(r.start, r.end-r.start);
/* /*
* Init clocks here so that they are available for system timer * Init clocks here so that they are available for system timer
* initialization. * initialization.
*/ */
if (cpu_is_u8500_family()) { if (cpu_is_u8500_family()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
u8500_of_clk_init(U8500_CLKRST1_BASE, u8500_of_clk_init(U8500_CLKRST1_BASE,
U8500_CLKRST2_BASE, U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE, U8500_CLKRST3_BASE,
U8500_CLKRST5_BASE, U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE); U8500_CLKRST6_BASE);
} else if (cpu_is_u9540()) { } else if (cpu_is_u9540()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE); U8500_CLKRST6_BASE);
} else if (cpu_is_u8540()) { } else if (cpu_is_u8540()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE); U8500_CLKRST6_BASE);
......
...@@ -72,7 +72,7 @@ static unsigned int partnumber(unsigned int asicid) ...@@ -72,7 +72,7 @@ static unsigned int partnumber(unsigned int asicid)
* DB9540 0x413fc090 0xFFFFDBF4 0x009540xx * DB9540 0x413fc090 0xFFFFDBF4 0x009540xx
*/ */
void __init ux500_map_io(void) void __init ux500_setup_id(void)
{ {
unsigned int cpuid = read_cpuid_id(); unsigned int cpuid = read_cpuid_id();
unsigned int asicid = 0; unsigned int asicid = 0;
......
...@@ -16,6 +16,8 @@ ...@@ -16,6 +16,8 @@
#include <linux/device.h> #include <linux/device.h>
#include <linux/smp.h> #include <linux/smp.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
...@@ -26,6 +28,9 @@ ...@@ -26,6 +28,9 @@
#include "db8500-regs.h" #include "db8500-regs.h"
#include "id.h" #include "id.h"
static void __iomem *scu_base;
static void __iomem *backupram;
/* This is called from headsmp.S to wakeup the secondary core */ /* This is called from headsmp.S to wakeup the secondary core */
extern void u8500_secondary_startup(void); extern void u8500_secondary_startup(void);
...@@ -41,16 +46,6 @@ static void write_pen_release(int val) ...@@ -41,16 +46,6 @@ static void write_pen_release(int val)
sync_cache_w(&pen_release); sync_cache_w(&pen_release);
} }
static void __iomem *scu_base_addr(void)
{
if (cpu_is_u8500_family() || cpu_is_ux540_family())
return __io_address(U8500_SCU_BASE);
else
ux500_unknown_soc();
return NULL;
}
static DEFINE_SPINLOCK(boot_lock); static DEFINE_SPINLOCK(boot_lock);
static void ux500_secondary_init(unsigned int cpu) static void ux500_secondary_init(unsigned int cpu)
...@@ -104,13 +99,6 @@ static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -104,13 +99,6 @@ static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
static void __init wakeup_secondary(void) static void __init wakeup_secondary(void)
{ {
void __iomem *backupram;
if (cpu_is_u8500_family() || cpu_is_ux540_family())
backupram = __io_address(U8500_BACKUPRAM0_BASE);
else
ux500_unknown_soc();
/* /*
* write the address of secondary startup into the backup ram register * write the address of secondary startup into the backup ram register
* at offset 0x1FF4, then write the magic number 0xA1FEED01 to the * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
...@@ -135,10 +123,16 @@ static void __init wakeup_secondary(void) ...@@ -135,10 +123,16 @@ static void __init wakeup_secondary(void)
*/ */
static void __init ux500_smp_init_cpus(void) static void __init ux500_smp_init_cpus(void)
{ {
void __iomem *scu_base = scu_base_addr();
unsigned int i, ncores; unsigned int i, ncores;
struct device_node *np;
ncores = scu_base ? scu_get_core_count(scu_base) : 1; np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
scu_base = of_iomap(np, 0);
of_node_put(np);
if (!scu_base)
return;
backupram = ioremap(U8500_BACKUPRAM0_BASE, SZ_8K);
ncores = scu_get_core_count(scu_base);
/* sanity check */ /* sanity check */
if (ncores > nr_cpu_ids) { if (ncores > nr_cpu_ids) {
...@@ -153,8 +147,7 @@ static void __init ux500_smp_init_cpus(void) ...@@ -153,8 +147,7 @@ static void __init ux500_smp_init_cpus(void)
static void __init ux500_smp_prepare_cpus(unsigned int max_cpus) static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
{ {
scu_enable(scu_base);
scu_enable(scu_base_addr());
wakeup_secondary(); wakeup_secondary();
} }
......
...@@ -15,6 +15,8 @@ ...@@ -15,6 +15,8 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/suspend.h> #include <linux/suspend.h>
#include <linux/platform_data/arm-ux500-pm.h> #include <linux/platform_data/arm-ux500-pm.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "db8500-regs.h" #include "db8500-regs.h"
#include "pm_domains.h" #include "pm_domains.h"
...@@ -42,6 +44,7 @@ ...@@ -42,6 +44,7 @@
#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C) #define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C)
static void __iomem *prcmu_base; static void __iomem *prcmu_base;
static void __iomem *dist_base;
/* This function decouple the gic from the prcmu */ /* This function decouple the gic from the prcmu */
int prcmu_gic_decouple(void) int prcmu_gic_decouple(void)
...@@ -88,7 +91,6 @@ bool prcmu_gic_pending_irq(void) ...@@ -88,7 +91,6 @@ bool prcmu_gic_pending_irq(void)
{ {
u32 pr; /* Pending register */ u32 pr; /* Pending register */
u32 er; /* Enable register */ u32 er; /* Enable register */
void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
int i; int i;
/* 5 registers. STI & PPI not skipped */ /* 5 registers. STI & PPI not skipped */
...@@ -143,7 +145,6 @@ bool prcmu_is_cpu_in_wfi(int cpu) ...@@ -143,7 +145,6 @@ bool prcmu_is_cpu_in_wfi(int cpu)
int prcmu_copy_gic_settings(void) int prcmu_copy_gic_settings(void)
{ {
u32 er; /* Enable register */ u32 er; /* Enable register */
void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
int i; int i;
/* We skip the STI and PPI */ /* We skip the STI and PPI */
...@@ -179,11 +180,21 @@ static const struct platform_suspend_ops ux500_suspend_ops = { ...@@ -179,11 +180,21 @@ static const struct platform_suspend_ops ux500_suspend_ops = {
void __init ux500_pm_init(u32 phy_base, u32 size) void __init ux500_pm_init(u32 phy_base, u32 size)
{ {
struct device_node *np;
prcmu_base = ioremap(phy_base, size); prcmu_base = ioremap(phy_base, size);
if (!prcmu_base) { if (!prcmu_base) {
pr_err("could not remap PRCMU for PM functions\n"); pr_err("could not remap PRCMU for PM functions\n");
return; return;
} }
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
dist_base = of_iomap(np, 0);
of_node_put(np);
if (!dist_base) {
pr_err("could not remap GIC dist base for PM functions\n");
return;
}
/* /*
* On watchdog reboot the GIC is in some cases decoupled. * On watchdog reboot the GIC is in some cases decoupled.
* This will make sure that the GIC is correctly configured. * This will make sure that the GIC is correctly configured.
......
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
void ux500_restart(enum reboot_mode mode, const char *cmd); void ux500_restart(enum reboot_mode mode, const char *cmd);
void __init ux500_map_io(void); void __init ux500_setup_id(void);
extern void __init ux500_init_irq(void); extern void __init ux500_init_irq(void);
...@@ -26,20 +26,6 @@ extern struct device *ux500_soc_device_init(const char *soc_id); ...@@ -26,20 +26,6 @@ extern struct device *ux500_soc_device_init(const char *soc_id);
extern void ux500_timer_init(void); extern void ux500_timer_init(void);
#define __IO_DEV_DESC(x, sz) { \
.virtual = IO_ADDRESS(x), \
.pfn = __phys_to_pfn(x), \
.length = sz, \
.type = MT_DEVICE, \
}
#define __MEM_DEV_DESC(x, sz) { \
.virtual = IO_ADDRESS(x), \
.pfn = __phys_to_pfn(x), \
.length = sz, \
.type = MT_MEMORY_RWX, \
}
extern struct smp_operations ux500_smp_ops; extern struct smp_operations ux500_smp_ops;
extern void ux500_cpu_die(unsigned int cpu); extern void ux500_cpu_die(unsigned int cpu);
......
...@@ -17,8 +17,6 @@ ...@@ -17,8 +17,6 @@
#ifndef __MACH_ZYNQ_COMMON_H__ #ifndef __MACH_ZYNQ_COMMON_H__
#define __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__
void zynq_secondary_startup(void);
extern int zynq_slcr_init(void); extern int zynq_slcr_init(void);
extern int zynq_early_slcr_init(void); extern int zynq_early_slcr_init(void);
extern void zynq_slcr_system_reset(void); extern void zynq_slcr_system_reset(void);
......
...@@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump: ...@@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump:
.globl zynq_secondary_trampoline_end .globl zynq_secondary_trampoline_end
zynq_secondary_trampoline_end: zynq_secondary_trampoline_end:
ENDPROC(zynq_secondary_trampoline) ENDPROC(zynq_secondary_trampoline)
ENTRY(zynq_secondary_startup)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(zynq_secondary_startup)
...@@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu) ...@@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu)
} }
EXPORT_SYMBOL(zynq_cpun_start); EXPORT_SYMBOL(zynq_cpun_start);
static int zynq_boot_secondary(unsigned int cpu, static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
struct task_struct *idle)
{ {
return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu); return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
} }
/* /*
......
...@@ -336,7 +336,7 @@ __v7_pj4b_setup: ...@@ -336,7 +336,7 @@ __v7_pj4b_setup:
__v7_setup: __v7_setup:
adr r12, __v7_setup_stack @ the local stack adr r12, __v7_setup_stack @ the local stack
stmia r12, {r0-r5, r7, r9, r11, lr} stmia r12, {r0-r5, r7, r9, r11, lr}
bl v7_flush_dcache_louis bl v7_invalidate_l1
ldmia r12, {r0-r5, r7, r9, r11, lr} ldmia r12, {r0-r5, r7, r9, r11, lr}
mrc p15, 0, r0, c0, c0, 0 @ read main ID register mrc p15, 0, r0, c0, c0, 0 @ read main ID register
......
/*
* Skeleton device tree; the bare minimum needed to boot; just include and
* add a compatible value. The bootloader will typically populate the memory
* node.
*/
/ {
#address-cells = <2>;
#size-cells = <1>;
chosen { };
aliases { };
memory { device_type = "memory"; reg = <0 0 0>; };
};
...@@ -845,7 +845,6 @@ config PATA_AT32 ...@@ -845,7 +845,6 @@ config PATA_AT32
config PATA_AT91 config PATA_AT91
tristate "PATA support for AT91SAM9260" tristate "PATA support for AT91SAM9260"
depends on ARM && SOC_AT91SAM9 depends on ARM && SOC_AT91SAM9
depends on !ARCH_MULTIPLATFORM
help help
This option enables support for IDE devices on the Atmel AT91SAM9260 SoC. This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
......
...@@ -24,11 +24,13 @@ ...@@ -24,11 +24,13 @@
#include <linux/ata.h> #include <linux/ata.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/libata.h> #include <linux/libata.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/atmel-smc.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/ata_platform.h> #include <linux/ata_platform.h>
#include <linux/platform_data/atmel.h> #include <linux/platform_data/atmel.h>
#include <linux/regmap.h>
#include <mach/at91sam9_smc.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#define DRV_NAME "pata_at91" #define DRV_NAME "pata_at91"
...@@ -57,6 +59,15 @@ struct smc_range { ...@@ -57,6 +59,15 @@ struct smc_range {
int max; int max;
}; };
struct regmap *smc;
struct at91sam9_smc_generic_fields {
struct regmap_field *setup;
struct regmap_field *pulse;
struct regmap_field *cycle;
struct regmap_field *mode;
} fields;
/** /**
* adjust_smc_value - adjust value for one of SMC registers. * adjust_smc_value - adjust value for one of SMC registers.
* @value: adjusted value * @value: adjusted value
...@@ -206,7 +217,6 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev, ...@@ -206,7 +217,6 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev,
{ {
int ret = 0; int ret = 0;
int use_iordy; int use_iordy;
struct sam9_smc_config smc;
unsigned int t6z; /* data tristate time in ns */ unsigned int t6z; /* data tristate time in ns */
unsigned int cycle; /* SMC Cycle width in MCK ticks */ unsigned int cycle; /* SMC Cycle width in MCK ticks */
unsigned int setup; /* SMC Setup width in MCK ticks */ unsigned int setup; /* SMC Setup width in MCK ticks */
...@@ -244,19 +254,21 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev, ...@@ -244,19 +254,21 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev,
dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles); dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
/* SMC Setup Register */ regmap_fields_write(fields.setup, info->cs,
smc.nwe_setup = smc.nrd_setup = setup; AT91SAM9_SMC_NRDSETUP(setup) |
smc.ncs_write_setup = smc.ncs_read_setup = 0; AT91SAM9_SMC_NWESETUP(setup) |
/* SMC Pulse Register */ AT91SAM9_SMC_NCS_NRDSETUP(0) |
smc.nwe_pulse = smc.nrd_pulse = pulse; AT91SAM9_SMC_NCS_WRSETUP(0));
smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse; regmap_fields_write(fields.pulse, info->cs,
/* SMC Cycle Register */ AT91SAM9_SMC_NRDPULSE(pulse) |
smc.write_cycle = smc.read_cycle = cycle; AT91SAM9_SMC_NWEPULSE(pulse) |
/* SMC Mode Register*/ AT91SAM9_SMC_NCS_NRDPULSE(cs_pulse) |
smc.tdf_cycles = tdf_cycles; AT91SAM9_SMC_NCS_WRPULSE(cs_pulse));
smc.mode = info->mode; regmap_fields_write(fields.cycle, info->cs,
AT91SAM9_SMC_NRDCYCLE(cycle) |
sam9_smc_configure(0, info->cs, &smc); AT91SAM9_SMC_NWECYCLE(cycle));
regmap_fields_write(fields.mode, info->cs, info->mode |
AT91_SMC_TDF_(tdf_cycles));
} }
static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev) static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
...@@ -280,21 +292,21 @@ static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev, ...@@ -280,21 +292,21 @@ static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
{ {
struct at91_ide_info *info = dev->link->ap->host->private_data; struct at91_ide_info *info = dev->link->ap->host->private_data;
unsigned int consumed; unsigned int consumed;
unsigned int mode;
unsigned long flags; unsigned long flags;
struct sam9_smc_config smc;
local_irq_save(flags); local_irq_save(flags);
sam9_smc_read_mode(0, info->cs, &smc); regmap_fields_read(fields.mode, info->cs, &mode);
/* set 16bit mode before writing data */ /* set 16bit mode before writing data */
smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16; regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
sam9_smc_write_mode(0, info->cs, &smc); AT91_SMC_DBW_16);
consumed = ata_sff_data_xfer(dev, buf, buflen, rw); consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
/* restore 8bit mode after data is written */ /* restore 8bit mode after data is written */
smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8; regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
sam9_smc_write_mode(0, info->cs, &smc); AT91_SMC_DBW_8);
local_irq_restore(flags); local_irq_restore(flags);
return consumed; return consumed;
...@@ -312,6 +324,36 @@ static struct ata_port_operations pata_at91_port_ops = { ...@@ -312,6 +324,36 @@ static struct ata_port_operations pata_at91_port_ops = {
.cable_detect = ata_cable_40wire, .cable_detect = ata_cable_40wire,
}; };
static int at91sam9_smc_fields_init(struct device *dev)
{
struct reg_field field = REG_FIELD(0, 0, 31);
field.id_size = 8;
field.id_offset = AT91SAM9_SMC_GENERIC_BLK_SZ;
field.reg = AT91SAM9_SMC_SETUP(AT91SAM9_SMC_GENERIC);
fields.setup = devm_regmap_field_alloc(dev, smc, field);
if (IS_ERR(fields.setup))
return PTR_ERR(fields.setup);
field.reg = AT91SAM9_SMC_PULSE(AT91SAM9_SMC_GENERIC);
fields.pulse = devm_regmap_field_alloc(dev, smc, field);
if (IS_ERR(fields.pulse))
return PTR_ERR(fields.pulse);
field.reg = AT91SAM9_SMC_CYCLE(AT91SAM9_SMC_GENERIC);
fields.cycle = devm_regmap_field_alloc(dev, smc, field);
if (IS_ERR(fields.cycle))
return PTR_ERR(fields.cycle);
field.reg = AT91SAM9_SMC_MODE(AT91SAM9_SMC_GENERIC);
fields.mode = devm_regmap_field_alloc(dev, smc, field);
if (IS_ERR(fields.mode))
return PTR_ERR(fields.mode);
return 0;
}
static int pata_at91_probe(struct platform_device *pdev) static int pata_at91_probe(struct platform_device *pdev)
{ {
struct at91_cf_data *board = dev_get_platdata(&pdev->dev); struct at91_cf_data *board = dev_get_platdata(&pdev->dev);
...@@ -341,6 +383,14 @@ static int pata_at91_probe(struct platform_device *pdev) ...@@ -341,6 +383,14 @@ static int pata_at91_probe(struct platform_device *pdev)
irq = board->irq_pin; irq = board->irq_pin;
smc = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "atmel,smc");
if (IS_ERR(smc))
return PTR_ERR(smc);
ret = at91sam9_smc_fields_init(dev);
if (ret < 0)
return ret;
/* init ata host */ /* init ata host */
host = ata_host_alloc(dev, 1); host = ata_host_alloc(dev, 1);
......
...@@ -277,7 +277,6 @@ config AT91_CF ...@@ -277,7 +277,6 @@ config AT91_CF
tristate "AT91 CompactFlash Controller" tristate "AT91 CompactFlash Controller"
depends on PCI depends on PCI
depends on PCMCIA && ARCH_AT91 depends on PCMCIA && ARCH_AT91
depends on !ARCH_MULTIPLATFORM
help help
Say Y here to support the CompactFlash controller on AT91 chips. Say Y here to support the CompactFlash controller on AT91 chips.
Or choose M to compile the driver as a module named "at91_cf". Or choose M to compile the driver as a module named "at91_cf".
......
...@@ -20,16 +20,15 @@ ...@@ -20,16 +20,15 @@
#include <linux/platform_data/atmel.h> #include <linux/platform_data/atmel.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/sizes.h> #include <linux/sizes.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/atmel-mc.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/of_gpio.h> #include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <pcmcia/ss.h> #include <pcmcia/ss.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
/* /*
* A0..A10 work in each range; A23 indicates I/O space; A25 is CFRNW; * A0..A10 work in each range; A23 indicates I/O space; A25 is CFRNW;
* some other bit in {A24,A22..A11} is nREG to flag memory access * some other bit in {A24,A22..A11} is nREG to flag memory access
...@@ -40,6 +39,8 @@ ...@@ -40,6 +39,8 @@
#define CF_IO_PHYS (1 << 23) #define CF_IO_PHYS (1 << 23)
#define CF_MEM_PHYS (0x017ff800) #define CF_MEM_PHYS (0x017ff800)
struct regmap *mc;
/*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/
struct at91_cf_socket { struct at91_cf_socket {
...@@ -155,10 +156,7 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io) ...@@ -155,10 +156,7 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
/* /*
* Use 16 bit accesses unless/until we need 8-bit i/o space. * Use 16 bit accesses unless/until we need 8-bit i/o space.
*/ *
csr = at91_ramc_read(0, AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
/*
* NOTE: this CF controller ignores IOIS16, so we can't really do * NOTE: this CF controller ignores IOIS16, so we can't really do
* MAP_AUTOSZ. The 16bit mode allows single byte access on either * MAP_AUTOSZ. The 16bit mode allows single byte access on either
* D0-D7 (even addr) or D8-D15 (odd), so it's close enough for many * D0-D7 (even addr) or D8-D15 (odd), so it's close enough for many
...@@ -169,13 +167,14 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io) ...@@ -169,13 +167,14 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
* CF 3.0 spec table 35 also giving the D8-D15 option. * CF 3.0 spec table 35 also giving the D8-D15 option.
*/ */
if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) { if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) {
csr |= AT91_SMC_DBW_8; csr = AT91_MC_SMC_DBW_8;
dev_dbg(&cf->pdev->dev, "8bit i/o bus\n"); dev_dbg(&cf->pdev->dev, "8bit i/o bus\n");
} else { } else {
csr |= AT91_SMC_DBW_16; csr = AT91_MC_SMC_DBW_16;
dev_dbg(&cf->pdev->dev, "16bit i/o bus\n"); dev_dbg(&cf->pdev->dev, "16bit i/o bus\n");
} }
at91_ramc_write(0, AT91_SMC_CSR(cf->board->chipselect), csr); regmap_update_bits(mc, AT91_MC_SMC_CSR(cf->board->chipselect),
AT91_MC_SMC_DBW, csr);
io->start = cf->socket.io_offset; io->start = cf->socket.io_offset;
io->stop = io->start + SZ_2K - 1; io->stop = io->start + SZ_2K - 1;
...@@ -236,6 +235,10 @@ static int at91_cf_dt_init(struct platform_device *pdev) ...@@ -236,6 +235,10 @@ static int at91_cf_dt_init(struct platform_device *pdev)
pdev->dev.platform_data = board; pdev->dev.platform_data = board;
mc = syscon_regmap_lookup_by_compatible("atmel,at91rm9200-sdramc");
if (IS_ERR(mc))
return PTR_ERR(mc);
return 0; return 0;
} }
#else #else
......
/*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
* registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
#define _LINUX_MFD_SYSCON_ATMEL_MC_H_
/* Memory Controller */
#define AT91_MC_RCR 0x00
#define AT91_MC_RCB BIT(0)
#define AT91_MC_ASR 0x04
#define AT91_MC_UNADD BIT(0)
#define AT91_MC_MISADD BIT(1)
#define AT91_MC_ABTSZ GENMASK(9, 8)
#define AT91_MC_ABTSZ_BYTE (0 << 8)
#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
#define AT91_MC_ABTSZ_WORD (2 << 8)
#define AT91_MC_ABTTYP GENMASK(11, 10)
#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
#define AT91_MC_ABTTYP_FETCH (2 << 10)
#define AT91_MC_MST(n) BIT(16 + (n))
#define AT91_MC_SVMST(n) BIT(24 + (n))
#define AT91_MC_AASR 0x08
#define AT91_MC_MPR 0x0c
#define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
/* External Bus Interface (EBI) registers */
#define AT91_MC_EBI_CSA 0x60
#define AT91_MC_EBI_CS(n) BIT(x)
#define AT91_MC_EBI_NUM_CS 8
#define AT91_MC_EBI_CFGR 0x64
#define AT91_MC_EBI_DBPUC BIT(0)
/* Static Memory Controller (SMC) registers */
#define AT91_MC_SMC_CSR(n) (0x70 + ((n) * 4))
#define AT91_MC_SMC_NWS GENMASK(6, 0)
#define AT91_MC_SMC_NWS_(x) ((x) << 0)
#define AT91_MC_SMC_WSEN BIT(7)
#define AT91_MC_SMC_TDF GENMASK(11, 8)
#define AT91_MC_SMC_TDF_(x) ((x) << 8)
#define AT91_MC_SMC_TDF_MAX 0xf
#define AT91_MC_SMC_BAT BIT(12)
#define AT91_MC_SMC_DBW GENMASK(14, 13)
#define AT91_MC_SMC_DBW_16 (1 << 13)
#define AT91_MC_SMC_DBW_8 (2 << 13)
#define AT91_MC_SMC_DPR BIT(15)
#define AT91_MC_SMC_ACSS GENMASK(17, 16)
#define AT91_MC_SMC_ACSS_(x) ((x) << 16)
#define AT91_MC_SMC_ACSS_MAX 3
#define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
#define AT91_MC_SMC_RWSETUP_(x) ((x) << 24)
#define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
#define AT91_MC_SMC_RWHOLD_(x) ((x) << 28)
#define AT91_MC_SMC_RWHOLDSETUP_MAX 7
/* SDRAM Controller registers */
#define AT91_MC_SDRAMC_MR 0x90
#define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
#define AT91_MC_SDRAMC_MODE_NORMAL (0 << 0)
#define AT91_MC_SDRAMC_MODE_NOP (1 << 0)
#define AT91_MC_SDRAMC_MODE_PRECHARGE (2 << 0)
#define AT91_MC_SDRAMC_MODE_LMR (3 << 0)
#define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0)
#define AT91_MC_SDRAMC_DBW_16 BIT(4)
#define AT91_MC_SDRAMC_TR 0x94
#define AT91_MC_SDRAMC_COUNT GENMASK(11, 0)
#define AT91_MC_SDRAMC_CR 0x98
#define AT91_MC_SDRAMC_NC GENMASK(1, 0)
#define AT91_MC_SDRAMC_NC_8 (0 << 0)
#define AT91_MC_SDRAMC_NC_9 (1 << 0)
#define AT91_MC_SDRAMC_NC_10 (2 << 0)
#define AT91_MC_SDRAMC_NC_11 (3 << 0)
#define AT91_MC_SDRAMC_NR GENMASK(3, 2)
#define AT91_MC_SDRAMC_NR_11 (0 << 2)
#define AT91_MC_SDRAMC_NR_12 (1 << 2)
#define AT91_MC_SDRAMC_NR_13 (2 << 2)
#define AT91_MC_SDRAMC_NB BIT(4)
#define AT91_MC_SDRAMC_NB_2 (0 << 4)
#define AT91_MC_SDRAMC_NB_4 (1 << 4)
#define AT91_MC_SDRAMC_CAS GENMASK(6, 5)
#define AT91_MC_SDRAMC_CAS_2 (2 << 5)
#define AT91_MC_SDRAMC_TWR GENMASK(10, 7)
#define AT91_MC_SDRAMC_TRC GENMASK(14, 11)
#define AT91_MC_SDRAMC_TRP GENMASK(18, 15)
#define AT91_MC_SDRAMC_TRCD GENMASK(22, 19)
#define AT91_MC_SDRAMC_TRAS GENMASK(26, 23)
#define AT91_MC_SDRAMC_TXSR GENMASK(30, 27)
#define AT91_MC_SDRAMC_SRR 0x9c
#define AT91_MC_SDRAMC_SRCB BIT(0)
#define AT91_MC_SDRAMC_LPR 0xa0
#define AT91_MC_SDRAMC_LPCB BIT(0)
#define AT91_MC_SDRAMC_IER 0xa4
#define AT91_MC_SDRAMC_IDR 0xa8
#define AT91_MC_SDRAMC_IMR 0xac
#define AT91_MC_SDRAMC_ISR 0xb0
#define AT91_MC_SDRAMC_RES BIT(0)
/* Burst Flash Controller register */
#define AT91_MC_BFC_MR 0xc0
#define AT91_MC_BFC_BFCOM GENMASK(1, 0)
#define AT91_MC_BFC_BFCOM_DISABLED (0 << 0)
#define AT91_MC_BFC_BFCOM_ASYNC (1 << 0)
#define AT91_MC_BFC_BFCOM_BURST (2 << 0)
#define AT91_MC_BFC_BFCC GENMASK(3, 2)
#define AT91_MC_BFC_BFCC_MCK (1 << 2)
#define AT91_MC_BFC_BFCC_DIV2 (2 << 2)
#define AT91_MC_BFC_BFCC_DIV4 (3 << 2)
#define AT91_MC_BFC_AVL GENMASK(7, 4)
#define AT91_MC_BFC_PAGES GENMASK(10, 8)
#define AT91_MC_BFC_PAGES_NO_PAGE (0 << 8)
#define AT91_MC_BFC_PAGES_16 (1 << 8)
#define AT91_MC_BFC_PAGES_32 (2 << 8)
#define AT91_MC_BFC_PAGES_64 (3 << 8)
#define AT91_MC_BFC_PAGES_128 (4 << 8)
#define AT91_MC_BFC_PAGES_256 (5 << 8)
#define AT91_MC_BFC_PAGES_512 (6 << 8)
#define AT91_MC_BFC_PAGES_1024 (7 << 8)
#define AT91_MC_BFC_OEL GENMASK(13, 12)
#define AT91_MC_BFC_BAAEN BIT(16)
#define AT91_MC_BFC_BFOEH BIT(17)
#define AT91_MC_BFC_MUXEN BIT(18)
#define AT91_MC_BFC_RDYEN BIT(19)
#endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */
/*
* arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Memory Controllers (SDRAMC only) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_SDRAMC_H
#define AT91RM9200_SDRAMC_H
/* SDRAM Controller registers */
#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
#endif
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