Commit c1d8b082 authored by Alexandre Belloni's avatar Alexandre Belloni Committed by Mark Brown

spi: dw-mmio: avoid hardcoded field mask

Define a mask for the IF_SI_OWNER field.
Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 6e249d1e
...@@ -36,6 +36,7 @@ struct dw_spi_mmio { ...@@ -36,6 +36,7 @@ struct dw_spi_mmio {
#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
#define OCELOT_IF_SI_OWNER_OFFSET 4 #define OCELOT_IF_SI_OWNER_OFFSET 4
#define JAGUAR2_IF_SI_OWNER_OFFSET 6 #define JAGUAR2_IF_SI_OWNER_OFFSET 6
#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
#define MSCC_IF_SI_OWNER_SISL 0 #define MSCC_IF_SI_OWNER_SISL 0
#define MSCC_IF_SI_OWNER_SIBM 1 #define MSCC_IF_SI_OWNER_SIBM 1
#define MSCC_IF_SI_OWNER_SIMC 2 #define MSCC_IF_SI_OWNER_SIMC 2
...@@ -102,7 +103,7 @@ static int dw_spi_mscc_init(struct platform_device *pdev, ...@@ -102,7 +103,7 @@ static int dw_spi_mscc_init(struct platform_device *pdev,
/* Select the owner of the SI interface */ /* Select the owner of the SI interface */
regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL, regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
0x3 << if_si_owner_offset, MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset); MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
dwsmmio->dws.set_cs = dw_spi_mscc_set_cs; dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
......
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