Commit c27989cc authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Greg Kroah-Hartman

dt-bindings: switch Exynos EHCI/OHCI bindings to use array of generic PHYs

Commit 69bec725 ("USB: core: let USB device know device node") added
support for attaching devicetree node for USB devices. Those nodes are
children of their USB host controller. However Exynos EHCI and OHCI
driver bindings already define child-nodes for each physical root hub
port and assigns respective PHY controller and parameters to them. This
leads to the conflict. A workaround for it has been merged as commit
01d40714 ("usb: exynos: add workaround for the USB device bindings
conflict"), but it disabled support for USB device binding for Exynos
EHCI/OHCI controllers.

To resolve it properly, lets move PHYs from the sub-nodes to a standard
array under the 'phys' property.
Suggested-by: default avatarMåns Rullgård <mans@mansr.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20190726081453.9456-2-m.szyprowski@samsung.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 2a0f4f16
...@@ -12,13 +12,11 @@ Required properties: ...@@ -12,13 +12,11 @@ Required properties:
- interrupts: interrupt number to the cpu. - interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock. - clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost". - clock-names: from common clock binding: Shall be "usbhost".
- port: if in the SoC there are EHCI phys, they should be listed here. - phys: from the *Generic PHY* bindings; array specifying phy(s) used
One phy per port. Each port should have following entries: by the root port.
- reg: port number on EHCI controller, e.g - phy-names: from the *Generic PHY* bindings; array of the names for
On Exynos5250, port 0 is USB2.0 otg phy each phy for the root ports, must be a subset of the following:
port 1 is HSIC phy0 "host", "hsic0", "hsic1".
port 2 is HSIC phy1
- phys: from the *Generic PHY* bindings; specifying phy used by port.
Optional properties: Optional properties:
- samsung,vbus-gpio: if present, specifies the GPIO that - samsung,vbus-gpio: if present, specifies the GPIO that
...@@ -35,12 +33,8 @@ Example: ...@@ -35,12 +33,8 @@ Example:
clocks = <&clock 285>; clocks = <&clock 285>;
clock-names = "usbhost"; clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2phy 1>; phys = <&usb2phy 1>;
}; phy-names = "host";
}; };
OHCI OHCI
...@@ -52,13 +46,11 @@ Required properties: ...@@ -52,13 +46,11 @@ Required properties:
- interrupts: interrupt number to the cpu. - interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock. - clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost". - clock-names: from common clock binding: Shall be "usbhost".
- port: if in the SoC there are OHCI phys, they should be listed here. - phys: from the *Generic PHY* bindings; array specifying phy(s) used
One phy per port. Each port should have following entries: by the root port.
- reg: port number on OHCI controller, e.g - phy-names: from the *Generic PHY* bindings; array of the names for
On Exynos5250, port 0 is USB2.0 otg phy each phy for the root ports, must be a subset of the following:
port 1 is HSIC phy0 "host", "hsic0", "hsic1".
port 2 is HSIC phy1
- phys: from the *Generic PHY* bindings, specifying phy used by port.
Example: Example:
usb@12120000 { usb@12120000 {
...@@ -69,13 +61,8 @@ Example: ...@@ -69,13 +61,8 @@ Example:
clocks = <&clock 285>; clocks = <&clock 285>;
clock-names = "usbhost"; clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2phy 1>; phys = <&usb2phy 1>;
}; phy-names = "host";
}; };
DWC3 DWC3
......
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