Commit c82dd884 authored by Chris Wilson's avatar Chris Wilson

Revert "drm/i915/fbc: Allow on unfenced surfaces, for recent gen"

This reverts commit 8678fdaf ("drm/i915/fbc: Allow on unfenced surfaces,
for recent gen") as Skylake has issues with unfenced FBC tracking (and
yes Skylake doesn't even enable FBC yet). Paulo would like to do a full
review of all existing workarounds to see if any more are missing prior
to allowing FBC on unfenced surfaces. In the meantime lets hope that all
framebuffers are idle and naturally fit within the mappable aperture.
Requested-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Fixes: 8678fdaf ("drm/i915/fbc: Allow on unfenced surfaces...");
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160824180053.24239-1-chris@chris-wilson.co.ukSigned-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 38cb2eca
...@@ -799,11 +799,9 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) ...@@ -799,11 +799,9 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
*/ */
if (cache->fb.tiling_mode != I915_TILING_X || if (cache->fb.tiling_mode != I915_TILING_X ||
cache->fb.fence_reg == I915_FENCE_REG_NONE) { cache->fb.fence_reg == I915_FENCE_REG_NONE) {
if (INTEL_GEN(dev_priv) < 5) {
fbc->no_fbc_reason = "framebuffer not tiled or fenced"; fbc->no_fbc_reason = "framebuffer not tiled or fenced";
return false; return false;
} }
}
if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
cache->plane.rotation != DRM_ROTATE_0) { cache->plane.rotation != DRM_ROTATE_0) {
fbc->no_fbc_reason = "rotation unsupported"; fbc->no_fbc_reason = "rotation unsupported";
......
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