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Commit c9bef4a6 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "We have no core changes but lots of incremental development in drivers
  all over the place: Renesas, NXP, Mediatek and Actions Semiconductor
  keep churning out new SoCs.

  I have some subtree maintainers for Renesas and Intel helping out to
  keep down the load, it's been working smoothly (Samsung also have a
  subtree but it was not used this cycle.)

  New drivers:

   - NXP (ex Freescale) i.MX 8 QXP SoC driver.

   - Mediatek MT6797 SoC driver.

   - Mediatek MT7629 SoC driver.

   - Actions Semiconductor S700 SoC driver.

   - Renesas RZ/A2 SoC driver.

   - Allwinner sunxi suniv F1C100 SoC driver.

   - Qualcomm PMS405 PMIC driver.

   - Microsemi Ocelot Jaguar2 SoC driver.

  Improvements:

   - Some RT improvements (using raw spinlocks where appropriate).

   - A lot of new pin sets on the Renesas PFC pin controllers.

   - GPIO hogs now work on the Qualcomm SPMI/SSBI pin controller GPIO
     chips, and Xway.

   - Major modernization of the Intel pin control drivers.

   - STM32 pin control driver will now synchronize usage of pins with
     another CPU using a hardware spinlock"

* tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (145 commits)
  dt-bindings: arm: fsl-scu: add imx8qm pinctrl support
  pinctrl: freescale: Break dependency on SOC_IMX8MQ for i.MX8MQ
  pinctrl: imx-scu: Depend on IMX_SCU
  pinctrl: ocelot: Add dependency on HAS_IOMEM
  pinctrl: ocelot: add MSCC Jaguar2 support
  pinctrl: bcm: ns: support updated DT binding as syscon subnode
  dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon
  MAINTAINERS: merge at91 pinctrl entries
  pinctrl: imx8qxp: break the dependency on SOC_IMX8QXP
  pinctrl: uniphier: constify uniphier_pinctrl_socdata
  pinctrl: mediatek: improve Kconfig dependencies
  pinctrl: msm: mark PM functions as __maybe_unused
  dt-bindings: pinctrl: sunxi: Add supply properties
  pinctrl: meson: meson8b: add the missing GPIO_GROUPs for BOOT and CARD
  pinctrl: meson: meson8: add the missing GPIO_GROUPs for BOOT and CARD
  pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
  pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
  pinctrl: meson: meson8b: fix the GPIO function for the GPIOAO pins
  pinctrl: meson: meson8: fix the GPIO function for the GPIOAO pins
  pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
  ...
parents 115502a6 88cc9fc4
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Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
View file @ c9bef4a6
......@@ -88,13 +88,16 @@ Pinctrl bindings based on SCU Message Protocol
This binding uses the i.MX common pinctrl binding[3].
Required properties:
- compatible: Should be "fsl,imx8qxp-iomuxc".
- compatible: Should be one of:
"fsl,imx8qm-iomuxc",
"fsl,imx8qxp-iomuxc".
Required properties for Pinctrl sub nodes:
- fsl,pins: Each entry consists of 3 integers which represents
the mux and config setting for one pin. The first 2
integers <pin_id mux_mode> are specified using a
PIN_FUNC_ID macro, which can be found in
<dt-bindings/pinctrl/pads-imx8qm.h>,
<dt-bindings/pinctrl/pads-imx8qxp.h>.
The last integer CONFIG is the pad setting value like
pull-up on this pin.
......
Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt 0 → 100644
View file @ c9bef4a6
Actions Semi S700 Pin Controller
This binding describes the pin controller found in the S700 SoC.
Required Properties:
- compatible: Should be "actions,s700-pinctrl"
- reg: Should contain the register base address and size of
the pin controller.
- clocks: phandle of the clock feeding the pin controller
- gpio-controller: Marks the device node as a GPIO controller.
- gpio-ranges: Specifies the mapping between gpio controller and
pin-controller pins.
- #gpio-cells: Should be two. The first cell is the gpio pin number
and the second cell is used for optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt. Shall be set to 2. The first cell
defines the interrupt number, the second encodes
the trigger flags described in
bindings/interrupt-controller/interrupts.txt
- interrupts: The interrupt outputs from the controller. There is one GPIO
interrupt per GPIO bank. The number of interrupts listed depends
on the number of GPIO banks on the SoC. The interrupts must be
ordered by bank, starting with bank 0.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
Pinmux functions are available only for the pin groups while pinconf
parameters are available for both pin groups and individual pins.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
Required Properties:
- pins: An array of strings, each string containing the name of a pin.
These pins are used for selecting the pull control and schmitt
trigger parameters. The following are the list of pins
available:
eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer,
eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk,
eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2,
ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp,
lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap,
lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18,
lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn,
dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2,
sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk,
sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx,
uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,
uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk,
i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1,
csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2,
dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb,
dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0,
dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2,
dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3
- groups: An array of strings, each string containing the name of a pin
group. These pin groups are used for selecting the pinmux
functions.
rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp,
rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp,
rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp,
i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp,
i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp,
ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp,
lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp,
dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp,
uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp,
sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp,
i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp,
pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp,
nand_ceb2_mfp, nand_ceb3_mfp
These pin groups are used for selecting the drive strength
parameters.
sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv,
rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv,
smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv,
pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv,
dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv,
uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv,
sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv
- function: An array of strings, each string containing the name of the
pinmux functions. These functions can only be selected by
the corresponding pin groups. The following are the list of
pinmux functions available:
nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1,
uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0,
sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30,
clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0
Optional Properties:
- bias-pull-down: No arguments. The specified pins should be configured as
pull down.
- bias-pull-up: No arguments. The specified pins should be configured as
pull up.
- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
pins
- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
pins
- drive-strength: Integer. Selects the drive strength for the specified
pins in mA.
Valid values are:
<2>
<4>
<8>
<12>
Example:
pinctrl: pinctrl@e01b0000 {
compatible = "actions,s700-pinctrl";
reg = <0x0 0xe01b0000 0x0 0x1000>;
clocks = <&cmu CLK_GPIO>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 136>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
uart3-default: uart3-default {
pinmux {
groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp";
function = "uart3";
};
pinconf {
groups = "uart3_all_drv";
drive-strength = <2>;
};
};
};
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
View file @ c9bef4a6
......@@ -29,6 +29,7 @@ Required properties:
"allwinner,sun50i-h5-pinctrl"
"allwinner,sun50i-h6-pinctrl"
"allwinner,sun50i-h6-r-pinctrl"
"allwinner,suniv-f1c100s-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
......@@ -43,6 +44,19 @@ Note: For backward compatibility reasons, the hosc and losc clocks are only
required if you need to use the optional input-debounce property. Any new
device tree should set them.
Each pin bank, depending on the SoC, can have an associated regulator:
- vcc-pa-supply: for the A10, A20, A31, A31s, A80 and R40 SoCs
- vcc-pb-supply: for the A31, A31s, A80 and V3s SoCs
- vcc-pc-supply: for the A10, A20, A31, A31s, A64, A80, H5, R40 and V3s SoCs
- vcc-pd-supply: for the A23, A31, A31s, A64, A80, A83t, H3, H5 and R40 SoCs
- vcc-pe-supply: for the A10, A20, A31, A31s, A64, A80, R40 and V3s SoCs
- vcc-pf-supply: for the A10, A20, A31, A31s, A80, R40 and V3s SoCs
- vcc-pg-supply: for the A10, A20, A31, A31s, A64, A80, H3, H5, R40 and V3s SoCs
- vcc-ph-supply: for the A31, A31s and A80 SoCs
- vcc-pl-supply: for the r-pinctrl of the A64, A80 and A83t SoCs
- vcc-pm-supply: for the r-pinctrl of the A31, A31s and A80 SoCs
Optional properties:
- input-debounce: Array of debouncing periods in microseconds. One period per
irq bank found in the controller. 0 if no setup required.
......
Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt
View file @ c9bef4a6
......@@ -7,13 +7,15 @@ configure controller correctly.
A list of pins varies across chipsets so few bindings are available.
Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
noce.
Required properties:
- compatible: must be one of:
"brcm,bcm4708-pinmux"
"brcm,bcm4709-pinmux"
"brcm,bcm53012-pinmux"
- reg: iomem address range of CRU (Central Resource Unit) pin registers
- reg-names: "cru_gpio_control" - the only needed & supported reg right now
- offset: offset of pin registers in the CRU block
Functions and their groups available for all chipsets:
- "spi": "spi_grp"
......@@ -37,16 +39,12 @@ Example:
#size-cells = <1>;
cru@100 {
compatible = "simple-bus";
compatible = "syscon", "simple-mfd";
reg = <0x100 0x1a4>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
pin-controller@1c0 {
pinctrl {
compatible = "brcm,bcm4708-pinmux";
reg = <0x1c0 0x24>;
reg-names = "cru_gpio_control";
offset = <0xc0>;
spi-pins {
function = "spi";
......
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
View file @ c9bef4a6
......@@ -7,55 +7,47 @@ Note:
This binding doc is only for the IOMUXC1 support in A7 Domain and it only
supports generic pin config.
Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
binding.
=== Pin Controller Node ===
Please refer to fsl,imx-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "fsl,imx7ulp-iomuxc1"
- reg: Should contain the base physical address and size of the iomuxc
registers.
=== Pin Configuration Node ===
- pinmux: One integers array, represents a group of pins mux setting.
The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
a specific function.
NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
and config register as follows:
<mux_conf_reg input_reg mux_mode input_val>
Refer to imx7ulp-pinfunc.h in in device tree source folder for all
available imx7ulp PIN_FUNC_ID.
Optional Properties:
- drive-strength Integer. Controls Drive Strength
0: Standard
1: Hi Driver
- drive-push-pull Bool. Enable Pin Push-pull
- drive-open-drain Bool. Enable Pin Open-drian
- slew-rate: Integer. Controls Slew Rate
0: Standard
1: Slow
- bias-disable: Bool. Pull disabled
- bias-pull-down: Bool. Pull down on pin
- bias-pull-up: Bool. Pull up on pin
- compatible: "fsl,imx7ulp-iomuxc1".
- fsl,pins: Each entry consists of 5 integers which represents the mux
and config setting for one pin. The first 4 integers
<mux_conf_reg input_reg mux_mode input_val> are specified
using a PIN_FUNC_ID macro, which can be found in
imx7ulp-pinfunc.h in the device tree source folder.
The last integer CONFIG is the pad setting value like
pull-up on this pin.
Please refer to i.MX7ULP Reference Manual for detailed
CONFIG settings.
CONFIG bits definition:
PAD_CTL_OBE (1 << 17)
PAD_CTL_IBE (1 << 16)
PAD_CTL_LK (1 << 16)
PAD_CTL_DSE_HI (1 << 6)
PAD_CTL_DSE_STD (0 << 6)
PAD_CTL_ODE (1 << 5)
PAD_CTL_PUSH_PULL (0 << 5)
PAD_CTL_SRE_SLOW (1 << 2)
PAD_CTL_SRE_STD (0 << 2)
PAD_CTL_PE (1 << 0)
Examples:
#include "imx7ulp-pinfunc.h"
/* Pin Controller Node */
iomuxc1: iomuxc@40ac0000 {
iomuxc1: pinctrl@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
/* Pin Configuration Node */
pinctrl_lpuart4: lpuart4grp {
pinmux = <
IMX7ULP_PAD_PTC3__LPUART4_RX
IMX7ULP_PAD_PTC2__LPUART4_TX
fsl,pins = <
IMX7ULP_PAD_PTC3__LPUART4_RX 0x1
IMX7ULP_PAD_PTC2__LPUART4_TX 0x1
>;
bias-pull-up;
};
};
Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
View file @ c9bef4a6
......@@ -2,7 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings
----------------------------------------------------
Required properties:
- compatible : Should be "mscc,ocelot-pinctrl"
- compatible : Should be "mscc,ocelot-pinctrl" or
"mscc,jaguar2-pinctrl"
- reg : Address and length of the register set for the device
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells : Must be 2.
......
Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt 0 → 100644
View file @ c9bef4a6
* MediaTek MT6797 Pin Controller
The MediaTek's MT6797 Pin controller is used to control SoC pins.
Required properties:
- compatible: Value should be one of the following.
"mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
- reg: Should contain address and size for gpio, iocfgl, iocfgb,
iocfgr and iocfgt register bases.
- reg-names: An array of strings describing the "reg" entries. Must
contain "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt".
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the gpio pin number
and the second cell is used for optional parameters.
Optional properties:
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs from the controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull, bias-pull-down, input-enable, input-schmitt-enable,
input-schmitt-disable, output-enable output-low, output-high,
drive-strength, and slew-rate are valid.
Valid arguments for 'slew-rate' are '0' for no slew rate controlled and
'1' for slower slew rate respectively. Valid arguments for 'drive-strength'
is limited, such as 2, 4, 8, 12, or 16 in mA.
Some optional vendor properties as defined are valid to specify in a
pinconf subnode:
- mediatek,tdsel: An integer describing the steps for output level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
- mediatek,rdsel: An integer describing the steps for input level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 63.
- mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2
or 3 for the advanced pull-up resistors.
- mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2,
or 3 for the advanced pull-down resistors.
Examples:
pio: pinctrl@10005000 {
compatible = "mediatek,mt6797-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x400>,
<0 0x10002400 0 0x400>,
<0 0x10002800 0 0x400>,
<0 0x10002C00 0 0x400>;
reg-names = "gpio", "iocfgl", "iocfgb",
"iocfgr", "iocfgt";
gpio-controller;
#gpio-cells = <2>;
uart1_pins_a: uart1 {
pins1 {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
View file @ c9bef4a6
......@@ -3,6 +3,7 @@
Required properties for the root node:
- compatible: Should be one of the following
"mediatek,mt7622-pinctrl" for MT7622 SoC
"mediatek,mt7629-pinctrl" for MT7629 SoC
- reg: offset and length of the pinctrl space
- gpio-controller: Marks the device node as a GPIO controller.
......@@ -324,6 +325,136 @@ group.
"uart4_2_rts_cts" "uart" 95, 96
"watchdog" "watchdog" 78
== Valid values for pins, function and groups on MT7629 ==
Pin #: Valid values for pins
-----------------------------
PIN 0: "TOP_5G_CLK"
PIN 1: "TOP_5G_DATA"
PIN 2: "WF0_5G_HB0"
PIN 3: "WF0_5G_HB1"
PIN 4: "WF0_5G_HB2"
PIN 5: "WF0_5G_HB3"
PIN 6: "WF0_5G_HB4"
PIN 7: "WF0_5G_HB5"
PIN 8: "WF0_5G_HB6"
PIN 9: "XO_REQ"
PIN 10: "TOP_RST_N"
PIN 11: "SYS_WATCHDOG"
PIN 12: "EPHY_LED0_N_JTDO"
PIN 13: "EPHY_LED1_N_JTDI"
PIN 14: "EPHY_LED2_N_JTMS"
PIN 15: "EPHY_LED3_N_JTCLK"
PIN 16: "EPHY_LED4_N_JTRST_N"
PIN 17: "WF2G_LED_N"
PIN 18: "WF5G_LED_N"
PIN 19: "I2C_SDA"
PIN 20: "I2C_SCL"
PIN 21: "GPIO_9"
PIN 22: "GPIO_10"
PIN 23: "GPIO_11"
PIN 24: "GPIO_12"
PIN 25: "UART1_TXD"
PIN 26: "UART1_RXD"
PIN 27: "UART1_CTS"
PIN 28: "UART1_RTS"
PIN 29: "UART2_TXD"
PIN 30: "UART2_RXD"
PIN 31: "UART2_CTS"
PIN 32: "UART2_RTS"
PIN 33: "MDI_TP_P1"
PIN 34: "MDI_TN_P1"
PIN 35: "MDI_RP_P1"
PIN 36: "MDI_RN_P1"
PIN 37: "MDI_RP_P2"
PIN 38: "MDI_RN_P2"
PIN 39: "MDI_TP_P2"
PIN 40: "MDI_TN_P2"
PIN 41: "MDI_TP_P3"
PIN 42: "MDI_TN_P3"
PIN 43: "MDI_RP_P3"
PIN 44: "MDI_RN_P3"
PIN 45: "MDI_RP_P4"
PIN 46: "MDI_RN_P4"
PIN 47: "MDI_TP_P4"
PIN 48: "MDI_TN_P4"
PIN 49: "SMI_MDC"
PIN 50: "SMI_MDIO"
PIN 51: "PCIE_PERESET_N"
PIN 52: "PWM_0"
PIN 53: "GPIO_0"
PIN 54: "GPIO_1"
PIN 55: "GPIO_2"
PIN 56: "GPIO_3"
PIN 57: "GPIO_4"
PIN 58: "GPIO_5"
PIN 59: "GPIO_6"
PIN 60: "GPIO_7"
PIN 61: "GPIO_8"
PIN 62: "SPI_CLK"
PIN 63: "SPI_CS"
PIN 64: "SPI_MOSI"
PIN 65: "SPI_MISO"
PIN 66: "SPI_WP"
PIN 67: "SPI_HOLD"
PIN 68: "UART0_TXD"
PIN 69: "UART0_RXD"
PIN 70: "TOP_2G_CLK"
PIN 71: "TOP_2G_DATA"
PIN 72: "WF0_2G_HB0"
PIN 73: "WF0_2G_HB1"
PIN 74: "WF0_2G_HB2"
PIN 75: "WF0_2G_HB3"
PIN 76: "WF0_2G_HB4"
PIN 77: "WF0_2G_HB5"
PIN 78: "WF0_2G_HB6"
Valid values for function are:
"eth", "i2c", "led", "flash", "pcie", "pwm", "spi", "uart",
"watchdog", "wifi"
Valid values for groups are:
Valid value function pins (in pin#)
----------------------------------------------------------------
"mdc_mdio" "eth" 23, 24
"i2c_0" "i2c" 19, 20
"i2c_1" "i2c" 53, 54
"ephy_leds" "led" 12, 13, 14, 15, 16,
17, 18
"ephy0_led" "led" 12
"ephy1_led" "led" 13
"ephy2_led" "led" 14
"ephy3_led" "led" 15
"ephy4_led" "led" 16
"wf2g_led" "led" 17
"wf5g_led" "led" 18
"snfi" "flash" 62, 63, 64, 65, 66, 67
"spi_nor" "flash" 62, 63, 64, 65, 66, 67
"pcie_pereset" "pcie" 51
"pcie_wake" "pcie" 55
"pcie_clkreq" "pcie" 56
"pwm_0" "pwm" 52
"pwm_1" "pwm" 61
"spi_0" "spi" 21, 22, 23, 24
"spi_1" "spi" 62, 63, 64, 65
"spi_wp" "spi" 66
"spi_hold" "spi" 67
"uart0_txd_rxd" "uart" 68, 69
"uart1_0_txd_rxd" "uart" 25, 26
"uart1_0_cts_rts" "uart" 27, 28
"uart1_1_txd_rxd" "uart" 53, 54
"uart1_1_cts_rts" "uart" 55, 56
"uart2_0_txd_rxd" "uart" 29, 30
"uart2_0_cts_rts" "uart" 31, 32
"uart2_1_txd_rxd" "uart" 57, 58
"uart2_1_cts_rts" "uart" 59, 60
"watchdog" "watchdog" 11
"wf0_2g" "wifi" 70, 71, 72, 73, 74,
75, 76, 77, 78
"wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6,
7, 8, 9, 10
Example:
pio: pinctrl@10211000 {
......
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
View file @ c9bef4a6
......@@ -92,7 +92,7 @@ to specify in a pin configuration subnode:
gpio1-gpio26 for pm8998
gpio1-gpio22 for pma8084
gpio1-gpio10 for pmi8994
gpio1-gpio11 for pms405
gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10)
- function:
Usage: required
......
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt 0 → 100644
View file @ c9bef4a6
Renesas RZ/A2 combined Pin and GPIO controller
The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO
function (port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
Pin controller node
-------------------
Required properties:
- compatible: shall be:
- "renesas,r7s9210-pinctrl": for RZ/A2M
- reg
Address base and length of the memory area where the pin controller
hardware is mapped to.
- gpio-controller
This pin controller also controls pins as GPIO
- #gpio-cells
Must be 2
- gpio-ranges
Expresses the total number of GPIO ports/pins in this SoC
Example: Pin controller node for RZ/A2M SoC (r7s9210)
pinctrl: pin-controller@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 176>;
};
Sub-nodes
---------
The child nodes of the pin controller designate pins to be used for
specific peripheral functions or as GPIO.
- Pin multiplexing sub-nodes:
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
The values for the pinmux properties are a combination of port name, pin
number and the desired function index. Use the RZA2_PINMUX macro located
in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h
to express the desired port pin.
Required properties:
- pinmux:
integer array representing pin number and pin multiplexing configuration.
When a pin has to be configured in alternate function mode, use this
property to identify the pin by its global index, and provide its
alternate function configuration number along with it.
When multiple pins are required to be configured as part of the same
alternate function they shall be specified as members of the same
argument list of a single "pinmux" property.
Helper macros to ease assembling the pin index from its position
(port where it sits on and pin number) and alternate function identifier
are provided by the pin controller header file at:
<dt-bindings/pinctrl/r7s9210-pinctrl.h>
Integers values in "pinmux" argument list are assembled as:
((PORT * 8 + PIN) | MUX_FUNC << 16)
Example: Board specific pins configuration
&pinctrl {
/* Serial Console */
scif4_pins: serial4 {
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
};
};
Example: Assigning a GPIO:
leds {
status = "okay";
compatible = "gpio-leds";
led0 {
/* P6_0 */
gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
View file @ c9bef4a6
......@@ -56,6 +56,7 @@ Optional properties:
More details in Documentation/devicetree/bindings/gpio/gpio.txt.
- st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
used to select GPIOs as interrupts).
- hwlocks: reference to a phandle of a hardware spinlock provider node.
Example 1:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
......
MAINTAINERS
View file @ c9bef4a6
......@@ -11919,18 +11919,12 @@ F: Documentation/driver-api/pinctl.rst
F: drivers/pinctrl/
F: include/linux/pinctrl/
PIN CONTROLLER - ATMEL AT91
M: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: drivers/pinctrl/pinctrl-at91.*
PIN CONTROLLER - ATMEL AT91 PIO4
PIN CONTROLLER - MICROCHIP AT91
M: Ludovic Desroches <ludovic.desroches@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-gpio@vger.kernel.org
S: Supported
F: drivers/pinctrl/pinctrl-at91-pio4.*
F: drivers/pinctrl/pinctrl-at91*
PIN CONTROLLER - FREESCALE
M: Dong Aisheng <aisheng.dong@nxp.com>
......@@ -11966,11 +11960,11 @@ F: Documentation/devicetree/bindings/pinctrl/qcom,*.txt
F: drivers/pinctrl/qcom/
PIN CONTROLLER - RENESAS
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
M: Geert Uytterhoeven <geert+renesas@glider.be>
L: linux-renesas-soc@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
S: Maintained
F: drivers/pinctrl/pinctrl-rz*
F: drivers/pinctrl/sh-pfc/
PIN CONTROLLER - SAMSUNG
......
drivers/pinctrl/Kconfig
View file @ c9bef4a6
......@@ -195,6 +195,17 @@ config PINCTRL_RZA1
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
config PINCTRL_RZA2
bool "Renesas RZ/A2 gpio and pinctrl driver"
depends on OF
depends on ARCH_R7S9210 || COMPILE_TEST
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_RZN1
bool "Renesas RZ/N1 pinctrl driver"
depends on OF
......@@ -339,15 +350,15 @@ config PINCTRL_RK805
This selects the pinctrl driver for RK805.
config PINCTRL_OCELOT
bool "Pinctrl driver for the Microsemi Ocelot SoCs"
default y
bool "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
depends on OF
depends on MSCC_OCELOT || COMPILE_TEST
depends on HAS_IOMEM
select GPIOLIB
select GPIOLIB_IRQCHIP
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select OF_GPIO
select REGMAP_MMIO
source "drivers/pinctrl/actions/Kconfig"
......
drivers/pinctrl/Makefile
View file @ c9bef4a6
......@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
......
drivers/pinctrl/actions/Kconfig
View file @ c9bef4a6
......@@ -9,6 +9,12 @@ config PINCTRL_OWL
help
Say Y here to enable Actions Semi OWL pinctrl driver
config PINCTRL_S700
bool "Actions Semi S700 pinctrl driver"
depends on PINCTRL_OWL
help
Say Y here to enable Actions Semi S700 pinctrl driver
config PINCTRL_S900
bool "Actions Semi S900 pinctrl driver"
depends on PINCTRL_OWL
......
drivers/pinctrl/actions/Makefile
View file @ c9bef4a6
obj-$(CONFIG_PINCTRL_OWL) += pinctrl-owl.o
obj-$(CONFIG_PINCTRL_S700) += pinctrl-s700.o
obj-$(CONFIG_PINCTRL_S900) += pinctrl-s900.o
drivers/pinctrl/actions/pinctrl-owl.c
View file @ c9bef4a6
......@@ -246,60 +246,6 @@ static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
return 0;
}
static int owl_pad_pinconf_arg2val(const struct owl_padinfo *info,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
*arg = OWL_PINCONF_PULL_HOLD;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*arg = OWL_PINCONF_PULL_HIZ;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = (*arg >= 1 ? 1 : 0);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
*arg = *arg == OWL_PINCONF_PULL_HOLD;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*arg = *arg == OWL_PINCONF_PULL_HIZ;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = *arg == OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = *arg == OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = *arg == 1;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
unsigned int pin,
unsigned long *config)
......@@ -318,7 +264,10 @@ static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
arg = owl_read_field(pctrl, reg, bit, width);
ret = owl_pad_pinconf_val2arg(info, param, &arg);
if (!pctrl->soc->padctl_val2arg)
return -ENOTSUPP;
ret = pctrl->soc->padctl_val2arg(info, param, &arg);
if (ret)
return ret;
......@@ -349,7 +298,10 @@ static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
if (ret)
return ret;
ret = owl_pad_pinconf_arg2val(info, param, &arg);
if (!pctrl->soc->padctl_arg2val)
return -ENOTSUPP;
ret = pctrl->soc->padctl_arg2val(info, param, &arg);
if (ret)
return ret;
......@@ -787,7 +739,7 @@ static void owl_gpio_irq_mask(struct irq_data *data)
val = readl_relaxed(gpio_base + port->intc_msk);
if (val == 0)
owl_gpio_update_reg(gpio_base + port->intc_ctl,
OWL_GPIO_CTLR_ENABLE, false);
OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
......@@ -811,7 +763,8 @@ static void owl_gpio_irq_unmask(struct irq_data *data)
/* enable port interrupt */
value = readl_relaxed(gpio_base + port->intc_ctl);
value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M);
value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
<< port->shared_ctl_offset * 5);
writel_relaxed(value, gpio_base + port->intc_ctl);
/* enable GPIO interrupt */
......@@ -849,7 +802,7 @@ static void owl_gpio_irq_ack(struct irq_data *data)
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->intc_ctl,
OWL_GPIO_CTLR_PENDING, true);
OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
......
drivers/pinctrl/actions/pinctrl-owl.h
View file @ c9bef4a6
......@@ -15,12 +15,135 @@
#define OWL_PINCONF_SLEW_SLOW 0
#define OWL_PINCONF_SLEW_FAST 1
enum owl_pinconf_pull {
OWL_PINCONF_PULL_HIZ,
OWL_PINCONF_PULL_DOWN,
OWL_PINCONF_PULL_UP,
OWL_PINCONF_PULL_HOLD,
};
#define MUX_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.funcs = group_name##_funcs, \
.nfuncs = ARRAY_SIZE(group_name##_funcs), \
.mfpctl_reg = MFCTL##reg, \
.mfpctl_shift = shift, \
.mfpctl_width = width, \
.drv_reg = -1, \
.drv_shift = -1, \
.drv_width = -1, \
.sr_reg = -1, \
.sr_shift = -1, \
.sr_width = -1, \
}
#define DRV_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.mfpctl_reg = -1, \
.mfpctl_shift = -1, \
.mfpctl_width = -1, \
.drv_reg = PAD_DRV##reg, \
.drv_shift = shift, \
.drv_width = width, \
.sr_reg = -1, \
.sr_shift = -1, \
.sr_width = -1, \
}
#define SR_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.mfpctl_reg = -1, \
.mfpctl_shift = -1, \
.mfpctl_width = -1, \
.drv_reg = -1, \
.drv_shift = -1, \
.drv_width = -1, \
.sr_reg = PAD_SR##reg, \
.sr_shift = shift, \
.sr_width = width, \
}
#define FUNCTION(fname) \
{ \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
/* PAD PULL UP/DOWN CONFIGURES */
#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
{ \
.reg = PAD_PULLCTL##pull_reg, \
.shift = pull_sft, \
.width = pull_wdt, \
}
#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
struct owl_pullctl pad_name##_pullctl_conf \
= PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
#define ST_CONF(st_reg, st_sft, st_wdt) \
{ \
.reg = PAD_ST##st_reg, \
.shift = st_sft, \
.width = st_wdt, \
}
#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \
struct owl_st pad_name##_st_conf \
= ST_CONF(st_reg, st_sft, st_wdt)
#define PAD_INFO(name) \
{ \
.pad = name, \
.pullctl = NULL, \
.st = NULL, \
}
#define PAD_INFO_ST(name) \
{ \
.pad = name, \
.pullctl = NULL, \
.st = &name##_st_conf, \
}
#define PAD_INFO_PULLCTL(name) \
{ \
.pad = name, \
.pullctl = &name##_pullctl_conf, \
.st = NULL, \
}
#define PAD_INFO_PULLCTL_ST(name) \
{ \
.pad = name, \
.pullctl = &name##_pullctl_conf, \
.st = &name##_st_conf, \
}
#define OWL_GPIO_PORT_A 0
#define OWL_GPIO_PORT_B 1
#define OWL_GPIO_PORT_C 2
#define OWL_GPIO_PORT_D 3
#define OWL_GPIO_PORT_E 4
#define OWL_GPIO_PORT_F 5
#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\
_intc_pd, _intc_msk, _intc_type, _share) \
[OWL_GPIO_PORT_##port] = { \
.offset = base, \
.pins = count, \
.outen = _outen, \
.inen = _inen, \
.dat = _dat, \
.intc_ctl = _intc_ctl, \
.intc_pd = _intc_pd, \
.intc_msk = _intc_msk, \
.intc_type = _intc_type, \
.shared_ctl_offset = _share, \
}
enum owl_pinconf_drv {
OWL_PINCONF_DRV_2MA,
......@@ -148,6 +271,7 @@ struct owl_gpio_port {
unsigned int intc_pd;
unsigned int intc_msk;
unsigned int intc_type;
u8 shared_ctl_offset;
};
/**
......@@ -174,6 +298,12 @@ struct owl_pinctrl_soc_data {
unsigned int ngpios;
const struct owl_gpio_port *ports;
unsigned int nports;
int (*padctl_val2arg)(const struct owl_padinfo *padinfo,
unsigned int param,
u32 *arg);
int (*padctl_arg2val)(const struct owl_padinfo *info,
unsigned int param,
u32 *arg);
};
int owl_pinctrl_probe(struct platform_device *pdev,
......
drivers/pinctrl/actions/pinctrl-s700.c 0 → 100644
View file @ c9bef4a6
This diff is collapsed.
drivers/pinctrl/actions/pinctrl-s900.c
View file @ c9bef4a6
......@@ -13,6 +13,7 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "pinctrl-owl.h"
/* Pinctrl registers offset */
......@@ -33,13 +34,6 @@
#define PAD_SR1 (0x0274)
#define PAD_SR2 (0x0278)
#define OWL_GPIO_PORT_A 0
#define OWL_GPIO_PORT_B 1
#define OWL_GPIO_PORT_C 2
#define OWL_GPIO_PORT_D 3
#define OWL_GPIO_PORT_E 4
#define OWL_GPIO_PORT_F 5
#define _GPIOA(offset) (offset)
#define _GPIOB(offset) (32 + (offset))
#define _GPIOC(offset) (64 + (offset))
......@@ -892,55 +886,6 @@ static unsigned int i2c2_sr_pads[] = { I2C2_SCLK, I2C2_SDATA };
static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK,
SENSOR0_CKOUT };
#define MUX_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.funcs = group_name##_funcs, \
.nfuncs = ARRAY_SIZE(group_name##_funcs), \
.mfpctl_reg = MFCTL##reg, \
.mfpctl_shift = shift, \
.mfpctl_width = width, \
.drv_reg = -1, \
.drv_shift = -1, \
.drv_width = -1, \
.sr_reg = -1, \
.sr_shift = -1, \
.sr_width = -1, \
}
#define DRV_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.mfpctl_reg = -1, \
.mfpctl_shift = -1, \
.mfpctl_width = -1, \
.drv_reg = PAD_DRV##reg, \
.drv_shift = shift, \
.drv_width = width, \
.sr_reg = -1, \
.sr_shift = -1, \
.sr_width = -1, \
}
#define SR_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.mfpctl_reg = -1, \
.mfpctl_shift = -1, \
.mfpctl_width = -1, \
.drv_reg = -1, \
.drv_shift = -1, \
.drv_width = -1, \
.sr_reg = PAD_SR##reg, \
.sr_shift = shift, \
.sr_width = width, \
}
/* Pinctrl groups */
static const struct owl_pingroup s900_groups[] = {
......@@ -1442,13 +1387,6 @@ static const char * const sirq2_groups[] = {
"sirq2_dummy",
};
#define FUNCTION(fname) \
{ \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
static const struct owl_pinmux_func s900_functions[] = {
[S900_MUX_ERAM] = FUNCTION(eram),
[S900_MUX_ETH_RMII] = FUNCTION(eth_rmii),
......@@ -1500,28 +1438,6 @@ static const struct owl_pinmux_func s900_functions[] = {
[S900_MUX_SIRQ1] = FUNCTION(sirq1),
[S900_MUX_SIRQ2] = FUNCTION(sirq2)
};
/* PAD PULL UP/DOWN CONFIGURES */
#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
{ \
.reg = PAD_PULLCTL##pull_reg, \
.shift = pull_sft, \
.width = pull_wdt, \
}
#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
struct owl_pullctl pad_name##_pullctl_conf \
= PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
#define ST_CONF(st_reg, st_sft, st_wdt) \
{ \
.reg = PAD_ST##st_reg, \
.shift = st_sft, \
.width = st_wdt, \
}
#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \
struct owl_st pad_name##_st_conf \
= ST_CONF(st_reg, st_sft, st_wdt)
/* PAD_PULLCTL0 */
static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2);
......@@ -1639,34 +1555,6 @@ static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
#define PAD_INFO(name) \
{ \
.pad = name, \
.pullctl = NULL, \
.st = NULL, \
}
#define PAD_INFO_ST(name) \
{ \
.pad = name, \
.pullctl = NULL, \
.st = &name##_st_conf, \
}
#define PAD_INFO_PULLCTL(name) \
{ \
.pad = name, \
.pullctl = &name##_pullctl_conf, \
.st = NULL, \
}
#define PAD_INFO_PULLCTL_ST(name) \
{ \
.pad = name, \
.pullctl = &name##_pullctl_conf, \
.st = &name##_st_conf, \
}
/* Pad info table */
static struct owl_padinfo s900_padinfo[NUM_PADS] = {
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
......@@ -1821,29 +1709,76 @@ static struct owl_padinfo s900_padinfo[NUM_PADS] = {
[SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
};
#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, \
_intc_ctl, _intc_pd, _intc_msk, _intc_type) \
[OWL_GPIO_PORT_##port] = { \
.offset = base, \
.pins = count, \
.outen = _outen, \
.inen = _inen, \
.dat = _dat, \
.intc_ctl = _intc_ctl, \
.intc_pd = _intc_pd, \
.intc_msk = _intc_msk, \
.intc_type = _intc_type, \
}
static const struct owl_gpio_port s900_gpio_ports[] = {
OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240),
OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C),
OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238),
OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234),
OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230),
OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178)
OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240, 0),
OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C, 0),
OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0),
OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234, 0),
OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230, 0),
OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178, 0)
};
enum s900_pinconf_pull {
OWL_PINCONF_PULL_HIZ,
OWL_PINCONF_PULL_DOWN,
OWL_PINCONF_PULL_UP,
OWL_PINCONF_PULL_HOLD,
};
static int s900_pad_pinconf_arg2val(const struct owl_padinfo *info,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
*arg = OWL_PINCONF_PULL_HOLD;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*arg = OWL_PINCONF_PULL_HIZ;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = (*arg >= 1 ? 1 : 0);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int s900_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
*arg = *arg == OWL_PINCONF_PULL_HOLD;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*arg = *arg == OWL_PINCONF_PULL_HIZ;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = *arg == OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = *arg == OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = *arg == 1;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static struct owl_pinctrl_soc_data s900_pinctrl_data = {
.padinfo = s900_padinfo,
.pins = (const struct pinctrl_pin_desc *)s900_pads,
......@@ -1854,7 +1789,9 @@ static struct owl_pinctrl_soc_data s900_pinctrl_data = {
.ngroups = ARRAY_SIZE(s900_groups),
.ngpios = NUM_GPIOS,
.ports = s900_gpio_ports,
.nports = ARRAY_SIZE(s900_gpio_ports)
.nports = ARRAY_SIZE(s900_gpio_ports),
.padctl_arg2val = s900_pad_pinconf_arg2val,
.padctl_val2arg = s900_pad_pinconf_val2arg,
};
static int s900_pinctrl_probe(struct platform_device *pdev)
......
drivers/pinctrl/aspeed/Makefile
View file @ c9bef4a6
# Aspeed pinctrl support
ccflags-y += -Woverride-init
ccflags-y += $(call cc-option,-Woverride-init)
obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o
obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View file @ c9bef4a6
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
*
......@@ -6,16 +7,6 @@
* This driver is inspired by:
* pinctrl-nomadik.c, please see original file for copyright information
* pinctrl-tegra.c, please see original file for copyright information
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/bitmap.h>
......@@ -72,10 +63,8 @@
#define GPIO_REG_OFFSET(p) ((p) / 32)
#define GPIO_REG_SHIFT(p) ((p) % 32)
enum bcm2835_pinconf_param {
/* argument: bcm2835_pinconf_pull */
BCM2835_PINCONF_PARAM_PULL = (PIN_CONFIG_END + 1),
};
/* argument: bcm2835_pinconf_pull */
#define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
struct bcm2835_pinctrl {
struct device *dev;
......@@ -90,7 +79,7 @@ struct bcm2835_pinctrl {
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range gpio_range;
spinlock_t irq_lock[BCM2835_NUM_BANKS];
raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
};
/* pins are just named GPIO0..GPIO53 */
......@@ -461,10 +450,10 @@ static void bcm2835_gpio_irq_enable(struct irq_data *data)
unsigned bank = GPIO_REG_OFFSET(gpio);
unsigned long flags;
spin_lock_irqsave(&pc->irq_lock[bank], flags);
raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
set_bit(offset, &pc->enabled_irq_map[bank]);
bcm2835_gpio_irq_config(pc, gpio, true);
spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
}
static void bcm2835_gpio_irq_disable(struct irq_data *data)
......@@ -476,12 +465,12 @@ static void bcm2835_gpio_irq_disable(struct irq_data *data)
unsigned bank = GPIO_REG_OFFSET(gpio);
unsigned long flags;
spin_lock_irqsave(&pc->irq_lock[bank], flags);
raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
bcm2835_gpio_irq_config(pc, gpio, false);
/* Clear events that were latched prior to clearing event sources */
bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
clear_bit(offset, &pc->enabled_irq_map[bank]);
spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
}
static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
......@@ -584,7 +573,7 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
unsigned long flags;
int ret;
spin_lock_irqsave(&pc->irq_lock[bank], flags);
raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
if (test_bit(offset, &pc->enabled_irq_map[bank]))
ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
......@@ -596,7 +585,7 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
else
irq_set_handler_locked(data, handle_level_irq);
spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
return ret;
}
......@@ -1047,7 +1036,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
for_each_set_bit(offset, &events, 32)
bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
spin_lock_init(&pc->irq_lock[i]);
raw_spin_lock_init(&pc->irq_lock[i]);
}
err = gpiochip_add_data(&pc->gpio_chip, pc);
......
drivers/pinctrl/bcm/pinctrl-ns.c
View file @ c9bef4a6
......@@ -5,6 +5,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
......@@ -12,6 +13,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#define FLAG_BCM4708 BIT(1)
......@@ -22,7 +24,8 @@ struct ns_pinctrl {
struct device *dev;
unsigned int chipset_flag;
struct pinctrl_dev *pctldev;
void __iomem *base;
struct regmap *regmap;
u32 offset;
struct pinctrl_desc pctldesc;
struct ns_pinctrl_group *groups;
......@@ -229,9 +232,9 @@ static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
unset |= BIT(pin_number);
}
tmp = readl(ns_pinctrl->base);
regmap_read(ns_pinctrl->regmap, ns_pinctrl->offset, &tmp);
tmp &= ~unset;
writel(tmp, ns_pinctrl->base);
regmap_write(ns_pinctrl->regmap, ns_pinctrl->offset, tmp);
return 0;
}
......@@ -263,13 +266,13 @@ static const struct of_device_id ns_pinctrl_of_match_table[] = {
static int ns_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
const struct of_device_id *of_id;
struct ns_pinctrl *ns_pinctrl;
struct pinctrl_desc *pctldesc;
struct pinctrl_pin_desc *pin;
struct ns_pinctrl_group *group;
struct ns_pinctrl_function *function;
struct resource *res;
int i;
ns_pinctrl = devm_kzalloc(dev, sizeof(*ns_pinctrl), GFP_KERNEL);
......@@ -287,12 +290,18 @@ static int ns_pinctrl_probe(struct platform_device *pdev)
return -EINVAL;
ns_pinctrl->chipset_flag = (uintptr_t)of_id->data;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"cru_gpio_control");
ns_pinctrl->base = devm_ioremap_resource(dev, res);
if (IS_ERR(ns_pinctrl->base)) {
dev_err(dev, "Failed to map pinctrl regs\n");
return PTR_ERR(ns_pinctrl->base);
ns_pinctrl->regmap = syscon_node_to_regmap(of_get_parent(np));
if (IS_ERR(ns_pinctrl->regmap)) {
int err = PTR_ERR(ns_pinctrl->regmap);
dev_err(dev, "Failed to map pinctrl regs: %d\n", err);
return err;
}
if (of_property_read_u32(np, "offset", &ns_pinctrl->offset)) {
dev_err(dev, "Failed to get register offset\n");
return -ENOENT;
}
memcpy(pctldesc, &ns_pinctrl_desc, sizeof(*pctldesc));
......
drivers/pinctrl/freescale/Kconfig
View file @ c9bef4a6
......@@ -5,6 +5,11 @@ config PINCTRL_IMX
select GENERIC_PINCONF
select REGMAP
config PINCTRL_IMX_SCU
bool
depends on IMX_SCU
select PINCTRL_IMX
config PINCTRL_IMX1_CORE
bool
select PINMUX
......@@ -119,11 +124,18 @@ config PINCTRL_IMX7ULP
config PINCTRL_IMX8MQ
bool "IMX8MQ pinctrl driver"
depends on SOC_IMX8MQ
depends on ARCH_MXC && ARM64
select PINCTRL_IMX
help
Say Y here to enable the imx8mq pinctrl driver
config PINCTRL_IMX8QXP
bool "IMX8QXP pinctrl driver"
depends on ARCH_MXC && ARM64
select PINCTRL_IMX_SCU
help
Say Y here to enable the imx8qxp pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
......
drivers/pinctrl/freescale/Makefile
View file @ c9bef4a6
# SPDX-License-Identifier: GPL-2.0
# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
......@@ -18,6 +19,7 @@ obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
......
drivers/pinctrl/freescale/pinctrl-imx.c
View file @ c9bef4a6
This diff is collapsed.
drivers/pinctrl/freescale/pinctrl-imx.h
View file @ c9bef4a6
......@@ -19,22 +19,43 @@ struct platform_device;
extern struct pinmux_ops imx_pmx_ops;
/**
* struct imx_pin - describes a single i.MX pin
* @pin: the pin_id of this pin
* struct imx_pin_mmio - MMIO pin configurations
* @mux_mode: the mux mode for this pin.
* @input_reg: the select input register offset for this pin if any
* 0 if no select input setting needed.
* @input_val: the select input value for this pin.
* @configs: the config for this pin.
*/
struct imx_pin {
unsigned int pin;
struct imx_pin_mmio {
unsigned int mux_mode;
u16 input_reg;
unsigned int input_val;
unsigned long config;
};
/**
* struct imx_pin_scu - SCU pin configurations
* @mux: the mux mode for this pin.
* @configs: the config for this pin.
*/
struct imx_pin_scu {
unsigned int mux_mode;
unsigned long config;
};
/**
* struct imx_pin - describes a single i.MX pin
* @pin: the pin_id of this pin
* @conf: config type of this pin, either mmio or scu
*/
struct imx_pin {
unsigned int pin;
union {
struct imx_pin_mmio mmio;
struct imx_pin_scu scu;
} conf;
};
/**
* struct imx_pin_reg - describe a pin reg map
* @mux_reg: mux register offset
......@@ -99,8 +120,9 @@ struct imx_pinctrl {
#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
{ .param = p, .mask = m, .shift = o, .invert = true, }
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
#define SHARE_MUX_CONF_REG BIT(0)
#define ZERO_OFFSET_VALID BIT(1)
#define IMX_USE_SCU BIT(2)
#define NO_MUX 0x0
#define NO_PAD 0x0
......@@ -113,4 +135,37 @@ struct imx_pinctrl {
int imx_pinctrl_probe(struct platform_device *pdev,
const struct imx_pinctrl_soc_info *info);
#ifdef CONFIG_PINCTRL_IMX_SCU
#define BM_PAD_CTL_GP_ENABLE BIT(30)
#define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
#define BP_PAD_CTL_IFMUX 27
int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *config);
int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *configs, unsigned num_configs);
void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p);
#else
static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
return -EINVAL;
}
static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
return -EINVAL;
}
static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id,
struct imx_pin *pin,
const __be32 **list_p)
{
}
#endif
#endif /* __DRIVERS_PINCTRL_IMX_H */
drivers/pinctrl/freescale/pinctrl-imx7ulp.c
View file @ c9bef4a6
......@@ -256,46 +256,8 @@ static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
#define BM_OBE_ENABLED BIT(17)
#define BM_IBE_ENABLED BIT(16)
#define BM_LK_ENABLED BIT(15)
#define BM_MUX_MODE 0xf00
#define BP_MUX_MODE 8
#define BM_PULL_ENABLED BIT(1)
static const struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = {
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, BIT(6), 6),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL, BIT(5), 5),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, BIT(2), 2),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_DISABLE, BIT(1), 1),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_PULL_UP, BIT(0), 0),
IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_DRIVE_OPEN_DRAIN, BIT(5), 5),
IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_BIAS_PULL_DOWN, BIT(0), 0),
};
static void imx7ulp_cfg_params_fixup(unsigned long *configs,
unsigned int num_configs,
u32 *raw_config)
{
enum pin_config_param param;
u32 param_val;
int i;
/* lock field disabled */
*raw_config &= ~BM_LK_ENABLED;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
param_val = pinconf_to_config_argument(configs[i]);
if ((param == PIN_CONFIG_BIAS_PULL_UP) ||
(param == PIN_CONFIG_BIAS_PULL_DOWN)) {
/* pull enabled */
*raw_config |= BM_PULL_ENABLED;
return;
}
}
}
static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
......@@ -326,10 +288,6 @@ static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
.gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
.mux_mask = BM_MUX_MODE,
.mux_shift = BP_MUX_MODE,
.generic_pinconf = true,
.decodes = imx7ulp_cfg_decodes,
.num_decodes = ARRAY_SIZE(imx7ulp_cfg_decodes),
.fixup = imx7ulp_cfg_params_fixup,
};
static const struct of_device_id imx7ulp_pinctrl_of_match[] = {
......
drivers/pinctrl/freescale/pinctrl-imx8qxp.c 0 → 100644
View file @ c9bef4a6
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_PERST_B),
IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_CLKREQ_B),
IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_WAKE_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC0),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC1),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC2),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CLK),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CMD),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA4),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA5),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA6),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA7),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_STROBE),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_RESET_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_RESET_B),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_VSELECT),
IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_RE_P_N),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_WP),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CD_B),
IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_DQS_P_N),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CLK),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CMD),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXC),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TX_CTL),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD0),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD1),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD2),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXC),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RX_CTL),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD0),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD1),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD2),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_REFCLK_125M_25M),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDIO),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDC),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FSR),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FST),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKR),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKT),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX0),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX1),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX2_RX3),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX3_RX2),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX4_RX1),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX5_RX0),
IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_RX),
IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_TX),
IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_EXT_CLK),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_SCK),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDO),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDI),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS0),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS1),
IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN1),
IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN0),
IMX_PINCTRL_PIN(IMX8QXP_MCLK_OUT0),
IMX_PINCTRL_PIN(IMX8QXP_UART1_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART1_RX),
IMX_PINCTRL_PIN(IMX8QXP_UART1_RTS_B),
IMX_PINCTRL_PIN(IMX8QXP_UART1_CTS_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXD),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXC),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_RXD),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXFS),
IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXD),
IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXC),
IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXFS),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_CS0),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDO),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDI),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_SCK),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_SCK),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDI),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDO),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS1),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS0),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN1),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN0),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN3),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN2),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN5),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN4),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_RX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_TX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_RX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_TX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_RX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART0_RX),
IMX_PINCTRL_PIN(IMX8QXP_UART0_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART2_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART2_RX),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
IMX_PINCTRL_PIN(IMX8QXP_JTAG_TRST_B),
IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SCL),
IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SDA),
IMX_PINCTRL_PIN(IMX8QXP_PMIC_INT_B),
IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_SCU_PMIC_STANDBY),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE0),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE1),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE2),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE3),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D00),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D01),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D02),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D03),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D04),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D05),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D06),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D07),
IMX_PINCTRL_PIN(IMX8QXP_CSI_HSYNC),
IMX_PINCTRL_PIN(IMX8QXP_CSI_VSYNC),
IMX_PINCTRL_PIN(IMX8QXP_CSI_PCLK),
IMX_PINCTRL_PIN(IMX8QXP_CSI_MCLK),
IMX_PINCTRL_PIN(IMX8QXP_CSI_EN),
IMX_PINCTRL_PIN(IMX8QXP_CSI_RESET),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_MCLK_OUT),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DQS),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS0_B),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS1_B),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SCLK),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SCLK),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DQS),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS0_B),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS1_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
};
static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
.pins = imx8qxp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
.flags = IMX_USE_SCU,
};
static const struct of_device_id imx8qxp_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8qxp-iomuxc", },
{ /* sentinel */ }
};
static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
{
int ret;
ret = imx_pinctrl_sc_ipc_init(pdev);
if (ret)
return ret;
return imx_pinctrl_probe(pdev, &imx8qxp_pinctrl_info);
}
static struct platform_driver imx8qxp_pinctrl_driver = {
.driver = {
.name = "imx8qxp-pinctrl",
.of_match_table = of_match_ptr(imx8qxp_pinctrl_of_match),
.suppress_bind_attrs = true,
},
.probe = imx8qxp_pinctrl_probe,
};
static int __init imx8qxp_pinctrl_init(void)
{
return platform_driver_register(&imx8qxp_pinctrl_driver);
}
arch_initcall(imx8qxp_pinctrl_init);
drivers/pinctrl/freescale/pinctrl-scu.c 0 → 100644
View file @ c9bef4a6
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/of_address.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "../core.h"
#include "pinctrl-imx.h"
enum pad_func_e {
IMX_SC_PAD_FUNC_SET = 15,
IMX_SC_PAD_FUNC_GET = 16,
};
struct imx_sc_msg_req_pad_set {
struct imx_sc_rpc_msg hdr;
u32 val;
u16 pad;
} __packed;
struct imx_sc_msg_req_pad_get {
struct imx_sc_rpc_msg hdr;
u16 pad;
} __packed;
struct imx_sc_msg_resp_pad_get {
struct imx_sc_rpc_msg hdr;
u32 val;
} __packed;
struct imx_sc_ipc *pinctrl_ipc_handle;
int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
{
return imx_scu_get_handle(&pinctrl_ipc_handle);
}
int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *config)
{
struct imx_sc_msg_req_pad_get msg;
struct imx_sc_msg_resp_pad_get *resp;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
int ret;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_PAD;
hdr->func = IMX_SC_PAD_FUNC_GET;
hdr->size = 2;
msg.pad = pin_id;
ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
if (ret)
return ret;
resp = (struct imx_sc_msg_resp_pad_get *)&msg;
*config = resp->val;
return 0;
}
int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *configs, unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct imx_sc_msg_req_pad_set msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
unsigned int mux = configs[0];
unsigned int conf = configs[1];
unsigned int val;
int ret;
/*
* Set mux and conf together in one IPC call
*/
WARN_ON(num_configs != 2);
val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
val |= mux << BP_PAD_CTL_IFMUX;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_PAD;
hdr->func = IMX_SC_PAD_FUNC_SET;
hdr->size = 3;
msg.pad = pin_id;
msg.val = val;
ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
dev_dbg(ipctl->dev, "write: pin_id %u config 0x%x val 0x%x\n",
pin_id, conf, val);
return ret;
}
void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_pin_scu *pin_scu = &pin->conf.scu;
const __be32 *list = *list_p;
pin->pin = be32_to_cpu(*list++);
*pin_id = pin->pin;
pin_scu->mux_mode = be32_to_cpu(*list++);
pin_scu->config = be32_to_cpu(*list++);
*list_p = list;
dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
pin_scu->mux_mode, pin_scu->config);
}
drivers/pinctrl/intel/pinctrl-baytrail.c
View file @ c9bef4a6
......@@ -705,7 +705,7 @@ static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
&byt_score_soc_data,
&byt_sus_soc_data,
&byt_ncore_soc_data,
NULL,
NULL
};
static struct byt_community *byt_get_community(struct byt_gpio *vg,
......@@ -1838,8 +1838,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
static int byt_gpio_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct byt_gpio *vg = platform_get_drvdata(pdev);
struct byt_gpio *vg = dev_get_drvdata(dev);
int i;
for (i = 0; i < vg->soc_data->npins; i++) {
......@@ -1867,8 +1866,7 @@ static int byt_gpio_suspend(struct device *dev)
static int byt_gpio_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct byt_gpio *vg = platform_get_drvdata(pdev);
struct byt_gpio *vg = dev_get_drvdata(dev);
int i;
for (i = 0; i < vg->soc_data->npins; i++) {
......
drivers/pinctrl/intel/pinctrl-broxton.c
View file @ c9bef4a6
......@@ -526,7 +526,7 @@ static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {
&bxt_west_soc_data,
&bxt_southwest_soc_data,
&bxt_south_soc_data,
NULL,
NULL
};
/* APL */
......@@ -990,7 +990,7 @@ static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {
&apl_northwest_soc_data,
&apl_west_soc_data,
&apl_southwest_soc_data,
NULL,
NULL
};
static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
......@@ -1003,18 +1003,13 @@ MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
{ "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data },
{ "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data },
{ },
{ }
};
static int bxt_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe_by_uid(pdev);
}
static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);
static struct platform_driver bxt_pinctrl_driver = {
.probe = bxt_pinctrl_probe,
.probe = intel_pinctrl_probe_by_uid,
.driver = {
.name = "broxton-pinctrl",
.acpi_match_table = bxt_pinctrl_acpi_match,
......
drivers/pinctrl/intel/pinctrl-cannonlake.c
View file @ c9bef4a6
......@@ -829,19 +829,14 @@ static const struct intel_pinctrl_soc_data cnllp_soc_data = {
static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
{ "INT3450", (kernel_ulong_t)&cnlh_soc_data },
{ "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
{ },
{ }
};
MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
static int cnl_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe_by_hid(pdev);
}
static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
static struct platform_driver cnl_pinctrl_driver = {
.probe = cnl_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "cannonlake-pinctrl",
.acpi_match_table = cnl_pinctrl_acpi_match,
......
drivers/pinctrl/intel/pinctrl-cedarfork.c
View file @ c9bef4a6
......@@ -6,7 +6,7 @@
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*/
#include <linux/acpi.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
......@@ -330,21 +330,16 @@ static const struct intel_pinctrl_soc_data cdf_soc_data = {
.ncommunities = ARRAY_SIZE(cdf_communities),
};
static int cdf_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &cdf_soc_data);
}
static INTEL_PINCTRL_PM_OPS(cdf_pinctrl_pm_ops);
static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
{ "INTC3001" },
{ "INTC3001", (kernel_ulong_t)&cdf_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, cdf_pinctrl_acpi_match);
static struct platform_driver cdf_pinctrl_driver = {
.probe = cdf_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "cedarfork-pinctrl",
.acpi_match_table = cdf_pinctrl_acpi_match,
......
drivers/pinctrl/intel/pinctrl-cherryview.c
View file @ c9bef4a6
......@@ -846,6 +846,19 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
return 0;
}
static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
unsigned int offset)
{
void __iomem *reg;
u32 value;
reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
value = readl(reg);
value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
value &= ~CHV_PADCTRL1_INVRXTX_MASK;
chv_writel(value, reg);
}
static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
......@@ -876,11 +889,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
}
/* Disable interrupt generation */
reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
value = readl(reg);
value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
value &= ~CHV_PADCTRL1_INVRXTX_MASK;
chv_writel(value, reg);
chv_gpio_clear_triggering(pctrl, offset);
reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
value = readl(reg);
......@@ -912,14 +921,11 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
void __iomem *reg;
u32 value;
raw_spin_lock_irqsave(&chv_lock, flags);
reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
chv_writel(value, reg);
if (!chv_pad_locked(pctrl, offset))
chv_gpio_clear_triggering(pctrl, offset);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
......@@ -1744,8 +1750,7 @@ static int chv_pinctrl_remove(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
static int chv_pinctrl_suspend_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
unsigned long flags;
int i;
......@@ -1778,8 +1783,7 @@ static int chv_pinctrl_suspend_noirq(struct device *dev)
static int chv_pinctrl_resume_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
unsigned long flags;
int i;
......
drivers/pinctrl/intel/pinctrl-denverton.c
View file @ c9bef4a6
......@@ -6,7 +6,7 @@
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*/
#include <linux/acpi.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
......@@ -257,21 +257,16 @@ static const struct intel_pinctrl_soc_data dnv_soc_data = {
.ncommunities = ARRAY_SIZE(dnv_communities),
};
static int dnv_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &dnv_soc_data);
}
static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
{ "INTC3000" },
{ "INTC3000", (kernel_ulong_t)&dnv_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
static struct platform_driver dnv_pinctrl_driver = {
.probe = dnv_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "denverton-pinctrl",
.acpi_match_table = dnv_pinctrl_acpi_match,
......
drivers/pinctrl/intel/pinctrl-geminilake.c
View file @ c9bef4a6
......@@ -445,7 +445,7 @@ static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {
&glk_north_soc_data,
&glk_audio_soc_data,
&glk_scc_soc_data,
NULL,
NULL
};
static const struct acpi_device_id glk_pinctrl_acpi_match[] = {
......
drivers/pinctrl/intel/pinctrl-icelake.c
View file @ c9bef4a6
......@@ -403,21 +403,16 @@ static const struct intel_pinctrl_soc_data icllp_soc_data = {
.ncommunities = ARRAY_SIZE(icllp_communities),
};
static int icl_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &icllp_soc_data);
}
static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
{ "INT3455" },
{ },
{ "INT3455", (kernel_ulong_t)&icllp_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
static struct platform_driver icl_pinctrl_driver = {
.probe = icl_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "icelake-pinctrl",
.acpi_match_table = icl_pinctrl_acpi_match,
......
drivers/pinctrl/intel/pinctrl-intel.c
View file @ c9bef4a6
......@@ -1301,7 +1301,7 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
return 0;
}
int intel_pinctrl_probe(struct platform_device *pdev,
static int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data)
{
struct intel_pinctrl *pctrl;
......@@ -1400,7 +1400,6 @@ int intel_pinctrl_probe(struct platform_device *pdev,
return 0;
}
EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
{
......@@ -1469,8 +1468,7 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int
int intel_pinctrl_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_community_context *communities;
struct intel_pad_context *pads;
int i;
......@@ -1531,8 +1529,7 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
int intel_pinctrl_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
const struct intel_community_context *communities;
const struct intel_pad_context *pads;
int i;
......
drivers/pinctrl/intel/pinctrl-intel.h
View file @ c9bef4a6
......@@ -173,8 +173,6 @@ struct intel_pinctrl_soc_data {
size_t ncommunities;
};
int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data);
int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
......
drivers/pinctrl/intel/pinctrl-lewisburg.c
View file @ c9bef4a6
......@@ -6,7 +6,7 @@
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*/
#include <linux/acpi.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
......@@ -308,21 +308,16 @@ static const struct intel_pinctrl_soc_data lbg_soc_data = {
.ncommunities = ARRAY_SIZE(lbg_communities),
};
static int lbg_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &lbg_soc_data);
}
static INTEL_PINCTRL_PM_OPS(lbg_pinctrl_pm_ops);
static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
{ "INT3536" },
{ "INT3536", (kernel_ulong_t)&lbg_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, lbg_pinctrl_acpi_match);
static struct platform_driver lbg_pinctrl_driver = {
.probe = lbg_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "lewisburg-pinctrl",
.acpi_match_table = lbg_pinctrl_acpi_match,
......
drivers/pinctrl/intel/pinctrl-merrifield.c
View file @ c9bef4a6
......@@ -6,7 +6,7 @@
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*/
#include <linux/bitops.h>
#include <linux/bits.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
......
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View file @ c9bef4a6
......@@ -591,15 +591,10 @@ static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
static int spt_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe_by_hid(pdev);
}
static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
static struct platform_driver spt_pinctrl_driver = {
.probe = spt_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "sunrisepoint-pinctrl",
.acpi_match_table = spt_pinctrl_acpi_match,
......
drivers/pinctrl/mediatek/Kconfig
View file @ c9bef4a6
......@@ -3,7 +3,7 @@ menu "MediaTek pinctrl drivers"
config EINT_MTK
bool "MediaTek External Interrupt Support"
depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || COMPILE_TEST
depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST
select GPIOLIB
select IRQ_DOMAIN
......@@ -17,7 +17,7 @@ config PINCTRL_MTK
select OF_GPIO
config PINCTRL_MTK_MOORE
bool "MediaTek Moore Core that implements generic binding"
bool
depends on OF
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
......@@ -26,7 +26,7 @@ config PINCTRL_MTK_MOORE
select OF_GPIO
config PINCTRL_MTK_PARIS
bool "MediaTek Paris Core that implements vendor binding"
bool
depends on OF
select PINMUX
select GENERIC_PINCONF
......@@ -45,8 +45,14 @@ config PINCTRL_MT2701
config PINCTRL_MT7623
bool "Mediatek MT7623 pin control with generic binding"
depends on MACH_MT7623 || COMPILE_TEST
depends on PINCTRL_MTK_MOORE
default y
default MACH_MT7623
select PINCTRL_MTK_MOORE
config PINCTRL_MT7629
bool "Mediatek MT7629 pin control"
depends on MACH_MT7629 || COMPILE_TEST
default MACH_MT7629
select PINCTRL_MTK_MOORE
config PINCTRL_MT8135
bool "Mediatek MT8135 pin control"
......@@ -77,11 +83,18 @@ config PINCTRL_MT6765
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT6797
bool "Mediatek MT6797 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MTK_MOORE
default y
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
config PINCTRL_MT8173
bool "Mediatek MT8173 pin control"
......
drivers/pinctrl/mediatek/Makefile
View file @ c9bef4a6
......@@ -11,8 +11,10 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
drivers/pinctrl/mediatek/pinctrl-mt6797.c 0 → 100644
View file @ c9bef4a6
// SPDX-License-Identifier: GPL-2.0
/*
* Based on pinctrl-mt6765.c
*
* Copyright (C) 2018 MediaTek Inc.
*
* Author: ZH Chen <zh.chen@mediatek.com>
*
* Copyright (C) Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*
*/
#include "pinctrl-mtk-mt6797.h"
#include "pinctrl-paris.h"
/*
* MT6797 have multiple bases to program pin configuration listed as the below:
* gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400,
* iocfg[r]:0x10002800, iocfg[t]:0x10002C00.
* _i_base could be used to indicate what base the pin should be mapped into.
*/
static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = {
PIN_FIELD(0, 261, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = {
PIN_FIELD(0, 261, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6797_pin_di_range[] = {
PIN_FIELD(0, 261, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6797_pin_do_range[] = {
PIN_FIELD(0, 261, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range),
};
static const char * const mt6797_pinctrl_register_base_names[] = {
"gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt",
};
static const struct mtk_pin_soc mt6797_data = {
.reg_cal = mt6797_reg_cals,
.pins = mtk_pins_mt6797,
.npins = ARRAY_SIZE(mtk_pins_mt6797),
.ngrps = ARRAY_SIZE(mtk_pins_mt6797),
.gpio_m = 0,
.base_names = mt6797_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names),
};
static const struct of_device_id mt6797_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt6797-pinctrl", },
{ }
};
static int mt6797_pinctrl_probe(struct platform_device *pdev)
{
return mtk_paris_pinctrl_probe(pdev, &mt6797_data);
}
static struct platform_driver mt6797_pinctrl_driver = {
.driver = {
.name = "mt6797-pinctrl",
.of_match_table = mt6797_pinctrl_of_match,
},
.probe = mt6797_pinctrl_probe,
};
static int __init mt6797_pinctrl_init(void)
{
return platform_driver_register(&mt6797_pinctrl_driver);
}
arch_initcall(mt6797_pinctrl_init);
drivers/pinctrl/mediatek/pinctrl-mt7629.c 0 → 100644
View file @ c9bef4a6
This diff is collapsed.
drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h 0 → 100644
View file @ c9bef4a6
This diff is collapsed.
drivers/pinctrl/mediatek/pinctrl-paris.c
View file @ c9bef4a6
......@@ -419,8 +419,8 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
pins = of_find_property(node, "pinmux", NULL);
if (!pins) {
dev_err(hw->dev, "missing pins property in node %s .\n",
node->name);
dev_err(hw->dev, "missing pins property in node %pOFn .\n",
node);
return -EINVAL;
}
......
drivers/pinctrl/meson/pinctrl-meson-gxl.c
View file @ c9bef4a6
......@@ -239,13 +239,9 @@ static const unsigned int eth_link_led_pins[] = { GPIOZ_14 };
static const unsigned int eth_act_led_pins[] = { GPIOZ_15 };
static const unsigned int tsin_a_d0_pins[] = { GPIODV_0 };
static const unsigned int tsin_a_d0_x_pins[] = { GPIOX_10 };
static const unsigned int tsin_a_clk_pins[] = { GPIODV_8 };
static const unsigned int tsin_a_clk_x_pins[] = { GPIOX_11 };
static const unsigned int tsin_a_sop_pins[] = { GPIODV_9 };
static const unsigned int tsin_a_sop_x_pins[] = { GPIOX_8 };
static const unsigned int tsin_a_d_valid_pins[] = { GPIODV_10 };
static const unsigned int tsin_a_d_valid_x_pins[] = { GPIOX_9 };
static const unsigned int tsin_a_fail_pins[] = { GPIODV_11 };
static const unsigned int tsin_a_dp_pins[] = {
GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7,
......@@ -432,10 +428,6 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GROUP(spi_miso, 5, 2),
GROUP(spi_ss0, 5, 1),
GROUP(spi_sclk, 5, 0),
GROUP(tsin_a_sop_x, 6, 3),
GROUP(tsin_a_d_valid_x, 6, 2),
GROUP(tsin_a_d0_x, 6, 1),
GROUP(tsin_a_clk_x, 6, 0),
/* Bank Z */
GROUP(eth_mdio, 4, 23),
......@@ -698,8 +690,8 @@ static const char * const eth_led_groups[] = {
};
static const char * const tsin_a_groups[] = {
"tsin_a_clk", "tsin_a_clk_x", "tsin_a_sop", "tsin_a_sop_x",
"tsin_a_d_valid", "tsin_a_d_valid_x", "tsin_a_d0", "tsin_a_d0_x",
"tsin_a_clk", "tsin_a_sop",
"tsin_a_d_valid", "tsin_a_d0",
"tsin_a_dp", "tsin_a_fail",
};
......
drivers/pinctrl/meson/pinctrl-meson8.c
View file @ c9bef4a6
......@@ -506,6 +506,32 @@ static struct meson_pmx_group meson8_cbus_groups[] = {
GPIO_GROUP(GPIOZ_12),
GPIO_GROUP(GPIOZ_13),
GPIO_GROUP(GPIOZ_14),
GPIO_GROUP(CARD_0),
GPIO_GROUP(CARD_1),
GPIO_GROUP(CARD_2),
GPIO_GROUP(CARD_3),
GPIO_GROUP(CARD_4),
GPIO_GROUP(CARD_5),
GPIO_GROUP(CARD_6),
GPIO_GROUP(BOOT_0),
GPIO_GROUP(BOOT_1),
GPIO_GROUP(BOOT_2),
GPIO_GROUP(BOOT_3),
GPIO_GROUP(BOOT_4),
GPIO_GROUP(BOOT_5),
GPIO_GROUP(BOOT_6),
GPIO_GROUP(BOOT_7),
GPIO_GROUP(BOOT_8),
GPIO_GROUP(BOOT_9),
GPIO_GROUP(BOOT_10),
GPIO_GROUP(BOOT_11),
GPIO_GROUP(BOOT_12),
GPIO_GROUP(BOOT_13),
GPIO_GROUP(BOOT_14),
GPIO_GROUP(BOOT_15),
GPIO_GROUP(BOOT_16),
GPIO_GROUP(BOOT_17),
GPIO_GROUP(BOOT_18),
/* bank X */
GROUP(sd_d0_a, 8, 5),
......@@ -774,7 +800,7 @@ static struct meson_pmx_group meson8_aobus_groups[] = {
GROUP(hdmi_cec_ao, 0, 17),
};
static const char * const gpio_groups[] = {
static const char * const gpio_periphs_groups[] = {
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
......@@ -807,7 +833,9 @@ static const char * const gpio_groups[] = {
"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
"BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
"GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
"GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
......@@ -994,7 +1022,7 @@ static const char * const hdmi_cec_ao_groups[] = {
};
static struct meson_pmx_func meson8_cbus_functions[] = {
FUNCTION(gpio),
FUNCTION(gpio_periphs),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
FUNCTION(pcm_a),
......@@ -1030,6 +1058,7 @@ static struct meson_pmx_func meson8_cbus_functions[] = {
};
static struct meson_pmx_func meson8_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(remote),
FUNCTION(i2c_slave_ao),
......
drivers/pinctrl/meson/pinctrl-meson8b.c
View file @ c9bef4a6
This diff is collapsed.
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View file @ c9bef4a6
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drivers/pinctrl/pinconf.c
View file @ c9bef4a6
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drivers/pinctrl/pinctrl-amd.c
View file @ c9bef4a6
......@@ -791,8 +791,7 @@ static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
static int amd_gpio_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
int i;
......@@ -810,8 +809,7 @@ static int amd_gpio_suspend(struct device *dev)
static int amd_gpio_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
int i;
......
drivers/pinctrl/pinctrl-at91-pio4.c
View file @ c9bef4a6
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drivers/pinctrl/pinctrl-lpc18xx.c
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drivers/pinctrl/pinctrl-max77620.c
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drivers/pinctrl/pinctrl-ocelot.c
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drivers/pinctrl/pinctrl-rockchip.c
View file @ c9bef4a6
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drivers/pinctrl/pinctrl-rza1.c
View file @ c9bef4a6
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drivers/pinctrl/pinctrl-rza2.c 0 → 100644
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drivers/pinctrl/pinctrl-rzn1.c
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drivers/pinctrl/pinctrl-sx150x.c
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drivers/pinctrl/pinctrl-xway.c
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drivers/pinctrl/pinctrl-zynq.c
View file @ c9bef4a6
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drivers/pinctrl/pinmux.c
View file @ c9bef4a6
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drivers/pinctrl/qcom/pinctrl-msm.c
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drivers/pinctrl/qcom/pinctrl-msm.h
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drivers/pinctrl/qcom/pinctrl-sdm845.c
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......@@ -1300,6 +1300,7 @@ static const struct of_device_id sdm845_pinctrl_of_match[] = {
static struct platform_driver sdm845_pinctrl_driver = {
.driver = {
.name = "sdm845-pinctrl",
.pm = &msm_pinctrl_dev_pm_ops,
.of_match_table = sdm845_pinctrl_of_match,
},
.probe = sdm845_pinctrl_probe,
......
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
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drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
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drivers/pinctrl/samsung/pinctrl-samsung.c
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drivers/pinctrl/sh-pfc/core.c
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drivers/pinctrl/sh-pfc/pfc-r8a7740.c
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drivers/pinctrl/sh-pfc/pfc-r8a77470.c
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drivers/pinctrl/sh-pfc/pfc-r8a7791.c
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drivers/pinctrl/sh-pfc/pfc-r8a7792.c
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drivers/pinctrl/sh-pfc/pfc-r8a7794.c
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drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
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drivers/pinctrl/sh-pfc/pfc-r8a7795.c
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drivers/pinctrl/sh-pfc/pfc-r8a7796.c
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drivers/pinctrl/sh-pfc/pfc-r8a77965.c
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drivers/pinctrl/sh-pfc/pfc-r8a77970.c
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drivers/pinctrl/sh-pfc/pfc-r8a77980.c
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drivers/pinctrl/sh-pfc/pfc-r8a77990.c
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drivers/pinctrl/sh-pfc/pfc-r8a77995.c
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drivers/pinctrl/sh-pfc/pfc-sh7264.c
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drivers/pinctrl/sh-pfc/pfc-sh7269.c
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drivers/pinctrl/sh-pfc/pfc-sh73a0.c
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drivers/pinctrl/sh-pfc/pfc-sh7734.c
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drivers/pinctrl/sh-pfc/sh_pfc.h
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drivers/pinctrl/sprd/pinctrl-sprd.c
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drivers/pinctrl/stm32/pinctrl-stm32.c
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drivers/pinctrl/sunxi/Kconfig
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drivers/pinctrl/sunxi/Makefile
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drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
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drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c 0 → 100644
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drivers/pinctrl/sunxi/pinctrl-sunxi.c
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drivers/pinctrl/sunxi/pinctrl-sunxi.h
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drivers/pinctrl/uniphier/pinctrl-uniphier.h
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include/dt-bindings/pinctrl/bcm2835.h
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include/dt-bindings/pinctrl/mt6797-pinfunc.h 0 → 100644
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include/dt-bindings/pinctrl/pads-imx8qm.h 0 → 100644
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include/dt-bindings/pinctrl/pads-imx8qxp.h 0 → 100644
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include/dt-bindings/pinctrl/r7s9210-pinctrl.h 0 → 100644
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