Commit cf0613d2 authored by Dave Airlie's avatar Dave Airlie

Merge branch 'gma500-next' of git://github.com/patjak/drm-gma500 into drm-next

SDVO support for minnowboard

* 'gma500-next' of git://github.com/patjak/drm-gma500:
  drm/gma500/mrst: Add SDVO to output init
  drm/gma500/mrst: Don't blindly guess a mode for LVDS
  drm/gma500/mrst: Setup GMBUS for oaktrail/mrst
  drm/gma500/mrst: Replace WMs and chickenbits with values from EMGD
  drm/gma500/mrst: Add aux register writes to SDVO
  drm/gma500/mrst: Properly route oaktrail hdmi hooks
  drm/gma500/mrst: Add aux register writes when programming pipe
  drm/gma500/mrst: Add SDVO clock calculation
  drm/gma500: Add aux device support for gmbus
  drm/gma500: Add support for aux pci vdc device
  drm/gma500: Add chip specific sdvo masks
  drm/gma500: Add Minnowboard to the IS_MRST() macro
parents 8d01e1ef cd3fdbe8
...@@ -634,6 +634,7 @@ const struct psb_ops cdv_chip_ops = { ...@@ -634,6 +634,7 @@ const struct psb_ops cdv_chip_ops = {
.crtcs = 2, .crtcs = 2,
.hdmi_mask = (1 << 0) | (1 << 1), .hdmi_mask = (1 << 0) | (1 << 1),
.lvds_mask = (1 << 1), .lvds_mask = (1 << 1),
.sdvo_mask = (1 << 0),
.cursor_needs_phys = 0, .cursor_needs_phys = 0,
.sgx_offset = MRST_SGX_OFFSET, .sgx_offset = MRST_SGX_OFFSET,
.chip_setup = cdv_chip_setup, .chip_setup = cdv_chip_setup,
......
...@@ -714,7 +714,7 @@ static void psb_setup_outputs(struct drm_device *dev) ...@@ -714,7 +714,7 @@ static void psb_setup_outputs(struct drm_device *dev)
clone_mask = (1 << INTEL_OUTPUT_ANALOG); clone_mask = (1 << INTEL_OUTPUT_ANALOG);
break; break;
case INTEL_OUTPUT_SDVO: case INTEL_OUTPUT_SDVO:
crtc_mask = ((1 << 0) | (1 << 1)); crtc_mask = dev_priv->ops->sdvo_mask;
clone_mask = (1 << INTEL_OUTPUT_SDVO); clone_mask = (1 << INTEL_OUTPUT_SDVO);
break; break;
case INTEL_OUTPUT_LVDS: case INTEL_OUTPUT_LVDS:
......
...@@ -51,6 +51,9 @@ ...@@ -51,6 +51,9 @@
#define wait_for(COND, MS) _wait_for(COND, MS, 1) #define wait_for(COND, MS) _wait_for(COND, MS, 1)
#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
#define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg))
#define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg))
/* Intel GPIO access functions */ /* Intel GPIO access functions */
#define I2C_RISEFALL_TIME 20 #define I2C_RISEFALL_TIME 20
...@@ -71,7 +74,8 @@ struct intel_gpio { ...@@ -71,7 +74,8 @@ struct intel_gpio {
void void
gma_intel_i2c_reset(struct drm_device *dev) gma_intel_i2c_reset(struct drm_device *dev)
{ {
REG_WRITE(GMBUS0, 0); struct drm_psb_private *dev_priv = dev->dev_private;
GMBUS_REG_WRITE(GMBUS0, 0);
} }
static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable) static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
...@@ -98,11 +102,10 @@ static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable) ...@@ -98,11 +102,10 @@ static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
static u32 get_reserved(struct intel_gpio *gpio) static u32 get_reserved(struct intel_gpio *gpio)
{ {
struct drm_psb_private *dev_priv = gpio->dev_priv; struct drm_psb_private *dev_priv = gpio->dev_priv;
struct drm_device *dev = dev_priv->dev;
u32 reserved = 0; u32 reserved = 0;
/* On most chips, these bits must be preserved in software. */ /* On most chips, these bits must be preserved in software. */
reserved = REG_READ(gpio->reg) & reserved = GMBUS_REG_READ(gpio->reg) &
(GPIO_DATA_PULLUP_DISABLE | (GPIO_DATA_PULLUP_DISABLE |
GPIO_CLOCK_PULLUP_DISABLE); GPIO_CLOCK_PULLUP_DISABLE);
...@@ -113,29 +116,26 @@ static int get_clock(void *data) ...@@ -113,29 +116,26 @@ static int get_clock(void *data)
{ {
struct intel_gpio *gpio = data; struct intel_gpio *gpio = data;
struct drm_psb_private *dev_priv = gpio->dev_priv; struct drm_psb_private *dev_priv = gpio->dev_priv;
struct drm_device *dev = dev_priv->dev;
u32 reserved = get_reserved(gpio); u32 reserved = get_reserved(gpio);
REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK); GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
REG_WRITE(gpio->reg, reserved); GMBUS_REG_WRITE(gpio->reg, reserved);
return (REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0; return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
} }
static int get_data(void *data) static int get_data(void *data)
{ {
struct intel_gpio *gpio = data; struct intel_gpio *gpio = data;
struct drm_psb_private *dev_priv = gpio->dev_priv; struct drm_psb_private *dev_priv = gpio->dev_priv;
struct drm_device *dev = dev_priv->dev;
u32 reserved = get_reserved(gpio); u32 reserved = get_reserved(gpio);
REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK); GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
REG_WRITE(gpio->reg, reserved); GMBUS_REG_WRITE(gpio->reg, reserved);
return (REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0; return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
} }
static void set_clock(void *data, int state_high) static void set_clock(void *data, int state_high)
{ {
struct intel_gpio *gpio = data; struct intel_gpio *gpio = data;
struct drm_psb_private *dev_priv = gpio->dev_priv; struct drm_psb_private *dev_priv = gpio->dev_priv;
struct drm_device *dev = dev_priv->dev;
u32 reserved = get_reserved(gpio); u32 reserved = get_reserved(gpio);
u32 clock_bits; u32 clock_bits;
...@@ -145,15 +145,14 @@ static void set_clock(void *data, int state_high) ...@@ -145,15 +145,14 @@ static void set_clock(void *data, int state_high)
clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
GPIO_CLOCK_VAL_MASK; GPIO_CLOCK_VAL_MASK;
REG_WRITE(gpio->reg, reserved | clock_bits); GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits);
REG_READ(gpio->reg); /* Posting */ GMBUS_REG_READ(gpio->reg); /* Posting */
} }
static void set_data(void *data, int state_high) static void set_data(void *data, int state_high)
{ {
struct intel_gpio *gpio = data; struct intel_gpio *gpio = data;
struct drm_psb_private *dev_priv = gpio->dev_priv; struct drm_psb_private *dev_priv = gpio->dev_priv;
struct drm_device *dev = dev_priv->dev;
u32 reserved = get_reserved(gpio); u32 reserved = get_reserved(gpio);
u32 data_bits; u32 data_bits;
...@@ -163,8 +162,8 @@ static void set_data(void *data, int state_high) ...@@ -163,8 +162,8 @@ static void set_data(void *data, int state_high)
data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
GPIO_DATA_VAL_MASK; GPIO_DATA_VAL_MASK;
REG_WRITE(gpio->reg, reserved | data_bits); GMBUS_REG_WRITE(gpio->reg, reserved | data_bits);
REG_READ(gpio->reg); GMBUS_REG_READ(gpio->reg);
} }
static struct i2c_adapter * static struct i2c_adapter *
...@@ -251,7 +250,6 @@ gmbus_xfer(struct i2c_adapter *adapter, ...@@ -251,7 +250,6 @@ gmbus_xfer(struct i2c_adapter *adapter,
struct intel_gmbus, struct intel_gmbus,
adapter); adapter);
struct drm_psb_private *dev_priv = adapter->algo_data; struct drm_psb_private *dev_priv = adapter->algo_data;
struct drm_device *dev = dev_priv->dev;
int i, reg_offset; int i, reg_offset;
if (bus->force_bit) if (bus->force_bit)
...@@ -260,28 +258,30 @@ gmbus_xfer(struct i2c_adapter *adapter, ...@@ -260,28 +258,30 @@ gmbus_xfer(struct i2c_adapter *adapter,
reg_offset = 0; reg_offset = 0;
REG_WRITE(GMBUS0 + reg_offset, bus->reg0); GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
for (i = 0; i < num; i++) { for (i = 0; i < num; i++) {
u16 len = msgs[i].len; u16 len = msgs[i].len;
u8 *buf = msgs[i].buf; u8 *buf = msgs[i].buf;
if (msgs[i].flags & I2C_M_RD) { if (msgs[i].flags & I2C_M_RD) {
REG_WRITE(GMBUS1 + reg_offset, GMBUS_REG_WRITE(GMBUS1 + reg_offset,
GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) | GMBUS_CYCLE_WAIT |
(i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
(len << GMBUS_BYTE_COUNT_SHIFT) | (len << GMBUS_BYTE_COUNT_SHIFT) |
(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
GMBUS_SLAVE_READ | GMBUS_SW_RDY); GMBUS_SLAVE_READ | GMBUS_SW_RDY);
REG_READ(GMBUS2+reg_offset); GMBUS_REG_READ(GMBUS2+reg_offset);
do { do {
u32 val, loop = 0; u32 val, loop = 0;
if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
(GMBUS_SATOER | GMBUS_HW_RDY), 50))
goto timeout; goto timeout;
if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
goto clear_err; goto clear_err;
val = REG_READ(GMBUS3 + reg_offset); val = GMBUS_REG_READ(GMBUS3 + reg_offset);
do { do {
*buf++ = val & 0xff; *buf++ = val & 0xff;
val >>= 8; val >>= 8;
...@@ -295,18 +295,20 @@ gmbus_xfer(struct i2c_adapter *adapter, ...@@ -295,18 +295,20 @@ gmbus_xfer(struct i2c_adapter *adapter,
val |= *buf++ << (8 * loop); val |= *buf++ << (8 * loop);
} while (--len && ++loop < 4); } while (--len && ++loop < 4);
REG_WRITE(GMBUS3 + reg_offset, val); GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
REG_WRITE(GMBUS1 + reg_offset, GMBUS_REG_WRITE(GMBUS1 + reg_offset,
(i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) | (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
(msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) | (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
REG_READ(GMBUS2+reg_offset); GMBUS_REG_READ(GMBUS2+reg_offset);
while (len) { while (len) {
if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
(GMBUS_SATOER | GMBUS_HW_RDY), 50))
goto timeout; goto timeout;
if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) if (GMBUS_REG_READ(GMBUS2 + reg_offset) &
GMBUS_SATOER)
goto clear_err; goto clear_err;
val = loop = 0; val = loop = 0;
...@@ -314,14 +316,14 @@ gmbus_xfer(struct i2c_adapter *adapter, ...@@ -314,14 +316,14 @@ gmbus_xfer(struct i2c_adapter *adapter,
val |= *buf++ << (8 * loop); val |= *buf++ << (8 * loop);
} while (--len && ++loop < 4); } while (--len && ++loop < 4);
REG_WRITE(GMBUS3 + reg_offset, val); GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
REG_READ(GMBUS2+reg_offset); GMBUS_REG_READ(GMBUS2+reg_offset);
} }
} }
if (i + 1 < num && wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50)) if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
goto timeout; goto timeout;
if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
goto clear_err; goto clear_err;
} }
...@@ -332,20 +334,20 @@ gmbus_xfer(struct i2c_adapter *adapter, ...@@ -332,20 +334,20 @@ gmbus_xfer(struct i2c_adapter *adapter,
* of resetting the GMBUS controller and so clearing the * of resetting the GMBUS controller and so clearing the
* BUS_ERROR raised by the slave's NAK. * BUS_ERROR raised by the slave's NAK.
*/ */
REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
REG_WRITE(GMBUS1 + reg_offset, 0); GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0);
done: done:
/* Mark the GMBUS interface as disabled. We will re-enable it at the /* Mark the GMBUS interface as disabled. We will re-enable it at the
* start of the next xfer, till then let it sleep. * start of the next xfer, till then let it sleep.
*/ */
REG_WRITE(GMBUS0 + reg_offset, 0); GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
return i; return i;
timeout: timeout:
DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n", DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
bus->reg0 & 0xff, bus->adapter.name); bus->reg0 & 0xff, bus->adapter.name);
REG_WRITE(GMBUS0 + reg_offset, 0); GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff); bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
...@@ -399,6 +401,11 @@ int gma_intel_setup_gmbus(struct drm_device *dev) ...@@ -399,6 +401,11 @@ int gma_intel_setup_gmbus(struct drm_device *dev)
if (dev_priv->gmbus == NULL) if (dev_priv->gmbus == NULL)
return -ENOMEM; return -ENOMEM;
if (IS_MRST(dev))
dev_priv->gmbus_reg = dev_priv->aux_reg;
else
dev_priv->gmbus_reg = dev_priv->vdc_reg;
for (i = 0; i < GMBUS_NUM_PORTS; i++) { for (i = 0; i < GMBUS_NUM_PORTS; i++) {
struct intel_gmbus *bus = &dev_priv->gmbus[i]; struct intel_gmbus *bus = &dev_priv->gmbus[i];
...@@ -487,6 +494,7 @@ void gma_intel_teardown_gmbus(struct drm_device *dev) ...@@ -487,6 +494,7 @@ void gma_intel_teardown_gmbus(struct drm_device *dev)
i2c_del_adapter(&bus->adapter); i2c_del_adapter(&bus->adapter);
} }
dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */
kfree(dev_priv->gmbus); kfree(dev_priv->gmbus);
dev_priv->gmbus = NULL; dev_priv->gmbus = NULL;
} }
This diff is collapsed.
...@@ -40,6 +40,9 @@ static int oaktrail_output_init(struct drm_device *dev) ...@@ -40,6 +40,9 @@ static int oaktrail_output_init(struct drm_device *dev)
dev_err(dev->dev, "DSI is not supported\n"); dev_err(dev->dev, "DSI is not supported\n");
if (dev_priv->hdmi_priv) if (dev_priv->hdmi_priv)
oaktrail_hdmi_init(dev, &dev_priv->mode_dev); oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
psb_intel_sdvo_init(dev, SDVOB);
return 0; return 0;
} }
...@@ -526,6 +529,7 @@ static int oaktrail_chip_setup(struct drm_device *dev) ...@@ -526,6 +529,7 @@ static int oaktrail_chip_setup(struct drm_device *dev)
psb_intel_opregion_init(dev); psb_intel_opregion_init(dev);
psb_intel_init_bios(dev); psb_intel_init_bios(dev);
} }
gma_intel_setup_gmbus(dev);
oaktrail_hdmi_setup(dev); oaktrail_hdmi_setup(dev);
return 0; return 0;
} }
...@@ -534,6 +538,7 @@ static void oaktrail_teardown(struct drm_device *dev) ...@@ -534,6 +538,7 @@ static void oaktrail_teardown(struct drm_device *dev)
{ {
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
gma_intel_teardown_gmbus(dev);
oaktrail_hdmi_teardown(dev); oaktrail_hdmi_teardown(dev);
if (!dev_priv->has_gct) if (!dev_priv->has_gct)
psb_intel_destroy_bios(dev); psb_intel_destroy_bios(dev);
...@@ -546,6 +551,7 @@ const struct psb_ops oaktrail_chip_ops = { ...@@ -546,6 +551,7 @@ const struct psb_ops oaktrail_chip_ops = {
.crtcs = 2, .crtcs = 2,
.hdmi_mask = (1 << 1), .hdmi_mask = (1 << 1),
.lvds_mask = (1 << 0), .lvds_mask = (1 << 0),
.sdvo_mask = (1 << 1),
.cursor_needs_phys = 0, .cursor_needs_phys = 0,
.sgx_offset = MRST_SGX_OFFSET, .sgx_offset = MRST_SGX_OFFSET,
......
...@@ -218,30 +218,6 @@ static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = { ...@@ -218,30 +218,6 @@ static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
.commit = oaktrail_lvds_commit, .commit = oaktrail_lvds_commit,
}; };
static struct drm_display_mode lvds_configuration_modes[] = {
/* hard coded fixed mode for TPO LTPS LPJ040K001A */
{ DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 33264, 800, 836,
846, 1056, 0, 480, 489, 491, 525, 0, 0) },
/* hard coded fixed mode for LVDS 800x480 */
{ DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30994, 800, 801,
802, 1024, 0, 480, 481, 482, 525, 0, 0) },
/* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
{ DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1072,
1104, 1184, 0, 600, 603, 604, 608, 0, 0) },
/* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
{ DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1104,
1136, 1184, 0, 600, 603, 604, 608, 0, 0) },
/* hard coded fixed mode for Sharp wsvga LVDS 1024x600 */
{ DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 48885, 1024, 1124,
1204, 1312, 0, 600, 607, 610, 621, 0, 0) },
/* hard coded fixed mode for LVDS 1024x768 */
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1184, 1344, 0, 768, 771, 777, 806, 0, 0) },
/* hard coded fixed mode for LVDS 1366x768 */
{ DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 77500, 1366, 1430,
1558, 1664, 0, 768, 769, 770, 776, 0, 0) },
};
/* Returns the panel fixed mode from configuration. */ /* Returns the panel fixed mode from configuration. */
static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev, static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev,
...@@ -303,10 +279,10 @@ static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev, ...@@ -303,10 +279,10 @@ static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev,
mode_dev->panel_fixed_mode = mode_dev->panel_fixed_mode =
drm_mode_duplicate(dev, drm_mode_duplicate(dev,
dev_priv->lfp_lvds_vbt_mode); dev_priv->lfp_lvds_vbt_mode);
/* Then guess */
/* If we still got no mode then bail */
if (mode_dev->panel_fixed_mode == NULL) if (mode_dev->panel_fixed_mode == NULL)
mode_dev->panel_fixed_mode return;
= drm_mode_duplicate(dev, &lvds_configuration_modes[2]);
drm_mode_set_name(mode_dev->panel_fixed_mode); drm_mode_set_name(mode_dev->panel_fixed_mode);
drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0); drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0);
......
...@@ -373,6 +373,7 @@ const struct psb_ops psb_chip_ops = { ...@@ -373,6 +373,7 @@ const struct psb_ops psb_chip_ops = {
.crtcs = 2, .crtcs = 2,
.hdmi_mask = (1 << 0), .hdmi_mask = (1 << 0),
.lvds_mask = (1 << 1), .lvds_mask = (1 << 1),
.sdvo_mask = (1 << 0),
.cursor_needs_phys = 1, .cursor_needs_phys = 1,
.sgx_offset = PSB_SGX_OFFSET, .sgx_offset = PSB_SGX_OFFSET,
.chip_setup = psb_chip_setup, .chip_setup = psb_chip_setup,
......
...@@ -251,6 +251,12 @@ static int psb_driver_unload(struct drm_device *dev) ...@@ -251,6 +251,12 @@ static int psb_driver_unload(struct drm_device *dev)
iounmap(dev_priv->sgx_reg); iounmap(dev_priv->sgx_reg);
dev_priv->sgx_reg = NULL; dev_priv->sgx_reg = NULL;
} }
if (dev_priv->aux_reg) {
iounmap(dev_priv->aux_reg);
dev_priv->aux_reg = NULL;
}
if (dev_priv->aux_pdev)
pci_dev_put(dev_priv->aux_pdev);
/* Destroy VBT data */ /* Destroy VBT data */
psb_intel_destroy_bios(dev); psb_intel_destroy_bios(dev);
...@@ -266,7 +272,7 @@ static int psb_driver_unload(struct drm_device *dev) ...@@ -266,7 +272,7 @@ static int psb_driver_unload(struct drm_device *dev)
static int psb_driver_load(struct drm_device *dev, unsigned long chipset) static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
{ {
struct drm_psb_private *dev_priv; struct drm_psb_private *dev_priv;
unsigned long resource_start; unsigned long resource_start, resource_len;
unsigned long irqflags; unsigned long irqflags;
int ret = -ENOMEM; int ret = -ENOMEM;
struct drm_connector *connector; struct drm_connector *connector;
...@@ -296,6 +302,30 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset) ...@@ -296,6 +302,30 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
if (!dev_priv->sgx_reg) if (!dev_priv->sgx_reg)
goto out_err; goto out_err;
if (IS_MRST(dev)) {
dev_priv->aux_pdev = pci_get_bus_and_slot(0, PCI_DEVFN(3, 0));
if (dev_priv->aux_pdev) {
resource_start = pci_resource_start(dev_priv->aux_pdev,
PSB_AUX_RESOURCE);
resource_len = pci_resource_len(dev_priv->aux_pdev,
PSB_AUX_RESOURCE);
dev_priv->aux_reg = ioremap_nocache(resource_start,
resource_len);
if (!dev_priv->aux_reg)
goto out_err;
DRM_DEBUG_KMS("Found aux vdc");
} else {
/* Couldn't find the aux vdc so map to primary vdc */
dev_priv->aux_reg = dev_priv->vdc_reg;
DRM_DEBUG_KMS("Couldn't find aux pci device");
}
dev_priv->gmbus_reg = dev_priv->aux_reg;
} else {
dev_priv->gmbus_reg = dev_priv->vdc_reg;
}
psb_intel_opregion_setup(dev); psb_intel_opregion_setup(dev);
ret = dev_priv->ops->chip_setup(dev); ret = dev_priv->ops->chip_setup(dev);
......
...@@ -45,7 +45,7 @@ enum { ...@@ -45,7 +45,7 @@ enum {
}; };
#define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108) #define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108)
#define IS_MRST(dev) (((dev)->pdev->device & 0xfffc) == 0x4100) #define IS_MRST(dev) (((dev)->pdev->device & 0xfff0) == 0x4100)
#define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130) #define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130)
#define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0) #define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0)
...@@ -75,6 +75,7 @@ enum { ...@@ -75,6 +75,7 @@ enum {
* PCI resource identifiers * PCI resource identifiers
*/ */
#define PSB_MMIO_RESOURCE 0 #define PSB_MMIO_RESOURCE 0
#define PSB_AUX_RESOURCE 0
#define PSB_GATT_RESOURCE 2 #define PSB_GATT_RESOURCE 2
#define PSB_GTT_RESOURCE 3 #define PSB_GTT_RESOURCE 3
/* /*
...@@ -455,6 +456,7 @@ struct psb_ops; ...@@ -455,6 +456,7 @@ struct psb_ops;
struct drm_psb_private { struct drm_psb_private {
struct drm_device *dev; struct drm_device *dev;
struct pci_dev *aux_pdev; /* Currently only used by mrst */
const struct psb_ops *ops; const struct psb_ops *ops;
const struct psb_offset *regmap; const struct psb_offset *regmap;
...@@ -486,6 +488,7 @@ struct drm_psb_private { ...@@ -486,6 +488,7 @@ struct drm_psb_private {
uint8_t __iomem *sgx_reg; uint8_t __iomem *sgx_reg;
uint8_t __iomem *vdc_reg; uint8_t __iomem *vdc_reg;
uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
uint32_t gatt_free_offset; uint32_t gatt_free_offset;
/* /*
...@@ -532,6 +535,7 @@ struct drm_psb_private { ...@@ -532,6 +535,7 @@ struct drm_psb_private {
/* gmbus */ /* gmbus */
struct intel_gmbus *gmbus; struct intel_gmbus *gmbus;
uint8_t __iomem *gmbus_reg;
/* Used by SDVO */ /* Used by SDVO */
int crt_ddc_pin; int crt_ddc_pin;
...@@ -672,6 +676,7 @@ struct psb_ops { ...@@ -672,6 +676,7 @@ struct psb_ops {
int sgx_offset; /* Base offset of SGX device */ int sgx_offset; /* Base offset of SGX device */
int hdmi_mask; /* Mask of HDMI CRTCs */ int hdmi_mask; /* Mask of HDMI CRTCs */
int lvds_mask; /* Mask of LVDS CRTCs */ int lvds_mask; /* Mask of LVDS CRTCs */
int sdvo_mask; /* Mask of SDVO CRTCs */
int cursor_needs_phys; /* If cursor base reg need physical address */ int cursor_needs_phys; /* If cursor base reg need physical address */
/* Sub functions */ /* Sub functions */
...@@ -927,7 +932,30 @@ static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) ...@@ -927,7 +932,30 @@ static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
return ioread32(dev_priv->vdc_reg + reg); return ioread32(dev_priv->vdc_reg + reg);
} }
static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
{
struct drm_psb_private *dev_priv = dev->dev_private;
return ioread32(dev_priv->aux_reg + reg);
}
#define REG_READ(reg) REGISTER_READ(dev, (reg)) #define REG_READ(reg) REGISTER_READ(dev, (reg))
#define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
/* Useful for post reads */
static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
uint32_t reg, int aux)
{
uint32_t val;
if (aux)
val = REG_READ_AUX(reg);
else
val = REG_READ(reg);
return val;
}
#define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
uint32_t val) uint32_t val)
...@@ -936,7 +964,26 @@ static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, ...@@ -936,7 +964,26 @@ static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
iowrite32((val), dev_priv->vdc_reg + (reg)); iowrite32((val), dev_priv->vdc_reg + (reg));
} }
static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
uint32_t val)
{
struct drm_psb_private *dev_priv = dev->dev_private;
iowrite32((val), dev_priv->aux_reg + (reg));
}
#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
#define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
uint32_t val, int aux)
{
if (aux)
REG_WRITE_AUX(reg, val);
else
REG_WRITE(reg, val);
}
#define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
static inline void REGISTER_WRITE16(struct drm_device *dev, static inline void REGISTER_WRITE16(struct drm_device *dev,
uint32_t reg, uint32_t val) uint32_t reg, uint32_t val)
......
...@@ -228,24 +228,26 @@ static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u3 ...@@ -228,24 +228,26 @@ static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u3
{ {
struct drm_device *dev = psb_intel_sdvo->base.base.dev; struct drm_device *dev = psb_intel_sdvo->base.base.dev;
u32 bval = val, cval = val; u32 bval = val, cval = val;
int i; int i, j;
int need_aux = IS_MRST(dev) ? 1 : 0;
for (j = 0; j <= need_aux; j++) {
if (psb_intel_sdvo->sdvo_reg == SDVOB)
cval = REG_READ_WITH_AUX(SDVOC, j);
else
bval = REG_READ_WITH_AUX(SDVOB, j);
if (psb_intel_sdvo->sdvo_reg == SDVOB) {
cval = REG_READ(SDVOC);
} else {
bval = REG_READ(SDVOB);
}
/* /*
* Write the registers twice for luck. Sometimes, * Write the registers twice for luck. Sometimes,
* writing them only once doesn't appear to 'stick'. * writing them only once doesn't appear to 'stick'.
* The BIOS does this too. Yay, magic * The BIOS does this too. Yay, magic
*/ */
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++) {
{ REG_WRITE_WITH_AUX(SDVOB, bval, j);
REG_WRITE(SDVOB, bval); REG_READ_WITH_AUX(SDVOB, j);
REG_READ(SDVOB); REG_WRITE_WITH_AUX(SDVOC, cval, j);
REG_WRITE(SDVOC, cval); REG_READ_WITH_AUX(SDVOC, j);
REG_READ(SDVOC); }
} }
} }
...@@ -995,6 +997,7 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder, ...@@ -995,6 +997,7 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
struct psb_intel_sdvo_dtd input_dtd; struct psb_intel_sdvo_dtd input_dtd;
int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode); int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode);
int rate; int rate;
int need_aux = IS_MRST(dev) ? 1 : 0;
if (!mode) if (!mode)
return; return;
...@@ -1060,7 +1063,11 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder, ...@@ -1060,7 +1063,11 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
return; return;
/* Set the SDVO control regs. */ /* Set the SDVO control regs. */
if (need_aux)
sdvox = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
else
sdvox = REG_READ(psb_intel_sdvo->sdvo_reg); sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
switch (psb_intel_sdvo->sdvo_reg) { switch (psb_intel_sdvo->sdvo_reg) {
case SDVOB: case SDVOB:
sdvox &= SDVOB_PRESERVE_MASK; sdvox &= SDVOB_PRESERVE_MASK;
...@@ -1090,6 +1097,8 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode) ...@@ -1090,6 +1097,8 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
struct drm_device *dev = encoder->dev; struct drm_device *dev = encoder->dev;
struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
u32 temp; u32 temp;
int i;
int need_aux = IS_MRST(dev) ? 1 : 0;
switch (mode) { switch (mode) {
case DRM_MODE_DPMS_ON: case DRM_MODE_DPMS_ON:
...@@ -1108,19 +1117,27 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode) ...@@ -1108,19 +1117,27 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode); psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
if (mode == DRM_MODE_DPMS_OFF) { if (mode == DRM_MODE_DPMS_OFF) {
if (need_aux)
temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
else
temp = REG_READ(psb_intel_sdvo->sdvo_reg); temp = REG_READ(psb_intel_sdvo->sdvo_reg);
if ((temp & SDVO_ENABLE) != 0) { if ((temp & SDVO_ENABLE) != 0) {
psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE); psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
} }
} }
} else { } else {
bool input1, input2; bool input1, input2;
int i;
u8 status; u8 status;
if (need_aux)
temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
else
temp = REG_READ(psb_intel_sdvo->sdvo_reg); temp = REG_READ(psb_intel_sdvo->sdvo_reg);
if ((temp & SDVO_ENABLE) == 0) if ((temp & SDVO_ENABLE) == 0)
psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE); psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++)
gma_wait_for_vblank(dev); gma_wait_for_vblank(dev);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment