Commit cfdf1fa2 authored by Kristian Høgsberg's avatar Kristian Høgsberg Committed by Eric Anholt

drm/i915: Implement IS_* macros using static tables

Instead of using the IS_I9XX etc macros that expand to a ton of
comparisons, use new struct intel_device_info to capture the
capabilities of the different chipsets.  The drm_i915_private struct
will be initialized to point to the device info that correspond to
the actual device and this way, testing for a specific capability is
just a matter of checking a bit field.
Signed-off-by: default avatarKristian Høgsberg <krh@bitplanet.net>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 49ae35f2
...@@ -1360,7 +1360,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -1360,7 +1360,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
resource_size_t base, size; resource_size_t base, size;
int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; int ret = 0, mmio_bar;
uint32_t agp_size, prealloc_size, prealloc_start; uint32_t agp_size, prealloc_size, prealloc_start;
/* i915 has 4 more counters */ /* i915 has 4 more counters */
...@@ -1376,8 +1376,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -1376,8 +1376,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = (void *)dev_priv; dev->dev_private = (void *)dev_priv;
dev_priv->dev = dev; dev_priv->dev = dev;
dev_priv->info = (struct intel_device_info *) flags;
/* Add register map (needed for suspend/resume) */ /* Add register map (needed for suspend/resume) */
mmio_bar = IS_I9XX(dev) ? 0 : 1;
base = drm_get_resource_start(dev, mmio_bar); base = drm_get_resource_start(dev, mmio_bar);
size = drm_get_resource_len(dev, mmio_bar); size = drm_get_resource_len(dev, mmio_bar);
......
...@@ -47,46 +47,122 @@ module_param_named(powersave, i915_powersave, int, 0400); ...@@ -47,46 +47,122 @@ module_param_named(powersave, i915_powersave, int, 0400);
static struct drm_driver driver; static struct drm_driver driver;
#define INTEL_VGA_DEVICE(id) { \ #define INTEL_VGA_DEVICE(id, info) { \
.class = PCI_CLASS_DISPLAY_VGA << 8, \ .class = PCI_CLASS_DISPLAY_VGA << 8, \
.class_mask = 0xffff00, \ .class_mask = 0xffff00, \
.vendor = 0x8086, \ .vendor = 0x8086, \
.device = id, \ .device = id, \
.subvendor = PCI_ANY_ID, \ .subvendor = PCI_ANY_ID, \
.subdevice = PCI_ANY_ID, \ .subdevice = PCI_ANY_ID, \
.driver_data = 0 } .driver_data = (unsigned long) info }
static struct pci_device_id pciidlist[] = { const static struct intel_device_info intel_i830_info = {
INTEL_VGA_DEVICE(0x3577), .is_i8xx = 1, .is_mobile = 1,
INTEL_VGA_DEVICE(0x2562), };
INTEL_VGA_DEVICE(0x3582),
INTEL_VGA_DEVICE(0x2572), const static struct intel_device_info intel_845g_info = {
INTEL_VGA_DEVICE(0x2582), .is_i8xx = 1,
INTEL_VGA_DEVICE(0x258a), };
INTEL_VGA_DEVICE(0x2592),
INTEL_VGA_DEVICE(0x2772), const static struct intel_device_info intel_i85x_info = {
INTEL_VGA_DEVICE(0x27a2), .is_i8xx = 1, .is_mobile = 1,
INTEL_VGA_DEVICE(0x27ae), };
INTEL_VGA_DEVICE(0x2972),
INTEL_VGA_DEVICE(0x2982), const static struct intel_device_info intel_i865g_info = {
INTEL_VGA_DEVICE(0x2992), .is_i8xx = 1,
INTEL_VGA_DEVICE(0x29a2), };
INTEL_VGA_DEVICE(0x29b2),
INTEL_VGA_DEVICE(0x29c2), const static struct intel_device_info intel_i915g_info = {
INTEL_VGA_DEVICE(0x29d2), .is_i915g = 1, .is_i9xx = 1,
INTEL_VGA_DEVICE(0x2a02), };
INTEL_VGA_DEVICE(0x2a12), const static struct intel_device_info intel_i915gm_info = {
INTEL_VGA_DEVICE(0x2a42), .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
INTEL_VGA_DEVICE(0x2e02), };
INTEL_VGA_DEVICE(0x2e12), const static struct intel_device_info intel_i945g_info = {
INTEL_VGA_DEVICE(0x2e22), .is_i9xx = 1, .has_hotplug = 1,
INTEL_VGA_DEVICE(0x2e32), };
INTEL_VGA_DEVICE(0x2e42), const static struct intel_device_info intel_i945gm_info = {
INTEL_VGA_DEVICE(0xa001), .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
INTEL_VGA_DEVICE(0xa011), .has_hotplug = 1,
INTEL_VGA_DEVICE(0x35e8), };
INTEL_VGA_DEVICE(0x0042),
INTEL_VGA_DEVICE(0x0046), const static struct intel_device_info intel_i965g_info = {
.is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
};
const static struct intel_device_info intel_i965gm_info = {
.is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
.is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_g33_info = {
.is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_g45_info = {
.is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
.has_pipe_cxsr = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_gm45_info = {
.is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
.has_pipe_cxsr = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_pineview_info = {
.is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
.has_pipe_cxsr = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_ironlake_d_info = {
.is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
.has_pipe_cxsr = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_ironlake_m_info = {
.is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
.need_gfx_hws = 1, .has_rc6 = 1,
.has_hotplug = 1,
};
const static struct pci_device_id pciidlist[] = {
INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
{0, 0, 0} {0, 0, 0}
}; };
......
...@@ -172,9 +172,30 @@ struct drm_i915_display_funcs { ...@@ -172,9 +172,30 @@ struct drm_i915_display_funcs {
struct intel_overlay; struct intel_overlay;
struct intel_device_info {
u8 is_mobile : 1;
u8 is_i8xx : 1;
u8 is_i915g : 1;
u8 is_i9xx : 1;
u8 is_i945gm : 1;
u8 is_i965g : 1;
u8 is_i965gm : 1;
u8 is_g33 : 1;
u8 need_gfx_hws : 1;
u8 is_g4x : 1;
u8 is_pineview : 1;
u8 is_ironlake : 1;
u8 has_fbc : 1;
u8 has_rc6 : 1;
u8 has_pipe_cxsr : 1;
u8 has_hotplug : 1;
};
typedef struct drm_i915_private { typedef struct drm_i915_private {
struct drm_device *dev; struct drm_device *dev;
const struct intel_device_info *info;
int has_gem; int has_gem;
void __iomem *regs; void __iomem *regs;
...@@ -983,67 +1004,33 @@ extern void g4x_disable_fbc(struct drm_device *dev); ...@@ -983,67 +1004,33 @@ extern void g4x_disable_fbc(struct drm_device *dev);
extern int i915_wrap_ring(struct drm_device * dev); extern int i915_wrap_ring(struct drm_device * dev);
extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define IS_I830(dev) ((dev)->pci_device == 0x3577) #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
#define IS_845G(dev) ((dev)->pci_device == 0x2562)
#define IS_I85X(dev) ((dev)->pci_device == 0x3582) #define IS_I830(dev) ((dev)->pci_device == 0x3577)
#define IS_I865G(dev) ((dev)->pci_device == 0x2572) #define IS_845G(dev) ((dev)->pci_device == 0x2562)
#define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || IS_I865G(dev)) #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) #define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx)
#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
#define IS_I945G(dev) ((dev)->pci_device == 0x2772) #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
(dev)->pci_device == 0x27AE) #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
(dev)->pci_device == 0x2982 || \ #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
(dev)->pci_device == 0x2992 || \ #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
(dev)->pci_device == 0x29A2 || \ #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
(dev)->pci_device == 0x2A02 || \ #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
(dev)->pci_device == 0x2A12 || \ #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
(dev)->pci_device == 0x2A42 || \ #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
(dev)->pci_device == 0x2E02 || \ #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
(dev)->pci_device == 0x2E12 || \
(dev)->pci_device == 0x2E22 || \
(dev)->pci_device == 0x2E32 || \
(dev)->pci_device == 0x2E42 || \
(dev)->pci_device == 0x0042 || \
(dev)->pci_device == 0x0046)
#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
(dev)->pci_device == 0x2A12)
#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
(dev)->pci_device == 0x2E12 || \
(dev)->pci_device == 0x2E22 || \
(dev)->pci_device == 0x2E32 || \
(dev)->pci_device == 0x2E42 || \
IS_GM45(dev))
#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
#define IS_PINEVIEW(dev) (IS_PINEVIEW_G(dev) || IS_PINEVIEW_M(dev))
#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
(dev)->pci_device == 0x29B2 || \
(dev)->pci_device == 0x29D2 || \
(IS_PINEVIEW(dev)))
#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
#define IS_IRONLAKE(dev) (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev)) #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
IS_IRONLAKE(dev))
#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
IS_PINEVIEW(dev) || IS_IRONLAKE_M(dev))
#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
IS_IRONLAKE(dev))
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming. * rows, which changed the alignment requirements and fence programming.
*/ */
...@@ -1055,17 +1042,14 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); ...@@ -1055,17 +1042,14 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
!IS_IRONLAKE(dev) && !IS_PINEVIEW(dev)) !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev)) #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
/* dsparb controlled by hw only */ /* dsparb controlled by hw only */
#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \ #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
(IS_I9XX(dev) || IS_GM45(dev)) && \ #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
!IS_PINEVIEW(dev) && \
!IS_IRONLAKE(dev))
#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IRONLAKE_M(dev))
#define PRIMARY_RINGBUFFER_SIZE (128*1024) #define PRIMARY_RINGBUFFER_SIZE (128*1024)
......
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