Commit d074aeb8 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman

staging: comedi: amcc_s5933.h: tidy up comment issues

Tidy up the comments to fix the checkpatch.pl isses:
WARNING: Block comments use * on subsequent lines
WARNING: line over 80 characters
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c0cb87af
/* /*
comedi/drivers/amcc_s5933.h * Stuff for AMCC S5933 PCI Controller
*
Stuff for AMCC S5933 PCI Controller * Author: Michal Dobes <dobes@tesnet.cz>
*
Author: Michal Dobes <dobes@tesnet.cz> * Inspirated from general-purpose AMCC S5933 PCI Matchmaker driver
* made by Andrea Cisternino <acister@pcape1.pi.infn.it>
Inspirated from general-purpose AMCC S5933 PCI Matchmaker driver * and as result of espionage from MITE code made by David A. Schleef.
made by Andrea Cisternino <acister@pcape1.pi.infn.it> * Thanks to AMCC for their on-line documentation and bus master DMA
and as result of espionage from MITE code made by David A. Schleef. * example.
Thanks to AMCC for their on-line documentation and bus master DMA */
example.
*/
#ifndef _AMCC_S5933_H_ #ifndef _AMCC_S5933_H_
#define _AMCC_S5933_H_ #define _AMCC_S5933_H_
...@@ -58,7 +56,7 @@ ...@@ -58,7 +56,7 @@
#define INTCSR_INTR_ASSERTED 0x800000 #define INTCSR_INTR_ASSERTED 0x800000
/****************************************************************************/ /****************************************************************************/
/* AMCC - PCI non-volatile ram command register (byte 3 of master control/status register) */ /* AMCC - PCI non-volatile ram command register (byte 3 of AMCC_OP_REG_MCSR) */
/****************************************************************************/ /****************************************************************************/
#define MCSR_NV_LOAD_LOW_ADDR 0x0 #define MCSR_NV_LOAD_LOW_ADDR 0x0
#define MCSR_NV_LOAD_HIGH_ADDR 0x20 #define MCSR_NV_LOAD_HIGH_ADDR 0x20
......
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