Commit d4988d4c authored by Rafał Miłecki's avatar Rafał Miłecki Committed by John W. Linville

bcma: add more core IDs

PCIe and ARM CR4 cores were found on 14e4:43b1 AKA BCM4352.
Reported-by: default avatarGabriel Thörnblad <gabriel@thornblad.com>
Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent becdbc59
...@@ -84,6 +84,8 @@ static const struct bcma_device_id_name bcma_bcm_device_names[] = { ...@@ -84,6 +84,8 @@ static const struct bcma_device_id_name bcma_bcm_device_names[] = {
{ BCMA_CORE_I2S, "I2S" }, { BCMA_CORE_I2S, "I2S" },
{ BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" }, { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
{ BCMA_CORE_SHIM, "SHIM" }, { BCMA_CORE_SHIM, "SHIM" },
{ BCMA_CORE_PCIE2, "PCIe Gen2" },
{ BCMA_CORE_ARM_CR4, "ARM CR4" },
{ BCMA_CORE_DEFAULT, "Default" }, { BCMA_CORE_DEFAULT, "Default" },
}; };
......
...@@ -134,7 +134,10 @@ struct bcma_host_ops { ...@@ -134,7 +134,10 @@ struct bcma_host_ops {
#define BCMA_CORE_I2S 0x834 #define BCMA_CORE_I2S 0x834
#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */ #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */ #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
#define BCMA_CORE_ARM_CR4 0x83e #define BCMA_CORE_PHY_AC 0x83B
#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
#define BCMA_CORE_USB30_DEV 0x83D
#define BCMA_CORE_ARM_CR4 0x83E
#define BCMA_CORE_DEFAULT 0xFFF #define BCMA_CORE_DEFAULT 0xFFF
#define BCMA_MAX_NR_CORES 16 #define BCMA_MAX_NR_CORES 16
......
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