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Commit d5b5d9d4 authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'regulator/topic/lp8755',... 

Merge remote-tracking branches 'regulator/topic/lp8755', 'regulator/topic/ltc3589', 'regulator/topic/max8952', 'regulator/topic/mc13xxx' and 'regulator/topic/palmas' into regulator-next
parents a627506a 57135250 53ddddca d7da152c 7dd33c1d b632815e
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Documentation/devicetree/bindings/mfd/palmas.txt
View file @ d5b5d9d4
......@@ -6,6 +6,7 @@ twl6037 (palmas)
tps65913 (palmas)
tps65914 (palmas)
tps659038
tps65917
Required properties:
- compatible : Should be from the list
......@@ -16,6 +17,7 @@ Required properties:
ti,tps65914
ti,tps80036
ti,tps659038
ti,tps65917
and also the generic series names
ti,palmas
- interrupt-controller : palmas has its own internal IRQs
......
Documentation/devicetree/bindings/regulator/palmas-pmic.txt
View file @ d5b5d9d4
......@@ -7,6 +7,7 @@ Required properties:
ti,twl6037-pmic
ti,tps65913-pmic
ti,tps65914-pmic
ti,tps65917-pmic
and also the generic series names
ti,palmas-pmic
- interrupt-parent : The parent interrupt controller which is palmas.
......
drivers/mfd/palmas.c
View file @ d5b5d9d4
......@@ -25,52 +25,6 @@
#include <linux/mfd/palmas.h>
#include <linux/of_device.h>
#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
PALMAS_EXT_CONTROL_ENABLE2 | \
PALMAS_EXT_CONTROL_NSLEEP)
struct palmas_sleep_requestor_info {
int id;
int reg_offset;
int bit_pos;
};
#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
[PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
.id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
.reg_offset = _offset, \
.bit_pos = _pos, \
}
static struct palmas_sleep_requestor_info sleep_req_info[] = {
EXTERNAL_REQUESTOR(REGEN1, 0, 0),
EXTERNAL_REQUESTOR(REGEN2, 0, 1),
EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
EXTERNAL_REQUESTOR(REGEN3, 0, 6),
EXTERNAL_REQUESTOR(SMPS12, 1, 0),
EXTERNAL_REQUESTOR(SMPS3, 1, 1),
EXTERNAL_REQUESTOR(SMPS45, 1, 2),
EXTERNAL_REQUESTOR(SMPS6, 1, 3),
EXTERNAL_REQUESTOR(SMPS7, 1, 4),
EXTERNAL_REQUESTOR(SMPS8, 1, 5),
EXTERNAL_REQUESTOR(SMPS9, 1, 6),
EXTERNAL_REQUESTOR(SMPS10, 1, 7),
EXTERNAL_REQUESTOR(LDO1, 2, 0),
EXTERNAL_REQUESTOR(LDO2, 2, 1),
EXTERNAL_REQUESTOR(LDO3, 2, 2),
EXTERNAL_REQUESTOR(LDO4, 2, 3),
EXTERNAL_REQUESTOR(LDO5, 2, 4),
EXTERNAL_REQUESTOR(LDO6, 2, 5),
EXTERNAL_REQUESTOR(LDO7, 2, 6),
EXTERNAL_REQUESTOR(LDO8, 2, 7),
EXTERNAL_REQUESTOR(LDO9, 3, 0),
EXTERNAL_REQUESTOR(LDOLN, 3, 1),
EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
};
static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
{
.reg_bits = 8,
......@@ -92,6 +46,133 @@ static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
},
};
static const struct regmap_irq tps65917_irqs[] = {
/* INT1 IRQs */
[TPS65917_RESERVED1] = {
.mask = TPS65917_RESERVED,
},
[TPS65917_PWRON_IRQ] = {
.mask = TPS65917_INT1_STATUS_PWRON,
},
[TPS65917_LONG_PRESS_KEY_IRQ] = {
.mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
},
[TPS65917_RESERVED2] = {
.mask = TPS65917_RESERVED,
},
[TPS65917_PWRDOWN_IRQ] = {
.mask = TPS65917_INT1_STATUS_PWRDOWN,
},
[TPS65917_HOTDIE_IRQ] = {
.mask = TPS65917_INT1_STATUS_HOTDIE,
},
[TPS65917_VSYS_MON_IRQ] = {
.mask = TPS65917_INT1_STATUS_VSYS_MON,
},
[TPS65917_RESERVED3] = {
.mask = TPS65917_RESERVED,
},
/* INT2 IRQs*/
[TPS65917_RESERVED4] = {
.mask = TPS65917_RESERVED,
.reg_offset = 1,
},
[TPS65917_OTP_ERROR_IRQ] = {
.mask = TPS65917_INT2_STATUS_OTP_ERROR,
.reg_offset = 1,
},
[TPS65917_WDT_IRQ] = {
.mask = TPS65917_INT2_STATUS_WDT,
.reg_offset = 1,
},
[TPS65917_RESERVED5] = {
.mask = TPS65917_RESERVED,
.reg_offset = 1,
},
[TPS65917_RESET_IN_IRQ] = {
.mask = TPS65917_INT2_STATUS_RESET_IN,
.reg_offset = 1,
},
[TPS65917_FSD_IRQ] = {
.mask = TPS65917_INT2_STATUS_FSD,
.reg_offset = 1,
},
[TPS65917_SHORT_IRQ] = {
.mask = TPS65917_INT2_STATUS_SHORT,
.reg_offset = 1,
},
[TPS65917_RESERVED6] = {
.mask = TPS65917_RESERVED,
.reg_offset = 1,
},
/* INT3 IRQs */
[TPS65917_GPADC_AUTO_0_IRQ] = {
.mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
.reg_offset = 2,
},
[TPS65917_GPADC_AUTO_1_IRQ] = {
.mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
.reg_offset = 2,
},
[TPS65917_GPADC_EOC_SW_IRQ] = {
.mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
.reg_offset = 2,
},
[TPS65917_RESREVED6] = {
.mask = TPS65917_RESERVED6,
.reg_offset = 2,
},
[TPS65917_RESERVED7] = {
.mask = TPS65917_RESERVED,
.reg_offset = 2,
},
[TPS65917_RESERVED8] = {
.mask = TPS65917_RESERVED,
.reg_offset = 2,
},
[TPS65917_RESERVED9] = {
.mask = TPS65917_RESERVED,
.reg_offset = 2,
},
[TPS65917_VBUS_IRQ] = {
.mask = TPS65917_INT3_STATUS_VBUS,
.reg_offset = 2,
},
/* INT4 IRQs */
[TPS65917_GPIO_0_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_0,
.reg_offset = 3,
},
[TPS65917_GPIO_1_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_1,
.reg_offset = 3,
},
[TPS65917_GPIO_2_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_2,
.reg_offset = 3,
},
[TPS65917_GPIO_3_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_3,
.reg_offset = 3,
},
[TPS65917_GPIO_4_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_4,
.reg_offset = 3,
},
[TPS65917_GPIO_5_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_5,
.reg_offset = 3,
},
[TPS65917_GPIO_6_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_6,
.reg_offset = 3,
},
[TPS65917_RESERVED10] = {
.mask = TPS65917_RESERVED10,
.reg_offset = 3,
},
};
static const struct regmap_irq palmas_irqs[] = {
/* INT1 IRQs */
[PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
......@@ -232,13 +313,26 @@ static struct regmap_irq_chip palmas_irq_chip = {
PALMAS_INT1_MASK),
};
static struct regmap_irq_chip tps65917_irq_chip = {
.name = "tps65917",
.irqs = tps65917_irqs,
.num_irqs = ARRAY_SIZE(tps65917_irqs),
.num_regs = 4,
.irq_reg_stride = 5,
.status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
PALMAS_INT1_STATUS),
.mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
PALMAS_INT1_MASK),
};
int palmas_ext_control_req_config(struct palmas *palmas,
enum palmas_external_requestor_id id, int ext_ctrl, bool enable)
{
struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata;
int preq_mask_bit = 0;
int reg_add = 0;
int bit_pos;
int ret;
int bit_pos, ret;
if (!(ext_ctrl & PALMAS_EXT_REQ))
return 0;
......@@ -257,8 +351,8 @@ int palmas_ext_control_req_config(struct palmas *palmas,
preq_mask_bit = 2;
}
bit_pos = sleep_req_info[id].bit_pos;
reg_add += sleep_req_info[id].reg_offset;
bit_pos = pmic_ddata->sleep_req_info[id].bit_pos;
reg_add += pmic_ddata->sleep_req_info[id].reg_offset;
if (enable)
ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
reg_add, BIT(bit_pos), BIT(bit_pos));
......@@ -357,14 +451,38 @@ static void palmas_power_off(void)
static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
static unsigned int tps659038_features;
struct palmas_driver_data {
unsigned int *features;
struct regmap_irq_chip *irq_chip;
};
static struct palmas_driver_data palmas_data = {
.features = &palmas_features,
.irq_chip = &palmas_irq_chip,
};
static struct palmas_driver_data tps659038_data = {
.features = &tps659038_features,
.irq_chip = &palmas_irq_chip,
};
static struct palmas_driver_data tps65917_data = {
.features = &tps659038_features,
.irq_chip = &tps65917_irq_chip,
};
static const struct of_device_id of_palmas_match_tbl[] = {
{
.compatible = "ti,palmas",
.data = &palmas_features,
.data = &palmas_data,
},
{
.compatible = "ti,tps659038",
.data = &tps659038_features,
.data = &tps659038_data,
},
{
.compatible = "ti,tps65917",
.data = &tps65917_data,
},
{ },
};
......@@ -375,9 +493,10 @@ static int palmas_i2c_probe(struct i2c_client *i2c,
{
struct palmas *palmas;
struct palmas_platform_data *pdata;
struct palmas_driver_data *driver_data;
struct device_node *node = i2c->dev.of_node;
int ret = 0, i;
unsigned int reg, addr, *features;
unsigned int reg, addr;
int slave;
const struct of_device_id *match;
......@@ -408,8 +527,8 @@ static int palmas_i2c_probe(struct i2c_client *i2c,
if (!match)
return -ENODATA;
features = (unsigned int *)match->data;
palmas->features = *features;
driver_data = (struct palmas_driver_data *)match->data;
palmas->features = *driver_data->features;
for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
if (i == 0)
......@@ -463,8 +582,8 @@ static int palmas_i2c_probe(struct i2c_client *i2c,
regmap_write(palmas->regmap[slave], addr, reg);
ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
IRQF_ONESHOT | pdata->irq_flags, 0, &palmas_irq_chip,
&palmas->irq_data);
IRQF_ONESHOT | pdata->irq_flags, 0,
driver_data->irq_chip, &palmas->irq_data);
if (ret < 0)
goto err_i2c;
......
drivers/regulator/lp8755.c
View file @ d5b5d9d4
......@@ -339,22 +339,18 @@ static int lp8755_regulator_init(struct lp8755_chip *pchip)
rconfig.init_data = pdata->buck_data[buck_num];
rconfig.of_node = pchip->dev->of_node;
pchip->rdev[buck_num] =
regulator_register(&lp8755_regulators[buck_num], &rconfig);
devm_regulator_register(pchip->dev,
&lp8755_regulators[buck_num], &rconfig);
if (IS_ERR(pchip->rdev[buck_num])) {
ret = PTR_ERR(pchip->rdev[buck_num]);
pchip->rdev[buck_num] = NULL;
dev_err(pchip->dev, "regulator init failed: buck %d\n",
buck_num);
goto err_buck;
return ret;
}
}
return 0;
err_buck:
for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
regulator_unregister(pchip->rdev[icnt]);
return ret;
}
static irqreturn_t lp8755_irq_handler(int irq, void *data)
......@@ -490,23 +486,19 @@ static int lp8755_probe(struct i2c_client *client,
ret = lp8755_regulator_init(pchip);
if (ret < 0) {
dev_err(&client->dev, "fail to initialize regulators\n");
goto err_regulator;
goto err;
}
pchip->irq = client->irq;
ret = lp8755_int_config(pchip);
if (ret < 0) {
dev_err(&client->dev, "fail to irq config\n");
goto err_irq;
goto err;
}
return ret;
err_irq:
for (icnt = 0; icnt < mphase_buck[pchip->mphase].nreg; icnt++)
regulator_unregister(pchip->rdev[icnt]);
err_regulator:
err:
/* output disable */
for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
lp8755_write(pchip, icnt, 0x00);
......@@ -519,9 +511,6 @@ static int lp8755_remove(struct i2c_client *client)
int icnt;
struct lp8755_chip *pchip = i2c_get_clientdata(client);
for (icnt = 0; icnt < mphase_buck[pchip->mphase].nreg; icnt++)
regulator_unregister(pchip->rdev[icnt]);
for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
lp8755_write(pchip, icnt, 0x00);
......
drivers/regulator/ltc3589.c
View file @ d5b5d9d4
......@@ -377,7 +377,7 @@ static bool ltc3589_volatile_reg(struct device *dev, unsigned int reg)
return false;
}
struct reg_default ltc3589_reg_defaults[] = {
static struct reg_default ltc3589_reg_defaults[] = {
{ LTC3589_SCR1, 0x00 },
{ LTC3589_OVEN, 0x00 },
{ LTC3589_SCR2, 0x00 },
......
drivers/regulator/max8952.c
View file @ d5b5d9d4
......@@ -229,7 +229,6 @@ static int max8952_pmic_probe(struct i2c_client *client,
config.ena_gpio_flags |= GPIOF_OUT_INIT_HIGH;
rdev = devm_regulator_register(&client->dev, &regulator, &config);
if (IS_ERR(rdev)) {
ret = PTR_ERR(rdev);
dev_err(&client->dev, "regulator init failed (%d)\n", ret);
......@@ -241,21 +240,19 @@ static int max8952_pmic_probe(struct i2c_client *client,
if (gpio_is_valid(pdata->gpio_vid0) &&
gpio_is_valid(pdata->gpio_vid1)) {
if (!gpio_request(pdata->gpio_vid0, "MAX8952 VID0"))
gpio_direction_output(pdata->gpio_vid0,
(pdata->default_mode) & 0x1);
else
unsigned long gpio_flags;
gpio_flags = max8952->vid0 ?
GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
if (devm_gpio_request_one(&client->dev, pdata->gpio_vid0,
gpio_flags, "MAX8952 VID0"))
err = 1;
if (!gpio_request(pdata->gpio_vid1, "MAX8952 VID1"))
gpio_direction_output(pdata->gpio_vid1,
(pdata->default_mode >> 1) & 0x1);
else {
if (!err)
gpio_free(pdata->gpio_vid0);
gpio_flags = max8952->vid1 ?
GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
if (devm_gpio_request_one(&client->dev, pdata->gpio_vid1,
gpio_flags, "MAX8952 VID1"))
err = 2;
}
} else
err = 3;
......@@ -314,16 +311,6 @@ static int max8952_pmic_probe(struct i2c_client *client,
return 0;
}
static int max8952_pmic_remove(struct i2c_client *client)
{
struct max8952_data *max8952 = i2c_get_clientdata(client);
struct max8952_platform_data *pdata = max8952->pdata;
gpio_free(pdata->gpio_vid0);
gpio_free(pdata->gpio_vid1);
return 0;
}
static const struct i2c_device_id max8952_ids[] = {
{ "max8952", 0 },
{ },
......@@ -332,7 +319,6 @@ MODULE_DEVICE_TABLE(i2c, max8952_ids);
static struct i2c_driver max8952_pmic_driver = {
.probe = max8952_pmic_probe,
.remove = max8952_pmic_remove,
.driver = {
.name = "max8952",
.of_match_table = of_match_ptr(max8952_dt_match),
......
drivers/regulator/mc13xxx-regulator-core.c
View file @ d5b5d9d4
......@@ -33,17 +33,12 @@ static int mc13xxx_regulator_enable(struct regulator_dev *rdev)
struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
int id = rdev_get_id(rdev);
int ret;
dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
mc13xxx_lock(priv->mc13xxx);
ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg,
mc13xxx_regulators[id].enable_bit,
mc13xxx_regulators[id].enable_bit);
mc13xxx_unlock(priv->mc13xxx);
return ret;
return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg,
mc13xxx_regulators[id].enable_bit,
mc13xxx_regulators[id].enable_bit);
}
static int mc13xxx_regulator_disable(struct regulator_dev *rdev)
......@@ -51,16 +46,11 @@ static int mc13xxx_regulator_disable(struct regulator_dev *rdev)
struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
int id = rdev_get_id(rdev);
int ret;
dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
mc13xxx_lock(priv->mc13xxx);
ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg,
mc13xxx_regulators[id].enable_bit, 0);
mc13xxx_unlock(priv->mc13xxx);
return ret;
return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg,
mc13xxx_regulators[id].enable_bit, 0);
}
static int mc13xxx_regulator_is_enabled(struct regulator_dev *rdev)
......@@ -70,10 +60,7 @@ static int mc13xxx_regulator_is_enabled(struct regulator_dev *rdev)
int ret, id = rdev_get_id(rdev);
unsigned int val;
mc13xxx_lock(priv->mc13xxx);
ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
mc13xxx_unlock(priv->mc13xxx);
if (ret)
return ret;
......@@ -86,15 +73,10 @@ static int mc13xxx_regulator_set_voltage_sel(struct regulator_dev *rdev,
struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
int id = rdev_get_id(rdev);
int ret;
mc13xxx_lock(priv->mc13xxx);
ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].vsel_reg,
mc13xxx_regulators[id].vsel_mask,
selector << mc13xxx_regulators[id].vsel_shift);
mc13xxx_unlock(priv->mc13xxx);
return ret;
return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].vsel_reg,
mc13xxx_regulators[id].vsel_mask,
selector << mc13xxx_regulators[id].vsel_shift);
}
static int mc13xxx_regulator_get_voltage(struct regulator_dev *rdev)
......@@ -106,11 +88,8 @@ static int mc13xxx_regulator_get_voltage(struct regulator_dev *rdev)
dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
mc13xxx_lock(priv->mc13xxx);
ret = mc13xxx_reg_read(priv->mc13xxx,
mc13xxx_regulators[id].vsel_reg, &val);
mc13xxx_unlock(priv->mc13xxx);
if (ret)
return ret;
......
drivers/regulator/mc13xxx.h
View file @ d5b5d9d4
......@@ -21,7 +21,6 @@ struct mc13xxx_regulator {
int vsel_reg;
int vsel_shift;
int vsel_mask;
int hi_bit;
};
struct mc13xxx_regulator_priv {
......
drivers/regulator/palmas-regulator.c
View file @ d5b5d9d4
......@@ -27,15 +27,6 @@
#include <linux/of_platform.h>
#include <linux/regulator/of_regulator.h>
struct regs_info {
char *name;
char *sname;
u8 vsel_addr;
u8 ctrl_addr;
u8 tstep_addr;
int sleep_id;
};
static const struct regulator_linear_range smps_low_ranges[] = {
REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0),
......@@ -50,7 +41,7 @@ static const struct regulator_linear_range smps_high_ranges[] = {
REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0),
};
static const struct regs_info palmas_regs_info[] = {
static struct palmas_regs_info palmas_generic_regs_info[] = {
{
.name = "SMPS12",
.sname = "smps1-in",
......@@ -236,6 +227,153 @@ static const struct regs_info palmas_regs_info[] = {
},
};
static struct palmas_regs_info tps65917_regs_info[] = {
{
.name = "SMPS1",
.sname = "smps1-in",
.vsel_addr = TPS65917_SMPS1_VOLTAGE,
.ctrl_addr = TPS65917_SMPS1_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
},
{
.name = "SMPS2",
.sname = "smps2-in",
.vsel_addr = TPS65917_SMPS2_VOLTAGE,
.ctrl_addr = TPS65917_SMPS2_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
},
{
.name = "SMPS3",
.sname = "smps3-in",
.vsel_addr = TPS65917_SMPS3_VOLTAGE,
.ctrl_addr = TPS65917_SMPS3_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
},
{
.name = "SMPS4",
.sname = "smps4-in",
.vsel_addr = TPS65917_SMPS4_VOLTAGE,
.ctrl_addr = TPS65917_SMPS4_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
},
{
.name = "SMPS5",
.sname = "smps5-in",
.vsel_addr = TPS65917_SMPS5_VOLTAGE,
.ctrl_addr = TPS65917_SMPS5_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
},
{
.name = "LDO1",
.sname = "ldo1-in",
.vsel_addr = TPS65917_LDO1_VOLTAGE,
.ctrl_addr = TPS65917_LDO1_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1,
},
{
.name = "LDO2",
.sname = "ldo2-in",
.vsel_addr = TPS65917_LDO2_VOLTAGE,
.ctrl_addr = TPS65917_LDO2_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2,
},
{
.name = "LDO3",
.sname = "ldo3-in",
.vsel_addr = TPS65917_LDO3_VOLTAGE,
.ctrl_addr = TPS65917_LDO3_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3,
},
{
.name = "LDO4",
.sname = "ldo4-in",
.vsel_addr = TPS65917_LDO4_VOLTAGE,
.ctrl_addr = TPS65917_LDO4_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4,
},
{
.name = "LDO5",
.sname = "ldo5-in",
.vsel_addr = TPS65917_LDO5_VOLTAGE,
.ctrl_addr = TPS65917_LDO5_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5,
},
{
.name = "REGEN1",
.ctrl_addr = TPS65917_REGEN1_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
},
{
.name = "REGEN2",
.ctrl_addr = TPS65917_REGEN2_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
},
{
.name = "REGEN3",
.ctrl_addr = TPS65917_REGEN3_CTRL,
.sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
},
};
#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
[PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
.id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
.reg_offset = _offset, \
.bit_pos = _pos, \
}
static struct palmas_sleep_requestor_info palma_sleep_req_info[] = {
EXTERNAL_REQUESTOR(REGEN1, 0, 0),
EXTERNAL_REQUESTOR(REGEN2, 0, 1),
EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
EXTERNAL_REQUESTOR(REGEN3, 0, 6),
EXTERNAL_REQUESTOR(SMPS12, 1, 0),
EXTERNAL_REQUESTOR(SMPS3, 1, 1),
EXTERNAL_REQUESTOR(SMPS45, 1, 2),
EXTERNAL_REQUESTOR(SMPS6, 1, 3),
EXTERNAL_REQUESTOR(SMPS7, 1, 4),
EXTERNAL_REQUESTOR(SMPS8, 1, 5),
EXTERNAL_REQUESTOR(SMPS9, 1, 6),
EXTERNAL_REQUESTOR(SMPS10, 1, 7),
EXTERNAL_REQUESTOR(LDO1, 2, 0),
EXTERNAL_REQUESTOR(LDO2, 2, 1),
EXTERNAL_REQUESTOR(LDO3, 2, 2),
EXTERNAL_REQUESTOR(LDO4, 2, 3),
EXTERNAL_REQUESTOR(LDO5, 2, 4),
EXTERNAL_REQUESTOR(LDO6, 2, 5),
EXTERNAL_REQUESTOR(LDO7, 2, 6),
EXTERNAL_REQUESTOR(LDO8, 2, 7),
EXTERNAL_REQUESTOR(LDO9, 3, 0),
EXTERNAL_REQUESTOR(LDOLN, 3, 1),
EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
};
#define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \
[TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
.id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \
.reg_offset = _offset, \
.bit_pos = _pos, \
}
static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = {
EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0),
EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1),
EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6),
EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0),
EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1),
EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2),
EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3),
EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4),
EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0),
EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1),
EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2),
EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3),
EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4),
};
static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
#define SMPS_CTRL_MODE_OFF 0x00
......@@ -296,12 +434,15 @@ static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
{
struct palmas_pmic *pmic = rdev_get_drvdata(dev);
int id = rdev_get_id(dev);
struct palmas_pmic *pmic = rdev_get_drvdata(dev);
struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
unsigned int reg;
bool rail_enable = true;
palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, &reg);
reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
if (reg == SMPS_CTRL_MODE_OFF)
......@@ -323,8 +464,7 @@ static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
if (rail_enable)
palmas_smps_write(pmic->palmas,
palmas_regs_info[id].ctrl_addr, reg);
palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg);
/* Switch the enable value to ensure this is used for enable */
pmic->desc[id].enable_val = pmic->current_reg_mode[id];
......@@ -355,10 +495,11 @@ static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
int ramp_delay)
{
struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
int id = rdev_get_id(rdev);
struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
unsigned int reg = 0;
unsigned int addr = palmas_regs_info[id].tstep_addr;
int ret;
/* SMPS3 and SMPS7 do not have tstep_addr setting */
......@@ -377,7 +518,7 @@ static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
else
reg = 1;
ret = palmas_smps_write(pmic->palmas, addr, reg);
ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg);
if (ret < 0) {
dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
return ret;
......@@ -424,13 +565,37 @@ static struct regulator_ops palmas_ops_smps10 = {
.get_bypass = regulator_get_bypass_regmap,
};
static struct regulator_ops tps65917_ops_smps = {
.is_enabled = regulator_is_enabled_regmap,
.enable = regulator_enable_regmap,
.disable = regulator_disable_regmap,
.set_mode = palmas_set_mode_smps,
.get_mode = palmas_get_mode_smps,
.get_voltage_sel = regulator_get_voltage_sel_regmap,
.set_voltage_sel = regulator_set_voltage_sel_regmap,
.list_voltage = regulator_list_voltage_linear_range,
.map_voltage = regulator_map_voltage_linear_range,
.set_voltage_time_sel = regulator_set_voltage_time_sel,
};
static struct regulator_ops tps65917_ops_ext_control_smps = {
.set_mode = palmas_set_mode_smps,
.get_mode = palmas_get_mode_smps,
.get_voltage_sel = regulator_get_voltage_sel_regmap,
.set_voltage_sel = regulator_set_voltage_sel_regmap,
.list_voltage = regulator_list_voltage_linear_range,
.map_voltage = regulator_map_voltage_linear_range,
};
static int palmas_is_enabled_ldo(struct regulator_dev *dev)
{
struct palmas_pmic *pmic = rdev_get_drvdata(dev);
int id = rdev_get_id(dev);
struct palmas_pmic *pmic = rdev_get_drvdata(dev);
struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
unsigned int reg;
palmas_ldo_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, &reg);
reg &= PALMAS_LDO1_CTRL_STATUS;
......@@ -463,14 +628,26 @@ static struct regulator_ops palmas_ops_extreg = {
static struct regulator_ops palmas_ops_ext_control_extreg = {
};
static struct regulator_ops tps65917_ops_ldo = {
.is_enabled = palmas_is_enabled_ldo,
.enable = regulator_enable_regmap,
.disable = regulator_disable_regmap,
.get_voltage_sel = regulator_get_voltage_sel_regmap,
.set_voltage_sel = regulator_set_voltage_sel_regmap,
.list_voltage = regulator_list_voltage_linear,
.map_voltage = regulator_map_voltage_linear,
.set_voltage_time_sel = regulator_set_voltage_time_sel,
};
static int palmas_regulator_config_external(struct palmas *palmas, int id,
struct palmas_reg_init *reg_init)
{
int sleep_id = palmas_regs_info[id].sleep_id;
struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
int ret;
ret = palmas_ext_control_req_config(palmas, sleep_id,
reg_init->roof_floor, true);
ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id,
reg_init->roof_floor, true);
if (ret < 0)
dev_err(palmas->dev,
"Ext control config for regulator %d failed %d\n",
......@@ -488,10 +665,10 @@ static int palmas_smps_init(struct palmas *palmas, int id,
struct palmas_reg_init *reg_init)
{
unsigned int reg;
unsigned int addr;
int ret;
addr = palmas_regs_info[id].ctrl_addr;
struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
unsigned int addr = rinfo->ctrl_addr;
ret = palmas_smps_read(palmas, addr, &reg);
if (ret)
......@@ -526,12 +703,11 @@ static int palmas_smps_init(struct palmas *palmas, int id,
if (ret)
return ret;
if (palmas_regs_info[id].vsel_addr && reg_init->vsel) {
addr = palmas_regs_info[id].vsel_addr;
if (rinfo->vsel_addr && reg_init->vsel) {
reg = reg_init->vsel;
ret = palmas_smps_write(palmas, addr, reg);
ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg);
if (ret)
return ret;
}
......@@ -539,7 +715,6 @@ static int palmas_smps_init(struct palmas *palmas, int id,
if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
(id != PALMAS_REG_SMPS10_OUT2)) {
/* Enable externally controlled regulator */
addr = palmas_regs_info[id].ctrl_addr;
ret = palmas_smps_read(palmas, addr, &reg);
if (ret < 0)
return ret;
......@@ -561,8 +736,10 @@ static int palmas_ldo_init(struct palmas *palmas, int id,
unsigned int reg;
unsigned int addr;
int ret;
struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
addr = palmas_regs_info[id].ctrl_addr;
addr = rinfo->ctrl_addr;
ret = palmas_ldo_read(palmas, addr, &reg);
if (ret)
......@@ -584,7 +761,6 @@ static int palmas_ldo_init(struct palmas *palmas, int id,
if (reg_init->roof_floor) {
/* Enable externally controlled regulator */
addr = palmas_regs_info[id].ctrl_addr;
ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
PALMAS_LDO1_CTRL_MODE_ACTIVE);
......@@ -605,8 +781,10 @@ static int palmas_extreg_init(struct palmas *palmas, int id,
unsigned int addr;
int ret;
unsigned int val = 0;
struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
addr = palmas_regs_info[id].ctrl_addr;
addr = rinfo->ctrl_addr;
if (reg_init->mode_sleep)
val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
......@@ -621,7 +799,6 @@ static int palmas_extreg_init(struct palmas *palmas, int id,
if (reg_init->roof_floor) {
/* Enable externally controlled regulator */
addr = palmas_regs_info[id].ctrl_addr;
ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
PALMAS_REGEN1_CTRL_MODE_ACTIVE);
......@@ -641,8 +818,11 @@ static void palmas_enable_ldo8_track(struct palmas *palmas)
unsigned int reg;
unsigned int addr;
int ret;
struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
struct palmas_regs_info *rinfo;
addr = palmas_regs_info[PALMAS_REG_LDO8].ctrl_addr;
rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8];
addr = rinfo->ctrl_addr;
ret = palmas_ldo_read(palmas, addr, &reg);
if (ret) {
......@@ -661,7 +841,7 @@ static void palmas_enable_ldo8_track(struct palmas *palmas)
* output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
* and can be set from 0.45 to 1.65 V.
*/
addr = palmas_regs_info[PALMAS_REG_LDO8].vsel_addr;
addr = rinfo->vsel_addr;
ret = palmas_ldo_read(palmas, addr, &reg);
if (ret) {
dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
......@@ -676,169 +856,230 @@ static void palmas_enable_ldo8_track(struct palmas *palmas)
return;
}
static struct of_regulator_match palmas_matches[] = {
{ .name = "smps12", },
{ .name = "smps123", },
{ .name = "smps3", },
{ .name = "smps45", },
{ .name = "smps457", },
{ .name = "smps6", },
{ .name = "smps7", },
{ .name = "smps8", },
{ .name = "smps9", },
{ .name = "smps10_out2", },
{ .name = "smps10_out1", },
{ .name = "ldo1", },
{ .name = "ldo2", },
{ .name = "ldo3", },
{ .name = "ldo4", },
{ .name = "ldo5", },
{ .name = "ldo6", },
{ .name = "ldo7", },
{ .name = "ldo8", },
{ .name = "ldo9", },
{ .name = "ldoln", },
{ .name = "ldousb", },
{ .name = "regen1", },
{ .name = "regen2", },
{ .name = "regen3", },
{ .name = "sysen1", },
{ .name = "sysen2", },
};
static void palmas_dt_to_pdata(struct device *dev,
struct device_node *node,
struct palmas_pmic_platform_data *pdata)
static int palmas_ldo_registration(struct palmas_pmic *pmic,
struct palmas_pmic_driver_data *ddata,
struct palmas_pmic_platform_data *pdata,
const char *pdev_name,
struct regulator_config config)
{
struct device_node *regulators;
u32 prop;
int idx, ret;
int id, ret;
struct regulator_dev *rdev;
struct palmas_reg_init *reg_init;
struct palmas_regs_info *rinfo;
struct regulator_desc *desc;
node = of_node_get(node);
regulators = of_get_child_by_name(node, "regulators");
if (!regulators) {
dev_info(dev, "regulator node not found\n");
return;
}
for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
if (pdata && pdata->reg_init[id])
reg_init = pdata->reg_init[id];
else
reg_init = NULL;
ret = of_regulator_match(dev, regulators, palmas_matches,
PALMAS_NUM_REGS);
of_node_put(regulators);
if (ret < 0) {
dev_err(dev, "Error parsing regulator init data: %d\n", ret);
return;
}
rinfo = &ddata->palmas_regs_info[id];
/* Miss out regulators which are not available due
* to alternate functions.
*/
for (idx = 0; idx < PALMAS_NUM_REGS; idx++) {
if (!palmas_matches[idx].init_data ||
!palmas_matches[idx].of_node)
continue;
/* Register the regulators */
desc = &pmic->desc[id];
desc->name = rinfo->name;
desc->id = id;
desc->type = REGULATOR_VOLTAGE;
desc->owner = THIS_MODULE;
pdata->reg_data[idx] = palmas_matches[idx].init_data;
if (id < PALMAS_REG_REGEN1) {
desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
if (reg_init && reg_init->roof_floor)
desc->ops = &palmas_ops_ext_control_ldo;
else
desc->ops = &palmas_ops_ldo;
desc->min_uV = 900000;
desc->uV_step = 50000;
desc->linear_min_sel = 1;
desc->enable_time = 500;
desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
rinfo->vsel_addr);
desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
rinfo->ctrl_addr);
desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
pdata->reg_init[idx] = devm_kzalloc(dev,
sizeof(struct palmas_reg_init), GFP_KERNEL);
/* Check if LDO8 is in tracking mode or not */
if (pdata && (id == PALMAS_REG_LDO8) &&
pdata->enable_ldo8_tracking) {
palmas_enable_ldo8_track(pmic->palmas);
desc->min_uV = 450000;
desc->uV_step = 25000;
}
pdata->reg_init[idx]->warm_reset =
of_property_read_bool(palmas_matches[idx].of_node,
"ti,warm-reset");
/* LOD6 in vibrator mode will have enable time 2000us */
if (pdata && pdata->ldo6_vibrator &&
(id == PALMAS_REG_LDO6))
desc->enable_time = 2000;
} else {
desc->n_voltages = 1;
if (reg_init && reg_init->roof_floor)
desc->ops = &palmas_ops_ext_control_extreg;
else
desc->ops = &palmas_ops_extreg;
desc->enable_reg =
PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
rinfo->ctrl_addr);
desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
}
ret = of_property_read_u32(palmas_matches[idx].of_node,
"ti,roof-floor", &prop);
/* EINVAL: Property not found */
if (ret != -EINVAL) {
int econtrol;
if (pdata)
config.init_data = pdata->reg_data[id];
else
config.init_data = NULL;
/* use default value, when no value is specified */
econtrol = PALMAS_EXT_CONTROL_NSLEEP;
if (!ret) {
switch (prop) {
case 1:
econtrol = PALMAS_EXT_CONTROL_ENABLE1;
break;
case 2:
econtrol = PALMAS_EXT_CONTROL_ENABLE2;
break;
case 3:
econtrol = PALMAS_EXT_CONTROL_NSLEEP;
break;
default:
WARN_ON(1);
dev_warn(dev,
"%s: Invalid roof-floor option: %u\n",
palmas_matches[idx].name, prop);
break;
}
}
pdata->reg_init[idx]->roof_floor = econtrol;
}
desc->supply_name = rinfo->sname;
config.of_node = ddata->palmas_matches[id].of_node;
ret = of_property_read_u32(palmas_matches[idx].of_node,
"ti,mode-sleep", &prop);
if (!ret)
pdata->reg_init[idx]->mode_sleep = prop;
rdev = devm_regulator_register(pmic->dev, desc, &config);
if (IS_ERR(rdev)) {
dev_err(pmic->dev,
"failed to register %s regulator\n",
pdev_name);
return PTR_ERR(rdev);
}
ret = of_property_read_bool(palmas_matches[idx].of_node,
"ti,smps-range");
if (ret)
pdata->reg_init[idx]->vsel =
PALMAS_SMPS12_VOLTAGE_RANGE;
/* Save regulator for cleanup */
pmic->rdev[id] = rdev;
if (idx == PALMAS_REG_LDO8)
pdata->enable_ldo8_tracking = of_property_read_bool(
palmas_matches[idx].of_node,
"ti,enable-ldo8-tracking");
/* Initialise sleep/init values from platform data */
if (pdata) {
reg_init = pdata->reg_init[id];
if (reg_init) {
if (id <= ddata->ldo_end)
ret = palmas_ldo_init(pmic->palmas, id,
reg_init);
else
ret = palmas_extreg_init(pmic->palmas,
id, reg_init);
if (ret)
return ret;
}
}
}
pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
return 0;
}
static int palmas_regulators_probe(struct platform_device *pdev)
static int tps65917_ldo_registration(struct palmas_pmic *pmic,
struct palmas_pmic_driver_data *ddata,
struct palmas_pmic_platform_data *pdata,
const char *pdev_name,
struct regulator_config config)
{
struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
struct device_node *node = pdev->dev.of_node;
int id, ret;
struct regulator_dev *rdev;
struct regulator_config config = { };
struct palmas_pmic *pmic;
struct palmas_reg_init *reg_init;
int id = 0, ret;
unsigned int addr, reg;
struct palmas_regs_info *rinfo;
struct regulator_desc *desc;
if (node && !pdata) {
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
if (pdata && pdata->reg_init[id])
reg_init = pdata->reg_init[id];
else
reg_init = NULL;
if (!pdata)
return -ENOMEM;
/* Miss out regulators which are not available due
* to alternate functions.
*/
rinfo = &ddata->palmas_regs_info[id];
palmas_dt_to_pdata(&pdev->dev, node, pdata);
}
/* Register the regulators */
desc = &pmic->desc[id];
desc->name = rinfo->name;
desc->id = id;
desc->type = REGULATOR_VOLTAGE;
desc->owner = THIS_MODULE;
if (id < TPS65917_REG_REGEN1) {
desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
if (reg_init && reg_init->roof_floor)
desc->ops = &palmas_ops_ext_control_ldo;
else
desc->ops = &tps65917_ops_ldo;
desc->min_uV = 900000;
desc->uV_step = 50000;
desc->linear_min_sel = 1;
desc->enable_time = 500;
desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
rinfo->vsel_addr);
desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
rinfo->ctrl_addr);
desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
/*
* To be confirmed. Discussion on going with PMIC Team.
* It is of the order of ~60mV/uS.
*/
desc->ramp_delay = 2500;
} else {
desc->n_voltages = 1;
if (reg_init && reg_init->roof_floor)
desc->ops = &palmas_ops_ext_control_extreg;
else
desc->ops = &palmas_ops_extreg;
desc->enable_reg =
PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
rinfo->ctrl_addr);
desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
}
pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
if (pdata)
config.init_data = pdata->reg_data[id];
else
config.init_data = NULL;
pmic->dev = &pdev->dev;
pmic->palmas = palmas;
palmas->pmic = pmic;
platform_set_drvdata(pdev, pmic);
desc->supply_name = rinfo->sname;
config.of_node = ddata->palmas_matches[id].of_node;
ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
if (ret)
return ret;
rdev = devm_regulator_register(pmic->dev, desc, &config);
if (IS_ERR(rdev)) {
dev_err(pmic->dev,
"failed to register %s regulator\n",
pdev_name);
return PTR_ERR(rdev);
}
if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN)
pmic->smps123 = 1;
/* Save regulator for cleanup */
pmic->rdev[id] = rdev;
if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
pmic->smps457 = 1;
/* Initialise sleep/init values from platform data */
if (pdata) {
reg_init = pdata->reg_init[id];
if (reg_init) {
if (id < TPS65917_REG_REGEN1)
ret = palmas_ldo_init(pmic->palmas,
id, reg_init);
else
ret = palmas_extreg_init(pmic->palmas,
id, reg_init);
if (ret)
return ret;
}
}
}
config.regmap = palmas->regmap[REGULATOR_SLAVE];
config.dev = &pdev->dev;
config.driver_data = pmic;
return 0;
}
for (id = 0; id < PALMAS_REG_LDO1; id++) {
static int palmas_smps_registration(struct palmas_pmic *pmic,
struct palmas_pmic_driver_data *ddata,
struct palmas_pmic_platform_data *pdata,
const char *pdev_name,
struct regulator_config config)
{
int id, ret;
unsigned int addr, reg;
struct regulator_dev *rdev;
struct palmas_reg_init *reg_init;
struct palmas_regs_info *rinfo;
struct regulator_desc *desc;
for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
bool ramp_delay_support = false;
/*
......@@ -872,30 +1113,31 @@ static int palmas_regulators_probe(struct platform_device *pdev)
break;
case PALMAS_REG_SMPS10_OUT1:
case PALMAS_REG_SMPS10_OUT2:
if (!PALMAS_PMIC_HAS(palmas, SMPS10_BOOST))
if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST))
continue;
}
rinfo = &ddata->palmas_regs_info[id];
desc = &pmic->desc[id];
if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
ramp_delay_support = true;
if (ramp_delay_support) {
addr = palmas_regs_info[id].tstep_addr;
addr = rinfo->tstep_addr;
ret = palmas_smps_read(pmic->palmas, addr, &reg);
if (ret < 0) {
dev_err(&pdev->dev,
dev_err(pmic->dev,
"reading TSTEP reg failed: %d\n", ret);
return ret;
}
pmic->desc[id].ramp_delay =
palmas_smps_ramp_delay[reg & 0x3];
pmic->ramp_delay[id] = pmic->desc[id].ramp_delay;
desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3];
pmic->ramp_delay[id] = desc->ramp_delay;
}
/* Initialise sleep/init values from platform data */
if (pdata && pdata->reg_init[id]) {
reg_init = pdata->reg_init[id];
ret = palmas_smps_init(palmas, id, reg_init);
ret = palmas_smps_init(pmic->palmas, id, reg_init);
if (ret)
return ret;
} else {
......@@ -903,31 +1145,28 @@ static int palmas_regulators_probe(struct platform_device *pdev)
}
/* Register the regulators */
pmic->desc[id].name = palmas_regs_info[id].name;
pmic->desc[id].id = id;
desc->name = rinfo->name;
desc->id = id;
switch (id) {
case PALMAS_REG_SMPS10_OUT1:
case PALMAS_REG_SMPS10_OUT2:
pmic->desc[id].n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
pmic->desc[id].ops = &palmas_ops_smps10;
pmic->desc[id].vsel_reg =
PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
PALMAS_SMPS10_CTRL);
pmic->desc[id].vsel_mask = SMPS10_VSEL;
pmic->desc[id].enable_reg =
PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
PALMAS_SMPS10_CTRL);
desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
desc->ops = &palmas_ops_smps10;
desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
PALMAS_SMPS10_CTRL);
desc->vsel_mask = SMPS10_VSEL;
desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
PALMAS_SMPS10_CTRL);
if (id == PALMAS_REG_SMPS10_OUT1)
pmic->desc[id].enable_mask = SMPS10_SWITCH_EN;
desc->enable_mask = SMPS10_SWITCH_EN;
else
pmic->desc[id].enable_mask = SMPS10_BOOST_EN;
pmic->desc[id].bypass_reg =
PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
PALMAS_SMPS10_CTRL);
pmic->desc[id].bypass_mask = SMPS10_BYPASS_EN;
pmic->desc[id].min_uV = 3750000;
pmic->desc[id].uV_step = 1250000;
desc->enable_mask = SMPS10_BOOST_EN;
desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
PALMAS_SMPS10_CTRL);
desc->bypass_mask = SMPS10_BYPASS_EN;
desc->min_uV = 3750000;
desc->uV_step = 1250000;
break;
default:
/*
......@@ -936,8 +1175,8 @@ static int palmas_regulators_probe(struct platform_device *pdev)
* otherwise we error in probe with unsupportable
* ranges. Read the current smps mode for later use.
*/
addr = palmas_regs_info[id].vsel_addr;
pmic->desc[id].n_linear_ranges = 3;
addr = rinfo->vsel_addr;
desc->n_linear_ranges = 3;
ret = palmas_smps_read(pmic->palmas, addr, &reg);
if (ret)
......@@ -945,56 +1184,50 @@ static int palmas_regulators_probe(struct platform_device *pdev)
if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
pmic->range[id] = 1;
if (pmic->range[id])
pmic->desc[id].linear_ranges = smps_high_ranges;
desc->linear_ranges = smps_high_ranges;
else
pmic->desc[id].linear_ranges = smps_low_ranges;
desc->linear_ranges = smps_low_ranges;
if (reg_init && reg_init->roof_floor)
pmic->desc[id].ops =
&palmas_ops_ext_control_smps;
desc->ops = &palmas_ops_ext_control_smps;
else
pmic->desc[id].ops = &palmas_ops_smps;
pmic->desc[id].n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
pmic->desc[id].vsel_reg =
PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
palmas_regs_info[id].vsel_addr);
pmic->desc[id].vsel_mask =
PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
desc->ops = &palmas_ops_smps;
desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
rinfo->vsel_addr);
desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
/* Read the smps mode for later use. */
addr = palmas_regs_info[id].ctrl_addr;
addr = rinfo->ctrl_addr;
ret = palmas_smps_read(pmic->palmas, addr, &reg);
if (ret)
return ret;
pmic->current_reg_mode[id] = reg &
PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
pmic->desc[id].enable_reg =
PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
palmas_regs_info[id].ctrl_addr);
pmic->desc[id].enable_mask =
PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
rinfo->ctrl_addr);
desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
/* set_mode overrides this value */
pmic->desc[id].enable_val = SMPS_CTRL_MODE_ON;
desc->enable_val = SMPS_CTRL_MODE_ON;
}
pmic->desc[id].type = REGULATOR_VOLTAGE;
pmic->desc[id].owner = THIS_MODULE;
desc->type = REGULATOR_VOLTAGE;
desc->owner = THIS_MODULE;
if (pdata)
config.init_data = pdata->reg_data[id];
else
config.init_data = NULL;
pmic->desc[id].supply_name = palmas_regs_info[id].sname;
config.of_node = palmas_matches[id].of_node;
desc->supply_name = rinfo->sname;
config.of_node = ddata->palmas_matches[id].of_node;
rdev = devm_regulator_register(&pdev->dev, &pmic->desc[id],
&config);
rdev = devm_regulator_register(pmic->dev, desc, &config);
if (IS_ERR(rdev)) {
dev_err(&pdev->dev,
dev_err(pmic->dev,
"failed to register %s regulator\n",
pdev->name);
pdev_name);
return PTR_ERR(rdev);
}
......@@ -1002,123 +1235,378 @@ static int palmas_regulators_probe(struct platform_device *pdev)
pmic->rdev[id] = rdev;
}
/* Start this loop from the id left from previous loop */
for (; id < PALMAS_NUM_REGS; id++) {
if (pdata && pdata->reg_init[id])
return 0;
}
static int tps65917_smps_registration(struct palmas_pmic *pmic,
struct palmas_pmic_driver_data *ddata,
struct palmas_pmic_platform_data *pdata,
const char *pdev_name,
struct regulator_config config)
{
int id, ret;
unsigned int addr, reg;
struct regulator_dev *rdev;
struct palmas_reg_init *reg_init;
struct palmas_regs_info *rinfo;
struct regulator_desc *desc;
for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
/*
* Miss out regulators which are not available due
* to slaving configurations.
*/
desc = &pmic->desc[id];
desc->n_linear_ranges = 3;
if ((id == TPS65917_REG_SMPS2) && pmic->smps12)
continue;
/* Initialise sleep/init values from platform data */
if (pdata && pdata->reg_init[id]) {
reg_init = pdata->reg_init[id];
else
ret = palmas_smps_init(pmic->palmas, id, reg_init);
if (ret)
return ret;
} else {
reg_init = NULL;
}
rinfo = &ddata->palmas_regs_info[id];
/* Miss out regulators which are not available due
* to alternate functions.
/* Register the regulators */
desc->name = rinfo->name;
desc->id = id;
/*
* Read and store the RANGE bit for later use
* This must be done before regulator is probed,
* otherwise we error in probe with unsupportable
* ranges. Read the current smps mode for later use.
*/
addr = rinfo->vsel_addr;
/* Register the regulators */
pmic->desc[id].name = palmas_regs_info[id].name;
pmic->desc[id].id = id;
pmic->desc[id].type = REGULATOR_VOLTAGE;
pmic->desc[id].owner = THIS_MODULE;
ret = palmas_smps_read(pmic->palmas, addr, &reg);
if (ret)
return ret;
if (reg & TPS65917_SMPS1_VOLTAGE_RANGE)
pmic->range[id] = 1;
if (id < PALMAS_REG_REGEN1) {
pmic->desc[id].n_voltages = PALMAS_LDO_NUM_VOLTAGES;
if (reg_init && reg_init->roof_floor)
pmic->desc[id].ops =
&palmas_ops_ext_control_ldo;
else
pmic->desc[id].ops = &palmas_ops_ldo;
pmic->desc[id].min_uV = 900000;
pmic->desc[id].uV_step = 50000;
pmic->desc[id].linear_min_sel = 1;
pmic->desc[id].enable_time = 500;
pmic->desc[id].vsel_reg =
PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
palmas_regs_info[id].vsel_addr);
pmic->desc[id].vsel_mask =
PALMAS_LDO1_VOLTAGE_VSEL_MASK;
pmic->desc[id].enable_reg =
PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
palmas_regs_info[id].ctrl_addr);
pmic->desc[id].enable_mask =
PALMAS_LDO1_CTRL_MODE_ACTIVE;
if (pmic->range[id])
desc->linear_ranges = smps_high_ranges;
else
desc->linear_ranges = smps_low_ranges;
/* Check if LDO8 is in tracking mode or not */
if (pdata && (id == PALMAS_REG_LDO8) &&
pdata->enable_ldo8_tracking) {
palmas_enable_ldo8_track(palmas);
pmic->desc[id].min_uV = 450000;
pmic->desc[id].uV_step = 25000;
}
if (reg_init && reg_init->roof_floor)
desc->ops = &tps65917_ops_ext_control_smps;
else
desc->ops = &tps65917_ops_smps;
desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
rinfo->vsel_addr);
desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
desc->ramp_delay = 2500;
/* Read the smps mode for later use. */
addr = rinfo->ctrl_addr;
ret = palmas_smps_read(pmic->palmas, addr, &reg);
if (ret)
return ret;
pmic->current_reg_mode[id] = reg &
PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
rinfo->ctrl_addr);
desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
/* set_mode overrides this value */
desc->enable_val = SMPS_CTRL_MODE_ON;
/* LOD6 in vibrator mode will have enable time 2000us */
if (pdata && pdata->ldo6_vibrator &&
(id == PALMAS_REG_LDO6))
pmic->desc[id].enable_time = 2000;
} else {
pmic->desc[id].n_voltages = 1;
if (reg_init && reg_init->roof_floor)
pmic->desc[id].ops =
&palmas_ops_ext_control_extreg;
else
pmic->desc[id].ops = &palmas_ops_extreg;
pmic->desc[id].enable_reg =
PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
palmas_regs_info[id].ctrl_addr);
pmic->desc[id].enable_mask =
PALMAS_REGEN1_CTRL_MODE_ACTIVE;
}
desc->type = REGULATOR_VOLTAGE;
desc->owner = THIS_MODULE;
if (pdata)
config.init_data = pdata->reg_data[id];
else
config.init_data = NULL;
pmic->desc[id].supply_name = palmas_regs_info[id].sname;
config.of_node = palmas_matches[id].of_node;
desc->supply_name = rinfo->sname;
config.of_node = ddata->palmas_matches[id].of_node;
rdev = devm_regulator_register(&pdev->dev, &pmic->desc[id],
&config);
rdev = devm_regulator_register(pmic->dev, desc, &config);
if (IS_ERR(rdev)) {
dev_err(&pdev->dev,
dev_err(pmic->dev,
"failed to register %s regulator\n",
pdev->name);
pdev_name);
return PTR_ERR(rdev);
}
/* Save regulator for cleanup */
pmic->rdev[id] = rdev;
}
/* Initialise sleep/init values from platform data */
if (pdata) {
reg_init = pdata->reg_init[id];
if (reg_init) {
if (id < PALMAS_REG_REGEN1)
ret = palmas_ldo_init(palmas,
id, reg_init);
else
ret = palmas_extreg_init(palmas,
id, reg_init);
if (ret)
return ret;
return 0;
}
static struct of_regulator_match palmas_matches[] = {
{ .name = "smps12", },
{ .name = "smps123", },
{ .name = "smps3", },
{ .name = "smps45", },
{ .name = "smps457", },
{ .name = "smps6", },
{ .name = "smps7", },
{ .name = "smps8", },
{ .name = "smps9", },
{ .name = "smps10_out2", },
{ .name = "smps10_out1", },
{ .name = "ldo1", },
{ .name = "ldo2", },
{ .name = "ldo3", },
{ .name = "ldo4", },
{ .name = "ldo5", },
{ .name = "ldo6", },
{ .name = "ldo7", },
{ .name = "ldo8", },
{ .name = "ldo9", },
{ .name = "ldoln", },
{ .name = "ldousb", },
{ .name = "regen1", },
{ .name = "regen2", },
{ .name = "regen3", },
{ .name = "sysen1", },
{ .name = "sysen2", },
};
static struct of_regulator_match tps65917_matches[] = {
{ .name = "smps1", },
{ .name = "smps2", },
{ .name = "smps3", },
{ .name = "smps4", },
{ .name = "smps5", },
{ .name = "ldo1", },
{ .name = "ldo2", },
{ .name = "ldo3", },
{ .name = "ldo4", },
{ .name = "ldo5", },
{ .name = "regen1", },
{ .name = "regen2", },
{ .name = "regen3", },
{ .name = "sysen1", },
{ .name = "sysen2", },
};
static struct palmas_pmic_driver_data palmas_ddata = {
.smps_start = PALMAS_REG_SMPS12,
.smps_end = PALMAS_REG_SMPS10_OUT1,
.ldo_begin = PALMAS_REG_LDO1,
.ldo_end = PALMAS_REG_LDOUSB,
.max_reg = PALMAS_NUM_REGS,
.palmas_regs_info = palmas_generic_regs_info,
.palmas_matches = palmas_matches,
.sleep_req_info = palma_sleep_req_info,
.smps_register = palmas_smps_registration,
.ldo_register = palmas_ldo_registration,
};
static struct palmas_pmic_driver_data tps65917_ddata = {
.smps_start = TPS65917_REG_SMPS1,
.smps_end = TPS65917_REG_SMPS5,
.ldo_begin = TPS65917_REG_LDO1,
.ldo_end = TPS65917_REG_LDO5,
.max_reg = TPS65917_NUM_REGS,
.palmas_regs_info = tps65917_regs_info,
.palmas_matches = tps65917_matches,
.sleep_req_info = tps65917_sleep_req_info,
.smps_register = tps65917_smps_registration,
.ldo_register = tps65917_ldo_registration,
};
static void palmas_dt_to_pdata(struct device *dev,
struct device_node *node,
struct palmas_pmic_platform_data *pdata,
struct palmas_pmic_driver_data *ddata)
{
struct device_node *regulators;
u32 prop;
int idx, ret;
node = of_node_get(node);
regulators = of_get_child_by_name(node, "regulators");
if (!regulators) {
dev_info(dev, "regulator node not found\n");
return;
}
ret = of_regulator_match(dev, regulators, ddata->palmas_matches,
ddata->max_reg);
of_node_put(regulators);
if (ret < 0) {
dev_err(dev, "Error parsing regulator init data: %d\n", ret);
return;
}
for (idx = 0; idx < ddata->max_reg; idx++) {
if (!ddata->palmas_matches[idx].init_data ||
!ddata->palmas_matches[idx].of_node)
continue;
pdata->reg_data[idx] = ddata->palmas_matches[idx].init_data;
pdata->reg_init[idx] = devm_kzalloc(dev,
sizeof(struct palmas_reg_init), GFP_KERNEL);
pdata->reg_init[idx]->warm_reset =
of_property_read_bool(ddata->palmas_matches[idx].of_node,
"ti,warm-reset");
ret = of_property_read_u32(ddata->palmas_matches[idx].of_node,
"ti,roof-floor", &prop);
/* EINVAL: Property not found */
if (ret != -EINVAL) {
int econtrol;
/* use default value, when no value is specified */
econtrol = PALMAS_EXT_CONTROL_NSLEEP;
if (!ret) {
switch (prop) {
case 1:
econtrol = PALMAS_EXT_CONTROL_ENABLE1;
break;
case 2:
econtrol = PALMAS_EXT_CONTROL_ENABLE2;
break;
case 3:
econtrol = PALMAS_EXT_CONTROL_NSLEEP;
break;
default:
WARN_ON(1);
dev_warn(dev,
"%s: Invalid roof-floor option: %u\n",
palmas_matches[idx].name, prop);
break;
}
}
pdata->reg_init[idx]->roof_floor = econtrol;
}
}
ret = of_property_read_u32(ddata->palmas_matches[idx].of_node,
"ti,mode-sleep", &prop);
if (!ret)
pdata->reg_init[idx]->mode_sleep = prop;
return 0;
ret = of_property_read_bool(ddata->palmas_matches[idx].of_node,
"ti,smps-range");
if (ret)
pdata->reg_init[idx]->vsel =
PALMAS_SMPS12_VOLTAGE_RANGE;
if (idx == PALMAS_REG_LDO8)
pdata->enable_ldo8_tracking = of_property_read_bool(
ddata->palmas_matches[idx].of_node,
"ti,enable-ldo8-tracking");
}
pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
}
static const struct of_device_id of_palmas_match_tbl[] = {
{ .compatible = "ti,palmas-pmic", },
{ .compatible = "ti,twl6035-pmic", },
{ .compatible = "ti,twl6036-pmic", },
{ .compatible = "ti,twl6037-pmic", },
{ .compatible = "ti,tps65913-pmic", },
{ .compatible = "ti,tps65914-pmic", },
{ .compatible = "ti,tps80036-pmic", },
{ .compatible = "ti,tps659038-pmic", },
static struct of_device_id of_palmas_match_tbl[] = {
{
.compatible = "ti,palmas-pmic",
.data = &palmas_ddata,
},
{
.compatible = "ti,twl6035-pmic",
.data = &palmas_ddata,
},
{
.compatible = "ti,twl6036-pmic",
.data = &palmas_ddata,
},
{
.compatible = "ti,twl6037-pmic",
.data = &palmas_ddata,
},
{
.compatible = "ti,tps65913-pmic",
.data = &palmas_ddata,
},
{
.compatible = "ti,tps65914-pmic",
.data = &palmas_ddata,
},
{
.compatible = "ti,tps80036-pmic",
.data = &palmas_ddata,
},
{
.compatible = "ti,tps659038-pmic",
.data = &palmas_ddata,
},
{
.compatible = "ti,tps65917-pmic",
.data = &tps65917_ddata,
},
{ /* end */ }
};
static int palmas_regulators_probe(struct platform_device *pdev)
{
struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
struct device_node *node = pdev->dev.of_node;
struct palmas_pmic_driver_data *driver_data;
struct regulator_config config = { };
struct palmas_pmic *pmic;
const char *pdev_name;
const struct of_device_id *match;
int ret = 0;
unsigned int reg;
match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev);
if (!match)
return -ENODATA;
driver_data = (struct palmas_pmic_driver_data *)match->data;
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
pmic->dev = &pdev->dev;
pmic->palmas = palmas;
palmas->pmic = pmic;
platform_set_drvdata(pdev, pmic);
pmic->palmas->pmic_ddata = driver_data;
palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data);
ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
if (ret)
return ret;
if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN)
pmic->smps123 = 1;
if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
pmic->smps457 = 1;
config.regmap = palmas->regmap[REGULATOR_SLAVE];
config.dev = &pdev->dev;
config.driver_data = pmic;
pdev_name = pdev->name;
ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name,
config);
if (ret)
return ret;
ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name,
config);
return ret;
}
static struct platform_driver palmas_driver = {
.driver = {
.name = "palmas-pmic",
......
include/linux/mfd/palmas.h
View file @ d5b5d9d4
......@@ -30,6 +30,8 @@
#define PALMAS_CHIP_ID 0xC035
#define PALMAS_CHIP_CHARGER_ID 0xC036
#define TPS65917_RESERVED -1
#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
((a) == PALMAS_CHIP_ID))
#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
......@@ -51,6 +53,8 @@ struct palmas_pmic;
struct palmas_gpadc;
struct palmas_resource;
struct palmas_usb;
struct palmas_pmic_driver_data;
struct palmas_pmic_platform_data;
enum palmas_usb_state {
PALMAS_USB_STATE_DISCONNECT,
......@@ -74,6 +78,8 @@ struct palmas {
struct mutex irq_lock;
struct regmap_irq_chip_data *irq_data;
struct palmas_pmic_driver_data *pmic_ddata;
/* Child Devices */
struct palmas_pmic *pmic;
struct palmas_gpadc *gpadc;
......@@ -86,6 +92,46 @@ struct palmas {
u8 pwm_muxed;
};
#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
PALMAS_EXT_CONTROL_ENABLE2 | \
PALMAS_EXT_CONTROL_NSLEEP)
struct palmas_sleep_requestor_info {
int id;
int reg_offset;
int bit_pos;
};
struct palmas_regs_info {
char *name;
char *sname;
u8 vsel_addr;
u8 ctrl_addr;
u8 tstep_addr;
int sleep_id;
};
struct palmas_pmic_driver_data {
int smps_start;
int smps_end;
int ldo_begin;
int ldo_end;
int max_reg;
struct palmas_regs_info *palmas_regs_info;
struct of_regulator_match *palmas_matches;
struct palmas_sleep_requestor_info *sleep_req_info;
int (*smps_register)(struct palmas_pmic *pmic,
struct palmas_pmic_driver_data *ddata,
struct palmas_pmic_platform_data *pdata,
const char *pdev_name,
struct regulator_config config);
int (*ldo_register)(struct palmas_pmic *pmic,
struct palmas_pmic_driver_data *ddata,
struct palmas_pmic_platform_data *pdata,
const char *pdev_name,
struct regulator_config config);
};
struct palmas_gpadc_platform_data {
/* Channel 3 current source is only enabled during conversion */
int ch3_current;
......@@ -184,6 +230,27 @@ enum palmas_regulators {
PALMAS_NUM_REGS,
};
enum tps65917_regulators {
/* SMPS regulators */
TPS65917_REG_SMPS1,
TPS65917_REG_SMPS2,
TPS65917_REG_SMPS3,
TPS65917_REG_SMPS4,
TPS65917_REG_SMPS5,
/* LDO regulators */
TPS65917_REG_LDO1,
TPS65917_REG_LDO2,
TPS65917_REG_LDO3,
TPS65917_REG_LDO4,
TPS65917_REG_LDO5,
TPS65917_REG_REGEN1,
TPS65917_REG_REGEN2,
TPS65917_REG_REGEN3,
/* Total number of regulators */
TPS65917_NUM_REGS,
};
/* External controll signal name */
enum {
PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
......@@ -228,6 +295,24 @@ enum palmas_external_requestor_id {
PALMAS_EXTERNAL_REQSTR_ID_MAX,
};
enum tps65917_external_requestor_id {
TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
TPS65917_EXTERNAL_REQSTR_ID_LDO1,
TPS65917_EXTERNAL_REQSTR_ID_LDO2,
TPS65917_EXTERNAL_REQSTR_ID_LDO3,
TPS65917_EXTERNAL_REQSTR_ID_LDO4,
TPS65917_EXTERNAL_REQSTR_ID_LDO5,
/* Last entry */
TPS65917_EXTERNAL_REQSTR_ID_MAX,
};
struct palmas_pmic_platform_data {
/* An array of pointers to regulator init data indexed by regulator
* ID
......@@ -349,6 +434,48 @@ struct palmas_gpadc_result {
#define PALMAS_MAX_CHANNELS 16
/* Define the tps65917 IRQ numbers */
enum tps65917_irqs {
/* INT1 registers */
TPS65917_RESERVED1,
TPS65917_PWRON_IRQ,
TPS65917_LONG_PRESS_KEY_IRQ,
TPS65917_RESERVED2,
TPS65917_PWRDOWN_IRQ,
TPS65917_HOTDIE_IRQ,
TPS65917_VSYS_MON_IRQ,
TPS65917_RESERVED3,
/* INT2 registers */
TPS65917_RESERVED4,
TPS65917_OTP_ERROR_IRQ,
TPS65917_WDT_IRQ,
TPS65917_RESERVED5,
TPS65917_RESET_IN_IRQ,
TPS65917_FSD_IRQ,
TPS65917_SHORT_IRQ,
TPS65917_RESERVED6,
/* INT3 registers */
TPS65917_GPADC_AUTO_0_IRQ,
TPS65917_GPADC_AUTO_1_IRQ,
TPS65917_GPADC_EOC_SW_IRQ,
TPS65917_RESREVED6,
TPS65917_RESERVED7,
TPS65917_RESERVED8,
TPS65917_RESERVED9,
TPS65917_VBUS_IRQ,
/* INT4 registers */
TPS65917_GPIO_0_IRQ,
TPS65917_GPIO_1_IRQ,
TPS65917_GPIO_2_IRQ,
TPS65917_GPIO_3_IRQ,
TPS65917_GPIO_4_IRQ,
TPS65917_GPIO_5_IRQ,
TPS65917_GPIO_6_IRQ,
TPS65917_RESERVED10,
/* Total Number IRQs */
TPS65917_NUM_IRQ,
};
/* Define the palmas IRQ numbers */
enum palmas_irqs {
/* INT1 registers */
......@@ -400,6 +527,7 @@ struct palmas_pmic {
int smps123;
int smps457;
int smps12;
int range[PALMAS_REG_SMPS10_OUT1];
unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
......@@ -2871,6 +2999,715 @@ enum usb_irq_events {
#define PALMAS_GPADC_TRIM15 0x0E
#define PALMAS_GPADC_TRIM16 0x0F
/* TPS65917 Interrupt registers */
/* Registers for function INTERRUPT */
#define TPS65917_INT1_STATUS 0x00
#define TPS65917_INT1_MASK 0x01
#define TPS65917_INT1_LINE_STATE 0x02
#define TPS65917_INT2_STATUS 0x05
#define TPS65917_INT2_MASK 0x06
#define TPS65917_INT2_LINE_STATE 0x07
#define TPS65917_INT3_STATUS 0x0A
#define TPS65917_INT3_MASK 0x0B
#define TPS65917_INT3_LINE_STATE 0x0C
#define TPS65917_INT4_STATUS 0x0F
#define TPS65917_INT4_MASK 0x10
#define TPS65917_INT4_LINE_STATE 0x11
#define TPS65917_INT4_EDGE_DETECT1 0x12
#define TPS65917_INT4_EDGE_DETECT2 0x13
#define TPS65917_INT_CTRL 0x14
/* Bit definitions for INT1_STATUS */
#define TPS65917_INT1_STATUS_VSYS_MON 0x40
#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
#define TPS65917_INT1_STATUS_HOTDIE 0x20
#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
#define TPS65917_INT1_STATUS_PWRDOWN 0x10
#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
#define TPS65917_INT1_STATUS_PWRON 0x02
#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
/* Bit definitions for INT1_MASK */
#define TPS65917_INT1_MASK_VSYS_MON 0x40
#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
#define TPS65917_INT1_MASK_HOTDIE 0x20
#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
#define TPS65917_INT1_MASK_PWRDOWN 0x10
#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
#define TPS65917_INT1_MASK_PWRON 0x02
#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
/* Bit definitions for INT1_LINE_STATE */
#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
#define TPS65917_INT1_LINE_STATE_PWRON 0x02
#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
/* Bit definitions for INT2_STATUS */
#define TPS65917_INT2_STATUS_SHORT 0x40
#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
#define TPS65917_INT2_STATUS_FSD 0x20
#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
#define TPS65917_INT2_STATUS_RESET_IN 0x10
#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
#define TPS65917_INT2_STATUS_WDT 0x04
#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
#define TPS65917_INT2_STATUS_OTP_ERROR 0x02
#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
/* Bit definitions for INT2_MASK */
#define TPS65917_INT2_MASK_SHORT 0x40
#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
#define TPS65917_INT2_MASK_FSD 0x20
#define TPS65917_INT2_MASK_FSD_SHIFT 0x05
#define TPS65917_INT2_MASK_RESET_IN 0x10
#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
#define TPS65917_INT2_MASK_WDT 0x04
#define TPS65917_INT2_MASK_WDT_SHIFT 0x02
#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
/* Bit definitions for INT2_LINE_STATE */
#define TPS65917_INT2_LINE_STATE_SHORT 0x40
#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
#define TPS65917_INT2_LINE_STATE_FSD 0x20
#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
#define TPS65917_INT2_LINE_STATE_WDT 0x04
#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
/* Bit definitions for INT3_STATUS */
#define TPS65917_INT3_STATUS_VBUS 0x80
#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
/* Bit definitions for INT3_MASK */
#define TPS65917_INT3_MASK_VBUS 0x80
#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
/* Bit definitions for INT3_LINE_STATE */
#define TPS65917_INT3_LINE_STATE_VBUS 0x80
#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
/* Bit definitions for INT4_STATUS */
#define TPS65917_INT4_STATUS_GPIO_6 0x40
#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
#define TPS65917_INT4_STATUS_GPIO_5 0x20
#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
#define TPS65917_INT4_STATUS_GPIO_4 0x10
#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
#define TPS65917_INT4_STATUS_GPIO_3 0x08
#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
#define TPS65917_INT4_STATUS_GPIO_2 0x04
#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
#define TPS65917_INT4_STATUS_GPIO_1 0x02
#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
#define TPS65917_INT4_STATUS_GPIO_0 0x01
#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
/* Bit definitions for INT4_MASK */
#define TPS65917_INT4_MASK_GPIO_6 0x40
#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
#define TPS65917_INT4_MASK_GPIO_5 0x20
#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
#define TPS65917_INT4_MASK_GPIO_4 0x10
#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
#define TPS65917_INT4_MASK_GPIO_3 0x08
#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
#define TPS65917_INT4_MASK_GPIO_2 0x04
#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
#define TPS65917_INT4_MASK_GPIO_1 0x02
#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
#define TPS65917_INT4_MASK_GPIO_0 0x01
#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
/* Bit definitions for INT4_LINE_STATE */
#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
/* Bit definitions for INT4_EDGE_DETECT1 */
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
/* Bit definitions for INT4_EDGE_DETECT2 */
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
/* Bit definitions for INT_CTRL */
#define TPS65917_INT_CTRL_INT_PENDING 0x04
#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
#define TPS65917_INT_CTRL_INT_CLEAR 0x01
#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
/* TPS65917 SMPS Registers */
/* Registers for function SMPS */
#define TPS65917_SMPS1_CTRL 0x00
#define TPS65917_SMPS1_FORCE 0x02
#define TPS65917_SMPS1_VOLTAGE 0x03
#define TPS65917_SMPS2_CTRL 0x04
#define TPS65917_SMPS2_FORCE 0x06
#define TPS65917_SMPS2_VOLTAGE 0x07
#define TPS65917_SMPS3_CTRL 0x0C
#define TPS65917_SMPS3_FORCE 0x0E
#define TPS65917_SMPS3_VOLTAGE 0x0F
#define TPS65917_SMPS4_CTRL 0x10
#define TPS65917_SMPS4_VOLTAGE 0x13
#define TPS65917_SMPS5_CTRL 0x18
#define TPS65917_SMPS5_VOLTAGE 0x1B
#define TPS65917_SMPS_CTRL 0x24
#define TPS65917_SMPS_PD_CTRL 0x25
#define TPS65917_SMPS_THERMAL_EN 0x27
#define TPS65917_SMPS_THERMAL_STATUS 0x28
#define TPS65917_SMPS_SHORT_STATUS 0x29
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
/* Bit definitions for SMPS1_CTRL */
#define TPS65917_SMPS1_CTRL_WR_S 0x80
#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for SMPS1_FORCE */
#define TPS65917_SMPS1_FORCE_CMD 0x80
#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS1_VOLTAGE */
#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS2_CTRL */
#define TPS65917_SMPS2_CTRL_WR_S 0x80
#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for SMPS2_FORCE */
#define TPS65917_SMPS2_FORCE_CMD 0x80
#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS2_VOLTAGE */
#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS3_CTRL */
#define TPS65917_SMPS3_CTRL_WR_S 0x80
#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for SMPS3_FORCE */
#define TPS65917_SMPS3_FORCE_CMD 0x80
#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS3_VOLTAGE */
#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS4_CTRL */
#define TPS65917_SMPS4_CTRL_WR_S 0x80
#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for SMPS4_VOLTAGE */
#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS5_CTRL */
#define TPS65917_SMPS5_CTRL_WR_S 0x80
#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for SMPS5_VOLTAGE */
#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for SMPS_CTRL */
#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
/* Bit definitions for SMPS_PD_CTRL */
#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
/* Bit definitions for SMPS_THERMAL_EN */
#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
/* Bit definitions for SMPS_THERMAL_STATUS */
#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
/* Bit definitions for SMPS_SHORT_STATUS */
#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
/* Bit definitions for SMPS_POWERGOOD_MASK1 */
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
/* Bit definitions for SMPS_POWERGOOD_MASK2 */
#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
/* Bit definitions for SMPS_PLL_CTRL */
#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
/* Registers for function LDO */
#define TPS65917_LDO1_CTRL 0x00
#define TPS65917_LDO1_VOLTAGE 0x01
#define TPS65917_LDO2_CTRL 0x02
#define TPS65917_LDO2_VOLTAGE 0x03
#define TPS65917_LDO3_CTRL 0x04
#define TPS65917_LDO3_VOLTAGE 0x05
#define TPS65917_LDO4_CTRL 0x0E
#define TPS65917_LDO4_VOLTAGE 0x0F
#define TPS65917_LDO5_CTRL 0x12
#define TPS65917_LDO5_VOLTAGE 0x13
#define TPS65917_LDO_PD_CTRL1 0x1B
#define TPS65917_LDO_PD_CTRL2 0x1C
#define TPS65917_LDO_SHORT_STATUS1 0x1D
#define TPS65917_LDO_SHORT_STATUS2 0x1E
#define TPS65917_LDO_PD_CTRL3 0x2D
#define TPS65917_LDO_SHORT_STATUS3 0x2E
/* Bit definitions for LDO1_CTRL */
#define TPS65917_LDO1_CTRL_WR_S 0x80
#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
#define TPS65917_LDO1_CTRL_STATUS 0x10
#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for LDO1_VOLTAGE */
#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for LDO2_CTRL */
#define TPS65917_LDO2_CTRL_WR_S 0x80
#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
#define TPS65917_LDO2_CTRL_STATUS 0x10
#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for LDO2_VOLTAGE */
#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for LDO3_CTRL */
#define TPS65917_LDO3_CTRL_WR_S 0x80
#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
#define TPS65917_LDO3_CTRL_STATUS 0x10
#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for LDO3_VOLTAGE */
#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for LDO4_CTRL */
#define TPS65917_LDO4_CTRL_WR_S 0x80
#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
#define TPS65917_LDO4_CTRL_STATUS 0x10
#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for LDO4_VOLTAGE */
#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for LDO5_CTRL */
#define TPS65917_LDO5_CTRL_WR_S 0x80
#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
#define TPS65917_LDO5_CTRL_STATUS 0x10
#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for LDO5_VOLTAGE */
#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
/* Bit definitions for LDO_PD_CTRL1 */
#define TPS65917_LDO_PD_CTRL1_LDO4 0x80
#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
#define TPS65917_LDO_PD_CTRL1_LDO2 0x02
#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
#define TPS65917_LDO_PD_CTRL1_LDO1 0x01
#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
/* Bit definitions for LDO_PD_CTRL2 */
#define TPS65917_LDO_PD_CTRL2_LDO3 0x04
#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
#define TPS65917_LDO_PD_CTRL2_LDO5 0x02
#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
/* Bit definitions for LDO_PD_CTRL3 */
#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
/* Bit definitions for LDO_SHORT_STATUS1 */
#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
/* Bit definitions for LDO_SHORT_STATUS2 */
#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
/* Bit definitions for LDO_SHORT_STATUS2 */
#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
/* Bit definitions for REGEN1_CTRL */
#define TPS65917_REGEN1_CTRL_STATUS 0x10
#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for PLLEN_CTRL */
#define TPS65917_PLLEN_CTRL_STATUS 0x10
#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for REGEN2_CTRL */
#define TPS65917_REGEN2_CTRL_STATUS 0x10
#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Bit definitions for NSLEEP_RES_ASSIGN */
#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
/* Bit definitions for NSLEEP_SMPS_ASSIGN */
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
/* Bit definitions for ENABLE1_RES_ASSIGN */
#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
/* Bit definitions for ENABLE1_SMPS_ASSIGN */
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
/* Bit definitions for ENABLE2_RES_ASSIGN */
#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
/* Bit definitions for ENABLE2_SMPS_ASSIGN */
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
/* Bit definitions for REGEN3_CTRL */
#define TPS65917_REGEN3_CTRL_STATUS 0x10
#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
/* Registers for function RESOURCE */
#define TPS65917_REGEN1_CTRL 0x2
#define TPS65917_PLLEN_CTRL 0x3
#define TPS65917_NSLEEP_RES_ASSIGN 0x6
#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
#define TPS65917_ENABLE1_RES_ASSIGN 0xA
#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
#define TPS65917_ENABLE2_RES_ASSIGN 0xE
#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
#define TPS65917_REGEN2_CTRL 0x12
#define TPS65917_REGEN3_CTRL 0x13
static inline int palmas_read(struct palmas *palmas, unsigned int base,
unsigned int reg, unsigned int *val)
{
......
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