Commit db2be4e9 authored by Nikhil Badola's avatar Nikhil Badola Committed by Felipe Balbi

usb: dwc3: Add frame length adjustment quirk

Add adjust_frame_length_quirk for writing to fladj register
which adjusts (micro)frame length to value provided by
"snps,quirk-frame-length-adjustment" property thus avoiding
USB 2.0 devices to time-out over a longer run
Signed-off-by: default avatarNikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 3737c544
...@@ -143,6 +143,32 @@ static int dwc3_soft_reset(struct dwc3 *dwc) ...@@ -143,6 +143,32 @@ static int dwc3_soft_reset(struct dwc3 *dwc)
return 0; return 0;
} }
/*
* dwc3_frame_length_adjustment - Adjusts frame length if required
* @dwc3: Pointer to our controller context structure
* @fladj: Value of GFLADJ_30MHZ to adjust frame length
*/
static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
{
u32 reg;
u32 dft;
if (dwc->revision < DWC3_REVISION_250A)
return;
if (fladj == 0)
return;
reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
dft = reg & DWC3_GFLADJ_30MHZ_MASK;
if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
"request value same as default, ignoring\n")) {
reg &= ~DWC3_GFLADJ_30MHZ_MASK;
reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
}
}
/** /**
* dwc3_free_one_event_buffer - Frees one event buffer * dwc3_free_one_event_buffer - Frees one event buffer
* @dwc: Pointer to our controller context structure * @dwc: Pointer to our controller context structure
...@@ -779,6 +805,7 @@ static int dwc3_probe(struct platform_device *pdev) ...@@ -779,6 +805,7 @@ static int dwc3_probe(struct platform_device *pdev)
u8 lpm_nyet_threshold; u8 lpm_nyet_threshold;
u8 tx_de_emphasis; u8 tx_de_emphasis;
u8 hird_threshold; u8 hird_threshold;
u32 fladj = 0;
int ret; int ret;
...@@ -886,6 +913,9 @@ static int dwc3_probe(struct platform_device *pdev) ...@@ -886,6 +913,9 @@ static int dwc3_probe(struct platform_device *pdev)
&tx_de_emphasis); &tx_de_emphasis);
of_property_read_string(node, "snps,hsphy_interface", of_property_read_string(node, "snps,hsphy_interface",
&dwc->hsphy_interface); &dwc->hsphy_interface);
of_property_read_u32(node,
"snps,quirk-frame-length-adjustment",
&fladj);
} else if (pdata) { } else if (pdata) {
dwc->maximum_speed = pdata->maximum_speed; dwc->maximum_speed = pdata->maximum_speed;
dwc->has_lpm_erratum = pdata->has_lpm_erratum; dwc->has_lpm_erratum = pdata->has_lpm_erratum;
...@@ -915,6 +945,7 @@ static int dwc3_probe(struct platform_device *pdev) ...@@ -915,6 +945,7 @@ static int dwc3_probe(struct platform_device *pdev)
tx_de_emphasis = pdata->tx_de_emphasis; tx_de_emphasis = pdata->tx_de_emphasis;
dwc->hsphy_interface = pdata->hsphy_interface; dwc->hsphy_interface = pdata->hsphy_interface;
fladj = pdata->fladj_value;
} }
/* default to superspeed if no maximum_speed passed */ /* default to superspeed if no maximum_speed passed */
...@@ -971,6 +1002,9 @@ static int dwc3_probe(struct platform_device *pdev) ...@@ -971,6 +1002,9 @@ static int dwc3_probe(struct platform_device *pdev)
goto err1; goto err1;
} }
/* Adjust Frame Length */
dwc3_frame_length_adjustment(dwc, fladj);
usb_phy_set_suspend(dwc->usb2_phy, 0); usb_phy_set_suspend(dwc->usb2_phy, 0);
usb_phy_set_suspend(dwc->usb3_phy, 0); usb_phy_set_suspend(dwc->usb3_phy, 0);
ret = phy_power_on(dwc->usb2_generic_phy); ret = phy_power_on(dwc->usb2_generic_phy);
......
...@@ -124,6 +124,7 @@ ...@@ -124,6 +124,7 @@
#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
#define DWC3_GHWPARAMS8 0xc600 #define DWC3_GHWPARAMS8 0xc600
#define DWC3_GFLADJ 0xc630
/* Device Registers */ /* Device Registers */
#define DWC3_DCFG 0xc700 #define DWC3_DCFG 0xc700
...@@ -234,6 +235,10 @@ ...@@ -234,6 +235,10 @@
/* Global HWPARAMS6 Register */ /* Global HWPARAMS6 Register */
#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
/* Global Frame Length Adjustment Register */
#define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
#define DWC3_GFLADJ_30MHZ_MASK 0x3f
/* Device Configuration Register */ /* Device Configuration Register */
#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
......
...@@ -46,5 +46,7 @@ struct dwc3_platform_data { ...@@ -46,5 +46,7 @@ struct dwc3_platform_data {
unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis_quirk:1;
unsigned tx_de_emphasis:2; unsigned tx_de_emphasis:2;
u32 fladj_value;
const char *hsphy_interface; const char *hsphy_interface;
}; };
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