Commit dc73b45a authored by Ben Skeggs's avatar Ben Skeggs

drm/nouveau: store supported dma mask in vmmgr

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent c0abf5c9
...@@ -69,6 +69,7 @@ struct nouveau_vmmgr { ...@@ -69,6 +69,7 @@ struct nouveau_vmmgr {
struct nouveau_subdev base; struct nouveau_subdev base;
u64 limit; u64 limit;
u8 dma_bits;
u32 pgt_bits; u32 pgt_bits;
u8 spg_shift; u8 spg_shift;
u8 lpg_shift; u8 lpg_shift;
......
...@@ -97,6 +97,7 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -97,6 +97,7 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.create = nv04_vm_create; priv->base.create = nv04_vm_create;
priv->base.limit = NV04_PDMA_SIZE; priv->base.limit = NV04_PDMA_SIZE;
priv->base.dma_bits = 32;
priv->base.pgt_bits = 32 - 12; priv->base.pgt_bits = 32 - 12;
priv->base.spg_shift = 12; priv->base.spg_shift = 12;
priv->base.lpg_shift = 12; priv->base.lpg_shift = 12;
......
...@@ -98,6 +98,7 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -98,6 +98,7 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.create = nv04_vm_create; priv->base.create = nv04_vm_create;
priv->base.limit = NV41_GART_SIZE; priv->base.limit = NV41_GART_SIZE;
priv->base.dma_bits = 39;
priv->base.pgt_bits = 32 - 12; priv->base.pgt_bits = 32 - 12;
priv->base.spg_shift = 12; priv->base.spg_shift = 12;
priv->base.lpg_shift = 12; priv->base.lpg_shift = 12;
......
...@@ -179,6 +179,7 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -179,6 +179,7 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.create = nv04_vm_create; priv->base.create = nv04_vm_create;
priv->base.limit = NV44_GART_SIZE; priv->base.limit = NV44_GART_SIZE;
priv->base.dma_bits = 39;
priv->base.pgt_bits = 32 - 12; priv->base.pgt_bits = 32 - 12;
priv->base.spg_shift = 12; priv->base.spg_shift = 12;
priv->base.lpg_shift = 12; priv->base.lpg_shift = 12;
......
...@@ -201,6 +201,7 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -201,6 +201,7 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret; return ret;
priv->base.limit = 1ULL << 40; priv->base.limit = 1ULL << 40;
priv->base.dma_bits = 40;
priv->base.pgt_bits = 29 - 12; priv->base.pgt_bits = 29 - 12;
priv->base.spg_shift = 12; priv->base.spg_shift = 12;
priv->base.lpg_shift = 16; priv->base.lpg_shift = 16;
......
...@@ -163,6 +163,7 @@ nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -163,6 +163,7 @@ nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret; return ret;
priv->base.limit = 1ULL << 40; priv->base.limit = 1ULL << 40;
priv->base.dma_bits = 40;
priv->base.pgt_bits = 27 - 12; priv->base.pgt_bits = 27 - 12;
priv->base.spg_shift = 12; priv->base.spg_shift = 12;
priv->base.lpg_shift = 17; priv->base.lpg_shift = 17;
......
...@@ -340,14 +340,10 @@ nouveau_ttm_init(struct nouveau_drm *drm) ...@@ -340,14 +340,10 @@ nouveau_ttm_init(struct nouveau_drm *drm)
u32 bits; u32 bits;
int ret; int ret;
if (nv_device(drm->device)->card_type >= NV_50) { bits = nouveau_vmmgr(drm->device)->dma_bits;
if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40))) if ( drm->agp.stat == ENABLED ||
bits = 40; !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
else
bits = 32; bits = 32;
} else {
bits = 32;
}
ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits)); ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits));
if (ret) if (ret)
......
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