drm/i915: Remove duplicate DDI enabling logic from MST path

The logic to enable a DDI in intel_mst_pre_enable_dp() is essentially
the same as in intel_ddi_pre_enable_dp(). So reuse the latter function
by calling the post_disable hook on the intel_dig_port instead of
duplicating that code.

v2: Don't oops because of a NULL encoder->crtc. (Ville)
v3: Warn for MST + PORT_E too. (Ville)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170302125857.14665-8-ander.conselvan.de.oliveira@intel.com
parent 3dc38eea
...@@ -1713,6 +1713,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, ...@@ -1713,6 +1713,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
enum port port = intel_ddi_get_encoder_port(encoder); enum port port = intel_ddi_get_encoder_port(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
intel_dp_set_link_params(intel_dp, link_rate, lane_count, intel_dp_set_link_params(intel_dp, link_rate, lane_count,
link_mst); link_mst);
if (encoder->type == INTEL_OUTPUT_EDP) if (encoder->type == INTEL_OUTPUT_EDP)
......
...@@ -159,26 +159,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, ...@@ -159,26 +159,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
if (intel_dp->active_mst_links == 0) { if (intel_dp->active_mst_links == 0)
intel_ddi_clk_select(&intel_dig_port->base, intel_dig_port->base.pre_enable(&intel_dig_port->base,
pipe_config->shared_dpll); pipe_config, NULL);
intel_display_power_get(dev_priv,
intel_dig_port->ddi_io_power_domain);
intel_prepare_dp_ddi_buffers(&intel_dig_port->base);
intel_dp_set_link_params(intel_dp,
pipe_config->port_clock,
pipe_config->lane_count,
true);
intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
intel_dp_stop_link_train(intel_dp);
}
ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr,
connector->port, connector->port,
......
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