Commit e1641531 authored by Shawn Guo's avatar Shawn Guo

pinctrl: imx: move hard-coding data into device tree

Currently, all imx pinctrl drivers maintain a big array of struct
imx_pin_reg which hard-codes data like register offset and mux mode
setting for each pin function.  Every time a new imx SoC support is
added, we need to add such a big mount of data.  With moving to single
kernel build, it's only matter of time to be blamed on memory consuming.

With DTC pre-processor support in place, the patch moves all these data
into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and
changing the PIN_FUNC_ID parsing code a little bit.

The pin id gets re-numbered based on mux register offset, or config
register offset if the pin has no mux register, so that kernel can
identify the pin id from register offsets provided by device tree.

As a bonus point of the change, those arbitrary magic numbers standing
for particular PIN_FUNC_ID in device tree sources are now replaced by
macros to improve the readability of dts files.
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Acked-by: default avatarDong Aisheng <dong.aisheng@linaro.org>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 36dffd8f
......@@ -24,9 +24,9 @@ Required properties for iomux controller:
Required properties for pin configuration node:
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
pins and functions of each SoC.
pin working on a specific function, which consists of a tuple of
<mux_reg conf_reg input_reg mux_val input_val>. CONFIG is the pad setting
value like pull-up on this pin.
Bits used for CONFIG:
NO_PAD_CTL(1 << 31): indicate this pin does not need config.
......
......@@ -29,956 +29,5 @@ PAD_CTL_DSE_MAX (2 << 1)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
See below for available PIN_FUNC_ID for imx35:
0 MX35_PAD_CAPTURE__GPT_CAPIN1
1 MX35_PAD_CAPTURE__GPT_CMPOUT2
2 MX35_PAD_CAPTURE__CSPI2_SS1
3 MX35_PAD_CAPTURE__EPIT1_EPITO
4 MX35_PAD_CAPTURE__CCM_CLK32K
5 MX35_PAD_CAPTURE__GPIO1_4
6 MX35_PAD_COMPARE__GPT_CMPOUT1
7 MX35_PAD_COMPARE__GPT_CAPIN2
8 MX35_PAD_COMPARE__GPT_CMPOUT3
9 MX35_PAD_COMPARE__EPIT2_EPITO
10 MX35_PAD_COMPARE__GPIO1_5
11 MX35_PAD_COMPARE__SDMA_EXTDMA_2
12 MX35_PAD_WDOG_RST__WDOG_WDOG_B
13 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE
14 MX35_PAD_WDOG_RST__GPIO1_6
15 MX35_PAD_GPIO1_0__GPIO1_0
16 MX35_PAD_GPIO1_0__CCM_PMIC_RDY
17 MX35_PAD_GPIO1_0__OWIRE_LINE
18 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0
19 MX35_PAD_GPIO1_1__GPIO1_1
20 MX35_PAD_GPIO1_1__PWM_PWMO
21 MX35_PAD_GPIO1_1__CSPI1_SS2
22 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT
23 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1
24 MX35_PAD_GPIO2_0__GPIO2_0
25 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK
26 MX35_PAD_GPIO3_0__GPIO3_0
27 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK
28 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B
29 MX35_PAD_POR_B__CCM_POR_B
30 MX35_PAD_CLKO__CCM_CLKO
31 MX35_PAD_CLKO__GPIO1_8
32 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0
33 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1
34 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0
35 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1
36 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26
37 MX35_PAD_VSTBY__CCM_VSTBY
38 MX35_PAD_VSTBY__GPIO1_7
39 MX35_PAD_A0__EMI_EIM_DA_L_0
40 MX35_PAD_A1__EMI_EIM_DA_L_1
41 MX35_PAD_A2__EMI_EIM_DA_L_2
42 MX35_PAD_A3__EMI_EIM_DA_L_3
43 MX35_PAD_A4__EMI_EIM_DA_L_4
44 MX35_PAD_A5__EMI_EIM_DA_L_5
45 MX35_PAD_A6__EMI_EIM_DA_L_6
46 MX35_PAD_A7__EMI_EIM_DA_L_7
47 MX35_PAD_A8__EMI_EIM_DA_H_8
48 MX35_PAD_A9__EMI_EIM_DA_H_9
49 MX35_PAD_A10__EMI_EIM_DA_H_10
50 MX35_PAD_MA10__EMI_MA10
51 MX35_PAD_A11__EMI_EIM_DA_H_11
52 MX35_PAD_A12__EMI_EIM_DA_H_12
53 MX35_PAD_A13__EMI_EIM_DA_H_13
54 MX35_PAD_A14__EMI_EIM_DA_H2_14
55 MX35_PAD_A15__EMI_EIM_DA_H2_15
56 MX35_PAD_A16__EMI_EIM_A_16
57 MX35_PAD_A17__EMI_EIM_A_17
58 MX35_PAD_A18__EMI_EIM_A_18
59 MX35_PAD_A19__EMI_EIM_A_19
60 MX35_PAD_A20__EMI_EIM_A_20
61 MX35_PAD_A21__EMI_EIM_A_21
62 MX35_PAD_A22__EMI_EIM_A_22
63 MX35_PAD_A23__EMI_EIM_A_23
64 MX35_PAD_A24__EMI_EIM_A_24
65 MX35_PAD_A25__EMI_EIM_A_25
66 MX35_PAD_SDBA1__EMI_EIM_SDBA1
67 MX35_PAD_SDBA0__EMI_EIM_SDBA0
68 MX35_PAD_SD0__EMI_DRAM_D_0
69 MX35_PAD_SD1__EMI_DRAM_D_1
70 MX35_PAD_SD2__EMI_DRAM_D_2
71 MX35_PAD_SD3__EMI_DRAM_D_3
72 MX35_PAD_SD4__EMI_DRAM_D_4
73 MX35_PAD_SD5__EMI_DRAM_D_5
74 MX35_PAD_SD6__EMI_DRAM_D_6
75 MX35_PAD_SD7__EMI_DRAM_D_7
76 MX35_PAD_SD8__EMI_DRAM_D_8
77 MX35_PAD_SD9__EMI_DRAM_D_9
78 MX35_PAD_SD10__EMI_DRAM_D_10
79 MX35_PAD_SD11__EMI_DRAM_D_11
80 MX35_PAD_SD12__EMI_DRAM_D_12
81 MX35_PAD_SD13__EMI_DRAM_D_13
82 MX35_PAD_SD14__EMI_DRAM_D_14
83 MX35_PAD_SD15__EMI_DRAM_D_15
84 MX35_PAD_SD16__EMI_DRAM_D_16
85 MX35_PAD_SD17__EMI_DRAM_D_17
86 MX35_PAD_SD18__EMI_DRAM_D_18
87 MX35_PAD_SD19__EMI_DRAM_D_19
88 MX35_PAD_SD20__EMI_DRAM_D_20
89 MX35_PAD_SD21__EMI_DRAM_D_21
90 MX35_PAD_SD22__EMI_DRAM_D_22
91 MX35_PAD_SD23__EMI_DRAM_D_23
92 MX35_PAD_SD24__EMI_DRAM_D_24
93 MX35_PAD_SD25__EMI_DRAM_D_25
94 MX35_PAD_SD26__EMI_DRAM_D_26
95 MX35_PAD_SD27__EMI_DRAM_D_27
96 MX35_PAD_SD28__EMI_DRAM_D_28
97 MX35_PAD_SD29__EMI_DRAM_D_29
98 MX35_PAD_SD30__EMI_DRAM_D_30
99 MX35_PAD_SD31__EMI_DRAM_D_31
100 MX35_PAD_DQM0__EMI_DRAM_DQM_0
101 MX35_PAD_DQM1__EMI_DRAM_DQM_1
102 MX35_PAD_DQM2__EMI_DRAM_DQM_2
103 MX35_PAD_DQM3__EMI_DRAM_DQM_3
104 MX35_PAD_EB0__EMI_EIM_EB0_B
105 MX35_PAD_EB1__EMI_EIM_EB1_B
106 MX35_PAD_OE__EMI_EIM_OE
107 MX35_PAD_CS0__EMI_EIM_CS0
108 MX35_PAD_CS1__EMI_EIM_CS1
109 MX35_PAD_CS1__EMI_NANDF_CE3
110 MX35_PAD_CS2__EMI_EIM_CS2
111 MX35_PAD_CS3__EMI_EIM_CS3
112 MX35_PAD_CS4__EMI_EIM_CS4
113 MX35_PAD_CS4__EMI_DTACK_B
114 MX35_PAD_CS4__EMI_NANDF_CE1
115 MX35_PAD_CS4__GPIO1_20
116 MX35_PAD_CS5__EMI_EIM_CS5
117 MX35_PAD_CS5__CSPI2_SS2
118 MX35_PAD_CS5__CSPI1_SS2
119 MX35_PAD_CS5__EMI_NANDF_CE2
120 MX35_PAD_CS5__GPIO1_21
121 MX35_PAD_NF_CE0__EMI_NANDF_CE0
122 MX35_PAD_NF_CE0__GPIO1_22
123 MX35_PAD_ECB__EMI_EIM_ECB
124 MX35_PAD_LBA__EMI_EIM_LBA
125 MX35_PAD_BCLK__EMI_EIM_BCLK
126 MX35_PAD_RW__EMI_EIM_RW
127 MX35_PAD_RAS__EMI_DRAM_RAS
128 MX35_PAD_CAS__EMI_DRAM_CAS
129 MX35_PAD_SDWE__EMI_DRAM_SDWE
130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0
131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1
132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK
133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0
134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1
135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2
136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3
137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B
138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3
139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC
140 MX35_PAD_NFWE_B__GPIO2_18
141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0
142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B
143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR
144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK
145 MX35_PAD_NFRE_B__GPIO2_19
146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1
147 MX35_PAD_NFALE__EMI_NANDF_ALE
148 MX35_PAD_NFALE__USB_TOP_USBH2_STP
149 MX35_PAD_NFALE__IPU_DISPB_CS0
150 MX35_PAD_NFALE__GPIO2_20
151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2
152 MX35_PAD_NFCLE__EMI_NANDF_CLE
153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT
154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS
155 MX35_PAD_NFCLE__GPIO2_21
156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3
157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B
158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7
159 MX35_PAD_NFWP_B__IPU_DISPB_WR
160 MX35_PAD_NFWP_B__GPIO2_22
161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL
162 MX35_PAD_NFRB__EMI_NANDF_RB
163 MX35_PAD_NFRB__IPU_DISPB_RD
164 MX35_PAD_NFRB__GPIO2_23
165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK
166 MX35_PAD_D15__EMI_EIM_D_15
167 MX35_PAD_D14__EMI_EIM_D_14
168 MX35_PAD_D13__EMI_EIM_D_13
169 MX35_PAD_D12__EMI_EIM_D_12
170 MX35_PAD_D11__EMI_EIM_D_11
171 MX35_PAD_D10__EMI_EIM_D_10
172 MX35_PAD_D9__EMI_EIM_D_9
173 MX35_PAD_D8__EMI_EIM_D_8
174 MX35_PAD_D7__EMI_EIM_D_7
175 MX35_PAD_D6__EMI_EIM_D_6
176 MX35_PAD_D5__EMI_EIM_D_5
177 MX35_PAD_D4__EMI_EIM_D_4
178 MX35_PAD_D3__EMI_EIM_D_3
179 MX35_PAD_D2__EMI_EIM_D_2
180 MX35_PAD_D1__EMI_EIM_D_1
181 MX35_PAD_D0__EMI_EIM_D_0
182 MX35_PAD_CSI_D8__IPU_CSI_D_8
183 MX35_PAD_CSI_D8__KPP_COL_0
184 MX35_PAD_CSI_D8__GPIO1_20
185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13
186 MX35_PAD_CSI_D9__IPU_CSI_D_9
187 MX35_PAD_CSI_D9__KPP_COL_1
188 MX35_PAD_CSI_D9__GPIO1_21
189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14
190 MX35_PAD_CSI_D10__IPU_CSI_D_10
191 MX35_PAD_CSI_D10__KPP_COL_2
192 MX35_PAD_CSI_D10__GPIO1_22
193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15
194 MX35_PAD_CSI_D11__IPU_CSI_D_11
195 MX35_PAD_CSI_D11__KPP_COL_3
196 MX35_PAD_CSI_D11__GPIO1_23
197 MX35_PAD_CSI_D12__IPU_CSI_D_12
198 MX35_PAD_CSI_D12__KPP_ROW_0
199 MX35_PAD_CSI_D12__GPIO1_24
200 MX35_PAD_CSI_D13__IPU_CSI_D_13
201 MX35_PAD_CSI_D13__KPP_ROW_1
202 MX35_PAD_CSI_D13__GPIO1_25
203 MX35_PAD_CSI_D14__IPU_CSI_D_14
204 MX35_PAD_CSI_D14__KPP_ROW_2
205 MX35_PAD_CSI_D14__GPIO1_26
206 MX35_PAD_CSI_D15__IPU_CSI_D_15
207 MX35_PAD_CSI_D15__KPP_ROW_3
208 MX35_PAD_CSI_D15__GPIO1_27
209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK
210 MX35_PAD_CSI_MCLK__GPIO1_28
211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC
212 MX35_PAD_CSI_VSYNC__GPIO1_29
213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC
214 MX35_PAD_CSI_HSYNC__GPIO1_30
215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK
216 MX35_PAD_CSI_PIXCLK__GPIO1_31
217 MX35_PAD_I2C1_CLK__I2C1_SCL
218 MX35_PAD_I2C1_CLK__GPIO2_24
219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK
220 MX35_PAD_I2C1_DAT__I2C1_SDA
221 MX35_PAD_I2C1_DAT__GPIO2_25
222 MX35_PAD_I2C2_CLK__I2C2_SCL
223 MX35_PAD_I2C2_CLK__CAN1_TXCAN
224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
225 MX35_PAD_I2C2_CLK__GPIO2_26
226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2
227 MX35_PAD_I2C2_DAT__I2C2_SDA
228 MX35_PAD_I2C2_DAT__CAN1_RXCAN
229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
230 MX35_PAD_I2C2_DAT__GPIO2_27
231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3
232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD
233 MX35_PAD_STXD4__GPIO2_28
234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0
235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
236 MX35_PAD_SRXD4__GPIO2_29
237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1
238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC
239 MX35_PAD_SCK4__GPIO2_30
240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2
241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS
242 MX35_PAD_STXFS4__GPIO2_31
243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3
244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD
245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1
246 MX35_PAD_STXD5__CSPI2_MOSI
247 MX35_PAD_STXD5__GPIO1_0
248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4
249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD
250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1
251 MX35_PAD_SRXD5__CSPI2_MISO
252 MX35_PAD_SRXD5__GPIO1_1
253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5
254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC
255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK
256 MX35_PAD_SCK5__CSPI2_SCLK
257 MX35_PAD_SCK5__GPIO1_2
258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6
259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS
260 MX35_PAD_STXFS5__CSPI2_RDY
261 MX35_PAD_STXFS5__GPIO1_3
262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7
263 MX35_PAD_SCKR__ESAI_SCKR
264 MX35_PAD_SCKR__GPIO1_4
265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10
266 MX35_PAD_FSR__ESAI_FSR
267 MX35_PAD_FSR__GPIO1_5
268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11
269 MX35_PAD_HCKR__ESAI_HCKR
270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS
271 MX35_PAD_HCKR__CSPI2_SS0
272 MX35_PAD_HCKR__IPU_FLASH_STROBE
273 MX35_PAD_HCKR__GPIO1_6
274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12
275 MX35_PAD_SCKT__ESAI_SCKT
276 MX35_PAD_SCKT__GPIO1_7
277 MX35_PAD_SCKT__IPU_CSI_D_0
278 MX35_PAD_SCKT__KPP_ROW_2
279 MX35_PAD_FST__ESAI_FST
280 MX35_PAD_FST__GPIO1_8
281 MX35_PAD_FST__IPU_CSI_D_1
282 MX35_PAD_FST__KPP_ROW_3
283 MX35_PAD_HCKT__ESAI_HCKT
284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC
285 MX35_PAD_HCKT__GPIO1_9
286 MX35_PAD_HCKT__IPU_CSI_D_2
287 MX35_PAD_HCKT__KPP_COL_3
288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0
289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC
290 MX35_PAD_TX5_RX0__CSPI2_SS2
291 MX35_PAD_TX5_RX0__CAN2_TXCAN
292 MX35_PAD_TX5_RX0__UART2_DTR
293 MX35_PAD_TX5_RX0__GPIO1_10
294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0
295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1
296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS
297 MX35_PAD_TX4_RX1__CSPI2_SS3
298 MX35_PAD_TX4_RX1__CAN2_RXCAN
299 MX35_PAD_TX4_RX1__UART2_DSR
300 MX35_PAD_TX4_RX1__GPIO1_11
301 MX35_PAD_TX4_RX1__IPU_CSI_D_3
302 MX35_PAD_TX4_RX1__KPP_ROW_0
303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2
304 MX35_PAD_TX3_RX2__I2C3_SCL
305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1
306 MX35_PAD_TX3_RX2__GPIO1_12
307 MX35_PAD_TX3_RX2__IPU_CSI_D_4
308 MX35_PAD_TX3_RX2__KPP_ROW_1
309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3
310 MX35_PAD_TX2_RX3__I2C3_SDA
311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2
312 MX35_PAD_TX2_RX3__GPIO1_13
313 MX35_PAD_TX2_RX3__IPU_CSI_D_5
314 MX35_PAD_TX2_RX3__KPP_COL_0
315 MX35_PAD_TX1__ESAI_TX1
316 MX35_PAD_TX1__CCM_PMIC_RDY
317 MX35_PAD_TX1__CSPI1_SS2
318 MX35_PAD_TX1__EMI_NANDF_CE3
319 MX35_PAD_TX1__UART2_RI
320 MX35_PAD_TX1__GPIO1_14
321 MX35_PAD_TX1__IPU_CSI_D_6
322 MX35_PAD_TX1__KPP_COL_1
323 MX35_PAD_TX0__ESAI_TX0
324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK
325 MX35_PAD_TX0__CSPI1_SS3
326 MX35_PAD_TX0__EMI_DTACK_B
327 MX35_PAD_TX0__UART2_DCD
328 MX35_PAD_TX0__GPIO1_15
329 MX35_PAD_TX0__IPU_CSI_D_7
330 MX35_PAD_TX0__KPP_COL_2
331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI
332 MX35_PAD_CSPI1_MOSI__GPIO1_16
333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2
334 MX35_PAD_CSPI1_MISO__CSPI1_MISO
335 MX35_PAD_CSPI1_MISO__GPIO1_17
336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3
337 MX35_PAD_CSPI1_SS0__CSPI1_SS0
338 MX35_PAD_CSPI1_SS0__OWIRE_LINE
339 MX35_PAD_CSPI1_SS0__CSPI2_SS3
340 MX35_PAD_CSPI1_SS0__GPIO1_18
341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4
342 MX35_PAD_CSPI1_SS1__CSPI1_SS1
343 MX35_PAD_CSPI1_SS1__PWM_PWMO
344 MX35_PAD_CSPI1_SS1__CCM_CLK32K
345 MX35_PAD_CSPI1_SS1__GPIO1_19
346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29
347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5
348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK
349 MX35_PAD_CSPI1_SCLK__GPIO3_4
350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30
351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1
352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY
353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5
354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31
355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2
356 MX35_PAD_RXD1__UART1_RXD_MUX
357 MX35_PAD_RXD1__CSPI2_MOSI
358 MX35_PAD_RXD1__KPP_COL_4
359 MX35_PAD_RXD1__GPIO3_6
360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16
361 MX35_PAD_TXD1__UART1_TXD_MUX
362 MX35_PAD_TXD1__CSPI2_MISO
363 MX35_PAD_TXD1__KPP_COL_5
364 MX35_PAD_TXD1__GPIO3_7
365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17
366 MX35_PAD_RTS1__UART1_RTS
367 MX35_PAD_RTS1__CSPI2_SCLK
368 MX35_PAD_RTS1__I2C3_SCL
369 MX35_PAD_RTS1__IPU_CSI_D_0
370 MX35_PAD_RTS1__KPP_COL_6
371 MX35_PAD_RTS1__GPIO3_8
372 MX35_PAD_RTS1__EMI_NANDF_CE1
373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18
374 MX35_PAD_CTS1__UART1_CTS
375 MX35_PAD_CTS1__CSPI2_RDY
376 MX35_PAD_CTS1__I2C3_SDA
377 MX35_PAD_CTS1__IPU_CSI_D_1
378 MX35_PAD_CTS1__KPP_COL_7
379 MX35_PAD_CTS1__GPIO3_9
380 MX35_PAD_CTS1__EMI_NANDF_CE2
381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19
382 MX35_PAD_RXD2__UART2_RXD_MUX
383 MX35_PAD_RXD2__KPP_ROW_4
384 MX35_PAD_RXD2__GPIO3_10
385 MX35_PAD_TXD2__UART2_TXD_MUX
386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK
387 MX35_PAD_TXD2__KPP_ROW_5
388 MX35_PAD_TXD2__GPIO3_11
389 MX35_PAD_RTS2__UART2_RTS
390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1
391 MX35_PAD_RTS2__CAN2_RXCAN
392 MX35_PAD_RTS2__IPU_CSI_D_2
393 MX35_PAD_RTS2__KPP_ROW_6
394 MX35_PAD_RTS2__GPIO3_12
395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC
396 MX35_PAD_RTS2__UART3_RXD_MUX
397 MX35_PAD_CTS2__UART2_CTS
398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1
399 MX35_PAD_CTS2__CAN2_TXCAN
400 MX35_PAD_CTS2__IPU_CSI_D_3
401 MX35_PAD_CTS2__KPP_ROW_7
402 MX35_PAD_CTS2__GPIO3_13
403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS
404 MX35_PAD_CTS2__UART3_TXD_MUX
405 MX35_PAD_RTCK__ARM11P_TOP_RTCK
406 MX35_PAD_TCK__SJC_TCK
407 MX35_PAD_TMS__SJC_TMS
408 MX35_PAD_TDI__SJC_TDI
409 MX35_PAD_TDO__SJC_TDO
410 MX35_PAD_TRSTB__SJC_TRSTB
411 MX35_PAD_DE_B__SJC_DE_B
412 MX35_PAD_SJC_MOD__SJC_MOD
413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR
415 MX35_PAD_USBOTG_PWR__GPIO3_14
416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC
418 MX35_PAD_USBOTG_OC__GPIO3_15
419 MX35_PAD_LD0__IPU_DISPB_DAT_0
420 MX35_PAD_LD0__GPIO2_0
421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0
422 MX35_PAD_LD1__IPU_DISPB_DAT_1
423 MX35_PAD_LD1__GPIO2_1
424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1
425 MX35_PAD_LD2__IPU_DISPB_DAT_2
426 MX35_PAD_LD2__GPIO2_2
427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2
428 MX35_PAD_LD3__IPU_DISPB_DAT_3
429 MX35_PAD_LD3__GPIO2_3
430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3
431 MX35_PAD_LD4__IPU_DISPB_DAT_4
432 MX35_PAD_LD4__GPIO2_4
433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4
434 MX35_PAD_LD5__IPU_DISPB_DAT_5
435 MX35_PAD_LD5__GPIO2_5
436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5
437 MX35_PAD_LD6__IPU_DISPB_DAT_6
438 MX35_PAD_LD6__GPIO2_6
439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6
440 MX35_PAD_LD7__IPU_DISPB_DAT_7
441 MX35_PAD_LD7__GPIO2_7
442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7
443 MX35_PAD_LD8__IPU_DISPB_DAT_8
444 MX35_PAD_LD8__GPIO2_8
445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8
446 MX35_PAD_LD9__IPU_DISPB_DAT_9
447 MX35_PAD_LD9__GPIO2_9
448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9
449 MX35_PAD_LD10__IPU_DISPB_DAT_10
450 MX35_PAD_LD10__GPIO2_10
451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10
452 MX35_PAD_LD11__IPU_DISPB_DAT_11
453 MX35_PAD_LD11__GPIO2_11
454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11
455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4
456 MX35_PAD_LD12__IPU_DISPB_DAT_12
457 MX35_PAD_LD12__GPIO2_12
458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12
459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5
460 MX35_PAD_LD13__IPU_DISPB_DAT_13
461 MX35_PAD_LD13__GPIO2_13
462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13
463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6
464 MX35_PAD_LD14__IPU_DISPB_DAT_14
465 MX35_PAD_LD14__GPIO2_14
466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0
467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7
468 MX35_PAD_LD15__IPU_DISPB_DAT_15
469 MX35_PAD_LD15__GPIO2_15
470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1
471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8
472 MX35_PAD_LD16__IPU_DISPB_DAT_16
473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC
474 MX35_PAD_LD16__GPIO2_16
475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2
476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9
477 MX35_PAD_LD17__IPU_DISPB_DAT_17
478 MX35_PAD_LD17__IPU_DISPB_CS2
479 MX35_PAD_LD17__GPIO2_17
480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3
481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10
482 MX35_PAD_LD18__IPU_DISPB_DAT_18
483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC
484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC
485 MX35_PAD_LD18__ESDHC3_CMD
486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3
487 MX35_PAD_LD18__GPIO3_24
488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4
489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11
490 MX35_PAD_LD19__IPU_DISPB_DAT_19
491 MX35_PAD_LD19__IPU_DISPB_BCLK
492 MX35_PAD_LD19__IPU_DISPB_CS1
493 MX35_PAD_LD19__ESDHC3_CLK
494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR
495 MX35_PAD_LD19__GPIO3_25
496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5
497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12
498 MX35_PAD_LD20__IPU_DISPB_DAT_20
499 MX35_PAD_LD20__IPU_DISPB_CS0
500 MX35_PAD_LD20__IPU_DISPB_SD_CLK
501 MX35_PAD_LD20__ESDHC3_DAT0
502 MX35_PAD_LD20__GPIO3_26
503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3
504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13
505 MX35_PAD_LD21__IPU_DISPB_DAT_21
506 MX35_PAD_LD21__IPU_DISPB_PAR_RS
507 MX35_PAD_LD21__IPU_DISPB_SER_RS
508 MX35_PAD_LD21__ESDHC3_DAT1
509 MX35_PAD_LD21__USB_TOP_USBOTG_STP
510 MX35_PAD_LD21__GPIO3_27
511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL
512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14
513 MX35_PAD_LD22__IPU_DISPB_DAT_22
514 MX35_PAD_LD22__IPU_DISPB_WR
515 MX35_PAD_LD22__IPU_DISPB_SD_D_I
516 MX35_PAD_LD22__ESDHC3_DAT2
517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT
518 MX35_PAD_LD22__GPIO3_28
519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR
520 MX35_PAD_LD22__ARM11P_TOP_TRCTL
521 MX35_PAD_LD23__IPU_DISPB_DAT_23
522 MX35_PAD_LD23__IPU_DISPB_RD
523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO
524 MX35_PAD_LD23__ESDHC3_DAT3
525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7
526 MX35_PAD_LD23__GPIO3_29
527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS
528 MX35_PAD_LD23__ARM11P_TOP_TRCLK
529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC
530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO
531 MX35_PAD_D3_HSYNC__GPIO3_30
532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE
533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15
534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK
535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK
536 MX35_PAD_D3_FPSHIFT__GPIO3_31
537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0
538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16
539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY
540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O
541 MX35_PAD_D3_DRDY__GPIO1_0
542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1
543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17
544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR
545 MX35_PAD_CONTRAST__GPIO1_1
546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2
547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18
548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC
549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1
550 MX35_PAD_D3_VSYNC__GPIO1_2
551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD
552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19
553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV
554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS
555 MX35_PAD_D3_REV__GPIO1_3
556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB
557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20
558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS
559 MX35_PAD_D3_CLS__IPU_DISPB_CS2
560 MX35_PAD_D3_CLS__GPIO1_4
561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0
562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21
563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC
565 MX35_PAD_D3_SPL__GPIO1_5
566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1
567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22
568 MX35_PAD_SD1_CMD__ESDHC1_CMD
569 MX35_PAD_SD1_CMD__MSHC_SCLK
570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC
571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4
572 MX35_PAD_SD1_CMD__GPIO1_6
573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL
574 MX35_PAD_SD1_CLK__ESDHC1_CLK
575 MX35_PAD_SD1_CLK__MSHC_BS
576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK
577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5
578 MX35_PAD_SD1_CLK__GPIO1_7
579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK
580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0
581 MX35_PAD_SD1_DATA0__MSHC_DATA_0
582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0
583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6
584 MX35_PAD_SD1_DATA0__GPIO1_8
585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23
586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1
587 MX35_PAD_SD1_DATA1__MSHC_DATA_1
588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS
589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0
590 MX35_PAD_SD1_DATA1__GPIO1_9
591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24
592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2
593 MX35_PAD_SD1_DATA2__MSHC_DATA_2
594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR
595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1
596 MX35_PAD_SD1_DATA2__GPIO1_10
597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25
598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3
599 MX35_PAD_SD1_DATA3__MSHC_DATA_3
600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD
601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2
602 MX35_PAD_SD1_DATA3__GPIO1_11
603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26
604 MX35_PAD_SD2_CMD__ESDHC2_CMD
605 MX35_PAD_SD2_CMD__I2C3_SCL
606 MX35_PAD_SD2_CMD__ESDHC1_DAT4
607 MX35_PAD_SD2_CMD__IPU_CSI_D_2
608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4
609 MX35_PAD_SD2_CMD__GPIO2_0
610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1
611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC
612 MX35_PAD_SD2_CLK__ESDHC2_CLK
613 MX35_PAD_SD2_CLK__I2C3_SDA
614 MX35_PAD_SD2_CLK__ESDHC1_DAT5
615 MX35_PAD_SD2_CLK__IPU_CSI_D_3
616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5
617 MX35_PAD_SD2_CLK__GPIO2_1
618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1
619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2
620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0
621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX
622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6
623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4
624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6
625 MX35_PAD_SD2_DATA0__GPIO2_2
626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK
627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1
628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX
629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7
630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5
631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0
632 MX35_PAD_SD2_DATA1__GPIO2_3
633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2
634 MX35_PAD_SD2_DATA2__UART3_RTS
635 MX35_PAD_SD2_DATA2__CAN1_RXCAN
636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6
637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1
638 MX35_PAD_SD2_DATA2__GPIO2_4
639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3
640 MX35_PAD_SD2_DATA3__UART3_CTS
641 MX35_PAD_SD2_DATA3__CAN1_TXCAN
642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7
643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2
644 MX35_PAD_SD2_DATA3__GPIO2_5
645 MX35_PAD_ATA_CS0__ATA_CS0
646 MX35_PAD_ATA_CS0__CSPI1_SS3
647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1
648 MX35_PAD_ATA_CS0__GPIO2_6
649 MX35_PAD_ATA_CS0__IPU_DIAGB_0
650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0
651 MX35_PAD_ATA_CS1__ATA_CS1
652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2
653 MX35_PAD_ATA_CS1__CSPI2_SS0
654 MX35_PAD_ATA_CS1__GPIO2_7
655 MX35_PAD_ATA_CS1__IPU_DIAGB_1
656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1
657 MX35_PAD_ATA_DIOR__ATA_DIOR
658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0
659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR
660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0
661 MX35_PAD_ATA_DIOR__CSPI2_SS1
662 MX35_PAD_ATA_DIOR__GPIO2_8
663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2
664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2
665 MX35_PAD_ATA_DIOW__ATA_DIOW
666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1
667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP
668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1
669 MX35_PAD_ATA_DIOW__CSPI2_MOSI
670 MX35_PAD_ATA_DIOW__GPIO2_9
671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3
672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3
673 MX35_PAD_ATA_DMACK__ATA_DMACK
674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2
675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT
676 MX35_PAD_ATA_DMACK__CSPI2_MISO
677 MX35_PAD_ATA_DMACK__GPIO2_10
678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4
679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0
680 MX35_PAD_ATA_RESET_B__ATA_RESET_B
681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3
682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0
683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O
684 MX35_PAD_ATA_RESET_B__CSPI2_RDY
685 MX35_PAD_ATA_RESET_B__GPIO2_11
686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5
687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1
688 MX35_PAD_ATA_IORDY__ATA_IORDY
689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4
690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1
691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO
692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4
693 MX35_PAD_ATA_IORDY__GPIO2_12
694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6
695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2
696 MX35_PAD_ATA_DATA0__ATA_DATA_0
697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5
698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2
699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC
700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5
701 MX35_PAD_ATA_DATA0__GPIO2_13
702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7
703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3
704 MX35_PAD_ATA_DATA1__ATA_DATA_1
705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6
706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3
707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK
708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6
709 MX35_PAD_ATA_DATA1__GPIO2_14
710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8
711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27
712 MX35_PAD_ATA_DATA2__ATA_DATA_2
713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7
714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4
715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS
716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7
717 MX35_PAD_ATA_DATA2__GPIO2_15
718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9
719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28
720 MX35_PAD_ATA_DATA3__ATA_DATA_3
721 MX35_PAD_ATA_DATA3__ESDHC3_CLK
722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5
723 MX35_PAD_ATA_DATA3__CSPI2_SCLK
724 MX35_PAD_ATA_DATA3__GPIO2_16
725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10
726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29
727 MX35_PAD_ATA_DATA4__ATA_DATA_4
728 MX35_PAD_ATA_DATA4__ESDHC3_CMD
729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6
730 MX35_PAD_ATA_DATA4__GPIO2_17
731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11
732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30
733 MX35_PAD_ATA_DATA5__ATA_DATA_5
734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7
735 MX35_PAD_ATA_DATA5__GPIO2_18
736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12
737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31
738 MX35_PAD_ATA_DATA6__ATA_DATA_6
739 MX35_PAD_ATA_DATA6__CAN1_TXCAN
740 MX35_PAD_ATA_DATA6__UART1_DTR
741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD
742 MX35_PAD_ATA_DATA6__GPIO2_19
743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13
744 MX35_PAD_ATA_DATA7__ATA_DATA_7
745 MX35_PAD_ATA_DATA7__CAN1_RXCAN
746 MX35_PAD_ATA_DATA7__UART1_DSR
747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD
748 MX35_PAD_ATA_DATA7__GPIO2_20
749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14
750 MX35_PAD_ATA_DATA8__ATA_DATA_8
751 MX35_PAD_ATA_DATA8__UART3_RTS
752 MX35_PAD_ATA_DATA8__UART1_RI
753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC
754 MX35_PAD_ATA_DATA8__GPIO2_21
755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15
756 MX35_PAD_ATA_DATA9__ATA_DATA_9
757 MX35_PAD_ATA_DATA9__UART3_CTS
758 MX35_PAD_ATA_DATA9__UART1_DCD
759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS
760 MX35_PAD_ATA_DATA9__GPIO2_22
761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16
762 MX35_PAD_ATA_DATA10__ATA_DATA_10
763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX
764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC
765 MX35_PAD_ATA_DATA10__GPIO2_23
766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17
767 MX35_PAD_ATA_DATA11__ATA_DATA_11
768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX
769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS
770 MX35_PAD_ATA_DATA11__GPIO2_24
771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18
772 MX35_PAD_ATA_DATA12__ATA_DATA_12
773 MX35_PAD_ATA_DATA12__I2C3_SCL
774 MX35_PAD_ATA_DATA12__GPIO2_25
775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19
776 MX35_PAD_ATA_DATA13__ATA_DATA_13
777 MX35_PAD_ATA_DATA13__I2C3_SDA
778 MX35_PAD_ATA_DATA13__GPIO2_26
779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20
780 MX35_PAD_ATA_DATA14__ATA_DATA_14
781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0
782 MX35_PAD_ATA_DATA14__KPP_ROW_0
783 MX35_PAD_ATA_DATA14__GPIO2_27
784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21
785 MX35_PAD_ATA_DATA15__ATA_DATA_15
786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1
787 MX35_PAD_ATA_DATA15__KPP_ROW_1
788 MX35_PAD_ATA_DATA15__GPIO2_28
789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22
790 MX35_PAD_ATA_INTRQ__ATA_INTRQ
791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2
792 MX35_PAD_ATA_INTRQ__KPP_ROW_2
793 MX35_PAD_ATA_INTRQ__GPIO2_29
794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23
795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN
796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3
797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3
798 MX35_PAD_ATA_BUFF_EN__GPIO2_30
799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24
800 MX35_PAD_ATA_DMARQ__ATA_DMARQ
801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4
802 MX35_PAD_ATA_DMARQ__KPP_COL_0
803 MX35_PAD_ATA_DMARQ__GPIO2_31
804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25
805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4
806 MX35_PAD_ATA_DA0__ATA_DA_0
807 MX35_PAD_ATA_DA0__IPU_CSI_D_5
808 MX35_PAD_ATA_DA0__KPP_COL_1
809 MX35_PAD_ATA_DA0__GPIO3_0
810 MX35_PAD_ATA_DA0__IPU_DIAGB_26
811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5
812 MX35_PAD_ATA_DA1__ATA_DA_1
813 MX35_PAD_ATA_DA1__IPU_CSI_D_6
814 MX35_PAD_ATA_DA1__KPP_COL_2
815 MX35_PAD_ATA_DA1__GPIO3_1
816 MX35_PAD_ATA_DA1__IPU_DIAGB_27
817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6
818 MX35_PAD_ATA_DA2__ATA_DA_2
819 MX35_PAD_ATA_DA2__IPU_CSI_D_7
820 MX35_PAD_ATA_DA2__KPP_COL_3
821 MX35_PAD_ATA_DA2__GPIO3_2
822 MX35_PAD_ATA_DA2__IPU_DIAGB_28
823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7
824 MX35_PAD_MLB_CLK__MLB_MLBCLK
825 MX35_PAD_MLB_CLK__GPIO3_3
826 MX35_PAD_MLB_DAT__MLB_MLBDAT
827 MX35_PAD_MLB_DAT__GPIO3_4
828 MX35_PAD_MLB_SIG__MLB_MLBSIG
829 MX35_PAD_MLB_SIG__GPIO3_5
830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK
831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4
832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX
833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR
834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI
835 MX35_PAD_FEC_TX_CLK__GPIO3_6
836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC
837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0
838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK
839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5
840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX
841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP
842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO
843 MX35_PAD_FEC_RX_CLK__GPIO3_7
844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I
845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1
846 MX35_PAD_FEC_RX_DV__FEC_RX_DV
847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6
848 MX35_PAD_FEC_RX_DV__UART3_RTS
849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT
850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK
851 MX35_PAD_FEC_RX_DV__GPIO3_8
852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK
853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2
854 MX35_PAD_FEC_COL__FEC_COL
855 MX35_PAD_FEC_COL__ESDHC1_DAT7
856 MX35_PAD_FEC_COL__UART3_CTS
857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0
858 MX35_PAD_FEC_COL__CSPI2_RDY
859 MX35_PAD_FEC_COL__GPIO3_9
860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS
861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3
862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0
863 MX35_PAD_FEC_RDATA0__PWM_PWMO
864 MX35_PAD_FEC_RDATA0__UART3_DTR
865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1
866 MX35_PAD_FEC_RDATA0__CSPI2_SS0
867 MX35_PAD_FEC_RDATA0__GPIO3_10
868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1
869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4
870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0
871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1
872 MX35_PAD_FEC_TDATA0__UART3_DSR
873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2
874 MX35_PAD_FEC_TDATA0__CSPI2_SS1
875 MX35_PAD_FEC_TDATA0__GPIO3_11
876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0
877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5
878 MX35_PAD_FEC_TX_EN__FEC_TX_EN
879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1
880 MX35_PAD_FEC_TX_EN__UART3_RI
881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3
882 MX35_PAD_FEC_TX_EN__GPIO3_12
883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS
884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6
885 MX35_PAD_FEC_MDC__FEC_MDC
886 MX35_PAD_FEC_MDC__CAN2_TXCAN
887 MX35_PAD_FEC_MDC__UART3_DCD
888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4
889 MX35_PAD_FEC_MDC__GPIO3_13
890 MX35_PAD_FEC_MDC__IPU_DISPB_WR
891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7
892 MX35_PAD_FEC_MDIO__FEC_MDIO
893 MX35_PAD_FEC_MDIO__CAN2_RXCAN
894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5
895 MX35_PAD_FEC_MDIO__GPIO3_14
896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD
897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8
898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR
899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE
900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK
901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6
902 MX35_PAD_FEC_TX_ERR__GPIO3_15
903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC
904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9
905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR
906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0
907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7
908 MX35_PAD_FEC_RX_ERR__KPP_COL_4
909 MX35_PAD_FEC_RX_ERR__GPIO3_16
910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO
911 MX35_PAD_FEC_CRS__FEC_CRS
912 MX35_PAD_FEC_CRS__IPU_CSI_D_1
913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR
914 MX35_PAD_FEC_CRS__KPP_COL_5
915 MX35_PAD_FEC_CRS__GPIO3_17
916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE
917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1
918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2
919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC
920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC
921 MX35_PAD_FEC_RDATA1__KPP_COL_6
922 MX35_PAD_FEC_RDATA1__GPIO3_18
923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0
924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1
925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3
926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS
927 MX35_PAD_FEC_TDATA1__KPP_COL_7
928 MX35_PAD_FEC_TDATA1__GPIO3_19
929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1
930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2
931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4
932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD
933 MX35_PAD_FEC_RDATA2__KPP_ROW_4
934 MX35_PAD_FEC_RDATA2__GPIO3_20
935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2
936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5
937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD
938 MX35_PAD_FEC_TDATA2__KPP_ROW_5
939 MX35_PAD_FEC_TDATA2__GPIO3_21
940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3
941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6
942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC
943 MX35_PAD_FEC_RDATA3__KPP_ROW_6
944 MX35_PAD_FEC_RDATA3__GPIO3_22
945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3
946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7
947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS
948 MX35_PAD_FEC_TDATA3__KPP_ROW_7
949 MX35_PAD_FEC_TDATA3__GPIO3_23
950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK
951 MX35_PAD_TEST_MODE__TCU_TEST_MODE
Refer to imx35-pinfunc.h in device tree source folder for all available
imx35 PIN_FUNC_ID.
......@@ -28,760 +28,5 @@ PAD_CTL_DSE_MAX (3 << 1)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
See below for available PIN_FUNC_ID for imx51:
MX51_PAD_EIM_D16__AUD4_RXFS 0
MX51_PAD_EIM_D16__AUD5_TXD 1
MX51_PAD_EIM_D16__EIM_D16 2
MX51_PAD_EIM_D16__GPIO2_0 3
MX51_PAD_EIM_D16__I2C1_SDA 4
MX51_PAD_EIM_D16__UART2_CTS 5
MX51_PAD_EIM_D16__USBH2_DATA0 6
MX51_PAD_EIM_D17__AUD5_RXD 7
MX51_PAD_EIM_D17__EIM_D17 8
MX51_PAD_EIM_D17__GPIO2_1 9
MX51_PAD_EIM_D17__UART2_RXD 10
MX51_PAD_EIM_D17__UART3_CTS 11
MX51_PAD_EIM_D17__USBH2_DATA1 12
MX51_PAD_EIM_D18__AUD5_TXC 13
MX51_PAD_EIM_D18__EIM_D18 14
MX51_PAD_EIM_D18__GPIO2_2 15
MX51_PAD_EIM_D18__UART2_TXD 16
MX51_PAD_EIM_D18__UART3_RTS 17
MX51_PAD_EIM_D18__USBH2_DATA2 18
MX51_PAD_EIM_D19__AUD4_RXC 19
MX51_PAD_EIM_D19__AUD5_TXFS 20
MX51_PAD_EIM_D19__EIM_D19 21
MX51_PAD_EIM_D19__GPIO2_3 22
MX51_PAD_EIM_D19__I2C1_SCL 23
MX51_PAD_EIM_D19__UART2_RTS 24
MX51_PAD_EIM_D19__USBH2_DATA3 25
MX51_PAD_EIM_D20__AUD4_TXD 26
MX51_PAD_EIM_D20__EIM_D20 27
MX51_PAD_EIM_D20__GPIO2_4 28
MX51_PAD_EIM_D20__SRTC_ALARM_DEB 29
MX51_PAD_EIM_D20__USBH2_DATA4 30
MX51_PAD_EIM_D21__AUD4_RXD 31
MX51_PAD_EIM_D21__EIM_D21 32
MX51_PAD_EIM_D21__GPIO2_5 33
MX51_PAD_EIM_D21__SRTC_ALARM_DEB 34
MX51_PAD_EIM_D21__USBH2_DATA5 35
MX51_PAD_EIM_D22__AUD4_TXC 36
MX51_PAD_EIM_D22__EIM_D22 37
MX51_PAD_EIM_D22__GPIO2_6 38
MX51_PAD_EIM_D22__USBH2_DATA6 39
MX51_PAD_EIM_D23__AUD4_TXFS 40
MX51_PAD_EIM_D23__EIM_D23 41
MX51_PAD_EIM_D23__GPIO2_7 42
MX51_PAD_EIM_D23__SPDIF_OUT1 43
MX51_PAD_EIM_D23__USBH2_DATA7 44
MX51_PAD_EIM_D24__AUD6_RXFS 45
MX51_PAD_EIM_D24__EIM_D24 46
MX51_PAD_EIM_D24__GPIO2_8 47
MX51_PAD_EIM_D24__I2C2_SDA 48
MX51_PAD_EIM_D24__UART3_CTS 49
MX51_PAD_EIM_D24__USBOTG_DATA0 50
MX51_PAD_EIM_D25__EIM_D25 51
MX51_PAD_EIM_D25__KEY_COL6 52
MX51_PAD_EIM_D25__UART2_CTS 53
MX51_PAD_EIM_D25__UART3_RXD 54
MX51_PAD_EIM_D25__USBOTG_DATA1 55
MX51_PAD_EIM_D26__EIM_D26 56
MX51_PAD_EIM_D26__KEY_COL7 57
MX51_PAD_EIM_D26__UART2_RTS 58
MX51_PAD_EIM_D26__UART3_TXD 59
MX51_PAD_EIM_D26__USBOTG_DATA2 60
MX51_PAD_EIM_D27__AUD6_RXC 61
MX51_PAD_EIM_D27__EIM_D27 62
MX51_PAD_EIM_D27__GPIO2_9 63
MX51_PAD_EIM_D27__I2C2_SCL 64
MX51_PAD_EIM_D27__UART3_RTS 65
MX51_PAD_EIM_D27__USBOTG_DATA3 66
MX51_PAD_EIM_D28__AUD6_TXD 67
MX51_PAD_EIM_D28__EIM_D28 68
MX51_PAD_EIM_D28__KEY_ROW4 69
MX51_PAD_EIM_D28__USBOTG_DATA4 70
MX51_PAD_EIM_D29__AUD6_RXD 71
MX51_PAD_EIM_D29__EIM_D29 72
MX51_PAD_EIM_D29__KEY_ROW5 73
MX51_PAD_EIM_D29__USBOTG_DATA5 74
MX51_PAD_EIM_D30__AUD6_TXC 75
MX51_PAD_EIM_D30__EIM_D30 76
MX51_PAD_EIM_D30__KEY_ROW6 77
MX51_PAD_EIM_D30__USBOTG_DATA6 78
MX51_PAD_EIM_D31__AUD6_TXFS 79
MX51_PAD_EIM_D31__EIM_D31 80
MX51_PAD_EIM_D31__KEY_ROW7 81
MX51_PAD_EIM_D31__USBOTG_DATA7 82
MX51_PAD_EIM_A16__EIM_A16 83
MX51_PAD_EIM_A16__GPIO2_10 84
MX51_PAD_EIM_A16__OSC_FREQ_SEL0 85
MX51_PAD_EIM_A17__EIM_A17 86
MX51_PAD_EIM_A17__GPIO2_11 87
MX51_PAD_EIM_A17__OSC_FREQ_SEL1 88
MX51_PAD_EIM_A18__BOOT_LPB0 89
MX51_PAD_EIM_A18__EIM_A18 90
MX51_PAD_EIM_A18__GPIO2_12 91
MX51_PAD_EIM_A19__BOOT_LPB1 92
MX51_PAD_EIM_A19__EIM_A19 93
MX51_PAD_EIM_A19__GPIO2_13 94
MX51_PAD_EIM_A20__BOOT_UART_SRC0 95
MX51_PAD_EIM_A20__EIM_A20 96
MX51_PAD_EIM_A20__GPIO2_14 97
MX51_PAD_EIM_A21__BOOT_UART_SRC1 98
MX51_PAD_EIM_A21__EIM_A21 99
MX51_PAD_EIM_A21__GPIO2_15 100
MX51_PAD_EIM_A22__EIM_A22 101
MX51_PAD_EIM_A22__GPIO2_16 102
MX51_PAD_EIM_A23__BOOT_HPN_EN 103
MX51_PAD_EIM_A23__EIM_A23 104
MX51_PAD_EIM_A23__GPIO2_17 105
MX51_PAD_EIM_A24__EIM_A24 106
MX51_PAD_EIM_A24__GPIO2_18 107
MX51_PAD_EIM_A24__USBH2_CLK 108
MX51_PAD_EIM_A25__DISP1_PIN4 109
MX51_PAD_EIM_A25__EIM_A25 110
MX51_PAD_EIM_A25__GPIO2_19 111
MX51_PAD_EIM_A25__USBH2_DIR 112
MX51_PAD_EIM_A26__CSI1_DATA_EN 113
MX51_PAD_EIM_A26__DISP2_EXT_CLK 114
MX51_PAD_EIM_A26__EIM_A26 115
MX51_PAD_EIM_A26__GPIO2_20 116
MX51_PAD_EIM_A26__USBH2_STP 117
MX51_PAD_EIM_A27__CSI2_DATA_EN 118
MX51_PAD_EIM_A27__DISP1_PIN1 119
MX51_PAD_EIM_A27__EIM_A27 120
MX51_PAD_EIM_A27__GPIO2_21 121
MX51_PAD_EIM_A27__USBH2_NXT 122
MX51_PAD_EIM_EB0__EIM_EB0 123
MX51_PAD_EIM_EB1__EIM_EB1 124
MX51_PAD_EIM_EB2__AUD5_RXFS 125
MX51_PAD_EIM_EB2__CSI1_D2 126
MX51_PAD_EIM_EB2__EIM_EB2 127
MX51_PAD_EIM_EB2__FEC_MDIO 128
MX51_PAD_EIM_EB2__GPIO2_22 129
MX51_PAD_EIM_EB2__GPT_CMPOUT1 130
MX51_PAD_EIM_EB3__AUD5_RXC 131
MX51_PAD_EIM_EB3__CSI1_D3 132
MX51_PAD_EIM_EB3__EIM_EB3 133
MX51_PAD_EIM_EB3__FEC_RDATA1 134
MX51_PAD_EIM_EB3__GPIO2_23 135
MX51_PAD_EIM_EB3__GPT_CMPOUT2 136
MX51_PAD_EIM_OE__EIM_OE 137
MX51_PAD_EIM_OE__GPIO2_24 138
MX51_PAD_EIM_CS0__EIM_CS0 139
MX51_PAD_EIM_CS0__GPIO2_25 140
MX51_PAD_EIM_CS1__EIM_CS1 141
MX51_PAD_EIM_CS1__GPIO2_26 142
MX51_PAD_EIM_CS2__AUD5_TXD 143
MX51_PAD_EIM_CS2__CSI1_D4 144
MX51_PAD_EIM_CS2__EIM_CS2 145
MX51_PAD_EIM_CS2__FEC_RDATA2 146
MX51_PAD_EIM_CS2__GPIO2_27 147
MX51_PAD_EIM_CS2__USBOTG_STP 148
MX51_PAD_EIM_CS3__AUD5_RXD 149
MX51_PAD_EIM_CS3__CSI1_D5 150
MX51_PAD_EIM_CS3__EIM_CS3 151
MX51_PAD_EIM_CS3__FEC_RDATA3 152
MX51_PAD_EIM_CS3__GPIO2_28 153
MX51_PAD_EIM_CS3__USBOTG_NXT 154
MX51_PAD_EIM_CS4__AUD5_TXC 155
MX51_PAD_EIM_CS4__CSI1_D6 156
MX51_PAD_EIM_CS4__EIM_CS4 157
MX51_PAD_EIM_CS4__FEC_RX_ER 158
MX51_PAD_EIM_CS4__GPIO2_29 159
MX51_PAD_EIM_CS4__USBOTG_CLK 160
MX51_PAD_EIM_CS5__AUD5_TXFS 161
MX51_PAD_EIM_CS5__CSI1_D7 162
MX51_PAD_EIM_CS5__DISP1_EXT_CLK 163
MX51_PAD_EIM_CS5__EIM_CS5 164
MX51_PAD_EIM_CS5__FEC_CRS 165
MX51_PAD_EIM_CS5__GPIO2_30 166
MX51_PAD_EIM_CS5__USBOTG_DIR 167
MX51_PAD_EIM_DTACK__EIM_DTACK 168
MX51_PAD_EIM_DTACK__GPIO2_31 169
MX51_PAD_EIM_LBA__EIM_LBA 170
MX51_PAD_EIM_LBA__GPIO3_1 171
MX51_PAD_EIM_CRE__EIM_CRE 172
MX51_PAD_EIM_CRE__GPIO3_2 173
MX51_PAD_DRAM_CS1__DRAM_CS1 174
MX51_PAD_NANDF_WE_B__GPIO3_3 175
MX51_PAD_NANDF_WE_B__NANDF_WE_B 176
MX51_PAD_NANDF_WE_B__PATA_DIOW 177
MX51_PAD_NANDF_WE_B__SD3_DATA0 178
MX51_PAD_NANDF_RE_B__GPIO3_4 179
MX51_PAD_NANDF_RE_B__NANDF_RE_B 180
MX51_PAD_NANDF_RE_B__PATA_DIOR 181
MX51_PAD_NANDF_RE_B__SD3_DATA1 182
MX51_PAD_NANDF_ALE__GPIO3_5 183
MX51_PAD_NANDF_ALE__NANDF_ALE 184
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 185
MX51_PAD_NANDF_CLE__GPIO3_6 186
MX51_PAD_NANDF_CLE__NANDF_CLE 187
MX51_PAD_NANDF_CLE__PATA_RESET_B 188
MX51_PAD_NANDF_WP_B__GPIO3_7 189
MX51_PAD_NANDF_WP_B__NANDF_WP_B 190
MX51_PAD_NANDF_WP_B__PATA_DMACK 191
MX51_PAD_NANDF_WP_B__SD3_DATA2 192
MX51_PAD_NANDF_RB0__ECSPI2_SS1 193
MX51_PAD_NANDF_RB0__GPIO3_8 194
MX51_PAD_NANDF_RB0__NANDF_RB0 195
MX51_PAD_NANDF_RB0__PATA_DMARQ 196
MX51_PAD_NANDF_RB0__SD3_DATA3 197
MX51_PAD_NANDF_RB1__CSPI_MOSI 198
MX51_PAD_NANDF_RB1__ECSPI2_RDY 199
MX51_PAD_NANDF_RB1__GPIO3_9 200
MX51_PAD_NANDF_RB1__NANDF_RB1 201
MX51_PAD_NANDF_RB1__PATA_IORDY 202
MX51_PAD_NANDF_RB1__SD4_CMD 203
MX51_PAD_NANDF_RB2__DISP2_WAIT 204
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 205
MX51_PAD_NANDF_RB2__FEC_COL 206
MX51_PAD_NANDF_RB2__GPIO3_10 207
MX51_PAD_NANDF_RB2__NANDF_RB2 208
MX51_PAD_NANDF_RB2__USBH3_H3_DP 209
MX51_PAD_NANDF_RB2__USBH3_NXT 210
MX51_PAD_NANDF_RB3__DISP1_WAIT 211
MX51_PAD_NANDF_RB3__ECSPI2_MISO 212
MX51_PAD_NANDF_RB3__FEC_RX_CLK 213
MX51_PAD_NANDF_RB3__GPIO3_11 214
MX51_PAD_NANDF_RB3__NANDF_RB3 215
MX51_PAD_NANDF_RB3__USBH3_CLK 216
MX51_PAD_NANDF_RB3__USBH3_H3_DM 217
MX51_PAD_GPIO_NAND__GPIO_NAND 218
MX51_PAD_GPIO_NAND__PATA_INTRQ 219
MX51_PAD_NANDF_CS0__GPIO3_16 220
MX51_PAD_NANDF_CS0__NANDF_CS0 221
MX51_PAD_NANDF_CS1__GPIO3_17 222
MX51_PAD_NANDF_CS1__NANDF_CS1 223
MX51_PAD_NANDF_CS2__CSPI_SCLK 224
MX51_PAD_NANDF_CS2__FEC_TX_ER 225
MX51_PAD_NANDF_CS2__GPIO3_18 226
MX51_PAD_NANDF_CS2__NANDF_CS2 227
MX51_PAD_NANDF_CS2__PATA_CS_0 228
MX51_PAD_NANDF_CS2__SD4_CLK 229
MX51_PAD_NANDF_CS2__USBH3_H1_DP 230
MX51_PAD_NANDF_CS3__FEC_MDC 231
MX51_PAD_NANDF_CS3__GPIO3_19 232
MX51_PAD_NANDF_CS3__NANDF_CS3 233
MX51_PAD_NANDF_CS3__PATA_CS_1 234
MX51_PAD_NANDF_CS3__SD4_DAT0 235
MX51_PAD_NANDF_CS3__USBH3_H1_DM 236
MX51_PAD_NANDF_CS4__FEC_TDATA1 237
MX51_PAD_NANDF_CS4__GPIO3_20 238
MX51_PAD_NANDF_CS4__NANDF_CS4 239
MX51_PAD_NANDF_CS4__PATA_DA_0 240
MX51_PAD_NANDF_CS4__SD4_DAT1 241
MX51_PAD_NANDF_CS4__USBH3_STP 242
MX51_PAD_NANDF_CS5__FEC_TDATA2 243
MX51_PAD_NANDF_CS5__GPIO3_21 244
MX51_PAD_NANDF_CS5__NANDF_CS5 245
MX51_PAD_NANDF_CS5__PATA_DA_1 246
MX51_PAD_NANDF_CS5__SD4_DAT2 247
MX51_PAD_NANDF_CS5__USBH3_DIR 248
MX51_PAD_NANDF_CS6__CSPI_SS3 249
MX51_PAD_NANDF_CS6__FEC_TDATA3 250
MX51_PAD_NANDF_CS6__GPIO3_22 251
MX51_PAD_NANDF_CS6__NANDF_CS6 252
MX51_PAD_NANDF_CS6__PATA_DA_2 253
MX51_PAD_NANDF_CS6__SD4_DAT3 254
MX51_PAD_NANDF_CS7__FEC_TX_EN 255
MX51_PAD_NANDF_CS7__GPIO3_23 256
MX51_PAD_NANDF_CS7__NANDF_CS7 257
MX51_PAD_NANDF_CS7__SD3_CLK 258
MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 259
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 260
MX51_PAD_NANDF_RDY_INT__GPIO3_24 261
MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 262
MX51_PAD_NANDF_RDY_INT__SD3_CMD 263
MX51_PAD_NANDF_D15__ECSPI2_MOSI 264
MX51_PAD_NANDF_D15__GPIO3_25 265
MX51_PAD_NANDF_D15__NANDF_D15 266
MX51_PAD_NANDF_D15__PATA_DATA15 267
MX51_PAD_NANDF_D15__SD3_DAT7 268
MX51_PAD_NANDF_D14__ECSPI2_SS3 269
MX51_PAD_NANDF_D14__GPIO3_26 270
MX51_PAD_NANDF_D14__NANDF_D14 271
MX51_PAD_NANDF_D14__PATA_DATA14 272
MX51_PAD_NANDF_D14__SD3_DAT6 273
MX51_PAD_NANDF_D13__ECSPI2_SS2 274
MX51_PAD_NANDF_D13__GPIO3_27 275
MX51_PAD_NANDF_D13__NANDF_D13 276
MX51_PAD_NANDF_D13__PATA_DATA13 277
MX51_PAD_NANDF_D13__SD3_DAT5 278
MX51_PAD_NANDF_D12__ECSPI2_SS1 279
MX51_PAD_NANDF_D12__GPIO3_28 280
MX51_PAD_NANDF_D12__NANDF_D12 281
MX51_PAD_NANDF_D12__PATA_DATA12 282
MX51_PAD_NANDF_D12__SD3_DAT4 283
MX51_PAD_NANDF_D11__FEC_RX_DV 284
MX51_PAD_NANDF_D11__GPIO3_29 285
MX51_PAD_NANDF_D11__NANDF_D11 286
MX51_PAD_NANDF_D11__PATA_DATA11 287
MX51_PAD_NANDF_D11__SD3_DATA3 288
MX51_PAD_NANDF_D10__GPIO3_30 289
MX51_PAD_NANDF_D10__NANDF_D10 290
MX51_PAD_NANDF_D10__PATA_DATA10 291
MX51_PAD_NANDF_D10__SD3_DATA2 292
MX51_PAD_NANDF_D9__FEC_RDATA0 293
MX51_PAD_NANDF_D9__GPIO3_31 294
MX51_PAD_NANDF_D9__NANDF_D9 295
MX51_PAD_NANDF_D9__PATA_DATA9 296
MX51_PAD_NANDF_D9__SD3_DATA1 297
MX51_PAD_NANDF_D8__FEC_TDATA0 298
MX51_PAD_NANDF_D8__GPIO4_0 299
MX51_PAD_NANDF_D8__NANDF_D8 300
MX51_PAD_NANDF_D8__PATA_DATA8 301
MX51_PAD_NANDF_D8__SD3_DATA0 302
MX51_PAD_NANDF_D7__GPIO4_1 303
MX51_PAD_NANDF_D7__NANDF_D7 304
MX51_PAD_NANDF_D7__PATA_DATA7 305
MX51_PAD_NANDF_D7__USBH3_DATA0 306
MX51_PAD_NANDF_D6__GPIO4_2 307
MX51_PAD_NANDF_D6__NANDF_D6 308
MX51_PAD_NANDF_D6__PATA_DATA6 309
MX51_PAD_NANDF_D6__SD4_LCTL 310
MX51_PAD_NANDF_D6__USBH3_DATA1 311
MX51_PAD_NANDF_D5__GPIO4_3 312
MX51_PAD_NANDF_D5__NANDF_D5 313
MX51_PAD_NANDF_D5__PATA_DATA5 314
MX51_PAD_NANDF_D5__SD4_WP 315
MX51_PAD_NANDF_D5__USBH3_DATA2 316
MX51_PAD_NANDF_D4__GPIO4_4 317
MX51_PAD_NANDF_D4__NANDF_D4 318
MX51_PAD_NANDF_D4__PATA_DATA4 319
MX51_PAD_NANDF_D4__SD4_CD 320
MX51_PAD_NANDF_D4__USBH3_DATA3 321
MX51_PAD_NANDF_D3__GPIO4_5 322
MX51_PAD_NANDF_D3__NANDF_D3 323
MX51_PAD_NANDF_D3__PATA_DATA3 324
MX51_PAD_NANDF_D3__SD4_DAT4 325
MX51_PAD_NANDF_D3__USBH3_DATA4 326
MX51_PAD_NANDF_D2__GPIO4_6 327
MX51_PAD_NANDF_D2__NANDF_D2 328
MX51_PAD_NANDF_D2__PATA_DATA2 329
MX51_PAD_NANDF_D2__SD4_DAT5 330
MX51_PAD_NANDF_D2__USBH3_DATA5 331
MX51_PAD_NANDF_D1__GPIO4_7 332
MX51_PAD_NANDF_D1__NANDF_D1 333
MX51_PAD_NANDF_D1__PATA_DATA1 334
MX51_PAD_NANDF_D1__SD4_DAT6 335
MX51_PAD_NANDF_D1__USBH3_DATA6 336
MX51_PAD_NANDF_D0__GPIO4_8 337
MX51_PAD_NANDF_D0__NANDF_D0 338
MX51_PAD_NANDF_D0__PATA_DATA0 339
MX51_PAD_NANDF_D0__SD4_DAT7 340
MX51_PAD_NANDF_D0__USBH3_DATA7 341
MX51_PAD_CSI1_D8__CSI1_D8 342
MX51_PAD_CSI1_D8__GPIO3_12 343
MX51_PAD_CSI1_D9__CSI1_D9 344
MX51_PAD_CSI1_D9__GPIO3_13 345
MX51_PAD_CSI1_D10__CSI1_D10 346
MX51_PAD_CSI1_D11__CSI1_D11 347
MX51_PAD_CSI1_D12__CSI1_D12 348
MX51_PAD_CSI1_D13__CSI1_D13 349
MX51_PAD_CSI1_D14__CSI1_D14 350
MX51_PAD_CSI1_D15__CSI1_D15 351
MX51_PAD_CSI1_D16__CSI1_D16 352
MX51_PAD_CSI1_D17__CSI1_D17 353
MX51_PAD_CSI1_D18__CSI1_D18 354
MX51_PAD_CSI1_D19__CSI1_D19 355
MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 356
MX51_PAD_CSI1_VSYNC__GPIO3_14 357
MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 358
MX51_PAD_CSI1_HSYNC__GPIO3_15 359
MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 360
MX51_PAD_CSI1_MCLK__CSI1_MCLK 361
MX51_PAD_CSI2_D12__CSI2_D12 362
MX51_PAD_CSI2_D12__GPIO4_9 363
MX51_PAD_CSI2_D13__CSI2_D13 364
MX51_PAD_CSI2_D13__GPIO4_10 365
MX51_PAD_CSI2_D14__CSI2_D14 366
MX51_PAD_CSI2_D15__CSI2_D15 367
MX51_PAD_CSI2_D16__CSI2_D16 368
MX51_PAD_CSI2_D17__CSI2_D17 369
MX51_PAD_CSI2_D18__CSI2_D18 370
MX51_PAD_CSI2_D18__GPIO4_11 371
MX51_PAD_CSI2_D19__CSI2_D19 372
MX51_PAD_CSI2_D19__GPIO4_12 373
MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 374
MX51_PAD_CSI2_VSYNC__GPIO4_13 375
MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 376
MX51_PAD_CSI2_HSYNC__GPIO4_14 377
MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 378
MX51_PAD_CSI2_PIXCLK__GPIO4_15 379
MX51_PAD_I2C1_CLK__GPIO4_16 380
MX51_PAD_I2C1_CLK__I2C1_CLK 381
MX51_PAD_I2C1_DAT__GPIO4_17 382
MX51_PAD_I2C1_DAT__I2C1_DAT 383
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 384
MX51_PAD_AUD3_BB_TXD__GPIO4_18 385
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 386
MX51_PAD_AUD3_BB_RXD__GPIO4_19 387
MX51_PAD_AUD3_BB_RXD__UART3_RXD 388
MX51_PAD_AUD3_BB_CK__AUD3_TXC 389
MX51_PAD_AUD3_BB_CK__GPIO4_20 390
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 391
MX51_PAD_AUD3_BB_FS__GPIO4_21 392
MX51_PAD_AUD3_BB_FS__UART3_TXD 393
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 394
MX51_PAD_CSPI1_MOSI__GPIO4_22 395
MX51_PAD_CSPI1_MOSI__I2C1_SDA 396
MX51_PAD_CSPI1_MISO__AUD4_RXD 397
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 398
MX51_PAD_CSPI1_MISO__GPIO4_23 399
MX51_PAD_CSPI1_SS0__AUD4_TXC 400
MX51_PAD_CSPI1_SS0__ECSPI1_SS0 401
MX51_PAD_CSPI1_SS0__GPIO4_24 402
MX51_PAD_CSPI1_SS1__AUD4_TXD 403
MX51_PAD_CSPI1_SS1__ECSPI1_SS1 404
MX51_PAD_CSPI1_SS1__GPIO4_25 405
MX51_PAD_CSPI1_RDY__AUD4_TXFS 406
MX51_PAD_CSPI1_RDY__ECSPI1_RDY 407
MX51_PAD_CSPI1_RDY__GPIO4_26 408
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 409
MX51_PAD_CSPI1_SCLK__GPIO4_27 410
MX51_PAD_CSPI1_SCLK__I2C1_SCL 411
MX51_PAD_UART1_RXD__GPIO4_28 412
MX51_PAD_UART1_RXD__UART1_RXD 413
MX51_PAD_UART1_TXD__GPIO4_29 414
MX51_PAD_UART1_TXD__PWM2_PWMO 415
MX51_PAD_UART1_TXD__UART1_TXD 416
MX51_PAD_UART1_RTS__GPIO4_30 417
MX51_PAD_UART1_RTS__UART1_RTS 418
MX51_PAD_UART1_CTS__GPIO4_31 419
MX51_PAD_UART1_CTS__UART1_CTS 420
MX51_PAD_UART2_RXD__FIRI_TXD 421
MX51_PAD_UART2_RXD__GPIO1_20 422
MX51_PAD_UART2_RXD__UART2_RXD 423
MX51_PAD_UART2_TXD__FIRI_RXD 424
MX51_PAD_UART2_TXD__GPIO1_21 425
MX51_PAD_UART2_TXD__UART2_TXD 426
MX51_PAD_UART3_RXD__CSI1_D0 427
MX51_PAD_UART3_RXD__GPIO1_22 428
MX51_PAD_UART3_RXD__UART1_DTR 429
MX51_PAD_UART3_RXD__UART3_RXD 430
MX51_PAD_UART3_TXD__CSI1_D1 431
MX51_PAD_UART3_TXD__GPIO1_23 432
MX51_PAD_UART3_TXD__UART1_DSR 433
MX51_PAD_UART3_TXD__UART3_TXD 434
MX51_PAD_OWIRE_LINE__GPIO1_24 435
MX51_PAD_OWIRE_LINE__OWIRE_LINE 436
MX51_PAD_OWIRE_LINE__SPDIF_OUT 437
MX51_PAD_KEY_ROW0__KEY_ROW0 438
MX51_PAD_KEY_ROW1__KEY_ROW1 439
MX51_PAD_KEY_ROW2__KEY_ROW2 440
MX51_PAD_KEY_ROW3__KEY_ROW3 441
MX51_PAD_KEY_COL0__KEY_COL0 442
MX51_PAD_KEY_COL0__PLL1_BYP 443
MX51_PAD_KEY_COL1__KEY_COL1 444
MX51_PAD_KEY_COL1__PLL2_BYP 445
MX51_PAD_KEY_COL2__KEY_COL2 446
MX51_PAD_KEY_COL2__PLL3_BYP 447
MX51_PAD_KEY_COL3__KEY_COL3 448
MX51_PAD_KEY_COL4__I2C2_SCL 449
MX51_PAD_KEY_COL4__KEY_COL4 450
MX51_PAD_KEY_COL4__SPDIF_OUT1 451
MX51_PAD_KEY_COL4__UART1_RI 452
MX51_PAD_KEY_COL4__UART3_RTS 453
MX51_PAD_KEY_COL5__I2C2_SDA 454
MX51_PAD_KEY_COL5__KEY_COL5 455
MX51_PAD_KEY_COL5__UART1_DCD 456
MX51_PAD_KEY_COL5__UART3_CTS 457
MX51_PAD_USBH1_CLK__CSPI_SCLK 458
MX51_PAD_USBH1_CLK__GPIO1_25 459
MX51_PAD_USBH1_CLK__I2C2_SCL 460
MX51_PAD_USBH1_CLK__USBH1_CLK 461
MX51_PAD_USBH1_DIR__CSPI_MOSI 462
MX51_PAD_USBH1_DIR__GPIO1_26 463
MX51_PAD_USBH1_DIR__I2C2_SDA 464
MX51_PAD_USBH1_DIR__USBH1_DIR 465
MX51_PAD_USBH1_STP__CSPI_RDY 466
MX51_PAD_USBH1_STP__GPIO1_27 467
MX51_PAD_USBH1_STP__UART3_RXD 468
MX51_PAD_USBH1_STP__USBH1_STP 469
MX51_PAD_USBH1_NXT__CSPI_MISO 470
MX51_PAD_USBH1_NXT__GPIO1_28 471
MX51_PAD_USBH1_NXT__UART3_TXD 472
MX51_PAD_USBH1_NXT__USBH1_NXT 473
MX51_PAD_USBH1_DATA0__GPIO1_11 474
MX51_PAD_USBH1_DATA0__UART2_CTS 475
MX51_PAD_USBH1_DATA0__USBH1_DATA0 476
MX51_PAD_USBH1_DATA1__GPIO1_12 477
MX51_PAD_USBH1_DATA1__UART2_RXD 478
MX51_PAD_USBH1_DATA1__USBH1_DATA1 479
MX51_PAD_USBH1_DATA2__GPIO1_13 480
MX51_PAD_USBH1_DATA2__UART2_TXD 481
MX51_PAD_USBH1_DATA2__USBH1_DATA2 482
MX51_PAD_USBH1_DATA3__GPIO1_14 483
MX51_PAD_USBH1_DATA3__UART2_RTS 484
MX51_PAD_USBH1_DATA3__USBH1_DATA3 485
MX51_PAD_USBH1_DATA4__CSPI_SS0 486
MX51_PAD_USBH1_DATA4__GPIO1_15 487
MX51_PAD_USBH1_DATA4__USBH1_DATA4 488
MX51_PAD_USBH1_DATA5__CSPI_SS1 489
MX51_PAD_USBH1_DATA5__GPIO1_16 490
MX51_PAD_USBH1_DATA5__USBH1_DATA5 491
MX51_PAD_USBH1_DATA6__CSPI_SS3 492
MX51_PAD_USBH1_DATA6__GPIO1_17 493
MX51_PAD_USBH1_DATA6__USBH1_DATA6 494
MX51_PAD_USBH1_DATA7__ECSPI1_SS3 495
MX51_PAD_USBH1_DATA7__ECSPI2_SS3 496
MX51_PAD_USBH1_DATA7__GPIO1_18 497
MX51_PAD_USBH1_DATA7__USBH1_DATA7 498
MX51_PAD_DI1_PIN11__DI1_PIN11 499
MX51_PAD_DI1_PIN11__ECSPI1_SS2 500
MX51_PAD_DI1_PIN11__GPIO3_0 501
MX51_PAD_DI1_PIN12__DI1_PIN12 502
MX51_PAD_DI1_PIN12__GPIO3_1 503
MX51_PAD_DI1_PIN13__DI1_PIN13 504
MX51_PAD_DI1_PIN13__GPIO3_2 505
MX51_PAD_DI1_D0_CS__DI1_D0_CS 506
MX51_PAD_DI1_D0_CS__GPIO3_3 507
MX51_PAD_DI1_D1_CS__DI1_D1_CS 508
MX51_PAD_DI1_D1_CS__DISP1_PIN14 509
MX51_PAD_DI1_D1_CS__DISP1_PIN5 510
MX51_PAD_DI1_D1_CS__GPIO3_4 511
MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 512
MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 513
MX51_PAD_DISPB2_SER_DIN__GPIO3_5 514
MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 515
MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 516
MX51_PAD_DISPB2_SER_DIO__GPIO3_6 517
MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 518
MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 519
MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 520
MX51_PAD_DISPB2_SER_CLK__GPIO3_7 521
MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 522
MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 523
MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 524
MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 525
MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 526
MX51_PAD_DISPB2_SER_RS__GPIO3_8 527
MX51_PAD_DISP1_DAT0__DISP1_DAT0 528
MX51_PAD_DISP1_DAT1__DISP1_DAT1 529
MX51_PAD_DISP1_DAT2__DISP1_DAT2 530
MX51_PAD_DISP1_DAT3__DISP1_DAT3 531
MX51_PAD_DISP1_DAT4__DISP1_DAT4 532
MX51_PAD_DISP1_DAT5__DISP1_DAT5 533
MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 534
MX51_PAD_DISP1_DAT6__DISP1_DAT6 535
MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 536
MX51_PAD_DISP1_DAT7__DISP1_DAT7 537
MX51_PAD_DISP1_DAT8__BOOT_SRC0 538
MX51_PAD_DISP1_DAT8__DISP1_DAT8 539
MX51_PAD_DISP1_DAT9__BOOT_SRC1 540
MX51_PAD_DISP1_DAT9__DISP1_DAT9 541
MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 542
MX51_PAD_DISP1_DAT10__DISP1_DAT10 543
MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 544
MX51_PAD_DISP1_DAT11__DISP1_DAT11 545
MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 546
MX51_PAD_DISP1_DAT12__DISP1_DAT12 547
MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 548
MX51_PAD_DISP1_DAT13__DISP1_DAT13 549
MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 550
MX51_PAD_DISP1_DAT14__DISP1_DAT14 551
MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 552
MX51_PAD_DISP1_DAT15__DISP1_DAT15 553
MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 554
MX51_PAD_DISP1_DAT16__DISP1_DAT16 555
MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 556
MX51_PAD_DISP1_DAT17__DISP1_DAT17 557
MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 558
MX51_PAD_DISP1_DAT18__DISP1_DAT18 559
MX51_PAD_DISP1_DAT18__DISP2_PIN11 560
MX51_PAD_DISP1_DAT18__DISP2_PIN5 561
MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 562
MX51_PAD_DISP1_DAT19__DISP1_DAT19 563
MX51_PAD_DISP1_DAT19__DISP2_PIN12 564
MX51_PAD_DISP1_DAT19__DISP2_PIN6 565
MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 566
MX51_PAD_DISP1_DAT20__DISP1_DAT20 567
MX51_PAD_DISP1_DAT20__DISP2_PIN13 568
MX51_PAD_DISP1_DAT20__DISP2_PIN7 569
MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 570
MX51_PAD_DISP1_DAT21__DISP1_DAT21 571
MX51_PAD_DISP1_DAT21__DISP2_PIN14 572
MX51_PAD_DISP1_DAT21__DISP2_PIN8 573
MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 574
MX51_PAD_DISP1_DAT22__DISP1_DAT22 575
MX51_PAD_DISP1_DAT22__DISP2_D0_CS 576
MX51_PAD_DISP1_DAT22__DISP2_DAT16 577
MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 578
MX51_PAD_DISP1_DAT23__DISP1_DAT23 579
MX51_PAD_DISP1_DAT23__DISP2_D1_CS 580
MX51_PAD_DISP1_DAT23__DISP2_DAT17 581
MX51_PAD_DISP1_DAT23__DISP2_SER_CS 582
MX51_PAD_DI1_PIN3__DI1_PIN3 583
MX51_PAD_DI1_PIN2__DI1_PIN2 584
MX51_PAD_DI_GP2__DISP1_SER_CLK 585
MX51_PAD_DI_GP2__DISP2_WAIT 586
MX51_PAD_DI_GP3__CSI1_DATA_EN 587
MX51_PAD_DI_GP3__DISP1_SER_DIO 588
MX51_PAD_DI_GP3__FEC_TX_ER 589
MX51_PAD_DI2_PIN4__CSI2_DATA_EN 590
MX51_PAD_DI2_PIN4__DI2_PIN4 591
MX51_PAD_DI2_PIN4__FEC_CRS 592
MX51_PAD_DI2_PIN2__DI2_PIN2 593
MX51_PAD_DI2_PIN2__FEC_MDC 594
MX51_PAD_DI2_PIN3__DI2_PIN3 595
MX51_PAD_DI2_PIN3__FEC_MDIO 596
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 597
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 598
MX51_PAD_DI_GP4__DI2_PIN15 599
MX51_PAD_DI_GP4__DISP1_SER_DIN 600
MX51_PAD_DI_GP4__DISP2_PIN1 601
MX51_PAD_DI_GP4__FEC_RDATA2 602
MX51_PAD_DISP2_DAT0__DISP2_DAT0 603
MX51_PAD_DISP2_DAT0__FEC_RDATA3 604
MX51_PAD_DISP2_DAT0__KEY_COL6 605
MX51_PAD_DISP2_DAT0__UART3_RXD 606
MX51_PAD_DISP2_DAT0__USBH3_CLK 607
MX51_PAD_DISP2_DAT1__DISP2_DAT1 608
MX51_PAD_DISP2_DAT1__FEC_RX_ER 609
MX51_PAD_DISP2_DAT1__KEY_COL7 610
MX51_PAD_DISP2_DAT1__UART3_TXD 611
MX51_PAD_DISP2_DAT1__USBH3_DIR 612
MX51_PAD_DISP2_DAT2__DISP2_DAT2 613
MX51_PAD_DISP2_DAT3__DISP2_DAT3 614
MX51_PAD_DISP2_DAT4__DISP2_DAT4 615
MX51_PAD_DISP2_DAT5__DISP2_DAT5 616
MX51_PAD_DISP2_DAT6__DISP2_DAT6 617
MX51_PAD_DISP2_DAT6__FEC_TDATA1 618
MX51_PAD_DISP2_DAT6__GPIO1_19 619
MX51_PAD_DISP2_DAT6__KEY_ROW4 620
MX51_PAD_DISP2_DAT6__USBH3_STP 621
MX51_PAD_DISP2_DAT7__DISP2_DAT7 622
MX51_PAD_DISP2_DAT7__FEC_TDATA2 623
MX51_PAD_DISP2_DAT7__GPIO1_29 624
MX51_PAD_DISP2_DAT7__KEY_ROW5 625
MX51_PAD_DISP2_DAT7__USBH3_NXT 626
MX51_PAD_DISP2_DAT8__DISP2_DAT8 627
MX51_PAD_DISP2_DAT8__FEC_TDATA3 628
MX51_PAD_DISP2_DAT8__GPIO1_30 629
MX51_PAD_DISP2_DAT8__KEY_ROW6 630
MX51_PAD_DISP2_DAT8__USBH3_DATA0 631
MX51_PAD_DISP2_DAT9__AUD6_RXC 632
MX51_PAD_DISP2_DAT9__DISP2_DAT9 633
MX51_PAD_DISP2_DAT9__FEC_TX_EN 634
MX51_PAD_DISP2_DAT9__GPIO1_31 635
MX51_PAD_DISP2_DAT9__USBH3_DATA1 636
MX51_PAD_DISP2_DAT10__DISP2_DAT10 637
MX51_PAD_DISP2_DAT10__DISP2_SER_CS 638
MX51_PAD_DISP2_DAT10__FEC_COL 639
MX51_PAD_DISP2_DAT10__KEY_ROW7 640
MX51_PAD_DISP2_DAT10__USBH3_DATA2 641
MX51_PAD_DISP2_DAT11__AUD6_TXD 642
MX51_PAD_DISP2_DAT11__DISP2_DAT11 643
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 644
MX51_PAD_DISP2_DAT11__GPIO1_10 645
MX51_PAD_DISP2_DAT11__USBH3_DATA3 646
MX51_PAD_DISP2_DAT12__AUD6_RXD 647
MX51_PAD_DISP2_DAT12__DISP2_DAT12 648
MX51_PAD_DISP2_DAT12__FEC_RX_DV 649
MX51_PAD_DISP2_DAT12__USBH3_DATA4 650
MX51_PAD_DISP2_DAT13__AUD6_TXC 651
MX51_PAD_DISP2_DAT13__DISP2_DAT13 652
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 653
MX51_PAD_DISP2_DAT13__USBH3_DATA5 654
MX51_PAD_DISP2_DAT14__AUD6_TXFS 655
MX51_PAD_DISP2_DAT14__DISP2_DAT14 656
MX51_PAD_DISP2_DAT14__FEC_RDATA0 657
MX51_PAD_DISP2_DAT14__USBH3_DATA6 658
MX51_PAD_DISP2_DAT15__AUD6_RXFS 659
MX51_PAD_DISP2_DAT15__DISP1_SER_CS 660
MX51_PAD_DISP2_DAT15__DISP2_DAT15 661
MX51_PAD_DISP2_DAT15__FEC_TDATA0 662
MX51_PAD_DISP2_DAT15__USBH3_DATA7 663
MX51_PAD_SD1_CMD__AUD5_RXFS 664
MX51_PAD_SD1_CMD__CSPI_MOSI 665
MX51_PAD_SD1_CMD__SD1_CMD 666
MX51_PAD_SD1_CLK__AUD5_RXC 667
MX51_PAD_SD1_CLK__CSPI_SCLK 668
MX51_PAD_SD1_CLK__SD1_CLK 669
MX51_PAD_SD1_DATA0__AUD5_TXD 670
MX51_PAD_SD1_DATA0__CSPI_MISO 671
MX51_PAD_SD1_DATA0__SD1_DATA0 672
MX51_PAD_EIM_DA0__EIM_DA0 673
MX51_PAD_EIM_DA1__EIM_DA1 674
MX51_PAD_EIM_DA2__EIM_DA2 675
MX51_PAD_EIM_DA3__EIM_DA3 676
MX51_PAD_SD1_DATA1__AUD5_RXD 677
MX51_PAD_SD1_DATA1__SD1_DATA1 678
MX51_PAD_EIM_DA4__EIM_DA4 679
MX51_PAD_EIM_DA5__EIM_DA5 680
MX51_PAD_EIM_DA6__EIM_DA6 681
MX51_PAD_EIM_DA7__EIM_DA7 682
MX51_PAD_SD1_DATA2__AUD5_TXC 683
MX51_PAD_SD1_DATA2__SD1_DATA2 684
MX51_PAD_EIM_DA10__EIM_DA10 685
MX51_PAD_EIM_DA11__EIM_DA11 686
MX51_PAD_EIM_DA8__EIM_DA8 687
MX51_PAD_EIM_DA9__EIM_DA9 688
MX51_PAD_SD1_DATA3__AUD5_TXFS 689
MX51_PAD_SD1_DATA3__CSPI_SS1 690
MX51_PAD_SD1_DATA3__SD1_DATA3 691
MX51_PAD_GPIO1_0__CSPI_SS2 692
MX51_PAD_GPIO1_0__GPIO1_0 693
MX51_PAD_GPIO1_0__SD1_CD 694
MX51_PAD_GPIO1_1__CSPI_MISO 695
MX51_PAD_GPIO1_1__GPIO1_1 696
MX51_PAD_GPIO1_1__SD1_WP 697
MX51_PAD_EIM_DA12__EIM_DA12 698
MX51_PAD_EIM_DA13__EIM_DA13 699
MX51_PAD_EIM_DA14__EIM_DA14 700
MX51_PAD_EIM_DA15__EIM_DA15 701
MX51_PAD_SD2_CMD__CSPI_MOSI 702
MX51_PAD_SD2_CMD__I2C1_SCL 703
MX51_PAD_SD2_CMD__SD2_CMD 704
MX51_PAD_SD2_CLK__CSPI_SCLK 705
MX51_PAD_SD2_CLK__I2C1_SDA 706
MX51_PAD_SD2_CLK__SD2_CLK 707
MX51_PAD_SD2_DATA0__CSPI_MISO 708
MX51_PAD_SD2_DATA0__SD1_DAT4 709
MX51_PAD_SD2_DATA0__SD2_DATA0 710
MX51_PAD_SD2_DATA1__SD1_DAT5 711
MX51_PAD_SD2_DATA1__SD2_DATA1 712
MX51_PAD_SD2_DATA1__USBH3_H2_DP 713
MX51_PAD_SD2_DATA2__SD1_DAT6 714
MX51_PAD_SD2_DATA2__SD2_DATA2 715
MX51_PAD_SD2_DATA2__USBH3_H2_DM 716
MX51_PAD_SD2_DATA3__CSPI_SS2 717
MX51_PAD_SD2_DATA3__SD1_DAT7 718
MX51_PAD_SD2_DATA3__SD2_DATA3 719
MX51_PAD_GPIO1_2__CCM_OUT_2 720
MX51_PAD_GPIO1_2__GPIO1_2 721
MX51_PAD_GPIO1_2__I2C2_SCL 722
MX51_PAD_GPIO1_2__PLL1_BYP 723
MX51_PAD_GPIO1_2__PWM1_PWMO 724
MX51_PAD_GPIO1_3__GPIO1_3 725
MX51_PAD_GPIO1_3__I2C2_SDA 726
MX51_PAD_GPIO1_3__PLL2_BYP 727
MX51_PAD_GPIO1_3__PWM2_PWMO 728
MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 729
MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 730
MX51_PAD_GPIO1_4__DISP2_EXT_CLK 731
MX51_PAD_GPIO1_4__EIM_RDY 732
MX51_PAD_GPIO1_4__GPIO1_4 733
MX51_PAD_GPIO1_4__WDOG1_WDOG_B 734
MX51_PAD_GPIO1_5__CSI2_MCLK 735
MX51_PAD_GPIO1_5__DISP2_PIN16 736
MX51_PAD_GPIO1_5__GPIO1_5 737
MX51_PAD_GPIO1_5__WDOG2_WDOG_B 738
MX51_PAD_GPIO1_6__DISP2_PIN17 739
MX51_PAD_GPIO1_6__GPIO1_6 740
MX51_PAD_GPIO1_6__REF_EN_B 741
MX51_PAD_GPIO1_7__CCM_OUT_0 742
MX51_PAD_GPIO1_7__GPIO1_7 743
MX51_PAD_GPIO1_7__SD2_WP 744
MX51_PAD_GPIO1_7__SPDIF_OUT1 745
MX51_PAD_GPIO1_8__CSI2_DATA_EN 746
MX51_PAD_GPIO1_8__GPIO1_8 747
MX51_PAD_GPIO1_8__SD2_CD 748
MX51_PAD_GPIO1_8__USBH3_PWR 749
MX51_PAD_GPIO1_9__CCM_OUT_1 750
MX51_PAD_GPIO1_9__DISP2_D1_CS 751
MX51_PAD_GPIO1_9__DISP2_SER_CS 752
MX51_PAD_GPIO1_9__GPIO1_9 753
MX51_PAD_GPIO1_9__SD2_LCTL 754
MX51_PAD_GPIO1_9__USBH3_OC 755
Refer to imx51-pinfunc.h in device tree source folder for all available
imx51 PIN_FUNC_ID.
......@@ -28,1175 +28,5 @@ PAD_CTL_DSE_MAX (3 << 1)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
See below for available PIN_FUNC_ID for imx53:
MX53_PAD_GPIO_19__KPP_COL_5 0
MX53_PAD_GPIO_19__GPIO4_5 1
MX53_PAD_GPIO_19__CCM_CLKO 2
MX53_PAD_GPIO_19__SPDIF_OUT1 3
MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 4
MX53_PAD_GPIO_19__ECSPI1_RDY 5
MX53_PAD_GPIO_19__FEC_TDATA_3 6
MX53_PAD_GPIO_19__SRC_INT_BOOT 7
MX53_PAD_KEY_COL0__KPP_COL_0 8
MX53_PAD_KEY_COL0__GPIO4_6 9
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 10
MX53_PAD_KEY_COL0__UART4_TXD_MUX 11
MX53_PAD_KEY_COL0__ECSPI1_SCLK 12
MX53_PAD_KEY_COL0__FEC_RDATA_3 13
MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 14
MX53_PAD_KEY_ROW0__KPP_ROW_0 15
MX53_PAD_KEY_ROW0__GPIO4_7 16
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 17
MX53_PAD_KEY_ROW0__UART4_RXD_MUX 18
MX53_PAD_KEY_ROW0__ECSPI1_MOSI 19
MX53_PAD_KEY_ROW0__FEC_TX_ER 20
MX53_PAD_KEY_COL1__KPP_COL_1 21
MX53_PAD_KEY_COL1__GPIO4_8 22
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 23
MX53_PAD_KEY_COL1__UART5_TXD_MUX 24
MX53_PAD_KEY_COL1__ECSPI1_MISO 25
MX53_PAD_KEY_COL1__FEC_RX_CLK 26
MX53_PAD_KEY_COL1__USBPHY1_TXREADY 27
MX53_PAD_KEY_ROW1__KPP_ROW_1 28
MX53_PAD_KEY_ROW1__GPIO4_9 29
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 30
MX53_PAD_KEY_ROW1__UART5_RXD_MUX 31
MX53_PAD_KEY_ROW1__ECSPI1_SS0 32
MX53_PAD_KEY_ROW1__FEC_COL 33
MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 34
MX53_PAD_KEY_COL2__KPP_COL_2 35
MX53_PAD_KEY_COL2__GPIO4_10 36
MX53_PAD_KEY_COL2__CAN1_TXCAN 37
MX53_PAD_KEY_COL2__FEC_MDIO 38
MX53_PAD_KEY_COL2__ECSPI1_SS1 39
MX53_PAD_KEY_COL2__FEC_RDATA_2 40
MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 41
MX53_PAD_KEY_ROW2__KPP_ROW_2 42
MX53_PAD_KEY_ROW2__GPIO4_11 43
MX53_PAD_KEY_ROW2__CAN1_RXCAN 44
MX53_PAD_KEY_ROW2__FEC_MDC 45
MX53_PAD_KEY_ROW2__ECSPI1_SS2 46
MX53_PAD_KEY_ROW2__FEC_TDATA_2 47
MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 48
MX53_PAD_KEY_COL3__KPP_COL_3 49
MX53_PAD_KEY_COL3__GPIO4_12 50
MX53_PAD_KEY_COL3__USBOH3_H2_DP 51
MX53_PAD_KEY_COL3__SPDIF_IN1 52
MX53_PAD_KEY_COL3__I2C2_SCL 53
MX53_PAD_KEY_COL3__ECSPI1_SS3 54
MX53_PAD_KEY_COL3__FEC_CRS 55
MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 56
MX53_PAD_KEY_ROW3__KPP_ROW_3 57
MX53_PAD_KEY_ROW3__GPIO4_13 58
MX53_PAD_KEY_ROW3__USBOH3_H2_DM 59
MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 60
MX53_PAD_KEY_ROW3__I2C2_SDA 61
MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 62
MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 63
MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 64
MX53_PAD_KEY_COL4__KPP_COL_4 65
MX53_PAD_KEY_COL4__GPIO4_14 66
MX53_PAD_KEY_COL4__CAN2_TXCAN 67
MX53_PAD_KEY_COL4__IPU_SISG_4 68
MX53_PAD_KEY_COL4__UART5_RTS 69
MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 70
MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 71
MX53_PAD_KEY_ROW4__KPP_ROW_4 72
MX53_PAD_KEY_ROW4__GPIO4_15 73
MX53_PAD_KEY_ROW4__CAN2_RXCAN 74
MX53_PAD_KEY_ROW4__IPU_SISG_5 75
MX53_PAD_KEY_ROW4__UART5_CTS 76
MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 77
MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 78
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 79
MX53_PAD_DI0_DISP_CLK__GPIO4_16 80
MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 81
MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 82
MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 83
MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 84
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 85
MX53_PAD_DI0_PIN15__GPIO4_17 86
MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 87
MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 88
MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 89
MX53_PAD_DI0_PIN15__USBPHY1_BVALID 90
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 91
MX53_PAD_DI0_PIN2__GPIO4_18 92
MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 93
MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 94
MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 95
MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 96
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 97
MX53_PAD_DI0_PIN3__GPIO4_19 98
MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 99
MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 100
MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 101
MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 102
MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 103
MX53_PAD_DI0_PIN4__GPIO4_20 104
MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 105
MX53_PAD_DI0_PIN4__ESDHC1_WP 106
MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 107
MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 108
MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 109
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 110
MX53_PAD_DISP0_DAT0__GPIO4_21 111
MX53_PAD_DISP0_DAT0__CSPI_SCLK 112
MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 113
MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 114
MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 115
MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 116
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 117
MX53_PAD_DISP0_DAT1__GPIO4_22 118
MX53_PAD_DISP0_DAT1__CSPI_MOSI 119
MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 120
MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 121
MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 122
MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 123
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 124
MX53_PAD_DISP0_DAT2__GPIO4_23 125
MX53_PAD_DISP0_DAT2__CSPI_MISO 126
MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 127
MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 128
MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 129
MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 130
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 131
MX53_PAD_DISP0_DAT3__GPIO4_24 132
MX53_PAD_DISP0_DAT3__CSPI_SS0 133
MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 134
MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 135
MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 136
MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 137
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 138
MX53_PAD_DISP0_DAT4__GPIO4_25 139
MX53_PAD_DISP0_DAT4__CSPI_SS1 140
MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 141
MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 142
MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 143
MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 144
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 145
MX53_PAD_DISP0_DAT5__GPIO4_26 146
MX53_PAD_DISP0_DAT5__CSPI_SS2 147
MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 148
MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 149
MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 150
MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 151
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 152
MX53_PAD_DISP0_DAT6__GPIO4_27 153
MX53_PAD_DISP0_DAT6__CSPI_SS3 154
MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 155
MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 156
MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 157
MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 158
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 159
MX53_PAD_DISP0_DAT7__GPIO4_28 160
MX53_PAD_DISP0_DAT7__CSPI_RDY 161
MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 162
MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 163
MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 164
MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 165
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 166
MX53_PAD_DISP0_DAT8__GPIO4_29 167
MX53_PAD_DISP0_DAT8__PWM1_PWMO 168
MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 169
MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 170
MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 171
MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 172
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 173
MX53_PAD_DISP0_DAT9__GPIO4_30 174
MX53_PAD_DISP0_DAT9__PWM2_PWMO 175
MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 176
MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 177
MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 178
MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 179
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 180
MX53_PAD_DISP0_DAT10__GPIO4_31 181
MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 182
MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 183
MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 184
MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 185
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 186
MX53_PAD_DISP0_DAT11__GPIO5_5 187
MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 188
MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 189
MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 190
MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 191
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 192
MX53_PAD_DISP0_DAT12__GPIO5_6 193
MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 194
MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 195
MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 196
MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 197
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 198
MX53_PAD_DISP0_DAT13__GPIO5_7 199
MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 200
MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 201
MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 202
MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 203
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 204
MX53_PAD_DISP0_DAT14__GPIO5_8 205
MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 206
MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 207
MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 208
MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 209
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 210
MX53_PAD_DISP0_DAT15__GPIO5_9 211
MX53_PAD_DISP0_DAT15__ECSPI1_SS1 212
MX53_PAD_DISP0_DAT15__ECSPI2_SS1 213
MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 214
MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 215
MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 216
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 217
MX53_PAD_DISP0_DAT16__GPIO5_10 218
MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 219
MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 220
MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 221
MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 222
MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 223
MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 224
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 225
MX53_PAD_DISP0_DAT17__GPIO5_11 226
MX53_PAD_DISP0_DAT17__ECSPI2_MISO 227
MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 228
MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 229
MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 230
MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 231
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 232
MX53_PAD_DISP0_DAT18__GPIO5_12 233
MX53_PAD_DISP0_DAT18__ECSPI2_SS0 234
MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 235
MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 236
MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 237
MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 238
MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 239
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 240
MX53_PAD_DISP0_DAT19__GPIO5_13 241
MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 242
MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 243
MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 244
MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 245
MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 246
MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 247
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 248
MX53_PAD_DISP0_DAT20__GPIO5_14 249
MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 250
MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 251
MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 252
MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 253
MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 254
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 255
MX53_PAD_DISP0_DAT21__GPIO5_15 256
MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 257
MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 258
MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 259
MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 260
MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 261
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 262
MX53_PAD_DISP0_DAT22__GPIO5_16 263
MX53_PAD_DISP0_DAT22__ECSPI1_MISO 264
MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 265
MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 266
MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 267
MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 268
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 269
MX53_PAD_DISP0_DAT23__GPIO5_17 270
MX53_PAD_DISP0_DAT23__ECSPI1_SS0 271
MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 272
MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 273
MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 274
MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 275
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 276
MX53_PAD_CSI0_PIXCLK__GPIO5_18 277
MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 278
MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 279
MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 280
MX53_PAD_CSI0_MCLK__GPIO5_19 281
MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 282
MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 283
MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 284
MX53_PAD_CSI0_MCLK__TPIU_TRCTL 285
MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 286
MX53_PAD_CSI0_DATA_EN__GPIO5_20 287
MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 288
MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 289
MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 290
MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 291
MX53_PAD_CSI0_VSYNC__GPIO5_21 292
MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 293
MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 294
MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 295
MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 296
MX53_PAD_CSI0_DAT4__GPIO5_22 297
MX53_PAD_CSI0_DAT4__KPP_COL_5 298
MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 299
MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 300
MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 301
MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 302
MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 303
MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 304
MX53_PAD_CSI0_DAT5__GPIO5_23 305
MX53_PAD_CSI0_DAT5__KPP_ROW_5 306
MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 307
MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 308
MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 309
MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 310
MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 311
MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 312
MX53_PAD_CSI0_DAT6__GPIO5_24 313
MX53_PAD_CSI0_DAT6__KPP_COL_6 314
MX53_PAD_CSI0_DAT6__ECSPI1_MISO 315
MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 316
MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 317
MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 318
MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 319
MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 320
MX53_PAD_CSI0_DAT7__GPIO5_25 321
MX53_PAD_CSI0_DAT7__KPP_ROW_6 322
MX53_PAD_CSI0_DAT7__ECSPI1_SS0 323
MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 324
MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 325
MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 326
MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 327
MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 328
MX53_PAD_CSI0_DAT8__GPIO5_26 329
MX53_PAD_CSI0_DAT8__KPP_COL_7 330
MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 331
MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 332
MX53_PAD_CSI0_DAT8__I2C1_SDA 333
MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 334
MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 335
MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 336
MX53_PAD_CSI0_DAT9__GPIO5_27 337
MX53_PAD_CSI0_DAT9__KPP_ROW_7 338
MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 339
MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 340
MX53_PAD_CSI0_DAT9__I2C1_SCL 341
MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 342
MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 343
MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 344
MX53_PAD_CSI0_DAT10__GPIO5_28 345
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 346
MX53_PAD_CSI0_DAT10__ECSPI2_MISO 347
MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 348
MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 349
MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 350
MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 351
MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 352
MX53_PAD_CSI0_DAT11__GPIO5_29 353
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 354
MX53_PAD_CSI0_DAT11__ECSPI2_SS0 355
MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 356
MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 357
MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 358
MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 359
MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 360
MX53_PAD_CSI0_DAT12__GPIO5_30 361
MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 362
MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 363
MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 364
MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 365
MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 366
MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 367
MX53_PAD_CSI0_DAT13__GPIO5_31 368
MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 369
MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 370
MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 371
MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 372
MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 373
MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 374
MX53_PAD_CSI0_DAT14__GPIO6_0 375
MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 376
MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 377
MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 378
MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 379
MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 380
MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 381
MX53_PAD_CSI0_DAT15__GPIO6_1 382
MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 383
MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 384
MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 385
MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 386
MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 387
MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 388
MX53_PAD_CSI0_DAT16__GPIO6_2 389
MX53_PAD_CSI0_DAT16__UART4_RTS 390
MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 391
MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 392
MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 393
MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 394
MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 395
MX53_PAD_CSI0_DAT17__GPIO6_3 396
MX53_PAD_CSI0_DAT17__UART4_CTS 397
MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 398
MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 399
MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 400
MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 401
MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 402
MX53_PAD_CSI0_DAT18__GPIO6_4 403
MX53_PAD_CSI0_DAT18__UART5_RTS 404
MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 405
MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 406
MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 407
MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 408
MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 409
MX53_PAD_CSI0_DAT19__GPIO6_5 410
MX53_PAD_CSI0_DAT19__UART5_CTS 411
MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 412
MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 413
MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 414
MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 415
MX53_PAD_EIM_A25__EMI_WEIM_A_25 416
MX53_PAD_EIM_A25__GPIO5_2 417
MX53_PAD_EIM_A25__ECSPI2_RDY 418
MX53_PAD_EIM_A25__IPU_DI1_PIN12 419
MX53_PAD_EIM_A25__CSPI_SS1 420
MX53_PAD_EIM_A25__IPU_DI0_D1_CS 421
MX53_PAD_EIM_A25__USBPHY1_BISTOK 422
MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 423
MX53_PAD_EIM_EB2__GPIO2_30 424
MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 425
MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 426
MX53_PAD_EIM_EB2__ECSPI1_SS0 427
MX53_PAD_EIM_EB2__I2C2_SCL 428
MX53_PAD_EIM_D16__EMI_WEIM_D_16 429
MX53_PAD_EIM_D16__GPIO3_16 430
MX53_PAD_EIM_D16__IPU_DI0_PIN5 431
MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 432
MX53_PAD_EIM_D16__ECSPI1_SCLK 433
MX53_PAD_EIM_D16__I2C2_SDA 434
MX53_PAD_EIM_D17__EMI_WEIM_D_17 435
MX53_PAD_EIM_D17__GPIO3_17 436
MX53_PAD_EIM_D17__IPU_DI0_PIN6 437
MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 438
MX53_PAD_EIM_D17__ECSPI1_MISO 439
MX53_PAD_EIM_D17__I2C3_SCL 440
MX53_PAD_EIM_D18__EMI_WEIM_D_18 441
MX53_PAD_EIM_D18__GPIO3_18 442
MX53_PAD_EIM_D18__IPU_DI0_PIN7 443
MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 444
MX53_PAD_EIM_D18__ECSPI1_MOSI 445
MX53_PAD_EIM_D18__I2C3_SDA 446
MX53_PAD_EIM_D18__IPU_DI1_D0_CS 447
MX53_PAD_EIM_D19__EMI_WEIM_D_19 448
MX53_PAD_EIM_D19__GPIO3_19 449
MX53_PAD_EIM_D19__IPU_DI0_PIN8 450
MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 451
MX53_PAD_EIM_D19__ECSPI1_SS1 452
MX53_PAD_EIM_D19__EPIT1_EPITO 453
MX53_PAD_EIM_D19__UART1_CTS 454
MX53_PAD_EIM_D19__USBOH3_USBH2_OC 455
MX53_PAD_EIM_D20__EMI_WEIM_D_20 456
MX53_PAD_EIM_D20__GPIO3_20 457
MX53_PAD_EIM_D20__IPU_DI0_PIN16 458
MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 459
MX53_PAD_EIM_D20__CSPI_SS0 460
MX53_PAD_EIM_D20__EPIT2_EPITO 461
MX53_PAD_EIM_D20__UART1_RTS 462
MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 463
MX53_PAD_EIM_D21__EMI_WEIM_D_21 464
MX53_PAD_EIM_D21__GPIO3_21 465
MX53_PAD_EIM_D21__IPU_DI0_PIN17 466
MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 467
MX53_PAD_EIM_D21__CSPI_SCLK 468
MX53_PAD_EIM_D21__I2C1_SCL 469
MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 470
MX53_PAD_EIM_D22__EMI_WEIM_D_22 471
MX53_PAD_EIM_D22__GPIO3_22 472
MX53_PAD_EIM_D22__IPU_DI0_PIN1 473
MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 474
MX53_PAD_EIM_D22__CSPI_MISO 475
MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 476
MX53_PAD_EIM_D23__EMI_WEIM_D_23 477
MX53_PAD_EIM_D23__GPIO3_23 478
MX53_PAD_EIM_D23__UART3_CTS 479
MX53_PAD_EIM_D23__UART1_DCD 480
MX53_PAD_EIM_D23__IPU_DI0_D0_CS 481
MX53_PAD_EIM_D23__IPU_DI1_PIN2 482
MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 483
MX53_PAD_EIM_D23__IPU_DI1_PIN14 484
MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 485
MX53_PAD_EIM_EB3__GPIO2_31 486
MX53_PAD_EIM_EB3__UART3_RTS 487
MX53_PAD_EIM_EB3__UART1_RI 488
MX53_PAD_EIM_EB3__IPU_DI1_PIN3 489
MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 490
MX53_PAD_EIM_EB3__IPU_DI1_PIN16 491
MX53_PAD_EIM_D24__EMI_WEIM_D_24 492
MX53_PAD_EIM_D24__GPIO3_24 493
MX53_PAD_EIM_D24__UART3_TXD_MUX 494
MX53_PAD_EIM_D24__ECSPI1_SS2 495
MX53_PAD_EIM_D24__CSPI_SS2 496
MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 497
MX53_PAD_EIM_D24__ECSPI2_SS2 498
MX53_PAD_EIM_D24__UART1_DTR 499
MX53_PAD_EIM_D25__EMI_WEIM_D_25 500
MX53_PAD_EIM_D25__GPIO3_25 501
MX53_PAD_EIM_D25__UART3_RXD_MUX 502
MX53_PAD_EIM_D25__ECSPI1_SS3 503
MX53_PAD_EIM_D25__CSPI_SS3 504
MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 505
MX53_PAD_EIM_D25__ECSPI2_SS3 506
MX53_PAD_EIM_D25__UART1_DSR 507
MX53_PAD_EIM_D26__EMI_WEIM_D_26 508
MX53_PAD_EIM_D26__GPIO3_26 509
MX53_PAD_EIM_D26__UART2_TXD_MUX 510
MX53_PAD_EIM_D26__FIRI_RXD 511
MX53_PAD_EIM_D26__IPU_CSI0_D_1 512
MX53_PAD_EIM_D26__IPU_DI1_PIN11 513
MX53_PAD_EIM_D26__IPU_SISG_2 514
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 515
MX53_PAD_EIM_D27__EMI_WEIM_D_27 516
MX53_PAD_EIM_D27__GPIO3_27 517
MX53_PAD_EIM_D27__UART2_RXD_MUX 518
MX53_PAD_EIM_D27__FIRI_TXD 519
MX53_PAD_EIM_D27__IPU_CSI0_D_0 520
MX53_PAD_EIM_D27__IPU_DI1_PIN13 521
MX53_PAD_EIM_D27__IPU_SISG_3 522
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 523
MX53_PAD_EIM_D28__EMI_WEIM_D_28 524
MX53_PAD_EIM_D28__GPIO3_28 525
MX53_PAD_EIM_D28__UART2_CTS 526
MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 527
MX53_PAD_EIM_D28__CSPI_MOSI 528
MX53_PAD_EIM_D28__I2C1_SDA 529
MX53_PAD_EIM_D28__IPU_EXT_TRIG 530
MX53_PAD_EIM_D28__IPU_DI0_PIN13 531
MX53_PAD_EIM_D29__EMI_WEIM_D_29 532
MX53_PAD_EIM_D29__GPIO3_29 533
MX53_PAD_EIM_D29__UART2_RTS 534
MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 535
MX53_PAD_EIM_D29__CSPI_SS0 536
MX53_PAD_EIM_D29__IPU_DI1_PIN15 537
MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 538
MX53_PAD_EIM_D29__IPU_DI0_PIN14 539
MX53_PAD_EIM_D30__EMI_WEIM_D_30 540
MX53_PAD_EIM_D30__GPIO3_30 541
MX53_PAD_EIM_D30__UART3_CTS 542
MX53_PAD_EIM_D30__IPU_CSI0_D_3 543
MX53_PAD_EIM_D30__IPU_DI0_PIN11 544
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 545
MX53_PAD_EIM_D30__USBOH3_USBH1_OC 546
MX53_PAD_EIM_D30__USBOH3_USBH2_OC 547
MX53_PAD_EIM_D31__EMI_WEIM_D_31 548
MX53_PAD_EIM_D31__GPIO3_31 549
MX53_PAD_EIM_D31__UART3_RTS 550
MX53_PAD_EIM_D31__IPU_CSI0_D_2 551
MX53_PAD_EIM_D31__IPU_DI0_PIN12 552
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 553
MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 554
MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 555
MX53_PAD_EIM_A24__EMI_WEIM_A_24 556
MX53_PAD_EIM_A24__GPIO5_4 557
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 558
MX53_PAD_EIM_A24__IPU_CSI1_D_19 559
MX53_PAD_EIM_A24__IPU_SISG_2 560
MX53_PAD_EIM_A24__USBPHY2_BVALID 561
MX53_PAD_EIM_A23__EMI_WEIM_A_23 562
MX53_PAD_EIM_A23__GPIO6_6 563
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 564
MX53_PAD_EIM_A23__IPU_CSI1_D_18 565
MX53_PAD_EIM_A23__IPU_SISG_3 566
MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 567
MX53_PAD_EIM_A22__EMI_WEIM_A_22 568
MX53_PAD_EIM_A22__GPIO2_16 569
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 570
MX53_PAD_EIM_A22__IPU_CSI1_D_17 571
MX53_PAD_EIM_A22__SRC_BT_CFG1_7 572
MX53_PAD_EIM_A21__EMI_WEIM_A_21 573
MX53_PAD_EIM_A21__GPIO2_17 574
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 575
MX53_PAD_EIM_A21__IPU_CSI1_D_16 576
MX53_PAD_EIM_A21__SRC_BT_CFG1_6 577
MX53_PAD_EIM_A20__EMI_WEIM_A_20 578
MX53_PAD_EIM_A20__GPIO2_18 579
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 580
MX53_PAD_EIM_A20__IPU_CSI1_D_15 581
MX53_PAD_EIM_A20__SRC_BT_CFG1_5 582
MX53_PAD_EIM_A19__EMI_WEIM_A_19 583
MX53_PAD_EIM_A19__GPIO2_19 584
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 585
MX53_PAD_EIM_A19__IPU_CSI1_D_14 586
MX53_PAD_EIM_A19__SRC_BT_CFG1_4 587
MX53_PAD_EIM_A18__EMI_WEIM_A_18 588
MX53_PAD_EIM_A18__GPIO2_20 589
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 590
MX53_PAD_EIM_A18__IPU_CSI1_D_13 591
MX53_PAD_EIM_A18__SRC_BT_CFG1_3 592
MX53_PAD_EIM_A17__EMI_WEIM_A_17 593
MX53_PAD_EIM_A17__GPIO2_21 594
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 595
MX53_PAD_EIM_A17__IPU_CSI1_D_12 596
MX53_PAD_EIM_A17__SRC_BT_CFG1_2 597
MX53_PAD_EIM_A16__EMI_WEIM_A_16 598
MX53_PAD_EIM_A16__GPIO2_22 599
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 600
MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 601
MX53_PAD_EIM_A16__SRC_BT_CFG1_1 602
MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 603
MX53_PAD_EIM_CS0__GPIO2_23 604
MX53_PAD_EIM_CS0__ECSPI2_SCLK 605
MX53_PAD_EIM_CS0__IPU_DI1_PIN5 606
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 607
MX53_PAD_EIM_CS1__GPIO2_24 608
MX53_PAD_EIM_CS1__ECSPI2_MOSI 609
MX53_PAD_EIM_CS1__IPU_DI1_PIN6 610
MX53_PAD_EIM_OE__EMI_WEIM_OE 611
MX53_PAD_EIM_OE__GPIO2_25 612
MX53_PAD_EIM_OE__ECSPI2_MISO 613
MX53_PAD_EIM_OE__IPU_DI1_PIN7 614
MX53_PAD_EIM_OE__USBPHY2_IDDIG 615
MX53_PAD_EIM_RW__EMI_WEIM_RW 616
MX53_PAD_EIM_RW__GPIO2_26 617
MX53_PAD_EIM_RW__ECSPI2_SS0 618
MX53_PAD_EIM_RW__IPU_DI1_PIN8 619
MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 620
MX53_PAD_EIM_LBA__EMI_WEIM_LBA 621
MX53_PAD_EIM_LBA__GPIO2_27 622
MX53_PAD_EIM_LBA__ECSPI2_SS1 623
MX53_PAD_EIM_LBA__IPU_DI1_PIN17 624
MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 625
MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 626
MX53_PAD_EIM_EB0__GPIO2_28 627
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 628
MX53_PAD_EIM_EB0__IPU_CSI1_D_11 629
MX53_PAD_EIM_EB0__GPC_PMIC_RDY 630
MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 631
MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 632
MX53_PAD_EIM_EB1__GPIO2_29 633
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 634
MX53_PAD_EIM_EB1__IPU_CSI1_D_10 635
MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 636
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 637
MX53_PAD_EIM_DA0__GPIO3_0 638
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 639
MX53_PAD_EIM_DA0__IPU_CSI1_D_9 640
MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 641
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 642
MX53_PAD_EIM_DA1__GPIO3_1 643
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 644
MX53_PAD_EIM_DA1__IPU_CSI1_D_8 645
MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 646
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 647
MX53_PAD_EIM_DA2__GPIO3_2 648
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 649
MX53_PAD_EIM_DA2__IPU_CSI1_D_7 650
MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 651
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 652
MX53_PAD_EIM_DA3__GPIO3_3 653
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 654
MX53_PAD_EIM_DA3__IPU_CSI1_D_6 655
MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 656
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 657
MX53_PAD_EIM_DA4__GPIO3_4 658
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 659
MX53_PAD_EIM_DA4__IPU_CSI1_D_5 660
MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 661
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 662
MX53_PAD_EIM_DA5__GPIO3_5 663
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 664
MX53_PAD_EIM_DA5__IPU_CSI1_D_4 665
MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 666
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 667
MX53_PAD_EIM_DA6__GPIO3_6 668
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 669
MX53_PAD_EIM_DA6__IPU_CSI1_D_3 670
MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 671
MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 672
MX53_PAD_EIM_DA7__GPIO3_7 673
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 674
MX53_PAD_EIM_DA7__IPU_CSI1_D_2 675
MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 676
MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 677
MX53_PAD_EIM_DA8__GPIO3_8 678
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 679
MX53_PAD_EIM_DA8__IPU_CSI1_D_1 680
MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 681
MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 682
MX53_PAD_EIM_DA9__GPIO3_9 683
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 684
MX53_PAD_EIM_DA9__IPU_CSI1_D_0 685
MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 686
MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 687
MX53_PAD_EIM_DA10__GPIO3_10 688
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 689
MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 690
MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 691
MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 692
MX53_PAD_EIM_DA11__GPIO3_11 693
MX53_PAD_EIM_DA11__IPU_DI1_PIN2 694
MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 695
MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 696
MX53_PAD_EIM_DA12__GPIO3_12 697
MX53_PAD_EIM_DA12__IPU_DI1_PIN3 698
MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 699
MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 700
MX53_PAD_EIM_DA13__GPIO3_13 701
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 702
MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 703
MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 704
MX53_PAD_EIM_DA14__GPIO3_14 705
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 706
MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 707
MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 708
MX53_PAD_EIM_DA15__GPIO3_15 709
MX53_PAD_EIM_DA15__IPU_DI1_PIN1 710
MX53_PAD_EIM_DA15__IPU_DI1_PIN4 711
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 712
MX53_PAD_NANDF_WE_B__GPIO6_12 713
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 714
MX53_PAD_NANDF_RE_B__GPIO6_13 715
MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 716
MX53_PAD_EIM_WAIT__GPIO5_0 717
MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 718
MX53_PAD_LVDS1_TX3_P__GPIO6_22 719
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 720
MX53_PAD_LVDS1_TX2_P__GPIO6_24 721
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 722
MX53_PAD_LVDS1_CLK_P__GPIO6_26 723
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 724
MX53_PAD_LVDS1_TX1_P__GPIO6_28 725
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 726
MX53_PAD_LVDS1_TX0_P__GPIO6_30 727
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 728
MX53_PAD_LVDS0_TX3_P__GPIO7_22 729
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 730
MX53_PAD_LVDS0_CLK_P__GPIO7_24 731
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 732
MX53_PAD_LVDS0_TX2_P__GPIO7_26 733
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 734
MX53_PAD_LVDS0_TX1_P__GPIO7_28 735
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 736
MX53_PAD_LVDS0_TX0_P__GPIO7_30 737
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 738
MX53_PAD_GPIO_10__GPIO4_0 739
MX53_PAD_GPIO_10__OSC32k_32K_OUT 740
MX53_PAD_GPIO_11__GPIO4_1 741
MX53_PAD_GPIO_12__GPIO4_2 742
MX53_PAD_GPIO_13__GPIO4_3 743
MX53_PAD_GPIO_14__GPIO4_4 744
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 745
MX53_PAD_NANDF_CLE__GPIO6_7 746
MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 747
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 748
MX53_PAD_NANDF_ALE__GPIO6_8 749
MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 750
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 751
MX53_PAD_NANDF_WP_B__GPIO6_9 752
MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 753
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 754
MX53_PAD_NANDF_RB0__GPIO6_10 755
MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 756
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 757
MX53_PAD_NANDF_CS0__GPIO6_11 758
MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 759
MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 760
MX53_PAD_NANDF_CS1__GPIO6_14 761
MX53_PAD_NANDF_CS1__MLB_MLBCLK 762
MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 763
MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 764
MX53_PAD_NANDF_CS2__GPIO6_15 765
MX53_PAD_NANDF_CS2__IPU_SISG_0 766
MX53_PAD_NANDF_CS2__ESAI1_TX0 767
MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 768
MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 769
MX53_PAD_NANDF_CS2__MLB_MLBSIG 770
MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 771
MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 772
MX53_PAD_NANDF_CS3__GPIO6_16 773
MX53_PAD_NANDF_CS3__IPU_SISG_1 774
MX53_PAD_NANDF_CS3__ESAI1_TX1 775
MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 776
MX53_PAD_NANDF_CS3__MLB_MLBDAT 777
MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 778
MX53_PAD_FEC_MDIO__FEC_MDIO 779
MX53_PAD_FEC_MDIO__GPIO1_22 780
MX53_PAD_FEC_MDIO__ESAI1_SCKR 781
MX53_PAD_FEC_MDIO__FEC_COL 782
MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 783
MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 784
MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 785
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 786
MX53_PAD_FEC_REF_CLK__GPIO1_23 787
MX53_PAD_FEC_REF_CLK__ESAI1_FSR 788
MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 789
MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 790
MX53_PAD_FEC_RX_ER__FEC_RX_ER 791
MX53_PAD_FEC_RX_ER__GPIO1_24 792
MX53_PAD_FEC_RX_ER__ESAI1_HCKR 793
MX53_PAD_FEC_RX_ER__FEC_RX_CLK 794
MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 795
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 796
MX53_PAD_FEC_CRS_DV__GPIO1_25 797
MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 798
MX53_PAD_FEC_RXD1__FEC_RDATA_1 799
MX53_PAD_FEC_RXD1__GPIO1_26 800
MX53_PAD_FEC_RXD1__ESAI1_FST 801
MX53_PAD_FEC_RXD1__MLB_MLBSIG 802
MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 803
MX53_PAD_FEC_RXD0__FEC_RDATA_0 804
MX53_PAD_FEC_RXD0__GPIO1_27 805
MX53_PAD_FEC_RXD0__ESAI1_HCKT 806
MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 807
MX53_PAD_FEC_TX_EN__FEC_TX_EN 808
MX53_PAD_FEC_TX_EN__GPIO1_28 809
MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 810
MX53_PAD_FEC_TXD1__FEC_TDATA_1 811
MX53_PAD_FEC_TXD1__GPIO1_29 812
MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 813
MX53_PAD_FEC_TXD1__MLB_MLBCLK 814
MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 815
MX53_PAD_FEC_TXD0__FEC_TDATA_0 816
MX53_PAD_FEC_TXD0__GPIO1_30 817
MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 818
MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 819
MX53_PAD_FEC_MDC__FEC_MDC 820
MX53_PAD_FEC_MDC__GPIO1_31 821
MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 822
MX53_PAD_FEC_MDC__MLB_MLBDAT 823
MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 824
MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 825
MX53_PAD_PATA_DIOW__PATA_DIOW 826
MX53_PAD_PATA_DIOW__GPIO6_17 827
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 828
MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 829
MX53_PAD_PATA_DMACK__PATA_DMACK 830
MX53_PAD_PATA_DMACK__GPIO6_18 831
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 832
MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 833
MX53_PAD_PATA_DMARQ__PATA_DMARQ 834
MX53_PAD_PATA_DMARQ__GPIO7_0 835
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 836
MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 837
MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 838
MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 839
MX53_PAD_PATA_BUFFER_EN__GPIO7_1 840
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 841
MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 842
MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 843
MX53_PAD_PATA_INTRQ__PATA_INTRQ 844
MX53_PAD_PATA_INTRQ__GPIO7_2 845
MX53_PAD_PATA_INTRQ__UART2_CTS 846
MX53_PAD_PATA_INTRQ__CAN1_TXCAN 847
MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 848
MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 849
MX53_PAD_PATA_DIOR__PATA_DIOR 850
MX53_PAD_PATA_DIOR__GPIO7_3 851
MX53_PAD_PATA_DIOR__UART2_RTS 852
MX53_PAD_PATA_DIOR__CAN1_RXCAN 853
MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 854
MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 855
MX53_PAD_PATA_RESET_B__GPIO7_4 856
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 857
MX53_PAD_PATA_RESET_B__UART1_CTS 858
MX53_PAD_PATA_RESET_B__CAN2_TXCAN 859
MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 860
MX53_PAD_PATA_IORDY__PATA_IORDY 861
MX53_PAD_PATA_IORDY__GPIO7_5 862
MX53_PAD_PATA_IORDY__ESDHC3_CLK 863
MX53_PAD_PATA_IORDY__UART1_RTS 864
MX53_PAD_PATA_IORDY__CAN2_RXCAN 865
MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 866
MX53_PAD_PATA_DA_0__PATA_DA_0 867
MX53_PAD_PATA_DA_0__GPIO7_6 868
MX53_PAD_PATA_DA_0__ESDHC3_RST 869
MX53_PAD_PATA_DA_0__OWIRE_LINE 870
MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 871
MX53_PAD_PATA_DA_1__PATA_DA_1 872
MX53_PAD_PATA_DA_1__GPIO7_7 873
MX53_PAD_PATA_DA_1__ESDHC4_CMD 874
MX53_PAD_PATA_DA_1__UART3_CTS 875
MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 876
MX53_PAD_PATA_DA_2__PATA_DA_2 877
MX53_PAD_PATA_DA_2__GPIO7_8 878
MX53_PAD_PATA_DA_2__ESDHC4_CLK 879
MX53_PAD_PATA_DA_2__UART3_RTS 880
MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 881
MX53_PAD_PATA_CS_0__PATA_CS_0 882
MX53_PAD_PATA_CS_0__GPIO7_9 883
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 884
MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 885
MX53_PAD_PATA_CS_1__PATA_CS_1 886
MX53_PAD_PATA_CS_1__GPIO7_10 887
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 888
MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 889
MX53_PAD_PATA_DATA0__PATA_DATA_0 890
MX53_PAD_PATA_DATA0__GPIO2_0 891
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 892
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 893
MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 894
MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 895
MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 896
MX53_PAD_PATA_DATA1__PATA_DATA_1 897
MX53_PAD_PATA_DATA1__GPIO2_1 898
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 899
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 900
MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 901
MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 902
MX53_PAD_PATA_DATA2__PATA_DATA_2 903
MX53_PAD_PATA_DATA2__GPIO2_2 904
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 905
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 906
MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 907
MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 908
MX53_PAD_PATA_DATA3__PATA_DATA_3 909
MX53_PAD_PATA_DATA3__GPIO2_3 910
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 911
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 912
MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 913
MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 914
MX53_PAD_PATA_DATA4__PATA_DATA_4 915
MX53_PAD_PATA_DATA4__GPIO2_4 916
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 917
MX53_PAD_PATA_DATA4__ESDHC4_DAT4 918
MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 919
MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 920
MX53_PAD_PATA_DATA5__PATA_DATA_5 921
MX53_PAD_PATA_DATA5__GPIO2_5 922
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 923
MX53_PAD_PATA_DATA5__ESDHC4_DAT5 924
MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 925
MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 926
MX53_PAD_PATA_DATA6__PATA_DATA_6 927
MX53_PAD_PATA_DATA6__GPIO2_6 928
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 929
MX53_PAD_PATA_DATA6__ESDHC4_DAT6 930
MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 931
MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 932
MX53_PAD_PATA_DATA7__PATA_DATA_7 933
MX53_PAD_PATA_DATA7__GPIO2_7 934
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 935
MX53_PAD_PATA_DATA7__ESDHC4_DAT7 936
MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 937
MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 938
MX53_PAD_PATA_DATA8__PATA_DATA_8 939
MX53_PAD_PATA_DATA8__GPIO2_8 940
MX53_PAD_PATA_DATA8__ESDHC1_DAT4 941
MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 942
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 943
MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 944
MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 945
MX53_PAD_PATA_DATA9__PATA_DATA_9 946
MX53_PAD_PATA_DATA9__GPIO2_9 947
MX53_PAD_PATA_DATA9__ESDHC1_DAT5 948
MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 949
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 950
MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 951
MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 952
MX53_PAD_PATA_DATA10__PATA_DATA_10 953
MX53_PAD_PATA_DATA10__GPIO2_10 954
MX53_PAD_PATA_DATA10__ESDHC1_DAT6 955
MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 956
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 957
MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 958
MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 959
MX53_PAD_PATA_DATA11__PATA_DATA_11 960
MX53_PAD_PATA_DATA11__GPIO2_11 961
MX53_PAD_PATA_DATA11__ESDHC1_DAT7 962
MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 963
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 964
MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 965
MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 966
MX53_PAD_PATA_DATA12__PATA_DATA_12 967
MX53_PAD_PATA_DATA12__GPIO2_12 968
MX53_PAD_PATA_DATA12__ESDHC2_DAT4 969
MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 970
MX53_PAD_PATA_DATA12__ESDHC4_DAT0 971
MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 972
MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 973
MX53_PAD_PATA_DATA13__PATA_DATA_13 974
MX53_PAD_PATA_DATA13__GPIO2_13 975
MX53_PAD_PATA_DATA13__ESDHC2_DAT5 976
MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 977
MX53_PAD_PATA_DATA13__ESDHC4_DAT1 978
MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 979
MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 980
MX53_PAD_PATA_DATA14__PATA_DATA_14 981
MX53_PAD_PATA_DATA14__GPIO2_14 982
MX53_PAD_PATA_DATA14__ESDHC2_DAT6 983
MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 984
MX53_PAD_PATA_DATA14__ESDHC4_DAT2 985
MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 986
MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 987
MX53_PAD_PATA_DATA15__PATA_DATA_15 988
MX53_PAD_PATA_DATA15__GPIO2_15 989
MX53_PAD_PATA_DATA15__ESDHC2_DAT7 990
MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 991
MX53_PAD_PATA_DATA15__ESDHC4_DAT3 992
MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 993
MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 994
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 995
MX53_PAD_SD1_DATA0__GPIO1_16 996
MX53_PAD_SD1_DATA0__GPT_CAPIN1 997
MX53_PAD_SD1_DATA0__CSPI_MISO 998
MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 999
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 1000
MX53_PAD_SD1_DATA1__GPIO1_17 1001
MX53_PAD_SD1_DATA1__GPT_CAPIN2 1002
MX53_PAD_SD1_DATA1__CSPI_SS0 1003
MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 1004
MX53_PAD_SD1_CMD__ESDHC1_CMD 1005
MX53_PAD_SD1_CMD__GPIO1_18 1006
MX53_PAD_SD1_CMD__GPT_CMPOUT1 1007
MX53_PAD_SD1_CMD__CSPI_MOSI 1008
MX53_PAD_SD1_CMD__CCM_PLL1_BYP 1009
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 1010
MX53_PAD_SD1_DATA2__GPIO1_19 1011
MX53_PAD_SD1_DATA2__GPT_CMPOUT2 1012
MX53_PAD_SD1_DATA2__PWM2_PWMO 1013
MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 1014
MX53_PAD_SD1_DATA2__CSPI_SS1 1015
MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 1016
MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 1017
MX53_PAD_SD1_CLK__ESDHC1_CLK 1018
MX53_PAD_SD1_CLK__GPIO1_20 1019
MX53_PAD_SD1_CLK__OSC32k_32K_OUT 1020
MX53_PAD_SD1_CLK__GPT_CLKIN 1021
MX53_PAD_SD1_CLK__CSPI_SCLK 1022
MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 1023
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 1024
MX53_PAD_SD1_DATA3__GPIO1_21 1025
MX53_PAD_SD1_DATA3__GPT_CMPOUT3 1026
MX53_PAD_SD1_DATA3__PWM1_PWMO 1027
MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 1028
MX53_PAD_SD1_DATA3__CSPI_SS2 1029
MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 1030
MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 1031
MX53_PAD_SD2_CLK__ESDHC2_CLK 1032
MX53_PAD_SD2_CLK__GPIO1_10 1033
MX53_PAD_SD2_CLK__KPP_COL_5 1034
MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1035
MX53_PAD_SD2_CLK__CSPI_SCLK 1036
MX53_PAD_SD2_CLK__SCC_RANDOM_V 1037
MX53_PAD_SD2_CMD__ESDHC2_CMD 1038
MX53_PAD_SD2_CMD__GPIO1_11 1039
MX53_PAD_SD2_CMD__KPP_ROW_5 1040
MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1041
MX53_PAD_SD2_CMD__CSPI_MOSI 1042
MX53_PAD_SD2_CMD__SCC_RANDOM 1043
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 1044
MX53_PAD_SD2_DATA3__GPIO1_12 1045
MX53_PAD_SD2_DATA3__KPP_COL_6 1046
MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 1047
MX53_PAD_SD2_DATA3__CSPI_SS2 1048
MX53_PAD_SD2_DATA3__SJC_DONE 1049
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 1050
MX53_PAD_SD2_DATA2__GPIO1_13 1051
MX53_PAD_SD2_DATA2__KPP_ROW_6 1052
MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 1053
MX53_PAD_SD2_DATA2__CSPI_SS1 1054
MX53_PAD_SD2_DATA2__SJC_FAIL 1055
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 1056
MX53_PAD_SD2_DATA1__GPIO1_14 1057
MX53_PAD_SD2_DATA1__KPP_COL_7 1058
MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 1059
MX53_PAD_SD2_DATA1__CSPI_SS0 1060
MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 1061
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 1062
MX53_PAD_SD2_DATA0__GPIO1_15 1063
MX53_PAD_SD2_DATA0__KPP_ROW_7 1064
MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 1065
MX53_PAD_SD2_DATA0__CSPI_MISO 1066
MX53_PAD_SD2_DATA0__RTIC_DONE_INT 1067
MX53_PAD_GPIO_0__CCM_CLKO 1068
MX53_PAD_GPIO_0__GPIO1_0 1069
MX53_PAD_GPIO_0__KPP_COL_5 1070
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 1071
MX53_PAD_GPIO_0__EPIT1_EPITO 1072
MX53_PAD_GPIO_0__SRTC_ALARM_DEB 1073
MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 1074
MX53_PAD_GPIO_0__CSU_TD 1075
MX53_PAD_GPIO_1__ESAI1_SCKR 1076
MX53_PAD_GPIO_1__GPIO1_1 1077
MX53_PAD_GPIO_1__KPP_ROW_5 1078
MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 1079
MX53_PAD_GPIO_1__PWM2_PWMO 1080
MX53_PAD_GPIO_1__WDOG2_WDOG_B 1081
MX53_PAD_GPIO_1__ESDHC1_CD 1082
MX53_PAD_GPIO_1__SRC_TESTER_ACK 1083
MX53_PAD_GPIO_9__ESAI1_FSR 1084
MX53_PAD_GPIO_9__GPIO1_9 1085
MX53_PAD_GPIO_9__KPP_COL_6 1086
MX53_PAD_GPIO_9__CCM_REF_EN_B 1087
MX53_PAD_GPIO_9__PWM1_PWMO 1088
MX53_PAD_GPIO_9__WDOG1_WDOG_B 1089
MX53_PAD_GPIO_9__ESDHC1_WP 1090
MX53_PAD_GPIO_9__SCC_FAIL_STATE 1091
MX53_PAD_GPIO_3__ESAI1_HCKR 1092
MX53_PAD_GPIO_3__GPIO1_3 1093
MX53_PAD_GPIO_3__I2C3_SCL 1094
MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 1095
MX53_PAD_GPIO_3__CCM_CLKO2 1096
MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 1097
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 1098
MX53_PAD_GPIO_3__MLB_MLBCLK 1099
MX53_PAD_GPIO_6__ESAI1_SCKT 1100
MX53_PAD_GPIO_6__GPIO1_6 1101
MX53_PAD_GPIO_6__I2C3_SDA 1102
MX53_PAD_GPIO_6__CCM_CCM_OUT_0 1103
MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 1104
MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 1105
MX53_PAD_GPIO_6__ESDHC2_LCTL 1106
MX53_PAD_GPIO_6__MLB_MLBSIG 1107
MX53_PAD_GPIO_2__ESAI1_FST 1108
MX53_PAD_GPIO_2__GPIO1_2 1109
MX53_PAD_GPIO_2__KPP_ROW_6 1110
MX53_PAD_GPIO_2__CCM_CCM_OUT_1 1111
MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 1112
MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 1113
MX53_PAD_GPIO_2__ESDHC2_WP 1114
MX53_PAD_GPIO_2__MLB_MLBDAT 1115
MX53_PAD_GPIO_4__ESAI1_HCKT 1116
MX53_PAD_GPIO_4__GPIO1_4 1117
MX53_PAD_GPIO_4__KPP_COL_7 1118
MX53_PAD_GPIO_4__CCM_CCM_OUT_2 1119
MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1120
MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 1121
MX53_PAD_GPIO_4__ESDHC2_CD 1122
MX53_PAD_GPIO_4__SCC_SEC_STATE 1123
MX53_PAD_GPIO_5__ESAI1_TX2_RX3 1124
MX53_PAD_GPIO_5__GPIO1_5 1125
MX53_PAD_GPIO_5__KPP_ROW_7 1126
MX53_PAD_GPIO_5__CCM_CLKO 1127
MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1128
MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 1129
MX53_PAD_GPIO_5__I2C3_SCL 1130
MX53_PAD_GPIO_5__CCM_PLL1_BYP 1131
MX53_PAD_GPIO_7__ESAI1_TX4_RX1 1132
MX53_PAD_GPIO_7__GPIO1_7 1133
MX53_PAD_GPIO_7__EPIT1_EPITO 1134
MX53_PAD_GPIO_7__CAN1_TXCAN 1135
MX53_PAD_GPIO_7__UART2_TXD_MUX 1136
MX53_PAD_GPIO_7__FIRI_RXD 1137
MX53_PAD_GPIO_7__SPDIF_PLOCK 1138
MX53_PAD_GPIO_7__CCM_PLL2_BYP 1139
MX53_PAD_GPIO_8__ESAI1_TX5_RX0 1140
MX53_PAD_GPIO_8__GPIO1_8 1141
MX53_PAD_GPIO_8__EPIT2_EPITO 1142
MX53_PAD_GPIO_8__CAN1_RXCAN 1143
MX53_PAD_GPIO_8__UART2_RXD_MUX 1144
MX53_PAD_GPIO_8__FIRI_TXD 1145
MX53_PAD_GPIO_8__SPDIF_SRCLK 1146
MX53_PAD_GPIO_8__CCM_PLL3_BYP 1147
MX53_PAD_GPIO_16__ESAI1_TX3_RX2 1148
MX53_PAD_GPIO_16__GPIO7_11 1149
MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 1150
MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 1151
MX53_PAD_GPIO_16__SPDIF_IN1 1152
MX53_PAD_GPIO_16__I2C3_SDA 1153
MX53_PAD_GPIO_16__SJC_DE_B 1154
MX53_PAD_GPIO_17__ESAI1_TX0 1155
MX53_PAD_GPIO_17__GPIO7_12 1156
MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 1157
MX53_PAD_GPIO_17__GPC_PMIC_RDY 1158
MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 1159
MX53_PAD_GPIO_17__SPDIF_OUT1 1160
MX53_PAD_GPIO_17__IPU_SNOOP2 1161
MX53_PAD_GPIO_17__SJC_JTAG_ACT 1162
MX53_PAD_GPIO_18__ESAI1_TX1 1163
MX53_PAD_GPIO_18__GPIO7_13 1164
MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 1165
MX53_PAD_GPIO_18__OWIRE_LINE 1166
MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 1167
MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 1168
MX53_PAD_GPIO_18__ESDHC1_LCTL 1169
MX53_PAD_GPIO_18__SRC_SYSTEM_RST 1170
Refer to imx53-pinfunc.h in device tree source folder for all available
imx53 PIN_FUNC_ID.
......@@ -34,1597 +34,5 @@ PAD_CTL_DSE_34ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
See below for available PIN_FUNC_ID for imx6q:
MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0
MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1
MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2
MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3
MX6Q_PAD_SD2_DAT1__KPP_COL_7 4
MX6Q_PAD_SD2_DAT1__GPIO_1_14 5
MX6Q_PAD_SD2_DAT1__CCM_WAIT 6
MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7
MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8
MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9
MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10
MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11
MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12
MX6Q_PAD_SD2_DAT2__GPIO_1_13 13
MX6Q_PAD_SD2_DAT2__CCM_STOP 14
MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15
MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16
MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17
MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18
MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19
MX6Q_PAD_SD2_DAT0__GPIO_1_15 20
MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21
MX6Q_PAD_SD2_DAT0__TESTO_2 22
MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24
MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25
MX6Q_PAD_RGMII_TXC__GPIO_6_19 26
MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27
MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28
MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29
MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30
MX6Q_PAD_RGMII_TD0__GPIO_6_20 31
MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32
MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33
MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34
MX6Q_PAD_RGMII_TD1__GPIO_6_21 35
MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36
MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37
MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38
MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39
MX6Q_PAD_RGMII_TD2__GPIO_6_22 40
MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41
MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42
MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43
MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44
MX6Q_PAD_RGMII_TD3__GPIO_6_23 45
MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46
MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48
MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49
MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50
MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51
MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52
MX6Q_PAD_RGMII_RD0__GPIO_6_25 53
MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54
MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56
MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57
MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58
MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59
MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60
MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61
MX6Q_PAD_RGMII_RD1__GPIO_6_27 62
MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63
MX6Q_PAD_RGMII_RD1__SJC_FAIL 64
MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65
MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66
MX6Q_PAD_RGMII_RD2__GPIO_6_28 67
MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68
MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69
MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70
MX6Q_PAD_RGMII_RD3__GPIO_6_29 71
MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72
MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73
MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74
MX6Q_PAD_RGMII_RXC__GPIO_6_30 75
MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76
MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77
MX6Q_PAD_EIM_A25__ECSPI4_SS1 78
MX6Q_PAD_EIM_A25__ECSPI2_RDY 79
MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80
MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81
MX6Q_PAD_EIM_A25__GPIO_5_2 82
MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83
MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84
MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85
MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86
MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87
MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88
MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89
MX6Q_PAD_EIM_EB2__GPIO_2_30 90
MX6Q_PAD_EIM_EB2__I2C2_SCL 91
MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92
MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93
MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94
MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95
MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96
MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97
MX6Q_PAD_EIM_D16__GPIO_3_16 98
MX6Q_PAD_EIM_D16__I2C2_SDA 99
MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100
MX6Q_PAD_EIM_D17__ECSPI1_MISO 101
MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102
MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103
MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104
MX6Q_PAD_EIM_D17__GPIO_3_17 105
MX6Q_PAD_EIM_D17__I2C3_SCL 106
MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107
MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108
MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109
MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110
MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111
MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112
MX6Q_PAD_EIM_D18__GPIO_3_18 113
MX6Q_PAD_EIM_D18__I2C3_SDA 114
MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115
MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116
MX6Q_PAD_EIM_D19__ECSPI1_SS1 117
MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118
MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119
MX6Q_PAD_EIM_D19__UART1_CTS 120
MX6Q_PAD_EIM_D19__GPIO_3_19 121
MX6Q_PAD_EIM_D19__EPIT1_EPITO 122
MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123
MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124
MX6Q_PAD_EIM_D20__ECSPI4_SS0 125
MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126
MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127
MX6Q_PAD_EIM_D20__UART1_RTS 128
MX6Q_PAD_EIM_D20__GPIO_3_20 129
MX6Q_PAD_EIM_D20__EPIT2_EPITO 130
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131
MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132
MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133
MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134
MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135
MX6Q_PAD_EIM_D21__GPIO_3_21 136
MX6Q_PAD_EIM_D21__I2C1_SCL 137
MX6Q_PAD_EIM_D21__SPDIF_IN1 138
MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139
MX6Q_PAD_EIM_D22__ECSPI4_MISO 140
MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141
MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142
MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143
MX6Q_PAD_EIM_D22__GPIO_3_22 144
MX6Q_PAD_EIM_D22__SPDIF_OUT1 145
MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146
MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147
MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148
MX6Q_PAD_EIM_D23__UART3_CTS 149
MX6Q_PAD_EIM_D23__UART1_DCD 150
MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151
MX6Q_PAD_EIM_D23__GPIO_3_23 152
MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153
MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154
MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155
MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156
MX6Q_PAD_EIM_EB3__UART3_RTS 157
MX6Q_PAD_EIM_EB3__UART1_RI 158
MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159
MX6Q_PAD_EIM_EB3__GPIO_2_31 160
MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161
MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162
MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163
MX6Q_PAD_EIM_D24__ECSPI4_SS2 164
MX6Q_PAD_EIM_D24__UART3_TXD 165
MX6Q_PAD_EIM_D24__ECSPI1_SS2 166
MX6Q_PAD_EIM_D24__ECSPI2_SS2 167
MX6Q_PAD_EIM_D24__GPIO_3_24 168
MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169
MX6Q_PAD_EIM_D24__UART1_DTR 170
MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171
MX6Q_PAD_EIM_D25__ECSPI4_SS3 172
MX6Q_PAD_EIM_D25__UART3_RXD 173
MX6Q_PAD_EIM_D25__ECSPI1_SS3 174
MX6Q_PAD_EIM_D25__ECSPI2_SS3 175
MX6Q_PAD_EIM_D25__GPIO_3_25 176
MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177
MX6Q_PAD_EIM_D25__UART1_DSR 178
MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179
MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180
MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181
MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182
MX6Q_PAD_EIM_D26__UART2_TXD 183
MX6Q_PAD_EIM_D26__GPIO_3_26 184
MX6Q_PAD_EIM_D26__IPU1_SISG_2 185
MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186
MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187
MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188
MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189
MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190
MX6Q_PAD_EIM_D27__UART2_RXD 191
MX6Q_PAD_EIM_D27__GPIO_3_27 192
MX6Q_PAD_EIM_D27__IPU1_SISG_3 193
MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194
MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195
MX6Q_PAD_EIM_D28__I2C1_SDA 196
MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197
MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198
MX6Q_PAD_EIM_D28__UART2_CTS 199
MX6Q_PAD_EIM_D28__GPIO_3_28 200
MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201
MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202
MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203
MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204
MX6Q_PAD_EIM_D29__ECSPI4_SS0 205
MX6Q_PAD_EIM_D29__UART2_RTS 206
MX6Q_PAD_EIM_D29__GPIO_3_29 207
MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208
MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209
MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210
MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211
MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212
MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213
MX6Q_PAD_EIM_D30__UART3_CTS 214
MX6Q_PAD_EIM_D30__GPIO_3_30 215
MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216
MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217
MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218
MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219
MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220
MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221
MX6Q_PAD_EIM_D31__UART3_RTS 222
MX6Q_PAD_EIM_D31__GPIO_3_31 223
MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224
MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225
MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226
MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227
MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228
MX6Q_PAD_EIM_A24__IPU2_SISG_2 229
MX6Q_PAD_EIM_A24__IPU1_SISG_2 230
MX6Q_PAD_EIM_A24__GPIO_5_4 231
MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232
MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233
MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234
MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235
MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236
MX6Q_PAD_EIM_A23__IPU2_SISG_3 237
MX6Q_PAD_EIM_A23__IPU1_SISG_3 238
MX6Q_PAD_EIM_A23__GPIO_6_6 239
MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240
MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241
MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242
MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243
MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244
MX6Q_PAD_EIM_A22__GPIO_2_16 245
MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246
MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247
MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248
MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249
MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250
MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251
MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252
MX6Q_PAD_EIM_A21__GPIO_2_17 253
MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254
MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255
MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256
MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257
MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258
MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259
MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260
MX6Q_PAD_EIM_A20__GPIO_2_18 261
MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262
MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263
MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264
MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265
MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266
MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267
MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268
MX6Q_PAD_EIM_A19__GPIO_2_19 269
MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270
MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271
MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272
MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273
MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274
MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275
MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276
MX6Q_PAD_EIM_A18__GPIO_2_20 277
MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278
MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279
MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280
MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281
MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282
MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283
MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284
MX6Q_PAD_EIM_A17__GPIO_2_21 285
MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286
MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287
MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288
MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289
MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290
MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291
MX6Q_PAD_EIM_A16__GPIO_2_22 292
MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293
MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294
MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295
MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296
MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297
MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298
MX6Q_PAD_EIM_CS0__GPIO_2_23 299
MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300
MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301
MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302
MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303
MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304
MX6Q_PAD_EIM_CS1__GPIO_2_24 305
MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306
MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307
MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308
MX6Q_PAD_EIM_OE__ECSPI2_MISO 309
MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310
MX6Q_PAD_EIM_OE__GPIO_2_25 311
MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312
MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313
MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314
MX6Q_PAD_EIM_RW__ECSPI2_SS0 315
MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316
MX6Q_PAD_EIM_RW__GPIO_2_26 317
MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318
MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319
MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320
MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321
MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322
MX6Q_PAD_EIM_LBA__GPIO_2_27 323
MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324
MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325
MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326
MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327
MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328
MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329
MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330
MX6Q_PAD_EIM_EB0__GPIO_2_28 331
MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332
MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333
MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334
MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335
MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336
MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337
MX6Q_PAD_EIM_EB1__GPIO_2_29 338
MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339
MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340
MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341
MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342
MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343
MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344
MX6Q_PAD_EIM_DA0__GPIO_3_0 345
MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346
MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347
MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348
MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349
MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350
MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351
MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352
MX6Q_PAD_EIM_DA1__GPIO_3_1 353
MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354
MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355
MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356
MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357
MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358
MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359
MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360
MX6Q_PAD_EIM_DA2__GPIO_3_2 361
MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362
MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363
MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364
MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365
MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366
MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367
MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368
MX6Q_PAD_EIM_DA3__GPIO_3_3 369
MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370
MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371
MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372
MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373
MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374
MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375
MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376
MX6Q_PAD_EIM_DA4__GPIO_3_4 377
MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378
MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379
MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380
MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381
MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382
MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383
MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384
MX6Q_PAD_EIM_DA5__GPIO_3_5 385
MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386
MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387
MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388
MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389
MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390
MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391
MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392
MX6Q_PAD_EIM_DA6__GPIO_3_6 393
MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394
MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395
MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396
MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397
MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398
MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399
MX6Q_PAD_EIM_DA7__GPIO_3_7 400
MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 401
MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 402
MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 403
MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 404
MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 405
MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 406
MX6Q_PAD_EIM_DA8__GPIO_3_8 407
MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 408
MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 409
MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 410
MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 411
MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 412
MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 413
MX6Q_PAD_EIM_DA9__GPIO_3_9 414
MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 415
MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 416
MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 417
MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 418
MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 419
MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 420
MX6Q_PAD_EIM_DA10__GPIO_3_10 421
MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 422
MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 423
MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 424
MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 425
MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 426
MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 427
MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 428
MX6Q_PAD_EIM_DA11__GPIO_3_11 429
MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 430
MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 431
MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 432
MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 433
MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 434
MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 435
MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 436
MX6Q_PAD_EIM_DA12__GPIO_3_12 437
MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 438
MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 439
MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 440
MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 441
MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK 442
MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 443
MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 444
MX6Q_PAD_EIM_DA13__GPIO_3_13 445
MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 446
MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 447
MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 448
MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 449
MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK 450
MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 451
MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 452
MX6Q_PAD_EIM_DA14__GPIO_3_14 453
MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 454
MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 455
MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 456
MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 457
MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 458
MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 459
MX6Q_PAD_EIM_DA15__GPIO_3_15 460
MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 461
MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 462
MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 463
MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B 464
MX6Q_PAD_EIM_WAIT__GPIO_5_0 465
MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 466
MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 467
MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK 468
MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 469
MX6Q_PAD_EIM_BCLK__GPIO_6_31 470
MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 471
MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK 472
MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK 473
MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 474
MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 475
MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 476
MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 477
MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 478
MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 479
MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 480
MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 481
MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 482
MX6Q_PAD_DI0_PIN15__GPIO_4_17 483
MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 484
MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 485
MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 486
MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 487
MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 488
MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 489
MX6Q_PAD_DI0_PIN2__GPIO_4_18 490
MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 491
MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 492
MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 493
MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 494
MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 495
MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 496
MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 497
MX6Q_PAD_DI0_PIN3__GPIO_4_19 498
MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 499
MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 500
MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 501
MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 502
MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 503
MX6Q_PAD_DI0_PIN4__USDHC1_WP 504
MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 505
MX6Q_PAD_DI0_PIN4__GPIO_4_20 506
MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 507
MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 508
MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 509
MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 510
MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 511
MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 512
MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN 513
MX6Q_PAD_DISP0_DAT0__GPIO_4_21 514
MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 515
MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 516
MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 517
MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 518
MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 519
MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL 520
MX6Q_PAD_DISP0_DAT1__GPIO_4_22 521
MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 522
MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 523
MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 524
MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 525
MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 526
MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 527
MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 528
MX6Q_PAD_DISP0_DAT2__GPIO_4_23 529
MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 530
MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 531
MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 532
MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 533
MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 534
MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 535
MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR 536
MX6Q_PAD_DISP0_DAT3__GPIO_4_24 537
MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 538
MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 539
MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 540
MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 541
MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 542
MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 543
MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 544
MX6Q_PAD_DISP0_DAT4__GPIO_4_25 545
MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 546
MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 547
MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 548
MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 549
MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 550
MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS 551
MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS 552
MX6Q_PAD_DISP0_DAT5__GPIO_4_26 553
MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 554
MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 555
MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 556
MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 557
MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 558
MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC 559
MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT 560
MX6Q_PAD_DISP0_DAT6__GPIO_4_27 561
MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 562
MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 563
MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 564
MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 565
MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 566
MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 567
MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 568
MX6Q_PAD_DISP0_DAT7__GPIO_4_28 569
MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 570
MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 571
MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 572
MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 573
MX6Q_PAD_DISP0_DAT8__PWM1_PWMO 574
MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B 575
MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 576
MX6Q_PAD_DISP0_DAT8__GPIO_4_29 577
MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 578
MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 579
MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 580
MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 581
MX6Q_PAD_DISP0_DAT9__PWM2_PWMO 582
MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B 583
MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 584
MX6Q_PAD_DISP0_DAT9__GPIO_4_30 585
MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 586
MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 587
MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 588
MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 589
MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 590
MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 591
MX6Q_PAD_DISP0_DAT10__GPIO_4_31 592
MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 593
MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 594
MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 595
MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 596
MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 597
MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 598
MX6Q_PAD_DISP0_DAT11__GPIO_5_5 599
MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 600
MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 601
MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 602
MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 603
MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED 604
MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 605
MX6Q_PAD_DISP0_DAT12__GPIO_5_6 606
MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 607
MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 608
MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 609
MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 610
MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 611
MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 612
MX6Q_PAD_DISP0_DAT13__GPIO_5_7 613
MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 614
MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 615
MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 616
MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 617
MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 618
MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 619
MX6Q_PAD_DISP0_DAT14__GPIO_5_8 620
MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 621
MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 622
MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 623
MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 624
MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 625
MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 626
MX6Q_PAD_DISP0_DAT15__GPIO_5_9 627
MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 628
MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 629
MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 630
MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 631
MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 632
MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 633
MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 634
MX6Q_PAD_DISP0_DAT16__GPIO_5_10 635
MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 636
MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 637
MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 638
MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 639
MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 640
MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 641
MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 642
MX6Q_PAD_DISP0_DAT17__GPIO_5_11 643
MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 644
MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 645
MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 646
MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 647
MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 648
MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 649
MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 650
MX6Q_PAD_DISP0_DAT18__GPIO_5_12 651
MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 652
MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 653
MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 654
MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 655
MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 656
MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 657
MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 658
MX6Q_PAD_DISP0_DAT19__GPIO_5_13 659
MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 660
MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 661
MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 662
MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 663
MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 664
MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 665
MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 666
MX6Q_PAD_DISP0_DAT20__GPIO_5_14 667
MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 668
MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 669
MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 670
MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 671
MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 672
MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 673
MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 674
MX6Q_PAD_DISP0_DAT21__GPIO_5_15 675
MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 676
MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 677
MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 678
MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 679
MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 680
MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 681
MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 682
MX6Q_PAD_DISP0_DAT22__GPIO_5_16 683
MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 684
MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 685
MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 686
MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 687
MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 688
MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 689
MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 690
MX6Q_PAD_DISP0_DAT23__GPIO_5_17 691
MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 692
MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 693
MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED 694
MX6Q_PAD_ENET_MDIO__ENET_MDIO 695
MX6Q_PAD_ENET_MDIO__ESAI1_SCKR 696
MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 697
MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT 698
MX6Q_PAD_ENET_MDIO__GPIO_1_22 699
MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK 700
MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED 701
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 702
MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR 703
MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 704
MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 705
MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK 706
MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH 707
MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 708
MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR 709
MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 710
MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT 711
MX6Q_PAD_ENET_RX_ER__GPIO_1_24 712
MX6Q_PAD_ENET_RX_ER__PHY_TDI 713
MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD 714
MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED 715
MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 716
MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT 717
MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK 718
MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 719
MX6Q_PAD_ENET_CRS_DV__PHY_TDO 720
MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD 721
MX6Q_PAD_ENET_RXD1__MLB_MLBSIG 722
MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 723
MX6Q_PAD_ENET_RXD1__ESAI1_FST 724
MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT 725
MX6Q_PAD_ENET_RXD1__GPIO_1_26 726
MX6Q_PAD_ENET_RXD1__PHY_TCK 727
MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON 728
MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT 729
MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 730
MX6Q_PAD_ENET_RXD0__ESAI1_HCKT 731
MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 732
MX6Q_PAD_ENET_RXD0__GPIO_1_27 733
MX6Q_PAD_ENET_RXD0__PHY_TMS 734
MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV 735
MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED 736
MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 737
MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 738
MX6Q_PAD_ENET_TX_EN__GPIO_1_28 739
MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI 740
MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH 741
MX6Q_PAD_ENET_TXD1__MLB_MLBCLK 742
MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 743
MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 744
MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 745
MX6Q_PAD_ENET_TXD1__GPIO_1_29 746
MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO 747
MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD 748
MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED 749
MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 750
MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 751
MX6Q_PAD_ENET_TXD0__GPIO_1_30 752
MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK 753
MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD 754
MX6Q_PAD_ENET_MDC__MLB_MLBDAT 755
MX6Q_PAD_ENET_MDC__ENET_MDC 756
MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 757
MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 758
MX6Q_PAD_ENET_MDC__GPIO_1_31 759
MX6Q_PAD_ENET_MDC__SATA_PHY_TMS 760
MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON 761
MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 762
MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 763
MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 764
MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 765
MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 766
MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 767
MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 768
MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 769
MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 770
MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 771
MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 772
MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 773
MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 774
MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 775
MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 776
MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 777
MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 778
MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 779
MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 780
MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 781
MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 782
MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 783
MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 784
MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 785
MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 786
MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 787
MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 788
MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 789
MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 790
MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 791
MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 792
MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 793
MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 794
MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 795
MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 796
MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 797
MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 798
MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 799
MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 800
MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 801
MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 802
MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 803
MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 804
MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 805
MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 806
MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 807
MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 808
MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 809
MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 810
MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 811
MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 812
MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 813
MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 814
MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 815
MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 816
MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 817
MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS 818
MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 819
MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 820
MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS 821
MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET 822
MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 823
MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 824
MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 825
MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 826
MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 827
MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 828
MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 829
MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 830
MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 831
MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE 832
MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 833
MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 834
MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 835
MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 836
MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 837
MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 838
MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 839
MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 840
MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 841
MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 842
MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 843
MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 844
MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 845
MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 846
MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 847
MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 848
MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 849
MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 850
MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 851
MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 852
MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 853
MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 854
MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 855
MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 856
MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 857
MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 858
MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 859
MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 860
MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 861
MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 862
MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 863
MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 864
MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 865
MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 866
MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 867
MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 868
MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 869
MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 870
MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 871
MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 872
MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 873
MX6Q_PAD_KEY_COL0__ENET_RDATA_3 874
MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC 875
MX6Q_PAD_KEY_COL0__KPP_COL_0 876
MX6Q_PAD_KEY_COL0__UART4_TXD 877
MX6Q_PAD_KEY_COL0__GPIO_4_6 878
MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT 879
MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST 880
MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 881
MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 882
MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 883
MX6Q_PAD_KEY_ROW0__KPP_ROW_0 884
MX6Q_PAD_KEY_ROW0__UART4_RXD 885
MX6Q_PAD_KEY_ROW0__GPIO_4_7 886
MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT 887
MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 888
MX6Q_PAD_KEY_COL1__ECSPI1_MISO 889
MX6Q_PAD_KEY_COL1__ENET_MDIO 890
MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 891
MX6Q_PAD_KEY_COL1__KPP_COL_1 892
MX6Q_PAD_KEY_COL1__UART5_TXD 893
MX6Q_PAD_KEY_COL1__GPIO_4_8 894
MX6Q_PAD_KEY_COL1__USDHC1_VSELECT 895
MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 896
MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 897
MX6Q_PAD_KEY_ROW1__ENET_COL 898
MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 899
MX6Q_PAD_KEY_ROW1__KPP_ROW_1 900
MX6Q_PAD_KEY_ROW1__UART5_RXD 901
MX6Q_PAD_KEY_ROW1__GPIO_4_9 902
MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT 903
MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 904
MX6Q_PAD_KEY_COL2__ECSPI1_SS1 905
MX6Q_PAD_KEY_COL2__ENET_RDATA_2 906
MX6Q_PAD_KEY_COL2__CAN1_TXCAN 907
MX6Q_PAD_KEY_COL2__KPP_COL_2 908
MX6Q_PAD_KEY_COL2__ENET_MDC 909
MX6Q_PAD_KEY_COL2__GPIO_4_10 910
MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP 911
MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 912
MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 913
MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 914
MX6Q_PAD_KEY_ROW2__CAN1_RXCAN 915
MX6Q_PAD_KEY_ROW2__KPP_ROW_2 916
MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT 917
MX6Q_PAD_KEY_ROW2__GPIO_4_11 918
MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 919
MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 920
MX6Q_PAD_KEY_COL3__ECSPI1_SS3 921
MX6Q_PAD_KEY_COL3__ENET_CRS 922
MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 923
MX6Q_PAD_KEY_COL3__KPP_COL_3 924
MX6Q_PAD_KEY_COL3__I2C2_SCL 925
MX6Q_PAD_KEY_COL3__GPIO_4_12 926
MX6Q_PAD_KEY_COL3__SPDIF_IN1 927
MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 928
MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT 929
MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK 930
MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 931
MX6Q_PAD_KEY_ROW3__KPP_ROW_3 932
MX6Q_PAD_KEY_ROW3__I2C2_SDA 933
MX6Q_PAD_KEY_ROW3__GPIO_4_13 934
MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT 935
MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 936
MX6Q_PAD_KEY_COL4__CAN2_TXCAN 937
MX6Q_PAD_KEY_COL4__IPU1_SISG_4 938
MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC 939
MX6Q_PAD_KEY_COL4__KPP_COL_4 940
MX6Q_PAD_KEY_COL4__UART5_RTS 941
MX6Q_PAD_KEY_COL4__GPIO_4_14 942
MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 943
MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944
MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945
MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946
MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947
MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948
MX6Q_PAD_KEY_ROW4__UART5_CTS 949
MX6Q_PAD_KEY_ROW4__GPIO_4_15 950
MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951
MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952
MX6Q_PAD_GPIO_0__CCM_CLKO 953
MX6Q_PAD_GPIO_0__KPP_COL_5 954
MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955
MX6Q_PAD_GPIO_0__EPIT1_EPITO 956
MX6Q_PAD_GPIO_0__GPIO_1_0 957
MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958
MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959
MX6Q_PAD_GPIO_1__ESAI1_SCKR 960
MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961
MX6Q_PAD_GPIO_1__KPP_ROW_5 962
MX6Q_PAD_GPIO_1__PWM2_PWMO 963
MX6Q_PAD_GPIO_1__GPIO_1_1 964
MX6Q_PAD_GPIO_1__USDHC1_CD 965
MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966
MX6Q_PAD_GPIO_9__ESAI1_FSR 967
MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968
MX6Q_PAD_GPIO_9__KPP_COL_6 969
MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970
MX6Q_PAD_GPIO_9__PWM1_PWMO 971
MX6Q_PAD_GPIO_9__GPIO_1_9 972
MX6Q_PAD_GPIO_9__USDHC1_WP 973
MX6Q_PAD_GPIO_9__SRC_EARLY_RST 974
MX6Q_PAD_GPIO_3__ESAI1_HCKR 975
MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 976
MX6Q_PAD_GPIO_3__I2C3_SCL 977
MX6Q_PAD_GPIO_3__ANATOP_24M_OUT 978
MX6Q_PAD_GPIO_3__CCM_CLKO2 979
MX6Q_PAD_GPIO_3__GPIO_1_3 980
MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC 981
MX6Q_PAD_GPIO_3__MLB_MLBCLK 982
MX6Q_PAD_GPIO_6__ESAI1_SCKT 983
MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 984
MX6Q_PAD_GPIO_6__I2C3_SDA 985
MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 986
MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB 987
MX6Q_PAD_GPIO_6__GPIO_1_6 988
MX6Q_PAD_GPIO_6__USDHC2_LCTL 989
MX6Q_PAD_GPIO_6__MLB_MLBSIG 990
MX6Q_PAD_GPIO_2__ESAI1_FST 991
MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 992
MX6Q_PAD_GPIO_2__KPP_ROW_6 993
MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 994
MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 995
MX6Q_PAD_GPIO_2__GPIO_1_2 996
MX6Q_PAD_GPIO_2__USDHC2_WP 997
MX6Q_PAD_GPIO_2__MLB_MLBDAT 998
MX6Q_PAD_GPIO_4__ESAI1_HCKT 999
MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 1000
MX6Q_PAD_GPIO_4__KPP_COL_7 1001
MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 1002
MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1003
MX6Q_PAD_GPIO_4__GPIO_1_4 1004
MX6Q_PAD_GPIO_4__USDHC2_CD 1005
MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA 1006
MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 1007
MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 1008
MX6Q_PAD_GPIO_5__KPP_ROW_7 1009
MX6Q_PAD_GPIO_5__CCM_CLKO 1010
MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1011
MX6Q_PAD_GPIO_5__GPIO_1_5 1012
MX6Q_PAD_GPIO_5__I2C3_SCL 1013
MX6Q_PAD_GPIO_5__CHEETAH_EVENTI 1014
MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 1015
MX6Q_PAD_GPIO_7__ECSPI5_RDY 1016
MX6Q_PAD_GPIO_7__EPIT1_EPITO 1017
MX6Q_PAD_GPIO_7__CAN1_TXCAN 1018
MX6Q_PAD_GPIO_7__UART2_TXD 1019
MX6Q_PAD_GPIO_7__GPIO_1_7 1020
MX6Q_PAD_GPIO_7__SPDIF_PLOCK 1021
MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE 1022
MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 1023
MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT 1024
MX6Q_PAD_GPIO_8__EPIT2_EPITO 1025
MX6Q_PAD_GPIO_8__CAN1_RXCAN 1026
MX6Q_PAD_GPIO_8__UART2_RXD 1027
MX6Q_PAD_GPIO_8__GPIO_1_8 1028
MX6Q_PAD_GPIO_8__SPDIF_SRCLK 1029
MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK 1030
MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 1031
MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 1032
MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT 1033
MX6Q_PAD_GPIO_16__USDHC1_LCTL 1034
MX6Q_PAD_GPIO_16__SPDIF_IN1 1035
MX6Q_PAD_GPIO_16__GPIO_7_11 1036
MX6Q_PAD_GPIO_16__I2C3_SDA 1037
MX6Q_PAD_GPIO_16__SJC_DE_B 1038
MX6Q_PAD_GPIO_17__ESAI1_TX0 1039
MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 1040
MX6Q_PAD_GPIO_17__CCM_PMIC_RDY 1041
MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 1042
MX6Q_PAD_GPIO_17__SPDIF_OUT1 1043
MX6Q_PAD_GPIO_17__GPIO_7_12 1044
MX6Q_PAD_GPIO_17__SJC_JTAG_ACT 1045
MX6Q_PAD_GPIO_18__ESAI1_TX1 1046
MX6Q_PAD_GPIO_18__ENET_RX_CLK 1047
MX6Q_PAD_GPIO_18__USDHC3_VSELECT 1048
MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 1049
MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK 1050
MX6Q_PAD_GPIO_18__GPIO_7_13 1051
MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 1052
MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST 1053
MX6Q_PAD_GPIO_19__KPP_COL_5 1054
MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 1055
MX6Q_PAD_GPIO_19__SPDIF_OUT1 1056
MX6Q_PAD_GPIO_19__CCM_CLKO 1057
MX6Q_PAD_GPIO_19__ECSPI1_RDY 1058
MX6Q_PAD_GPIO_19__GPIO_4_5 1059
MX6Q_PAD_GPIO_19__ENET_TX_ER 1060
MX6Q_PAD_GPIO_19__SRC_INT_BOOT 1061
MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 1062
MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 1063
MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 1064
MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 1065
MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 1066
MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO 1067
MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 1068
MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 1069
MX6Q_PAD_CSI0_MCLK__CCM_CLKO 1070
MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 1071
MX6Q_PAD_CSI0_MCLK__GPIO_5_19 1072
MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 1073
MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL 1074
MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN 1075
MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 1076
MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 1077
MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 1078
MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 1079
MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 1080
MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK 1081
MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 1082
MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 1083
MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 1084
MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 1085
MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 1086
MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 1087
MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 1088
MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 1089
MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 1090
MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 1091
MX6Q_PAD_CSI0_DAT4__KPP_COL_5 1092
MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 1093
MX6Q_PAD_CSI0_DAT4__GPIO_5_22 1094
MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 1095
MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 1096
MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 1097
MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 1098
MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 1099
MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 1100
MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 1101
MX6Q_PAD_CSI0_DAT5__GPIO_5_23 1102
MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 1103
MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 1104
MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 1105
MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 1106
MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 1107
MX6Q_PAD_CSI0_DAT6__KPP_COL_6 1108
MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 1109
MX6Q_PAD_CSI0_DAT6__GPIO_5_24 1110
MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 1111
MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 1112
MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 1113
MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 1114
MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 1115
MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 1116
MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 1117
MX6Q_PAD_CSI0_DAT7__GPIO_5_25 1118
MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 1119
MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 1120
MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 1121
MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 1122
MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 1123
MX6Q_PAD_CSI0_DAT8__KPP_COL_7 1124
MX6Q_PAD_CSI0_DAT8__I2C1_SDA 1125
MX6Q_PAD_CSI0_DAT8__GPIO_5_26 1126
MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 1127
MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 1128
MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 1129
MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 1130
MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 1131
MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 1132
MX6Q_PAD_CSI0_DAT9__I2C1_SCL 1133
MX6Q_PAD_CSI0_DAT9__GPIO_5_27 1134
MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 1135
MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 1136
MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 1137
MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 1138
MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 1139
MX6Q_PAD_CSI0_DAT10__UART1_TXD 1140
MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 1141
MX6Q_PAD_CSI0_DAT10__GPIO_5_28 1142
MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 1143
MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 1144
MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 1145
MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 1146
MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 1147
MX6Q_PAD_CSI0_DAT11__UART1_RXD 1148
MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 1149
MX6Q_PAD_CSI0_DAT11__GPIO_5_29 1150
MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 1151
MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 1152
MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 1153
MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 1154
MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 1155
MX6Q_PAD_CSI0_DAT12__UART4_TXD 1156
MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 1157
MX6Q_PAD_CSI0_DAT12__GPIO_5_30 1158
MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 1159
MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 1160
MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 1161
MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 1162
MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 1163
MX6Q_PAD_CSI0_DAT13__UART4_RXD 1164
MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 1165
MX6Q_PAD_CSI0_DAT13__GPIO_5_31 1166
MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 1167
MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 1168
MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 1169
MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 1170
MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 1171
MX6Q_PAD_CSI0_DAT14__UART5_TXD 1172
MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 1173
MX6Q_PAD_CSI0_DAT14__GPIO_6_0 1174
MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 1175
MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 1176
MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 1177
MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 1178
MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 1179
MX6Q_PAD_CSI0_DAT15__UART5_RXD 1180
MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 1181
MX6Q_PAD_CSI0_DAT15__GPIO_6_1 1182
MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 1183
MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 1184
MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 1185
MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 1186
MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 1187
MX6Q_PAD_CSI0_DAT16__UART4_RTS 1188
MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 1189
MX6Q_PAD_CSI0_DAT16__GPIO_6_2 1190
MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 1191
MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 1192
MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 1193
MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 1194
MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 1195
MX6Q_PAD_CSI0_DAT17__UART4_CTS 1196
MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 1197
MX6Q_PAD_CSI0_DAT17__GPIO_6_3 1198
MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 1199
MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 1200
MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 1201
MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 1202
MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 1203
MX6Q_PAD_CSI0_DAT18__UART5_RTS 1204
MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 1205
MX6Q_PAD_CSI0_DAT18__GPIO_6_4 1206
MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 1207
MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 1208
MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 1209
MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 1210
MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 1211
MX6Q_PAD_CSI0_DAT19__UART5_CTS 1212
MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 1213
MX6Q_PAD_CSI0_DAT19__GPIO_6_5 1214
MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 1215
MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 1216
MX6Q_PAD_JTAG_TMS__SJC_TMS 1217
MX6Q_PAD_JTAG_MOD__SJC_MOD 1218
MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB 1219
MX6Q_PAD_JTAG_TDI__SJC_TDI 1220
MX6Q_PAD_JTAG_TCK__SJC_TCK 1221
MX6Q_PAD_JTAG_TDO__SJC_TDO 1222
MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 1223
MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 1224
MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 1225
MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 1226
MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 1227
MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 1228
MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 1229
MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 1230
MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 1231
MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 1232
MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 1233
MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM 1234
MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ 1235
MX6Q_PAD_POR_B__SRC_POR_B 1236
MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 1237
MX6Q_PAD_RESET_IN_B__SRC_RESET_B 1238
MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 1239
MX6Q_PAD_TEST_MODE__TCU_TEST_MODE 1240
MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 1241
MX6Q_PAD_SD3_DAT7__UART1_TXD 1242
MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 1243
MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 1244
MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 1245
MX6Q_PAD_SD3_DAT7__GPIO_6_17 1246
MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 1247
MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV 1248
MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 1249
MX6Q_PAD_SD3_DAT6__UART1_RXD 1250
MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 1251
MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 1252
MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 1253
MX6Q_PAD_SD3_DAT6__GPIO_6_18 1254
MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 1255
MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 1256
MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 1257
MX6Q_PAD_SD3_DAT5__UART2_TXD 1258
MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 1259
MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 1260
MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 1261
MX6Q_PAD_SD3_DAT5__GPIO_7_0 1262
MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 1263
MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 1264
MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 1265
MX6Q_PAD_SD3_DAT4__UART2_RXD 1266
MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 1267
MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 1268
MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 1269
MX6Q_PAD_SD3_DAT4__GPIO_7_1 1270
MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 1271
MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 1272
MX6Q_PAD_SD3_CMD__USDHC3_CMD 1273
MX6Q_PAD_SD3_CMD__UART2_CTS 1274
MX6Q_PAD_SD3_CMD__CAN1_TXCAN 1275
MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 1276
MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 1277
MX6Q_PAD_SD3_CMD__GPIO_7_2 1278
MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 1279
MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 1280
MX6Q_PAD_SD3_CLK__USDHC3_CLK 1281
MX6Q_PAD_SD3_CLK__UART2_RTS 1282
MX6Q_PAD_SD3_CLK__CAN1_RXCAN 1283
MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 1284
MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 1285
MX6Q_PAD_SD3_CLK__GPIO_7_3 1286
MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 1287
MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 1288
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 1289
MX6Q_PAD_SD3_DAT0__UART1_CTS 1290
MX6Q_PAD_SD3_DAT0__CAN2_TXCAN 1291
MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 1292
MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 1293
MX6Q_PAD_SD3_DAT0__GPIO_7_4 1294
MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 1295
MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 1296
MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 1297
MX6Q_PAD_SD3_DAT1__UART1_RTS 1298
MX6Q_PAD_SD3_DAT1__CAN2_RXCAN 1299
MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 1300
MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 1301
MX6Q_PAD_SD3_DAT1__GPIO_7_5 1302
MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 1303
MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 1304
MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 1305
MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 1306
MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 1307
MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 1308
MX6Q_PAD_SD3_DAT2__GPIO_7_6 1309
MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 1310
MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 1311
MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 1312
MX6Q_PAD_SD3_DAT3__UART3_CTS 1313
MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 1314
MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 1315
MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 1316
MX6Q_PAD_SD3_DAT3__GPIO_7_7 1317
MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 1318
MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 1319
MX6Q_PAD_SD3_RST__USDHC3_RST 1320
MX6Q_PAD_SD3_RST__UART3_RTS 1321
MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 1322
MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 1323
MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 1324
MX6Q_PAD_SD3_RST__GPIO_7_8 1325
MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 1326
MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 1327
MX6Q_PAD_NANDF_CLE__RAWNAND_CLE 1328
MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 1329
MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 1330
MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 1331
MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 1332
MX6Q_PAD_NANDF_CLE__GPIO_6_7 1333
MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 1334
MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 1335
MX6Q_PAD_NANDF_ALE__RAWNAND_ALE 1336
MX6Q_PAD_NANDF_ALE__USDHC4_RST 1337
MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 1338
MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 1339
MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 1340
MX6Q_PAD_NANDF_ALE__GPIO_6_8 1341
MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 1342
MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 1343
MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN 1344
MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 1345
MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 1346
MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 1347
MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 1348
MX6Q_PAD_NANDF_WP_B__GPIO_6_9 1349
MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 1350
MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 1351
MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 1352
MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 1353
MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 1354
MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 1355
MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 1356
MX6Q_PAD_NANDF_RB0__GPIO_6_10 1357
MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 1358
MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 1359
MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N 1360
MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 1361
MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 1362
MX6Q_PAD_NANDF_CS0__GPIO_6_11 1363
MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 1364
MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N 1365
MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT 1366
MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT 1367
MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 1368
MX6Q_PAD_NANDF_CS1__GPIO_6_14 1369
MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT 1370
MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N 1371
MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 1372
MX6Q_PAD_NANDF_CS2__ESAI1_TX0 1373
MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE 1374
MX6Q_PAD_NANDF_CS2__CCM_CLKO2 1375
MX6Q_PAD_NANDF_CS2__GPIO_6_15 1376
MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 1377
MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N 1378
MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 1379
MX6Q_PAD_NANDF_CS3__ESAI1_TX1 1380
MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 1381
MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 1382
MX6Q_PAD_NANDF_CS3__GPIO_6_16 1383
MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 1384
MX6Q_PAD_NANDF_CS3__TPSMP_CLK 1385
MX6Q_PAD_SD4_CMD__USDHC4_CMD 1386
MX6Q_PAD_SD4_CMD__RAWNAND_RDN 1387
MX6Q_PAD_SD4_CMD__UART3_TXD 1388
MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 1389
MX6Q_PAD_SD4_CMD__GPIO_7_9 1390
MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR 1391
MX6Q_PAD_SD4_CLK__USDHC4_CLK 1392
MX6Q_PAD_SD4_CLK__RAWNAND_WRN 1393
MX6Q_PAD_SD4_CLK__UART3_RXD 1394
MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 1395
MX6Q_PAD_SD4_CLK__GPIO_7_10 1396
MX6Q_PAD_NANDF_D0__RAWNAND_D0 1397
MX6Q_PAD_NANDF_D0__USDHC1_DAT4 1398
MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 1399
MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 1400
MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 1401
MX6Q_PAD_NANDF_D0__GPIO_2_0 1402
MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 1403
MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 1404
MX6Q_PAD_NANDF_D1__RAWNAND_D1 1405
MX6Q_PAD_NANDF_D1__USDHC1_DAT5 1406
MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 1407
MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 1408
MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 1409
MX6Q_PAD_NANDF_D1__GPIO_2_1 1410
MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 1411
MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 1412
MX6Q_PAD_NANDF_D2__RAWNAND_D2 1413
MX6Q_PAD_NANDF_D2__USDHC1_DAT6 1414
MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 1415
MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 1416
MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 1417
MX6Q_PAD_NANDF_D2__GPIO_2_2 1418
MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 1419
MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 1420
MX6Q_PAD_NANDF_D3__RAWNAND_D3 1421
MX6Q_PAD_NANDF_D3__USDHC1_DAT7 1422
MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 1423
MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 1424
MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 1425
MX6Q_PAD_NANDF_D3__GPIO_2_3 1426
MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 1427
MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 1428
MX6Q_PAD_NANDF_D4__RAWNAND_D4 1429
MX6Q_PAD_NANDF_D4__USDHC2_DAT4 1430
MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 1431
MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 1432
MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 1433
MX6Q_PAD_NANDF_D4__GPIO_2_4 1434
MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 1435
MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 1436
MX6Q_PAD_NANDF_D5__RAWNAND_D5 1437
MX6Q_PAD_NANDF_D5__USDHC2_DAT5 1438
MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 1439
MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 1440
MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 1441
MX6Q_PAD_NANDF_D5__GPIO_2_5 1442
MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 1443
MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 1444
MX6Q_PAD_NANDF_D6__RAWNAND_D6 1445
MX6Q_PAD_NANDF_D6__USDHC2_DAT6 1446
MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 1447
MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 1448
MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 1449
MX6Q_PAD_NANDF_D6__GPIO_2_6 1450
MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 1451
MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 1452
MX6Q_PAD_NANDF_D7__RAWNAND_D7 1453
MX6Q_PAD_NANDF_D7__USDHC2_DAT7 1454
MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 1455
MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 1456
MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 1457
MX6Q_PAD_NANDF_D7__GPIO_2_7 1458
MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 1459
MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 1460
MX6Q_PAD_SD4_DAT0__RAWNAND_D8 1461
MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 1462
MX6Q_PAD_SD4_DAT0__RAWNAND_DQS 1463
MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 1464
MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 1465
MX6Q_PAD_SD4_DAT0__GPIO_2_8 1466
MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 1467
MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 1468
MX6Q_PAD_SD4_DAT1__RAWNAND_D9 1469
MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 1470
MX6Q_PAD_SD4_DAT1__PWM3_PWMO 1471
MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 1472
MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 1473
MX6Q_PAD_SD4_DAT1__GPIO_2_9 1474
MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 1475
MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 1476
MX6Q_PAD_SD4_DAT2__RAWNAND_D10 1477
MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 1478
MX6Q_PAD_SD4_DAT2__PWM4_PWMO 1479
MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 1480
MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 1481
MX6Q_PAD_SD4_DAT2__GPIO_2_10 1482
MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 1483
MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 1484
MX6Q_PAD_SD4_DAT3__RAWNAND_D11 1485
MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 1486
MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 1487
MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 1488
MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489
MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490
MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491
MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492
MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493
MX6Q_PAD_SD4_DAT4__UART2_RXD 1494
MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495
MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496
MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497
MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498
MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499
MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500
MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501
MX6Q_PAD_SD4_DAT5__UART2_RTS 1502
MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503
MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504
MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505
MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506
MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507
MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508
MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509
MX6Q_PAD_SD4_DAT6__UART2_CTS 1510
MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511
MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512
MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513
MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514
MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515
MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516
MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517
MX6Q_PAD_SD4_DAT7__UART2_TXD 1518
MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519
MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520
MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521
MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522
MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523
MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524
MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525
MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526
MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527
MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528
MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529
MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530
MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531
MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532
MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533
MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534
MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535
MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536
MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537
MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538
MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539
MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540
MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541
MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542
MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543
MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544
MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545
MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546
MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547
MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548
MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549
MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550
MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551
MX6Q_PAD_SD1_CMD__GPIO_1_18 1552
MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553
MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554
MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555
MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556
MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557
MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558
MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559
MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560
MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561
MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562
MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563
MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564
MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565
MX6Q_PAD_SD1_CLK__GPIO_1_20 1566
MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567
MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568
MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569
MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570
MX6Q_PAD_SD2_CLK__KPP_COL_5 1571
MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572
MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573
MX6Q_PAD_SD2_CLK__GPIO_1_10 1574
MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575
MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576
MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577
MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578
MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579
MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580
MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581
MX6Q_PAD_SD2_CMD__GPIO_1_11 1582
MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583
MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584
MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585
MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586
MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587
MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588
MX6Q_PAD_SD2_DAT3__SJC_DONE 1589
MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590
MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID 1591
MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID 1592
Refer to imx6q-pinfunc.h in device tree source folder for all available
imx6q PIN_FUNC_ID.
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX35_PINFUNC_H
#define __DTS_IMX35_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
#define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
#define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
#define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
#define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
#define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
#define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
#define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
#define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
#define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
#define MX35_PAD_COMPARE__GPIO1_5 0x008 0x32c 0x854 0x5 0x0
#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x008 0x32c 0x000 0x7 0x0
#define MX35_PAD_WDOG_RST__WDOG_WDOG_B 0x00c 0x330 0x000 0x0 0x0
#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE 0x00c 0x330 0x000 0x3 0x0
#define MX35_PAD_WDOG_RST__GPIO1_6 0x00c 0x330 0x858 0x5 0x0
#define MX35_PAD_GPIO1_0__GPIO1_0 0x010 0x334 0x82c 0x0 0x0
#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY 0x010 0x334 0x7d4 0x1 0x0
#define MX35_PAD_GPIO1_0__OWIRE_LINE 0x010 0x334 0x990 0x2 0x0
#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 0x010 0x334 0x000 0x7 0x0
#define MX35_PAD_GPIO1_1__GPIO1_1 0x014 0x338 0x838 0x0 0x0
#define MX35_PAD_GPIO1_1__PWM_PWMO 0x014 0x338 0x000 0x2 0x0
#define MX35_PAD_GPIO1_1__CSPI1_SS2 0x014 0x338 0x7d8 0x3 0x0
#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT 0x014 0x338 0x000 0x6 0x0
#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 0x014 0x338 0x000 0x7 0x0
#define MX35_PAD_GPIO2_0__GPIO2_0 0x018 0x33c 0x868 0x0 0x0
#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK 0x018 0x33c 0x000 0x1 0x0
#define MX35_PAD_GPIO3_0__GPIO3_0 0x01c 0x340 0x8e8 0x0 0x0
#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK 0x01c 0x340 0x000 0x1 0x0
#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B 0x000 0x344 0x000 0x0 0x0
#define MX35_PAD_POR_B__CCM_POR_B 0x000 0x348 0x000 0x0 0x0
#define MX35_PAD_CLKO__CCM_CLKO 0x020 0x34c 0x000 0x0 0x0
#define MX35_PAD_CLKO__GPIO1_8 0x020 0x34c 0x860 0x5 0x0
#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 0x000 0x350 0x000 0x0 0x0
#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 0x000 0x354 0x000 0x0 0x0
#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 0x000 0x358 0x000 0x0 0x0
#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 0x000 0x35c 0x000 0x0 0x0
#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 0x000 0x360 0x000 0x0 0x0
#define MX35_PAD_VSTBY__CCM_VSTBY 0x024 0x364 0x000 0x0 0x0
#define MX35_PAD_VSTBY__GPIO1_7 0x024 0x364 0x85c 0x5 0x0
#define MX35_PAD_A0__EMI_EIM_DA_L_0 0x028 0x368 0x000 0x0 0x0
#define MX35_PAD_A1__EMI_EIM_DA_L_1 0x02c 0x36c 0x000 0x0 0x0
#define MX35_PAD_A2__EMI_EIM_DA_L_2 0x030 0x370 0x000 0x0 0x0
#define MX35_PAD_A3__EMI_EIM_DA_L_3 0x034 0x374 0x000 0x0 0x0
#define MX35_PAD_A4__EMI_EIM_DA_L_4 0x038 0x378 0x000 0x0 0x0
#define MX35_PAD_A5__EMI_EIM_DA_L_5 0x03c 0x37c 0x000 0x0 0x0
#define MX35_PAD_A6__EMI_EIM_DA_L_6 0x040 0x380 0x000 0x0 0x0
#define MX35_PAD_A7__EMI_EIM_DA_L_7 0x044 0x384 0x000 0x0 0x0
#define MX35_PAD_A8__EMI_EIM_DA_H_8 0x048 0x388 0x000 0x0 0x0
#define MX35_PAD_A9__EMI_EIM_DA_H_9 0x04c 0x38c 0x000 0x0 0x0
#define MX35_PAD_A10__EMI_EIM_DA_H_10 0x050 0x390 0x000 0x0 0x0
#define MX35_PAD_MA10__EMI_MA10 0x054 0x394 0x000 0x0 0x0
#define MX35_PAD_A11__EMI_EIM_DA_H_11 0x058 0x398 0x000 0x0 0x0
#define MX35_PAD_A12__EMI_EIM_DA_H_12 0x05c 0x39c 0x000 0x0 0x0
#define MX35_PAD_A13__EMI_EIM_DA_H_13 0x060 0x3a0 0x000 0x0 0x0
#define MX35_PAD_A14__EMI_EIM_DA_H2_14 0x064 0x3a4 0x000 0x0 0x0
#define MX35_PAD_A15__EMI_EIM_DA_H2_15 0x068 0x3a8 0x000 0x0 0x0
#define MX35_PAD_A16__EMI_EIM_A_16 0x06c 0x3ac 0x000 0x0 0x0
#define MX35_PAD_A17__EMI_EIM_A_17 0x070 0x3b0 0x000 0x0 0x0
#define MX35_PAD_A18__EMI_EIM_A_18 0x074 0x3b4 0x000 0x0 0x0
#define MX35_PAD_A19__EMI_EIM_A_19 0x078 0x3b8 0x000 0x0 0x0
#define MX35_PAD_A20__EMI_EIM_A_20 0x07c 0x3bc 0x000 0x0 0x0
#define MX35_PAD_A21__EMI_EIM_A_21 0x080 0x3c0 0x000 0x0 0x0
#define MX35_PAD_A22__EMI_EIM_A_22 0x084 0x3c4 0x000 0x0 0x0
#define MX35_PAD_A23__EMI_EIM_A_23 0x088 0x3c8 0x000 0x0 0x0
#define MX35_PAD_A24__EMI_EIM_A_24 0x08c 0x3cc 0x000 0x0 0x0
#define MX35_PAD_A25__EMI_EIM_A_25 0x090 0x3d0 0x000 0x0 0x0
#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 0x000 0x3d4 0x000 0x0 0x0
#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 0x000 0x3d8 0x000 0x0 0x0
#define MX35_PAD_SD0__EMI_DRAM_D_0 0x000 0x3dc 0x000 0x0 0x0
#define MX35_PAD_SD1__EMI_DRAM_D_1 0x000 0x3e0 0x000 0x0 0x0
#define MX35_PAD_SD2__EMI_DRAM_D_2 0x000 0x3e4 0x000 0x0 0x0
#define MX35_PAD_SD3__EMI_DRAM_D_3 0x000 0x3e8 0x000 0x0 0x0
#define MX35_PAD_SD4__EMI_DRAM_D_4 0x000 0x3ec 0x000 0x0 0x0
#define MX35_PAD_SD5__EMI_DRAM_D_5 0x000 0x3f0 0x000 0x0 0x0
#define MX35_PAD_SD6__EMI_DRAM_D_6 0x000 0x3f4 0x000 0x0 0x0
#define MX35_PAD_SD7__EMI_DRAM_D_7 0x000 0x3f8 0x000 0x0 0x0
#define MX35_PAD_SD8__EMI_DRAM_D_8 0x000 0x3fc 0x000 0x0 0x0
#define MX35_PAD_SD9__EMI_DRAM_D_9 0x000 0x400 0x000 0x0 0x0
#define MX35_PAD_SD10__EMI_DRAM_D_10 0x000 0x404 0x000 0x0 0x0
#define MX35_PAD_SD11__EMI_DRAM_D_11 0x000 0x408 0x000 0x0 0x0
#define MX35_PAD_SD12__EMI_DRAM_D_12 0x000 0x40c 0x000 0x0 0x0
#define MX35_PAD_SD13__EMI_DRAM_D_13 0x000 0x410 0x000 0x0 0x0
#define MX35_PAD_SD14__EMI_DRAM_D_14 0x000 0x414 0x000 0x0 0x0
#define MX35_PAD_SD15__EMI_DRAM_D_15 0x000 0x418 0x000 0x0 0x0
#define MX35_PAD_SD16__EMI_DRAM_D_16 0x000 0x41c 0x000 0x0 0x0
#define MX35_PAD_SD17__EMI_DRAM_D_17 0x000 0x420 0x000 0x0 0x0
#define MX35_PAD_SD18__EMI_DRAM_D_18 0x000 0x424 0x000 0x0 0x0
#define MX35_PAD_SD19__EMI_DRAM_D_19 0x000 0x428 0x000 0x0 0x0
#define MX35_PAD_SD20__EMI_DRAM_D_20 0x000 0x42c 0x000 0x0 0x0
#define MX35_PAD_SD21__EMI_DRAM_D_21 0x000 0x430 0x000 0x0 0x0
#define MX35_PAD_SD22__EMI_DRAM_D_22 0x000 0x434 0x000 0x0 0x0
#define MX35_PAD_SD23__EMI_DRAM_D_23 0x000 0x438 0x000 0x0 0x0
#define MX35_PAD_SD24__EMI_DRAM_D_24 0x000 0x43c 0x000 0x0 0x0
#define MX35_PAD_SD25__EMI_DRAM_D_25 0x000 0x440 0x000 0x0 0x0
#define MX35_PAD_SD26__EMI_DRAM_D_26 0x000 0x444 0x000 0x0 0x0
#define MX35_PAD_SD27__EMI_DRAM_D_27 0x000 0x448 0x000 0x0 0x0
#define MX35_PAD_SD28__EMI_DRAM_D_28 0x000 0x44c 0x000 0x0 0x0
#define MX35_PAD_SD29__EMI_DRAM_D_29 0x000 0x450 0x000 0x0 0x0
#define MX35_PAD_SD30__EMI_DRAM_D_30 0x000 0x454 0x000 0x0 0x0
#define MX35_PAD_SD31__EMI_DRAM_D_31 0x000 0x458 0x000 0x0 0x0
#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 0x000 0x45c 0x000 0x0 0x0
#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 0x000 0x460 0x000 0x0 0x0
#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 0x000 0x464 0x000 0x0 0x0
#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 0x000 0x468 0x000 0x0 0x0
#define MX35_PAD_EB0__EMI_EIM_EB0_B 0x094 0x46c 0x000 0x0 0x0
#define MX35_PAD_EB1__EMI_EIM_EB1_B 0x098 0x470 0x000 0x0 0x0
#define MX35_PAD_OE__EMI_EIM_OE 0x09c 0x474 0x000 0x0 0x0
#define MX35_PAD_CS0__EMI_EIM_CS0 0x0a0 0x478 0x000 0x0 0x0
#define MX35_PAD_CS1__EMI_EIM_CS1 0x0a4 0x47c 0x000 0x0 0x0
#define MX35_PAD_CS1__EMI_NANDF_CE3 0x0a4 0x47c 0x000 0x3 0x0
#define MX35_PAD_CS2__EMI_EIM_CS2 0x0a8 0x480 0x000 0x0 0x0
#define MX35_PAD_CS3__EMI_EIM_CS3 0x0ac 0x484 0x000 0x0 0x0
#define MX35_PAD_CS4__EMI_EIM_CS4 0x0b0 0x488 0x000 0x0 0x0
#define MX35_PAD_CS4__EMI_DTACK_B 0x0b0 0x488 0x800 0x1 0x0
#define MX35_PAD_CS4__EMI_NANDF_CE1 0x0b0 0x488 0x000 0x3 0x0
#define MX35_PAD_CS4__GPIO1_20 0x0b0 0x488 0x83c 0x5 0x0
#define MX35_PAD_CS5__EMI_EIM_CS5 0x0b4 0x48c 0x000 0x0 0x0
#define MX35_PAD_CS5__CSPI2_SS2 0x0b4 0x48c 0x7f8 0x1 0x0
#define MX35_PAD_CS5__CSPI1_SS2 0x0b4 0x48c 0x7d8 0x2 0x1
#define MX35_PAD_CS5__EMI_NANDF_CE2 0x0b4 0x48c 0x000 0x3 0x0
#define MX35_PAD_CS5__GPIO1_21 0x0b4 0x48c 0x840 0x5 0x0
#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 0x0b8 0x490 0x000 0x0 0x0
#define MX35_PAD_NF_CE0__GPIO1_22 0x0b8 0x490 0x844 0x5 0x0
#define MX35_PAD_ECB__EMI_EIM_ECB 0x000 0x494 0x000 0x0 0x0
#define MX35_PAD_LBA__EMI_EIM_LBA 0x0bc 0x498 0x000 0x0 0x0
#define MX35_PAD_BCLK__EMI_EIM_BCLK 0x0c0 0x49c 0x000 0x0 0x0
#define MX35_PAD_RW__EMI_EIM_RW 0x0c4 0x4a0 0x000 0x0 0x0
#define MX35_PAD_RAS__EMI_DRAM_RAS 0x000 0x4a4 0x000 0x0 0x0
#define MX35_PAD_CAS__EMI_DRAM_CAS 0x000 0x4a8 0x000 0x0 0x0
#define MX35_PAD_SDWE__EMI_DRAM_SDWE 0x000 0x4ac 0x000 0x0 0x0
#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 0x000 0x4b0 0x000 0x0 0x0
#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 0x000 0x4b4 0x000 0x0 0x0
#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK 0x000 0x4b8 0x000 0x0 0x0
#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 0x000 0x4bc 0x000 0x0 0x0
#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 0x000 0x4c0 0x000 0x0 0x0
#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 0x000 0x4c4 0x000 0x0 0x0
#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 0x000 0x4c8 0x000 0x0 0x0
#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B 0x0c8 0x4cc 0x000 0x0 0x0
#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 0x0c8 0x4cc 0x9d8 0x1 0x0
#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC 0x0c8 0x4cc 0x924 0x2 0x0
#define MX35_PAD_NFWE_B__GPIO2_18 0x0c8 0x4cc 0x88c 0x5 0x0
#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 0x0c8 0x4cc 0x000 0x7 0x0
#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B 0x0cc 0x4d0 0x000 0x0 0x0
#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR 0x0cc 0x4d0 0x9ec 0x1 0x0
#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK 0x0cc 0x4d0 0x000 0x2 0x0
#define MX35_PAD_NFRE_B__GPIO2_19 0x0cc 0x4d0 0x890 0x5 0x0
#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 0x0cc 0x4d0 0x000 0x7 0x0
#define MX35_PAD_NFALE__EMI_NANDF_ALE 0x0d0 0x4d4 0x000 0x0 0x0
#define MX35_PAD_NFALE__USB_TOP_USBH2_STP 0x0d0 0x4d4 0x000 0x1 0x0
#define MX35_PAD_NFALE__IPU_DISPB_CS0 0x0d0 0x4d4 0x000 0x2 0x0
#define MX35_PAD_NFALE__GPIO2_20 0x0d0 0x4d4 0x898 0x5 0x0
#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 0x0d0 0x4d4 0x000 0x7 0x0
#define MX35_PAD_NFCLE__EMI_NANDF_CLE 0x0d4 0x4d8 0x000 0x0 0x0
#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT 0x0d4 0x4d8 0x9f0 0x1 0x0
#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS 0x0d4 0x4d8 0x000 0x2 0x0
#define MX35_PAD_NFCLE__GPIO2_21 0x0d4 0x4d8 0x89c 0x5 0x0
#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 0x0d4 0x4d8 0x000 0x7 0x0
#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B 0x0d8 0x4dc 0x000 0x0 0x0
#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 0x0d8 0x4dc 0x9e8 0x1 0x0
#define MX35_PAD_NFWP_B__IPU_DISPB_WR 0x0d8 0x4dc 0x000 0x2 0x0
#define MX35_PAD_NFWP_B__GPIO2_22 0x0d8 0x4dc 0x8a0 0x5 0x0
#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL 0x0d8 0x4dc 0x000 0x7 0x0
#define MX35_PAD_NFRB__EMI_NANDF_RB 0x0dc 0x4e0 0x000 0x0 0x0
#define MX35_PAD_NFRB__IPU_DISPB_RD 0x0dc 0x4e0 0x000 0x2 0x0
#define MX35_PAD_NFRB__GPIO2_23 0x0dc 0x4e0 0x8a4 0x5 0x0
#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK 0x0dc 0x4e0 0x000 0x7 0x0
#define MX35_PAD_D15__EMI_EIM_D_15 0x000 0x4e4 0x000 0x0 0x0
#define MX35_PAD_D14__EMI_EIM_D_14 0x000 0x4e8 0x000 0x0 0x0
#define MX35_PAD_D13__EMI_EIM_D_13 0x000 0x4ec 0x000 0x0 0x0
#define MX35_PAD_D12__EMI_EIM_D_12 0x000 0x4f0 0x000 0x0 0x0
#define MX35_PAD_D11__EMI_EIM_D_11 0x000 0x4f4 0x000 0x0 0x0
#define MX35_PAD_D10__EMI_EIM_D_10 0x000 0x4f8 0x000 0x0 0x0
#define MX35_PAD_D9__EMI_EIM_D_9 0x000 0x4fc 0x000 0x0 0x0
#define MX35_PAD_D8__EMI_EIM_D_8 0x000 0x500 0x000 0x0 0x0
#define MX35_PAD_D7__EMI_EIM_D_7 0x000 0x504 0x000 0x0 0x0
#define MX35_PAD_D6__EMI_EIM_D_6 0x000 0x508 0x000 0x0 0x0
#define MX35_PAD_D5__EMI_EIM_D_5 0x000 0x50c 0x000 0x0 0x0
#define MX35_PAD_D4__EMI_EIM_D_4 0x000 0x510 0x000 0x0 0x0
#define MX35_PAD_D3__EMI_EIM_D_3 0x000 0x514 0x000 0x0 0x0
#define MX35_PAD_D2__EMI_EIM_D_2 0x000 0x518 0x000 0x0 0x0
#define MX35_PAD_D1__EMI_EIM_D_1 0x000 0x51c 0x000 0x0 0x0
#define MX35_PAD_D0__EMI_EIM_D_0 0x000 0x520 0x000 0x0 0x0
#define MX35_PAD_CSI_D8__IPU_CSI_D_8 0x0e0 0x524 0x000 0x0 0x0
#define MX35_PAD_CSI_D8__KPP_COL_0 0x0e0 0x524 0x950 0x1 0x0
#define MX35_PAD_CSI_D8__GPIO1_20 0x0e0 0x524 0x83c 0x5 0x1
#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 0x0e0 0x524 0x000 0x7 0x0
#define MX35_PAD_CSI_D9__IPU_CSI_D_9 0x0e4 0x528 0x000 0x0 0x0
#define MX35_PAD_CSI_D9__KPP_COL_1 0x0e4 0x528 0x954 0x1 0x0
#define MX35_PAD_CSI_D9__GPIO1_21 0x0e4 0x528 0x840 0x5 0x1
#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 0x0e4 0x528 0x000 0x7 0x0
#define MX35_PAD_CSI_D10__IPU_CSI_D_10 0x0e8 0x52c 0x000 0x0 0x0
#define MX35_PAD_CSI_D10__KPP_COL_2 0x0e8 0x52c 0x958 0x1 0x0
#define MX35_PAD_CSI_D10__GPIO1_22 0x0e8 0x52c 0x844 0x5 0x1
#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 0x0e8 0x52c 0x000 0x7 0x0
#define MX35_PAD_CSI_D11__IPU_CSI_D_11 0x0ec 0x530 0x000 0x0 0x0
#define MX35_PAD_CSI_D11__KPP_COL_3 0x0ec 0x530 0x95c 0x1 0x0
#define MX35_PAD_CSI_D11__GPIO1_23 0x0ec 0x530 0x000 0x5 0x0
#define MX35_PAD_CSI_D12__IPU_CSI_D_12 0x0f0 0x534 0x000 0x0 0x0
#define MX35_PAD_CSI_D12__KPP_ROW_0 0x0f0 0x534 0x970 0x1 0x0
#define MX35_PAD_CSI_D12__GPIO1_24 0x0f0 0x534 0x000 0x5 0x0
#define MX35_PAD_CSI_D13__IPU_CSI_D_13 0x0f4 0x538 0x000 0x0 0x0
#define MX35_PAD_CSI_D13__KPP_ROW_1 0x0f4 0x538 0x974 0x1 0x0
#define MX35_PAD_CSI_D13__GPIO1_25 0x0f4 0x538 0x000 0x5 0x0
#define MX35_PAD_CSI_D14__IPU_CSI_D_14 0x0f8 0x53c 0x000 0x0 0x0
#define MX35_PAD_CSI_D14__KPP_ROW_2 0x0f8 0x53c 0x978 0x1 0x0
#define MX35_PAD_CSI_D14__GPIO1_26 0x0f8 0x53c 0x000 0x5 0x0
#define MX35_PAD_CSI_D15__IPU_CSI_D_15 0x0fc 0x540 0x97c 0x0 0x0
#define MX35_PAD_CSI_D15__KPP_ROW_3 0x0fc 0x540 0x000 0x1 0x0
#define MX35_PAD_CSI_D15__GPIO1_27 0x0fc 0x540 0x000 0x5 0x0
#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK 0x100 0x544 0x000 0x0 0x0
#define MX35_PAD_CSI_MCLK__GPIO1_28 0x100 0x544 0x000 0x5 0x0
#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC 0x104 0x548 0x000 0x0 0x0
#define MX35_PAD_CSI_VSYNC__GPIO1_29 0x104 0x548 0x000 0x5 0x0
#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC 0x108 0x54c 0x000 0x0 0x0
#define MX35_PAD_CSI_HSYNC__GPIO1_30 0x108 0x54c 0x000 0x5 0x0
#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK 0x10c 0x550 0x000 0x0 0x0
#define MX35_PAD_CSI_PIXCLK__GPIO1_31 0x10c 0x550 0x000 0x5 0x0
#define MX35_PAD_I2C1_CLK__I2C1_SCL 0x110 0x554 0x000 0x0 0x0
#define MX35_PAD_I2C1_CLK__GPIO2_24 0x110 0x554 0x8a8 0x5 0x0
#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK 0x110 0x554 0x000 0x6 0x0
#define MX35_PAD_I2C1_DAT__I2C1_SDA 0x114 0x558 0x000 0x0 0x0
#define MX35_PAD_I2C1_DAT__GPIO2_25 0x114 0x558 0x8ac 0x5 0x0
#define MX35_PAD_I2C2_CLK__I2C2_SCL 0x118 0x55c 0x000 0x0 0x0
#define MX35_PAD_I2C2_CLK__CAN1_TXCAN 0x118 0x55c 0x000 0x1 0x0
#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR 0x118 0x55c 0x000 0x2 0x0
#define MX35_PAD_I2C2_CLK__GPIO2_26 0x118 0x55c 0x8b0 0x5 0x0
#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 0x118 0x55c 0x000 0x6 0x0
#define MX35_PAD_I2C2_DAT__I2C2_SDA 0x11c 0x560 0x000 0x0 0x0
#define MX35_PAD_I2C2_DAT__CAN1_RXCAN 0x11c 0x560 0x7c8 0x1 0x0
#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC 0x11c 0x560 0x9f4 0x2 0x0
#define MX35_PAD_I2C2_DAT__GPIO2_27 0x11c 0x560 0x8b4 0x5 0x0
#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 0x11c 0x560 0x000 0x6 0x0
#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x120 0x564 0x000 0x0 0x0
#define MX35_PAD_STXD4__GPIO2_28 0x120 0x564 0x8b8 0x5 0x0
#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 0x120 0x564 0x000 0x7 0x0
#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x124 0x568 0x000 0x0 0x0
#define MX35_PAD_SRXD4__GPIO2_29 0x124 0x568 0x8bc 0x5 0x0
#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 0x124 0x568 0x000 0x7 0x0
#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x128 0x56c 0x000 0x0 0x0
#define MX35_PAD_SCK4__GPIO2_30 0x128 0x56c 0x8c4 0x5 0x0
#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 0x128 0x56c 0x000 0x7 0x0
#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x12c 0x570 0x000 0x0 0x0
#define MX35_PAD_STXFS4__GPIO2_31 0x12c 0x570 0x8c8 0x5 0x0
#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 0x12c 0x570 0x000 0x7 0x0
#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD 0x130 0x574 0x000 0x0 0x0
#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 0x130 0x574 0x000 0x1 0x0
#define MX35_PAD_STXD5__CSPI2_MOSI 0x130 0x574 0x7ec 0x2 0x0
#define MX35_PAD_STXD5__GPIO1_0 0x130 0x574 0x82c 0x5 0x1
#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 0x130 0x574 0x000 0x7 0x0
#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD 0x134 0x578 0x000 0x0 0x0
#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 0x134 0x578 0x998 0x1 0x0
#define MX35_PAD_SRXD5__CSPI2_MISO 0x134 0x578 0x7e8 0x2 0x0
#define MX35_PAD_SRXD5__GPIO1_1 0x134 0x578 0x838 0x5 0x1
#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 0x134 0x578 0x000 0x7 0x0
#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC 0x138 0x57c 0x000 0x0 0x0
#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK 0x138 0x57c 0x994 0x1 0x0
#define MX35_PAD_SCK5__CSPI2_SCLK 0x138 0x57c 0x7e0 0x2 0x0
#define MX35_PAD_SCK5__GPIO1_2 0x138 0x57c 0x848 0x5 0x0
#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 0x138 0x57c 0x000 0x7 0x0
#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS 0x13c 0x580 0x000 0x0 0x0
#define MX35_PAD_STXFS5__CSPI2_RDY 0x13c 0x580 0x7e4 0x2 0x0
#define MX35_PAD_STXFS5__GPIO1_3 0x13c 0x580 0x84c 0x5 0x0
#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 0x13c 0x580 0x000 0x7 0x0
#define MX35_PAD_SCKR__ESAI_SCKR 0x140 0x584 0x000 0x0 0x0
#define MX35_PAD_SCKR__GPIO1_4 0x140 0x584 0x850 0x5 0x1
#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 0x140 0x584 0x000 0x7 0x0
#define MX35_PAD_FSR__ESAI_FSR 0x144 0x588 0x000 0x0 0x0
#define MX35_PAD_FSR__GPIO1_5 0x144 0x588 0x854 0x5 0x1
#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 0x144 0x588 0x000 0x7 0x0
#define MX35_PAD_HCKR__ESAI_HCKR 0x148 0x58c 0x000 0x0 0x0
#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS 0x148 0x58c 0x000 0x1 0x0
#define MX35_PAD_HCKR__CSPI2_SS0 0x148 0x58c 0x7f0 0x2 0x0
#define MX35_PAD_HCKR__IPU_FLASH_STROBE 0x148 0x58c 0x000 0x3 0x0
#define MX35_PAD_HCKR__GPIO1_6 0x148 0x58c 0x858 0x5 0x1
#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 0x148 0x58c 0x000 0x7 0x0
#define MX35_PAD_SCKT__ESAI_SCKT 0x14c 0x590 0x000 0x0 0x0
#define MX35_PAD_SCKT__GPIO1_7 0x14c 0x590 0x85c 0x5 0x1
#define MX35_PAD_SCKT__IPU_CSI_D_0 0x14c 0x590 0x930 0x6 0x0
#define MX35_PAD_SCKT__KPP_ROW_2 0x14c 0x590 0x978 0x7 0x1
#define MX35_PAD_FST__ESAI_FST 0x150 0x594 0x000 0x0 0x0
#define MX35_PAD_FST__GPIO1_8 0x150 0x594 0x860 0x5 0x1
#define MX35_PAD_FST__IPU_CSI_D_1 0x150 0x594 0x934 0x6 0x0
#define MX35_PAD_FST__KPP_ROW_3 0x150 0x594 0x97c 0x7 0x1
#define MX35_PAD_HCKT__ESAI_HCKT 0x154 0x598 0x000 0x0 0x0
#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC 0x154 0x598 0x7a8 0x1 0x0
#define MX35_PAD_HCKT__GPIO1_9 0x154 0x598 0x864 0x5 0x0
#define MX35_PAD_HCKT__IPU_CSI_D_2 0x154 0x598 0x938 0x6 0x0
#define MX35_PAD_HCKT__KPP_COL_3 0x154 0x598 0x95c 0x7 0x1
#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 0x158 0x59c 0x000 0x0 0x0
#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC 0x158 0x59c 0x000 0x1 0x0
#define MX35_PAD_TX5_RX0__CSPI2_SS2 0x158 0x59c 0x7f8 0x2 0x1
#define MX35_PAD_TX5_RX0__CAN2_TXCAN 0x158 0x59c 0x000 0x3 0x0
#define MX35_PAD_TX5_RX0__UART2_DTR 0x158 0x59c 0x000 0x4 0x0
#define MX35_PAD_TX5_RX0__GPIO1_10 0x158 0x59c 0x830 0x5 0x0
#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 0x158 0x59c 0x000 0x7 0x0
#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 0x15c 0x5a0 0x000 0x0 0x0
#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS 0x15c 0x5a0 0x000 0x1 0x0
#define MX35_PAD_TX4_RX1__CSPI2_SS3 0x15c 0x5a0 0x7fc 0x2 0x0
#define MX35_PAD_TX4_RX1__CAN2_RXCAN 0x15c 0x5a0 0x7cc 0x3 0x0
#define MX35_PAD_TX4_RX1__UART2_DSR 0x15c 0x5a0 0x000 0x4 0x0
#define MX35_PAD_TX4_RX1__GPIO1_11 0x15c 0x5a0 0x834 0x5 0x0
#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 0x15c 0x5a0 0x93c 0x6 0x0
#define MX35_PAD_TX4_RX1__KPP_ROW_0 0x15c 0x5a0 0x970 0x7 0x1
#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 0x160 0x5a4 0x000 0x0 0x0
#define MX35_PAD_TX3_RX2__I2C3_SCL 0x160 0x5a4 0x91c 0x1 0x0
#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 0x160 0x5a4 0x000 0x3 0x0
#define MX35_PAD_TX3_RX2__GPIO1_12 0x160 0x5a4 0x000 0x5 0x0
#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 0x160 0x5a4 0x940 0x6 0x0
#define MX35_PAD_TX3_RX2__KPP_ROW_1 0x160 0x5a4 0x974 0x7 0x1
#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 0x164 0x5a8 0x000 0x0 0x0
#define MX35_PAD_TX2_RX3__I2C3_SDA 0x164 0x5a8 0x920 0x1 0x0
#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 0x164 0x5a8 0x000 0x3 0x0
#define MX35_PAD_TX2_RX3__GPIO1_13 0x164 0x5a8 0x000 0x5 0x0
#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 0x164 0x5a8 0x944 0x6 0x0
#define MX35_PAD_TX2_RX3__KPP_COL_0 0x164 0x5a8 0x950 0x7 0x1
#define MX35_PAD_TX1__ESAI_TX1 0x168 0x5ac 0x000 0x0 0x0
#define MX35_PAD_TX1__CCM_PMIC_RDY 0x168 0x5ac 0x7d4 0x1 0x1
#define MX35_PAD_TX1__CSPI1_SS2 0x168 0x5ac 0x7d8 0x2 0x2
#define MX35_PAD_TX1__EMI_NANDF_CE3 0x168 0x5ac 0x000 0x3 0x0
#define MX35_PAD_TX1__UART2_RI 0x168 0x5ac 0x000 0x4 0x0
#define MX35_PAD_TX1__GPIO1_14 0x168 0x5ac 0x000 0x5 0x0
#define MX35_PAD_TX1__IPU_CSI_D_6 0x168 0x5ac 0x948 0x6 0x0
#define MX35_PAD_TX1__KPP_COL_1 0x168 0x5ac 0x954 0x7 0x1
#define MX35_PAD_TX0__ESAI_TX0 0x16c 0x5b0 0x000 0x0 0x0
#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK 0x16c 0x5b0 0x994 0x1 0x1
#define MX35_PAD_TX0__CSPI1_SS3 0x16c 0x5b0 0x7dc 0x2 0x0
#define MX35_PAD_TX0__EMI_DTACK_B 0x16c 0x5b0 0x800 0x3 0x1
#define MX35_PAD_TX0__UART2_DCD 0x16c 0x5b0 0x000 0x4 0x0
#define MX35_PAD_TX0__GPIO1_15 0x16c 0x5b0 0x000 0x5 0x0
#define MX35_PAD_TX0__IPU_CSI_D_7 0x16c 0x5b0 0x94c 0x6 0x0
#define MX35_PAD_TX0__KPP_COL_2 0x16c 0x5b0 0x958 0x7 0x1
#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI 0x170 0x5b4 0x000 0x0 0x0
#define MX35_PAD_CSPI1_MOSI__GPIO1_16 0x170 0x5b4 0x000 0x5 0x0
#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 0x170 0x5b4 0x000 0x7 0x0
#define MX35_PAD_CSPI1_MISO__CSPI1_MISO 0x174 0x5b8 0x000 0x0 0x0
#define MX35_PAD_CSPI1_MISO__GPIO1_17 0x174 0x5b8 0x000 0x5 0x0
#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 0x174 0x5b8 0x000 0x7 0x0
#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 0x178 0x5bc 0x000 0x0 0x0
#define MX35_PAD_CSPI1_SS0__OWIRE_LINE 0x178 0x5bc 0x990 0x1 0x1
#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 0x178 0x5bc 0x7fc 0x2 0x1
#define MX35_PAD_CSPI1_SS0__GPIO1_18 0x178 0x5bc 0x000 0x5 0x0
#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 0x178 0x5bc 0x000 0x7 0x0
#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 0x17c 0x5c0 0x000 0x0 0x0
#define MX35_PAD_CSPI1_SS1__PWM_PWMO 0x17c 0x5c0 0x000 0x1 0x0
#define MX35_PAD_CSPI1_SS1__CCM_CLK32K 0x17c 0x5c0 0x7d0 0x2 0x1
#define MX35_PAD_CSPI1_SS1__GPIO1_19 0x17c 0x5c0 0x000 0x5 0x0
#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 0x17c 0x5c0 0x000 0x6 0x0
#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 0x17c 0x5c0 0x000 0x7 0x0
#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK 0x180 0x5c4 0x000 0x0 0x0
#define MX35_PAD_CSPI1_SCLK__GPIO3_4 0x180 0x5c4 0x904 0x5 0x0
#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 0x180 0x5c4 0x000 0x6 0x0
#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 0x180 0x5c4 0x000 0x7 0x0
#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY 0x184 0x5c8 0x000 0x0 0x0
#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 0x184 0x5c8 0x908 0x5 0x0
#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 0x184 0x5c8 0x000 0x6 0x0
#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 0x184 0x5c8 0x000 0x7 0x0
#define MX35_PAD_RXD1__UART1_RXD_MUX 0x188 0x5cc 0x000 0x0 0x0
#define MX35_PAD_RXD1__CSPI2_MOSI 0x188 0x5cc 0x7ec 0x1 0x1
#define MX35_PAD_RXD1__KPP_COL_4 0x188 0x5cc 0x960 0x4 0x0
#define MX35_PAD_RXD1__GPIO3_6 0x188 0x5cc 0x90c 0x5 0x0
#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 0x188 0x5cc 0x000 0x7 0x0
#define MX35_PAD_TXD1__UART1_TXD_MUX 0x18c 0x5d0 0x000 0x0 0x0
#define MX35_PAD_TXD1__CSPI2_MISO 0x18c 0x5d0 0x7e8 0x1 0x1
#define MX35_PAD_TXD1__KPP_COL_5 0x18c 0x5d0 0x964 0x4 0x0
#define MX35_PAD_TXD1__GPIO3_7 0x18c 0x5d0 0x910 0x5 0x0
#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 0x18c 0x5d0 0x000 0x7 0x0
#define MX35_PAD_RTS1__UART1_RTS 0x190 0x5d4 0x000 0x0 0x0
#define MX35_PAD_RTS1__CSPI2_SCLK 0x190 0x5d4 0x7e0 0x1 0x1
#define MX35_PAD_RTS1__I2C3_SCL 0x190 0x5d4 0x91c 0x2 0x1
#define MX35_PAD_RTS1__IPU_CSI_D_0 0x190 0x5d4 0x930 0x3 0x1
#define MX35_PAD_RTS1__KPP_COL_6 0x190 0x5d4 0x968 0x4 0x0
#define MX35_PAD_RTS1__GPIO3_8 0x190 0x5d4 0x914 0x5 0x0
#define MX35_PAD_RTS1__EMI_NANDF_CE1 0x190 0x5d4 0x000 0x6 0x0
#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 0x190 0x5d4 0x000 0x7 0x0
#define MX35_PAD_CTS1__UART1_CTS 0x194 0x5d8 0x000 0x0 0x0
#define MX35_PAD_CTS1__CSPI2_RDY 0x194 0x5d8 0x7e4 0x1 0x1
#define MX35_PAD_CTS1__I2C3_SDA 0x194 0x5d8 0x920 0x2 0x1
#define MX35_PAD_CTS1__IPU_CSI_D_1 0x194 0x5d8 0x934 0x3 0x1
#define MX35_PAD_CTS1__KPP_COL_7 0x194 0x5d8 0x96c 0x4 0x0
#define MX35_PAD_CTS1__GPIO3_9 0x194 0x5d8 0x918 0x5 0x0
#define MX35_PAD_CTS1__EMI_NANDF_CE2 0x194 0x5d8 0x000 0x6 0x0
#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 0x194 0x5d8 0x000 0x7 0x0
#define MX35_PAD_RXD2__UART2_RXD_MUX 0x198 0x5dc 0x000 0x0 0x0
#define MX35_PAD_RXD2__KPP_ROW_4 0x198 0x5dc 0x980 0x4 0x0
#define MX35_PAD_RXD2__GPIO3_10 0x198 0x5dc 0x8ec 0x5 0x0
#define MX35_PAD_TXD2__UART2_TXD_MUX 0x19c 0x5e0 0x000 0x0 0x0
#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK 0x19c 0x5e0 0x994 0x1 0x2
#define MX35_PAD_TXD2__KPP_ROW_5 0x19c 0x5e0 0x984 0x4 0x0
#define MX35_PAD_TXD2__GPIO3_11 0x19c 0x5e0 0x8f0 0x5 0x0
#define MX35_PAD_RTS2__UART2_RTS 0x1a0 0x5e4 0x000 0x0 0x0
#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 0x1a0 0x5e4 0x998 0x1 0x1
#define MX35_PAD_RTS2__CAN2_RXCAN 0x1a0 0x5e4 0x7cc 0x2 0x1
#define MX35_PAD_RTS2__IPU_CSI_D_2 0x1a0 0x5e4 0x938 0x3 0x1
#define MX35_PAD_RTS2__KPP_ROW_6 0x1a0 0x5e4 0x988 0x4 0x0
#define MX35_PAD_RTS2__GPIO3_12 0x1a0 0x5e4 0x8f4 0x5 0x0
#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC 0x1a0 0x5e4 0x000 0x6 0x0
#define MX35_PAD_RTS2__UART3_RXD_MUX 0x1a0 0x5e4 0x9a0 0x7 0x0
#define MX35_PAD_CTS2__UART2_CTS 0x1a4 0x5e8 0x000 0x0 0x0
#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 0x1a4 0x5e8 0x000 0x1 0x0
#define MX35_PAD_CTS2__CAN2_TXCAN 0x1a4 0x5e8 0x000 0x2 0x0
#define MX35_PAD_CTS2__IPU_CSI_D_3 0x1a4 0x5e8 0x93c 0x3 0x1
#define MX35_PAD_CTS2__KPP_ROW_7 0x1a4 0x5e8 0x98c 0x4 0x0
#define MX35_PAD_CTS2__GPIO3_13 0x1a4 0x5e8 0x8f8 0x5 0x0
#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS 0x1a4 0x5e8 0x000 0x6 0x0
#define MX35_PAD_CTS2__UART3_TXD_MUX 0x1a4 0x5e8 0x000 0x7 0x0
#define MX35_PAD_RTCK__ARM11P_TOP_RTCK 0x000 0x5ec 0x000 0x0 0x0
#define MX35_PAD_TCK__SJC_TCK 0x000 0x5f0 0x000 0x0 0x0
#define MX35_PAD_TMS__SJC_TMS 0x000 0x5f4 0x000 0x0 0x0
#define MX35_PAD_TDI__SJC_TDI 0x000 0x5f8 0x000 0x0 0x0
#define MX35_PAD_TDO__SJC_TDO 0x000 0x5fc 0x000 0x0 0x0
#define MX35_PAD_TRSTB__SJC_TRSTB 0x000 0x600 0x000 0x0 0x0
#define MX35_PAD_DE_B__SJC_DE_B 0x000 0x604 0x000 0x0 0x0
#define MX35_PAD_SJC_MOD__SJC_MOD 0x000 0x608 0x000 0x0 0x0
#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR 0x1a8 0x60c 0x000 0x0 0x0
#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR 0x1a8 0x60c 0x000 0x1 0x0
#define MX35_PAD_USBOTG_PWR__GPIO3_14 0x1a8 0x60c 0x8fc 0x5 0x0
#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC 0x1ac 0x610 0x000 0x0 0x0
#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC 0x1ac 0x610 0x9f4 0x1 0x1
#define MX35_PAD_USBOTG_OC__GPIO3_15 0x1ac 0x610 0x900 0x5 0x0
#define MX35_PAD_LD0__IPU_DISPB_DAT_0 0x1b0 0x614 0x000 0x0 0x0
#define MX35_PAD_LD0__GPIO2_0 0x1b0 0x614 0x868 0x5 0x1
#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 0x1b0 0x614 0x000 0x6 0x0
#define MX35_PAD_LD1__IPU_DISPB_DAT_1 0x1b4 0x618 0x000 0x0 0x0
#define MX35_PAD_LD1__GPIO2_1 0x1b4 0x618 0x894 0x5 0x0
#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 0x1b4 0x618 0x000 0x6 0x0
#define MX35_PAD_LD2__IPU_DISPB_DAT_2 0x1b8 0x61c 0x000 0x0 0x0
#define MX35_PAD_LD2__GPIO2_2 0x1b8 0x61c 0x8c0 0x5 0x0
#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 0x1b8 0x61c 0x000 0x6 0x0
#define MX35_PAD_LD3__IPU_DISPB_DAT_3 0x1bc 0x620 0x000 0x0 0x0
#define MX35_PAD_LD3__GPIO2_3 0x1bc 0x620 0x8cc 0x5 0x0
#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 0x1bc 0x620 0x000 0x6 0x0
#define MX35_PAD_LD4__IPU_DISPB_DAT_4 0x1c0 0x624 0x000 0x0 0x0
#define MX35_PAD_LD4__GPIO2_4 0x1c0 0x624 0x8d0 0x5 0x0
#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 0x1c0 0x624 0x000 0x6 0x0
#define MX35_PAD_LD5__IPU_DISPB_DAT_5 0x1c4 0x628 0x000 0x0 0x0
#define MX35_PAD_LD5__GPIO2_5 0x1c4 0x628 0x8d4 0x5 0x0
#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 0x1c4 0x628 0x000 0x6 0x0
#define MX35_PAD_LD6__IPU_DISPB_DAT_6 0x1c8 0x62c 0x000 0x0 0x0
#define MX35_PAD_LD6__GPIO2_6 0x1c8 0x62c 0x8d8 0x5 0x0
#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 0x1c8 0x62c 0x000 0x6 0x0
#define MX35_PAD_LD7__IPU_DISPB_DAT_7 0x1cc 0x630 0x000 0x0 0x0
#define MX35_PAD_LD7__GPIO2_7 0x1cc 0x630 0x8dc 0x5 0x0
#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 0x1cc 0x630 0x000 0x6 0x0
#define MX35_PAD_LD8__IPU_DISPB_DAT_8 0x1d0 0x634 0x000 0x0 0x0
#define MX35_PAD_LD8__GPIO2_8 0x1d0 0x634 0x8e0 0x5 0x0
#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 0x1d0 0x634 0x000 0x6 0x0
#define MX35_PAD_LD9__IPU_DISPB_DAT_9 0x1d4 0x638 0x000 0x0 0x0
#define MX35_PAD_LD9__GPIO2_9 0x1d4 0x638 0x8e4 0x5 0x0
#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 0x1d4 0x638 0x000 0x6 0x0
#define MX35_PAD_LD10__IPU_DISPB_DAT_10 0x1d8 0x63c 0x000 0x0 0x0
#define MX35_PAD_LD10__GPIO2_10 0x1d8 0x63c 0x86c 0x5 0x0
#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 0x1d8 0x63c 0x000 0x6 0x0
#define MX35_PAD_LD11__IPU_DISPB_DAT_11 0x1dc 0x640 0x000 0x0 0x0
#define MX35_PAD_LD11__GPIO2_11 0x1dc 0x640 0x870 0x5 0x0
#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 0x1dc 0x640 0x000 0x6 0x0
#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 0x1dc 0x640 0x000 0x7 0x0
#define MX35_PAD_LD12__IPU_DISPB_DAT_12 0x1e0 0x644 0x000 0x0 0x0
#define MX35_PAD_LD12__GPIO2_12 0x1e0 0x644 0x874 0x5 0x0
#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 0x1e0 0x644 0x000 0x6 0x0
#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 0x1e0 0x644 0x000 0x7 0x0
#define MX35_PAD_LD13__IPU_DISPB_DAT_13 0x1e4 0x648 0x000 0x0 0x0
#define MX35_PAD_LD13__GPIO2_13 0x1e4 0x648 0x878 0x5 0x0
#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 0x1e4 0x648 0x000 0x6 0x0
#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 0x1e4 0x648 0x000 0x7 0x0
#define MX35_PAD_LD14__IPU_DISPB_DAT_14 0x1e8 0x64c 0x000 0x0 0x0
#define MX35_PAD_LD14__GPIO2_14 0x1e8 0x64c 0x87c 0x5 0x0
#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 0x1e8 0x64c 0x000 0x6 0x0
#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 0x1e8 0x64c 0x000 0x7 0x0
#define MX35_PAD_LD15__IPU_DISPB_DAT_15 0x1ec 0x650 0x000 0x0 0x0
#define MX35_PAD_LD15__GPIO2_15 0x1ec 0x650 0x880 0x5 0x0
#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 0x1ec 0x650 0x000 0x6 0x0
#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 0x1ec 0x650 0x000 0x7 0x0
#define MX35_PAD_LD16__IPU_DISPB_DAT_16 0x1f0 0x654 0x000 0x0 0x0
#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC 0x1f0 0x654 0x928 0x2 0x0
#define MX35_PAD_LD16__GPIO2_16 0x1f0 0x654 0x884 0x5 0x0
#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 0x1f0 0x654 0x000 0x6 0x0
#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 0x1f0 0x654 0x000 0x7 0x0
#define MX35_PAD_LD17__IPU_DISPB_DAT_17 0x1f4 0x658 0x000 0x0 0x0
#define MX35_PAD_LD17__IPU_DISPB_CS2 0x1f4 0x658 0x000 0x2 0x0
#define MX35_PAD_LD17__GPIO2_17 0x1f4 0x658 0x888 0x5 0x0
#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 0x1f4 0x658 0x000 0x6 0x0
#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 0x1f4 0x658 0x000 0x7 0x0
#define MX35_PAD_LD18__IPU_DISPB_DAT_18 0x1f8 0x65c 0x000 0x0 0x0
#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC 0x1f8 0x65c 0x924 0x1 0x1
#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC 0x1f8 0x65c 0x928 0x2 0x1
#define MX35_PAD_LD18__ESDHC3_CMD 0x1f8 0x65c 0x818 0x3 0x0
#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 0x1f8 0x65c 0x9b0 0x4 0x0
#define MX35_PAD_LD18__GPIO3_24 0x1f8 0x65c 0x000 0x5 0x0
#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 0x1f8 0x65c 0x000 0x6 0x0
#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 0x1f8 0x65c 0x000 0x7 0x0
#define MX35_PAD_LD19__IPU_DISPB_DAT_19 0x1fc 0x660 0x000 0x0 0x0
#define MX35_PAD_LD19__IPU_DISPB_BCLK 0x1fc 0x660 0x000 0x1 0x0
#define MX35_PAD_LD19__IPU_DISPB_CS1 0x1fc 0x660 0x000 0x2 0x0
#define MX35_PAD_LD19__ESDHC3_CLK 0x1fc 0x660 0x814 0x3 0x0
#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR 0x1fc 0x660 0x9c4 0x4 0x0
#define MX35_PAD_LD19__GPIO3_25 0x1fc 0x660 0x000 0x5 0x0
#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 0x1fc 0x660 0x000 0x6 0x0
#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 0x1fc 0x660 0x000 0x7 0x0
#define MX35_PAD_LD20__IPU_DISPB_DAT_20 0x200 0x664 0x000 0x0 0x0
#define MX35_PAD_LD20__IPU_DISPB_CS0 0x200 0x664 0x000 0x1 0x0
#define MX35_PAD_LD20__IPU_DISPB_SD_CLK 0x200 0x664 0x000 0x2 0x0
#define MX35_PAD_LD20__ESDHC3_DAT0 0x200 0x664 0x81c 0x3 0x0
#define MX35_PAD_LD20__GPIO3_26 0x200 0x664 0x000 0x5 0x0
#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 0x200 0x664 0x000 0x6 0x0
#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 0x200 0x664 0x000 0x7 0x0
#define MX35_PAD_LD21__IPU_DISPB_DAT_21 0x204 0x668 0x000 0x0 0x0
#define MX35_PAD_LD21__IPU_DISPB_PAR_RS 0x204 0x668 0x000 0x1 0x0
#define MX35_PAD_LD21__IPU_DISPB_SER_RS 0x204 0x668 0x000 0x2 0x0
#define MX35_PAD_LD21__ESDHC3_DAT1 0x204 0x668 0x820 0x3 0x0
#define MX35_PAD_LD21__USB_TOP_USBOTG_STP 0x204 0x668 0x000 0x4 0x0
#define MX35_PAD_LD21__GPIO3_27 0x204 0x668 0x000 0x5 0x0
#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x204 0x668 0x000 0x6 0x0
#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 0x204 0x668 0x000 0x7 0x0
#define MX35_PAD_LD22__IPU_DISPB_DAT_22 0x208 0x66c 0x000 0x0 0x0
#define MX35_PAD_LD22__IPU_DISPB_WR 0x208 0x66c 0x000 0x1 0x0
#define MX35_PAD_LD22__IPU_DISPB_SD_D_I 0x208 0x66c 0x92c 0x2 0x0
#define MX35_PAD_LD22__ESDHC3_DAT2 0x208 0x66c 0x824 0x3 0x0
#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT 0x208 0x66c 0x9c8 0x4 0x0
#define MX35_PAD_LD22__GPIO3_28 0x208 0x66c 0x000 0x5 0x0
#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR 0x208 0x66c 0x000 0x6 0x0
#define MX35_PAD_LD22__ARM11P_TOP_TRCTL 0x208 0x66c 0x000 0x7 0x0
#define MX35_PAD_LD23__IPU_DISPB_DAT_23 0x20c 0x670 0x000 0x0 0x0
#define MX35_PAD_LD23__IPU_DISPB_RD 0x20c 0x670 0x000 0x1 0x0
#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO 0x20c 0x670 0x92c 0x2 0x1
#define MX35_PAD_LD23__ESDHC3_DAT3 0x20c 0x670 0x828 0x3 0x0
#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 0x20c 0x670 0x9c0 0x4 0x0
#define MX35_PAD_LD23__GPIO3_29 0x20c 0x670 0x000 0x5 0x0
#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS 0x20c 0x670 0x000 0x6 0x0
#define MX35_PAD_LD23__ARM11P_TOP_TRCLK 0x20c 0x670 0x000 0x7 0x0
#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x210 0x674 0x000 0x0 0x0
#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO 0x210 0x674 0x92c 0x2 0x2
#define MX35_PAD_D3_HSYNC__GPIO3_30 0x210 0x674 0x000 0x5 0x0
#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE 0x210 0x674 0x000 0x6 0x0
#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 0x210 0x674 0x000 0x7 0x0
#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x214 0x678 0x000 0x0 0x0
#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK 0x214 0x678 0x000 0x2 0x0
#define MX35_PAD_D3_FPSHIFT__GPIO3_31 0x214 0x678 0x000 0x5 0x0
#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 0x214 0x678 0x000 0x6 0x0
#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 0x214 0x678 0x000 0x7 0x0
#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x218 0x67c 0x000 0x0 0x0
#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O 0x218 0x67c 0x000 0x2 0x0
#define MX35_PAD_D3_DRDY__GPIO1_0 0x218 0x67c 0x82c 0x5 0x2
#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 0x218 0x67c 0x000 0x6 0x0
#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 0x218 0x67c 0x000 0x7 0x0
#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x21c 0x680 0x000 0x0 0x0
#define MX35_PAD_CONTRAST__GPIO1_1 0x21c 0x680 0x838 0x5 0x2
#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 0x21c 0x680 0x000 0x6 0x0
#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 0x21c 0x680 0x000 0x7 0x0
#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x220 0x684 0x000 0x0 0x0
#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 0x220 0x684 0x000 0x2 0x0
#define MX35_PAD_D3_VSYNC__GPIO1_2 0x220 0x684 0x848 0x5 0x1
#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD 0x220 0x684 0x000 0x6 0x0
#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 0x220 0x684 0x000 0x7 0x0
#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV 0x224 0x688 0x000 0x0 0x0
#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0
#define MX35_PAD_D3_REV__GPIO1_3 0x224 0x688 0x84c 0x5 0x1
#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB 0x224 0x688 0x000 0x6 0x0
#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 0x224 0x688 0x000 0x7 0x0
#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS 0x228 0x68c 0x000 0x0 0x0
#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 0x228 0x68c 0x000 0x2 0x0
#define MX35_PAD_D3_CLS__GPIO1_4 0x228 0x68c 0x850 0x5 0x2
#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 0x228 0x68c 0x000 0x6 0x0
#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 0x228 0x68c 0x000 0x7 0x0
#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL 0x22c 0x690 0x000 0x0 0x0
#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC 0x22c 0x690 0x928 0x2 0x2
#define MX35_PAD_D3_SPL__GPIO1_5 0x22c 0x690 0x854 0x5 0x2
#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 0x22c 0x690 0x000 0x6 0x0
#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 0x22c 0x690 0x000 0x7 0x0
#define MX35_PAD_SD1_CMD__ESDHC1_CMD 0x230 0x694 0x000 0x0 0x0
#define MX35_PAD_SD1_CMD__MSHC_SCLK 0x230 0x694 0x000 0x1 0x0
#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC 0x230 0x694 0x924 0x3 0x2
#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 0x230 0x694 0x9b4 0x4 0x0
#define MX35_PAD_SD1_CMD__GPIO1_6 0x230 0x694 0x858 0x5 0x2
#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL 0x230 0x694 0x000 0x7 0x0
#define MX35_PAD_SD1_CLK__ESDHC1_CLK 0x234 0x698 0x000 0x0 0x0
#define MX35_PAD_SD1_CLK__MSHC_BS 0x234 0x698 0x000 0x1 0x0
#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK 0x234 0x698 0x000 0x3 0x0
#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 0x234 0x698 0x9b8 0x4 0x0
#define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2
#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK 0x234 0x698 0x000 0x7 0x0
#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x238 0x69c 0x000 0x0 0x0
#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 0x238 0x69c 0x000 0x1 0x0
#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 0x238 0x69c 0x000 0x3 0x0
#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 0x238 0x69c 0x9bc 0x4 0x0
#define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2
#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 0x238 0x69c 0x000 0x7 0x0
#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x23c 0x6a0 0x000 0x0 0x0
#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 0x23c 0x6a0 0x000 0x1 0x0
#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS 0x23c 0x6a0 0x000 0x3 0x0
#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 0x23c 0x6a0 0x9a4 0x4 0x0
#define MX35_PAD_SD1_DATA1__GPIO1_9 0x23c 0x6a0 0x864 0x5 0x1
#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 0x23c 0x6a0 0x000 0x7 0x0
#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x240 0x6a4 0x000 0x0 0x0
#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 0x240 0x6a4 0x000 0x1 0x0
#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR 0x240 0x6a4 0x000 0x3 0x0
#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 0x240 0x6a4 0x9a8 0x4 0x0
#define MX35_PAD_SD1_DATA2__GPIO1_10 0x240 0x6a4 0x830 0x5 0x1
#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 0x240 0x6a4 0x000 0x7 0x0
#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x244 0x6a8 0x000 0x0 0x0
#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 0x244 0x6a8 0x000 0x1 0x0
#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD 0x244 0x6a8 0x000 0x3 0x0
#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 0x244 0x6a8 0x9ac 0x4 0x0
#define MX35_PAD_SD1_DATA3__GPIO1_11 0x244 0x6a8 0x834 0x5 0x1
#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 0x244 0x6a8 0x000 0x7 0x0
#define MX35_PAD_SD2_CMD__ESDHC2_CMD 0x248 0x6ac 0x000 0x0 0x0
#define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2
#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0
#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2
#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 0x248 0x6ac 0x9dc 0x4 0x0
#define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2
#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 0x248 0x6ac 0x000 0x6 0x0
#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC 0x248 0x6ac 0x928 0x7 0x3
#define MX35_PAD_SD2_CLK__ESDHC2_CLK 0x24c 0x6b0 0x000 0x0 0x0
#define MX35_PAD_SD2_CLK__I2C3_SDA 0x24c 0x6b0 0x920 0x1 0x2
#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 0x24c 0x6b0 0x808 0x2 0x0
#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 0x24c 0x6b0 0x93c 0x3 0x2
#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 0x24c 0x6b0 0x9e0 0x4 0x0
#define MX35_PAD_SD2_CLK__GPIO2_1 0x24c 0x6b0 0x894 0x5 0x1
#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 0x24c 0x6b0 0x998 0x6 0x2
#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 0x24c 0x6b0 0x000 0x7 0x0
#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 0x250 0x6b4 0x000 0x0 0x0
#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX 0x250 0x6b4 0x9a0 0x1 0x1
#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0
#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 0x250 0x6b4 0x940 0x3 0x1
#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 0x250 0x6b4 0x9e4 0x4 0x0
#define MX35_PAD_SD2_DATA0__GPIO2_2 0x250 0x6b4 0x8c0 0x5 0x1
#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK 0x250 0x6b4 0x994 0x6 0x3
#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 0x254 0x6b8 0x000 0x0 0x0
#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX 0x254 0x6b8 0x000 0x1 0x0
#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0
#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 0x254 0x6b8 0x944 0x3 0x1
#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 0x254 0x6b8 0x9cc 0x4 0x0
#define MX35_PAD_SD2_DATA1__GPIO2_3 0x254 0x6b8 0x8cc 0x5 0x1
#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 0x258 0x6bc 0x000 0x0 0x0
#define MX35_PAD_SD2_DATA2__UART3_RTS 0x258 0x6bc 0x99c 0x1 0x0
#define MX35_PAD_SD2_DATA2__CAN1_RXCAN 0x258 0x6bc 0x7c8 0x2 0x1
#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 0x258 0x6bc 0x948 0x3 0x1
#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 0x258 0x6bc 0x9d0 0x4 0x0
#define MX35_PAD_SD2_DATA2__GPIO2_4 0x258 0x6bc 0x8d0 0x5 0x1
#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 0x25c 0x6c0 0x000 0x0 0x0
#define MX35_PAD_SD2_DATA3__UART3_CTS 0x25c 0x6c0 0x000 0x1 0x0
#define MX35_PAD_SD2_DATA3__CAN1_TXCAN 0x25c 0x6c0 0x000 0x2 0x0
#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 0x25c 0x6c0 0x94c 0x3 0x1
#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 0x25c 0x6c0 0x9d4 0x4 0x0
#define MX35_PAD_SD2_DATA3__GPIO2_5 0x25c 0x6c0 0x8d4 0x5 0x1
#define MX35_PAD_ATA_CS0__ATA_CS0 0x260 0x6c4 0x000 0x0 0x0
#define MX35_PAD_ATA_CS0__CSPI1_SS3 0x260 0x6c4 0x7dc 0x1 0x1
#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 0x260 0x6c4 0x000 0x3 0x0
#define MX35_PAD_ATA_CS0__GPIO2_6 0x260 0x6c4 0x8d8 0x5 0x1
#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 0x260 0x6c4 0x000 0x6 0x0
#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 0x260 0x6c4 0x000 0x7 0x0
#define MX35_PAD_ATA_CS1__ATA_CS1 0x264 0x6c8 0x000 0x0 0x0
#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 0x264 0x6c8 0x000 0x3 0x0
#define MX35_PAD_ATA_CS1__CSPI2_SS0 0x264 0x6c8 0x7f0 0x4 0x1
#define MX35_PAD_ATA_CS1__GPIO2_7 0x264 0x6c8 0x8dc 0x5 0x1
#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 0x264 0x6c8 0x000 0x6 0x0
#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 0x264 0x6c8 0x000 0x7 0x0
#define MX35_PAD_ATA_DIOR__ATA_DIOR 0x268 0x6cc 0x000 0x0 0x0
#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 0x268 0x6cc 0x81c 0x1 0x1
#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR 0x268 0x6cc 0x9c4 0x2 0x1
#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 0x268 0x6cc 0x000 0x3 0x0
#define MX35_PAD_ATA_DIOR__CSPI2_SS1 0x268 0x6cc 0x7f4 0x4 0x1
#define MX35_PAD_ATA_DIOR__GPIO2_8 0x268 0x6cc 0x8e0 0x5 0x1
#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 0x268 0x6cc 0x000 0x6 0x0
#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 0x268 0x6cc 0x000 0x7 0x0
#define MX35_PAD_ATA_DIOW__ATA_DIOW 0x26c 0x6d0 0x000 0x0 0x0
#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 0x26c 0x6d0 0x820 0x1 0x1
#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP 0x26c 0x6d0 0x000 0x2 0x0
#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 0x26c 0x6d0 0x000 0x3 0x0
#define MX35_PAD_ATA_DIOW__CSPI2_MOSI 0x26c 0x6d0 0x7ec 0x4 0x2
#define MX35_PAD_ATA_DIOW__GPIO2_9 0x26c 0x6d0 0x8e4 0x5 0x1
#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 0x26c 0x6d0 0x000 0x6 0x0
#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 0x26c 0x6d0 0x000 0x7 0x0
#define MX35_PAD_ATA_DMACK__ATA_DMACK 0x270 0x6d4 0x000 0x0 0x0
#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 0x270 0x6d4 0x824 0x1 0x1
#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT 0x270 0x6d4 0x9c8 0x2 0x1
#define MX35_PAD_ATA_DMACK__CSPI2_MISO 0x270 0x6d4 0x7e8 0x4 0x2
#define MX35_PAD_ATA_DMACK__GPIO2_10 0x270 0x6d4 0x86c 0x5 0x1
#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 0x270 0x6d4 0x000 0x6 0x0
#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 0x270 0x6d4 0x000 0x7 0x0
#define MX35_PAD_ATA_RESET_B__ATA_RESET_B 0x274 0x6d8 0x000 0x0 0x0
#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 0x274 0x6d8 0x828 0x1 0x1
#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 0x274 0x6d8 0x9a4 0x2 0x1
#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O 0x274 0x6d8 0x000 0x3 0x0
#define MX35_PAD_ATA_RESET_B__CSPI2_RDY 0x274 0x6d8 0x7e4 0x4 0x2
#define MX35_PAD_ATA_RESET_B__GPIO2_11 0x274 0x6d8 0x870 0x5 0x1
#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 0x274 0x6d8 0x000 0x6 0x0
#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 0x274 0x6d8 0x000 0x7 0x0
#define MX35_PAD_ATA_IORDY__ATA_IORDY 0x278 0x6dc 0x000 0x0 0x0
#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 0x278 0x6dc 0x000 0x1 0x0
#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 0x278 0x6dc 0x9a8 0x2 0x1
#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO 0x278 0x6dc 0x92c 0x3 0x3
#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 0x278 0x6dc 0x000 0x4 0x0
#define MX35_PAD_ATA_IORDY__GPIO2_12 0x278 0x6dc 0x874 0x5 0x1
#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 0x278 0x6dc 0x000 0x6 0x0
#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 0x278 0x6dc 0x000 0x7 0x0
#define MX35_PAD_ATA_DATA0__ATA_DATA_0 0x27c 0x6e0 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 0x27c 0x6e0 0x000 0x1 0x0
#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 0x27c 0x6e0 0x9ac 0x2 0x1
#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC 0x27c 0x6e0 0x928 0x3 0x4
#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 0x27c 0x6e0 0x000 0x4 0x0
#define MX35_PAD_ATA_DATA0__GPIO2_13 0x27c 0x6e0 0x878 0x5 0x1
#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 0x27c 0x6e0 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 0x27c 0x6e0 0x000 0x7 0x0
#define MX35_PAD_ATA_DATA1__ATA_DATA_1 0x280 0x6e4 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 0x280 0x6e4 0x000 0x1 0x0
#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 0x280 0x6e4 0x9b0 0x2 0x1
#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK 0x280 0x6e4 0x000 0x3 0x0
#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 0x280 0x6e4 0x000 0x4 0x0
#define MX35_PAD_ATA_DATA1__GPIO2_14 0x280 0x6e4 0x87c 0x5 0x1
#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 0x280 0x6e4 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 0x280 0x6e4 0x000 0x7 0x0
#define MX35_PAD_ATA_DATA2__ATA_DATA_2 0x284 0x6e8 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 0x284 0x6e8 0x000 0x1 0x0
#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 0x284 0x6e8 0x9b4 0x2 0x1
#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS 0x284 0x6e8 0x000 0x3 0x0
#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 0x284 0x6e8 0x000 0x4 0x0
#define MX35_PAD_ATA_DATA2__GPIO2_15 0x284 0x6e8 0x880 0x5 0x1
#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 0x284 0x6e8 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 0x284 0x6e8 0x000 0x7 0x0
#define MX35_PAD_ATA_DATA3__ATA_DATA_3 0x288 0x6ec 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA3__ESDHC3_CLK 0x288 0x6ec 0x814 0x1 0x1
#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 0x288 0x6ec 0x9b8 0x2 0x1
#define MX35_PAD_ATA_DATA3__CSPI2_SCLK 0x288 0x6ec 0x7e0 0x4 0x2
#define MX35_PAD_ATA_DATA3__GPIO2_16 0x288 0x6ec 0x884 0x5 0x1
#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 0x288 0x6ec 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 0x288 0x6ec 0x000 0x7 0x0
#define MX35_PAD_ATA_DATA4__ATA_DATA_4 0x28c 0x6f0 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA4__ESDHC3_CMD 0x28c 0x6f0 0x818 0x1 0x1
#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 0x28c 0x6f0 0x9bc 0x2 0x1
#define MX35_PAD_ATA_DATA4__GPIO2_17 0x28c 0x6f0 0x888 0x5 0x1
#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 0x28c 0x6f0 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 0x28c 0x6f0 0x000 0x7 0x0
#define MX35_PAD_ATA_DATA5__ATA_DATA_5 0x290 0x6f4 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 0x290 0x6f4 0x9c0 0x2 0x1
#define MX35_PAD_ATA_DATA5__GPIO2_18 0x290 0x6f4 0x88c 0x5 0x1
#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 0x290 0x6f4 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 0x290 0x6f4 0x000 0x7 0x0
#define MX35_PAD_ATA_DATA6__ATA_DATA_6 0x294 0x6f8 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA6__CAN1_TXCAN 0x294 0x6f8 0x000 0x1 0x0
#define MX35_PAD_ATA_DATA6__UART1_DTR 0x294 0x6f8 0x000 0x2 0x0
#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD 0x294 0x6f8 0x7b4 0x3 0x0
#define MX35_PAD_ATA_DATA6__GPIO2_19 0x294 0x6f8 0x890 0x5 0x1
#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 0x294 0x6f8 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA7__ATA_DATA_7 0x298 0x6fc 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA7__CAN1_RXCAN 0x298 0x6fc 0x7c8 0x1 0x2
#define MX35_PAD_ATA_DATA7__UART1_DSR 0x298 0x6fc 0x000 0x2 0x0
#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD 0x298 0x6fc 0x7b0 0x3 0x0
#define MX35_PAD_ATA_DATA7__GPIO2_20 0x298 0x6fc 0x898 0x5 0x1
#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 0x298 0x6fc 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA8__ATA_DATA_8 0x29c 0x700 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA8__UART3_RTS 0x29c 0x700 0x99c 0x1 0x1
#define MX35_PAD_ATA_DATA8__UART1_RI 0x29c 0x700 0x000 0x2 0x0
#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC 0x29c 0x700 0x7c0 0x3 0x0
#define MX35_PAD_ATA_DATA8__GPIO2_21 0x29c 0x700 0x89c 0x5 0x1
#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 0x29c 0x700 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA9__ATA_DATA_9 0x2a0 0x704 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA9__UART3_CTS 0x2a0 0x704 0x000 0x1 0x0
#define MX35_PAD_ATA_DATA9__UART1_DCD 0x2a0 0x704 0x000 0x2 0x0
#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS 0x2a0 0x704 0x7c4 0x3 0x0
#define MX35_PAD_ATA_DATA9__GPIO2_22 0x2a0 0x704 0x8a0 0x5 0x1
#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 0x2a0 0x704 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA10__ATA_DATA_10 0x2a4 0x708 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX 0x2a4 0x708 0x9a0 0x1 0x2
#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC 0x2a4 0x708 0x7b8 0x3 0x0
#define MX35_PAD_ATA_DATA10__GPIO2_23 0x2a4 0x708 0x8a4 0x5 0x1
#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 0x2a4 0x708 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA11__ATA_DATA_11 0x2a8 0x70c 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX 0x2a8 0x70c 0x000 0x1 0x0
#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS 0x2a8 0x70c 0x7bc 0x3 0x0
#define MX35_PAD_ATA_DATA11__GPIO2_24 0x2a8 0x70c 0x8a8 0x5 0x1
#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 0x2a8 0x70c 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA12__ATA_DATA_12 0x2ac 0x710 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA12__I2C3_SCL 0x2ac 0x710 0x91c 0x1 0x3
#define MX35_PAD_ATA_DATA12__GPIO2_25 0x2ac 0x710 0x8ac 0x5 0x1
#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 0x2ac 0x710 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA13__ATA_DATA_13 0x2b0 0x714 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA13__I2C3_SDA 0x2b0 0x714 0x920 0x1 0x3
#define MX35_PAD_ATA_DATA13__GPIO2_26 0x2b0 0x714 0x8b0 0x5 0x1
#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 0x2b0 0x714 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA14__ATA_DATA_14 0x2b4 0x718 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 0x2b4 0x718 0x930 0x1 0x2
#define MX35_PAD_ATA_DATA14__KPP_ROW_0 0x2b4 0x718 0x970 0x3 0x2
#define MX35_PAD_ATA_DATA14__GPIO2_27 0x2b4 0x718 0x8b4 0x5 0x1
#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 0x2b4 0x718 0x000 0x6 0x0
#define MX35_PAD_ATA_DATA15__ATA_DATA_15 0x2b8 0x71c 0x000 0x0 0x0
#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 0x2b8 0x71c 0x934 0x1 0x2
#define MX35_PAD_ATA_DATA15__KPP_ROW_1 0x2b8 0x71c 0x974 0x3 0x2
#define MX35_PAD_ATA_DATA15__GPIO2_28 0x2b8 0x71c 0x8b8 0x5 0x1
#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 0x2b8 0x71c 0x000 0x6 0x0
#define MX35_PAD_ATA_INTRQ__ATA_INTRQ 0x2bc 0x720 0x000 0x0 0x0
#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 0x2bc 0x720 0x938 0x1 0x3
#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 0x2bc 0x720 0x978 0x3 0x2
#define MX35_PAD_ATA_INTRQ__GPIO2_29 0x2bc 0x720 0x8bc 0x5 0x1
#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 0x2bc 0x720 0x000 0x6 0x0
#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN 0x2c0 0x724 0x000 0x0 0x0
#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 0x2c0 0x724 0x93c 0x1 0x3
#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 0x2c0 0x724 0x97c 0x3 0x2
#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 0x2c0 0x724 0x8c4 0x5 0x1
#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 0x2c0 0x724 0x000 0x6 0x0
#define MX35_PAD_ATA_DMARQ__ATA_DMARQ 0x2c4 0x728 0x000 0x0 0x0
#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 0x2c4 0x728 0x940 0x1 0x2
#define MX35_PAD_ATA_DMARQ__KPP_COL_0 0x2c4 0x728 0x950 0x3 0x2
#define MX35_PAD_ATA_DMARQ__GPIO2_31 0x2c4 0x728 0x8c8 0x5 0x1
#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 0x2c4 0x728 0x000 0x6 0x0
#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 0x2c4 0x728 0x000 0x7 0x0
#define MX35_PAD_ATA_DA0__ATA_DA_0 0x2c8 0x72c 0x000 0x0 0x0
#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 0x2c8 0x72c 0x944 0x1 0x2
#define MX35_PAD_ATA_DA0__KPP_COL_1 0x2c8 0x72c 0x954 0x3 0x2
#define MX35_PAD_ATA_DA0__GPIO3_0 0x2c8 0x72c 0x8e8 0x5 0x1
#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 0x2c8 0x72c 0x000 0x6 0x0
#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 0x2c8 0x72c 0x000 0x7 0x0
#define MX35_PAD_ATA_DA1__ATA_DA_1 0x2cc 0x730 0x000 0x0 0x0
#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 0x2cc 0x730 0x948 0x1 0x2
#define MX35_PAD_ATA_DA1__KPP_COL_2 0x2cc 0x730 0x958 0x3 0x2
#define MX35_PAD_ATA_DA1__GPIO3_1 0x2cc 0x730 0x000 0x5 0x0
#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 0x2cc 0x730 0x000 0x6 0x0
#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 0x2cc 0x730 0x000 0x7 0x0
#define MX35_PAD_ATA_DA2__ATA_DA_2 0x2d0 0x734 0x000 0x0 0x0
#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 0x2d0 0x734 0x94c 0x1 0x2
#define MX35_PAD_ATA_DA2__KPP_COL_3 0x2d0 0x734 0x95c 0x3 0x2
#define MX35_PAD_ATA_DA2__GPIO3_2 0x2d0 0x734 0x000 0x5 0x0
#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 0x2d0 0x734 0x000 0x6 0x0
#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 0x2d0 0x734 0x000 0x7 0x0
#define MX35_PAD_MLB_CLK__MLB_MLBCLK 0x2d4 0x738 0x000 0x0 0x0
#define MX35_PAD_MLB_CLK__GPIO3_3 0x2d4 0x738 0x000 0x5 0x0
#define MX35_PAD_MLB_DAT__MLB_MLBDAT 0x2d8 0x73c 0x000 0x0 0x0
#define MX35_PAD_MLB_DAT__GPIO3_4 0x2d8 0x73c 0x904 0x5 0x1
#define MX35_PAD_MLB_SIG__MLB_MLBSIG 0x2dc 0x740 0x000 0x0 0x0
#define MX35_PAD_MLB_SIG__GPIO3_5 0x2dc 0x740 0x908 0x5 0x1
#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x2e0 0x744 0x000 0x0 0x0
#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 0x2e0 0x744 0x804 0x1 0x1
#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX 0x2e0 0x744 0x9a0 0x2 0x3
#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR 0x2e0 0x744 0x9ec 0x3 0x1
#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI 0x2e0 0x744 0x7ec 0x4 0x3
#define MX35_PAD_FEC_TX_CLK__GPIO3_6 0x2e0 0x744 0x90c 0x5 0x1
#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC 0x2e0 0x744 0x928 0x6 0x5
#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 0x2e0 0x744 0x000 0x7 0x0
#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x2e4 0x748 0x000 0x0 0x0
#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 0x2e4 0x748 0x808 0x1 0x1
#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX 0x2e4 0x748 0x000 0x2 0x0
#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP 0x2e4 0x748 0x000 0x3 0x0
#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO 0x2e4 0x748 0x7e8 0x4 0x3
#define MX35_PAD_FEC_RX_CLK__GPIO3_7 0x2e4 0x748 0x910 0x5 0x1
#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I 0x2e4 0x748 0x92c 0x6 0x4
#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 0x2e4 0x748 0x000 0x7 0x0
#define MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x2e8 0x74c 0x000 0x0 0x0
#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 0x2e8 0x74c 0x80c 0x1 0x1
#define MX35_PAD_FEC_RX_DV__UART3_RTS 0x2e8 0x74c 0x99c 0x2 0x2
#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT 0x2e8 0x74c 0x9f0 0x3 0x1
#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK 0x2e8 0x74c 0x7e0 0x4 0x3
#define MX35_PAD_FEC_RX_DV__GPIO3_8 0x2e8 0x74c 0x914 0x5 0x1
#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK 0x2e8 0x74c 0x000 0x6 0x0
#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 0x2e8 0x74c 0x000 0x7 0x0
#define MX35_PAD_FEC_COL__FEC_COL 0x2ec 0x750 0x000 0x0 0x0
#define MX35_PAD_FEC_COL__ESDHC1_DAT7 0x2ec 0x750 0x810 0x1 0x1
#define MX35_PAD_FEC_COL__UART3_CTS 0x2ec 0x750 0x000 0x2 0x0
#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 0x2ec 0x750 0x9cc 0x3 0x1
#define MX35_PAD_FEC_COL__CSPI2_RDY 0x2ec 0x750 0x7e4 0x4 0x3
#define MX35_PAD_FEC_COL__GPIO3_9 0x2ec 0x750 0x918 0x5 0x1
#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS 0x2ec 0x750 0x000 0x6 0x0
#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 0x2ec 0x750 0x000 0x7 0x0
#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x2f0 0x754 0x000 0x0 0x0
#define MX35_PAD_FEC_RDATA0__PWM_PWMO 0x2f0 0x754 0x000 0x1 0x0
#define MX35_PAD_FEC_RDATA0__UART3_DTR 0x2f0 0x754 0x000 0x2 0x0
#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 0x2f0 0x754 0x9d0 0x3 0x1
#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 0x2f0 0x754 0x7f0 0x4 0x2
#define MX35_PAD_FEC_RDATA0__GPIO3_10 0x2f0 0x754 0x8ec 0x5 0x1
#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 0x2f0 0x754 0x000 0x6 0x0
#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 0x2f0 0x754 0x000 0x7 0x0
#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x2f4 0x758 0x000 0x0 0x0
#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 0x2f4 0x758 0x000 0x1 0x0
#define MX35_PAD_FEC_TDATA0__UART3_DSR 0x2f4 0x758 0x000 0x2 0x0
#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 0x2f4 0x758 0x9d4 0x3 0x1
#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 0x2f4 0x758 0x7f4 0x4 0x2
#define MX35_PAD_FEC_TDATA0__GPIO3_11 0x2f4 0x758 0x8f0 0x5 0x1
#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 0x2f4 0x758 0x000 0x6 0x0
#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 0x2f4 0x758 0x000 0x7 0x0
#define MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x2f8 0x75c 0x000 0x0 0x0
#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 0x2f8 0x75c 0x998 0x1 0x3
#define MX35_PAD_FEC_TX_EN__UART3_RI 0x2f8 0x75c 0x000 0x2 0x0
#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 0x2f8 0x75c 0x9d8 0x3 0x1
#define MX35_PAD_FEC_TX_EN__GPIO3_12 0x2f8 0x75c 0x8f4 0x5 0x1
#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS 0x2f8 0x75c 0x000 0x6 0x0
#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 0x2f8 0x75c 0x000 0x7 0x0
#define MX35_PAD_FEC_MDC__FEC_MDC 0x2fc 0x760 0x000 0x0 0x0
#define MX35_PAD_FEC_MDC__CAN2_TXCAN 0x2fc 0x760 0x000 0x1 0x0
#define MX35_PAD_FEC_MDC__UART3_DCD 0x2fc 0x760 0x000 0x2 0x0
#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 0x2fc 0x760 0x9dc 0x3 0x1
#define MX35_PAD_FEC_MDC__GPIO3_13 0x2fc 0x760 0x8f8 0x5 0x1
#define MX35_PAD_FEC_MDC__IPU_DISPB_WR 0x2fc 0x760 0x000 0x6 0x0
#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 0x2fc 0x760 0x000 0x7 0x0
#define MX35_PAD_FEC_MDIO__FEC_MDIO 0x300 0x764 0x000 0x0 0x0
#define MX35_PAD_FEC_MDIO__CAN2_RXCAN 0x300 0x764 0x7cc 0x1 0x2
#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 0x300 0x764 0x9e0 0x3 0x1
#define MX35_PAD_FEC_MDIO__GPIO3_14 0x300 0x764 0x8fc 0x5 0x1
#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD 0x300 0x764 0x000 0x6 0x0
#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 0x300 0x764 0x000 0x7 0x0
#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x304 0x768 0x000 0x0 0x0
#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE 0x304 0x768 0x990 0x1 0x2
#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK 0x304 0x768 0x994 0x2 0x4
#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 0x304 0x768 0x9e4 0x3 0x1
#define MX35_PAD_FEC_TX_ERR__GPIO3_15 0x304 0x768 0x900 0x5 0x1
#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC 0x304 0x768 0x924 0x6 0x3
#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 0x304 0x768 0x000 0x7 0x0
#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x308 0x76c 0x000 0x0 0x0
#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 0x308 0x76c 0x930 0x1 0x3
#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 0x308 0x76c 0x9e8 0x3 0x1
#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 0x308 0x76c 0x960 0x4 0x1
#define MX35_PAD_FEC_RX_ERR__GPIO3_16 0x308 0x76c 0x000 0x5 0x0
#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO 0x308 0x76c 0x92c 0x6 0x5
#define MX35_PAD_FEC_CRS__FEC_CRS 0x30c 0x770 0x000 0x0 0x0
#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 0x30c 0x770 0x934 0x1 0x3
#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR 0x30c 0x770 0x000 0x3 0x0
#define MX35_PAD_FEC_CRS__KPP_COL_5 0x30c 0x770 0x964 0x4 0x1
#define MX35_PAD_FEC_CRS__GPIO3_17 0x30c 0x770 0x000 0x5 0x0
#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE 0x30c 0x770 0x000 0x6 0x0
#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x310 0x774 0x000 0x0 0x0
#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 0x310 0x774 0x938 0x1 0x4
#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC 0x310 0x774 0x000 0x2 0x0
#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC 0x310 0x774 0x9f4 0x3 0x2
#define MX35_PAD_FEC_RDATA1__KPP_COL_6 0x310 0x774 0x968 0x4 0x1
#define MX35_PAD_FEC_RDATA1__GPIO3_18 0x310 0x774 0x000 0x5 0x0
#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 0x310 0x774 0x000 0x6 0x0
#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x314 0x778 0x000 0x0 0x0
#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 0x314 0x778 0x93c 0x1 0x4
#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS 0x314 0x778 0x7bc 0x2 0x1
#define MX35_PAD_FEC_TDATA1__KPP_COL_7 0x314 0x778 0x96c 0x4 0x1
#define MX35_PAD_FEC_TDATA1__GPIO3_19 0x314 0x778 0x000 0x5 0x0
#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 0x314 0x778 0x000 0x6 0x0
#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x318 0x77c 0x000 0x0 0x0
#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 0x318 0x77c 0x940 0x1 0x3
#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD 0x318 0x77c 0x7b4 0x2 0x1
#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 0x318 0x77c 0x980 0x4 0x1
#define MX35_PAD_FEC_RDATA2__GPIO3_20 0x318 0x77c 0x000 0x5 0x0
#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x31c 0x780 0x000 0x0 0x0
#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 0x31c 0x780 0x944 0x1 0x3
#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD 0x31c 0x780 0x7b0 0x2 0x1
#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 0x31c 0x780 0x984 0x4 0x1
#define MX35_PAD_FEC_TDATA2__GPIO3_21 0x31c 0x780 0x000 0x5 0x0
#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x320 0x784 0x000 0x0 0x0
#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 0x320 0x784 0x948 0x1 0x3
#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC 0x320 0x784 0x7c0 0x2 0x1
#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 0x320 0x784 0x988 0x4 0x1
#define MX35_PAD_FEC_RDATA3__GPIO3_22 0x320 0x784 0x000 0x6 0x0
#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x324 0x788 0x000 0x0 0x0
#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 0x324 0x788 0x94c 0x1 0x3
#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS 0x324 0x788 0x7c4 0x2 0x1
#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 0x324 0x788 0x98c 0x4 0x1
#define MX35_PAD_FEC_TDATA3__GPIO3_23 0x324 0x788 0x000 0x5 0x0
#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK 0x000 0x78c 0x000 0x0 0x0
#define MX35_PAD_TEST_MODE__TCU_TEST_MODE 0x000 0x790 0x000 0x0 0x0
#endif /* __DTS_IMX35_PINFUNC_H */
......@@ -222,13 +222,13 @@ &iomuxc {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
MX51_PAD_GPIO1_0__SD1_CD 0x20d5
MX51_PAD_GPIO1_1__SD1_WP 0x20d5
MX51_PAD_GPIO1_5__GPIO1_5 0x100
MX51_PAD_GPIO1_6__GPIO1_6 0x100
MX51_PAD_EIM_A27__GPIO2_21 0x5
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
>;
};
};
......
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX51_PINFUNC_H
#define __DTS_IMX51_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0
#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0
#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0
#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0
#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0
#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1
#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0
#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0
#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0
#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0
#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0
#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0
#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0
#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0
#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0
#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0
#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0
#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0
#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0
#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0
#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0
#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0
#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0
#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0
#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0
#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0
#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0
#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0
#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0
#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0
#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0
#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0
#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0
#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0
#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0
#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0
#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0
#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0
#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0
#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0
#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0
#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0
#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0
#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0
#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0
#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0
#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0
#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3
#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0
#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0
#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0
#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0
#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0
#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0
#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0
#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0
#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0
#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0
#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0
#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0
#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0
#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0
#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0
#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0
#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0
#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0
#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0
#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0
#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0
#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0
#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0
#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0
#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0
#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0
#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0
#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0
#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0
#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0
#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0
#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0
#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0
#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0
#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0
#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0
#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0
#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0
#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0
#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0
#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0
#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0
#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0
#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0
#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0
#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0
#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0
#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0
#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0
#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0
#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0
#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0
#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0
#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0
#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0
#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0
#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0
#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0
#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0
#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0
#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0
#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0
#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0
#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0
#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0
#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0
#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0
#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0
#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0
#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0
#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0
#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0
#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0
#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0
#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0
#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0
#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0
#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1
#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0
#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0
#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0
#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0
#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0
#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1
#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0
#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0
#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0
#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0
#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0
#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1
#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0
#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0
#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0
#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0
#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0
#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1
#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0
#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0
#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0
#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0
#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0
#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0
#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0
#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0
#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0
#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0
#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0
#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0
#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0
#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0
#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0
#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0
#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0
#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0
#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0
#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0
#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0
#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0
#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0
#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0
#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0
#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0
#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0
#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0
#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0
#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0
#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0
#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0
#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0
#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0
#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0
#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0
#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0
#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0
#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0
#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0
#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0
#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0
#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0
#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0
#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0
#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0
#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0
#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0
#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0
#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0
#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0
#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0
#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0
#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0
#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0
#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0
#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0
#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0
#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0
#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0
#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0
#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0
#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0
#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0
#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0
#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0
#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0
#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0
#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0
#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0
#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0
#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1
#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0
#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0
#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0
#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0
#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0
#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1
#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0
#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0
#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0
#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1
#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0
#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0
#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0
#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0
#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1
#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0
#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0
#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0
#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0
#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1
#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0
#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0
#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0
#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0
#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0
#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0
#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0
#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0
#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0
#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0
#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0
#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0
#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0
#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0
#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0
#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0
#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0
#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0
#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0
#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0
#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0
#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0
#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0
#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0
#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0
#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0
#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0
#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0
#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0
#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0
#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0
#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0
#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0
#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1
#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0
#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0
#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0
#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0
#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0
#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0
#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0
#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0
#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0
#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0
#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0
#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0
#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0
#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0
#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0
#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0
#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0
#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0
#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0
#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0
#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0
#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0
#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0
#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0
#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0
#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0
#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0
#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0
#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0
#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0
#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0
#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2
#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0
#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0
#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0
#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1
#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1
#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0
#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1
#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1
#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0
#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1
#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0
#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1
#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0
#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0
#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0
#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0
#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0
#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0
#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0
#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0
#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0
#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0
#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0
#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2
#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0
#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0
#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0
#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0
#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0
#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0
#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4
#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0
#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0
#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0
#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0
#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0
#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0
#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0
#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0
#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0
#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0
#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0
#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0
#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0
#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0
#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0
#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1
#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0
#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0
#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0
#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4
#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1
#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0
#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0
#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0
#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1
#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0
#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2
#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0
#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1
#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2
#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0
#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0
#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0
#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6
#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0
#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0
#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0
#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0
#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4
#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5
#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0
#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1
#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1
#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0
#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0
#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1
#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1
#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0
#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1
#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0
#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0
#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0
#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1
#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1
#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0
#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1
#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1
#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0
#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1
#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 0x2c8 0x6c8 0x000 0x2 0x0
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0
#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0
#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0
#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0
#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0
#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1
#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1
#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0
#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0
#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1
#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1
#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0
#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0
#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1
#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0
#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1
#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0
#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1
#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1
#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8
#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1
#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1
#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1
#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1
#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1
#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1
#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1
#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1
#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1
#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1
#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1
#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1
#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1
#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0
#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1
#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1
#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1
#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1
#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1
#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1
#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1
#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1
#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1
#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1
#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2
#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0
#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1
#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2
#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2
#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1
#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0
#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2
#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0
#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2
#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0
#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2
#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1
#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0
#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0
#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0
#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0
#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2
#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0
#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0
#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0
#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3
#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2
#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0
#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3
#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2
#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3
#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0
#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0
#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1
#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0
#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0
#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0
#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3
#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1
#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0
#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0
#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3
#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1
#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0
#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0
#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1
#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1
#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0
#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0
#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0
#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0
#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0
#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0
#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0
#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0
#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0
#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0
#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0
#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0
#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0
#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2
#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0
#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0
#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0
#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0
#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0
#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0
#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0
#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0
#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0
#endif /* __DTS_IMX51_PINFUNC_H */
......@@ -11,6 +11,7 @@
*/
#include "skeleton.dtsi"
#include "imx51-pinfunc.h"
/ {
aliases {
......@@ -251,10 +252,10 @@ iomuxc: iomuxc@73fa8000 {
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
>;
};
};
......@@ -262,46 +263,46 @@ pinctrl_audmux_1: audmuxgrp-1 {
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
>;
};
pinctrl_fec_2: fecgrp-2 {
fsl,pins = <
589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */
592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */
594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */
596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */
598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */
604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */
644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
>;
};
};
......@@ -309,9 +310,9 @@ pinctrl_fec_2: fecgrp-2 {
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
>;
};
};
......@@ -319,12 +320,12 @@ pinctrl_ecspi1_1: ecspi1grp-1 {
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp-1 {
fsl,pins = <
666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
>;
};
};
......@@ -332,12 +333,12 @@ pinctrl_esdhc1_1: esdhc1grp-1 {
esdhc2 {
pinctrl_esdhc2_1: esdhc2grp-1 {
fsl,pins = <
704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
>;
};
};
......@@ -345,8 +346,8 @@ pinctrl_esdhc2_1: esdhc2grp-1 {
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
>;
};
};
......@@ -354,32 +355,32 @@ pinctrl_i2c2_1: i2c2grp-1 {
ipu_disp1 {
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
fsl,pins = <
528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
>;
};
};
......@@ -387,26 +388,26 @@ pinctrl_ipu_disp1_1: ipudisp1grp-1 {
ipu_disp2 {
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
fsl,pins = <
603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
MX51_PAD_DI_GP4__DI2_PIN15 0x5
>;
};
};
......@@ -414,10 +415,10 @@ pinctrl_ipu_disp2_1: ipudisp2grp-1 {
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
>;
};
};
......@@ -425,8 +426,8 @@ pinctrl_uart1_1: uart1grp-1 {
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
>;
};
};
......@@ -434,17 +435,17 @@ pinctrl_uart2_1: uart2grp-1 {
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
>;
};
pinctrl_uart3_2: uart3grp-2 {
fsl,pins = <
434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */
430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
>;
};
};
......@@ -452,14 +453,14 @@ pinctrl_uart3_2: uart3grp-2 {
kpp {
pinctrl_kpp_1: kppgrp-1 {
fsl,pins = <
438 0xe0 /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
439 0xe0 /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
440 0xe0 /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
441 0xe0 /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
442 0xe8 /* MX51_PAD_KEY_COL0__KEY_COL0 */
444 0xe8 /* MX51_PAD_KEY_COL1__KEY_COL1 */
446 0xe8 /* MX51_PAD_KEY_COL2__KEY_COL2 */
448 0xe8 /* MX51_PAD_KEY_COL3__KEY_COL3 */
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
>;
};
};
......
......@@ -112,40 +112,40 @@ &iomuxc {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
MX53_PAD_GPIO_1__GPIO1_1 0x80000000
MX53_PAD_GPIO_9__GPIO1_9 0x80000000
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
MX53_PAD_GPIO_10__GPIO4_0 0x80000000
MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000
MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000
MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000
MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000
MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000
MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000
MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000
MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000
MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000
MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000
MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000
MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000
MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000
MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000
MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000
MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000
MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000
MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000
MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000
MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000
MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
>;
};
};
......
......@@ -82,14 +82,14 @@ &iomuxc {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
MX53_PAD_EIM_D19__GPIO3_19 0x80000000
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
MX53_PAD_EIM_DA14__GPIO3_14 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
>;
};
};
......
......@@ -21,51 +21,57 @@ / {
&iomuxc {
lvds1 {
pinctrl_lvds1_1: lvds1-grp1 {
fsl,pins = <730 0x10000 /* LVDS0_TX3 */
732 0x10000 /* LVDS0_CLK */
734 0x10000 /* LVDS0_TX2 */
736 0x10000 /* LVDS0_TX1 */
738 0x10000>; /* LVDS0_TX0 */
fsl,pins = <
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
>;
};
pinctrl_lvds1_2: lvds1-grp2 {
fsl,pins = <720 0x10000 /* LVDS1_TX3 */
722 0x10000 /* LVDS1_TX2 */
724 0x10000 /* LVDS1_CLK */
726 0x10000 /* LVDS1_TX1 */
728 0x10000>; /* LVDS1_TX0 */
fsl,pins = <
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
>;
};
};
disp1 {
pinctrl_disp1_1: disp1-grp1 {
fsl,pins = <689 0x10000 /* DISP1_DRDY */
482 0x10000 /* DISP1_HSYNC */
489 0x10000 /* DISP1_VSYNC */
515 0x10000 /* DISP1_DAT_22 */
523 0x10000 /* DISP1_DAT_23 */
545 0x10000 /* DISP1_DAT_21 */
553 0x10000 /* DISP1_DAT_20 */
558 0x10000 /* DISP1_DAT_19 */
564 0x10000 /* DISP1_DAT_18 */
570 0x10000 /* DISP1_DAT_17 */
575 0x10000 /* DISP1_DAT_16 */
580 0x10000 /* DISP1_DAT_15 */
585 0x10000 /* DISP1_DAT_14 */
590 0x10000 /* DISP1_DAT_13 */
595 0x10000 /* DISP1_DAT_12 */
628 0x10000 /* DISP1_DAT_11 */
634 0x10000 /* DISP1_DAT_10 */
639 0x10000 /* DISP1_DAT_9 */
644 0x10000 /* DISP1_DAT_8 */
649 0x10000 /* DISP1_DAT_7 */
654 0x10000 /* DISP1_DAT_6 */
659 0x10000 /* DISP1_DAT_5 */
664 0x10000 /* DISP1_DAT_4 */
669 0x10000 /* DISP1_DAT_3 */
674 0x10000 /* DISP1_DAT_2 */
679 0x10000 /* DISP1_DAT_1 */
684 0x10000>; /* DISP1_DAT_0 */
fsl,pins = <
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */
MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */
MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000
>;
};
};
};
......
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX53_PINFUNC_H
#define __DTS_IMX53_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0
#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0
#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0
#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0
#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0
#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0
#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0
#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0
#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1
#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0
#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0
#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0
#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0
#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0
#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0
#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0
#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0
#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0
#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0
#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0
#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0
#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1
#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0
#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0
#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0
#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0
#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0
#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0
#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0
#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0
#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0
#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0
#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0
#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0
#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0
#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0
#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0
#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0
#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0
#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0
#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0
#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0
#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0
#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0
#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0
#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0
#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0
#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0
#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0
#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0
#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0
#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0
#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0
#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0
#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0
#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0
#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0
#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0
#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0
#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0
#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0
#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0
#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0
#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0
#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0
#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0
#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0
#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0
#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0
#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0
#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0
#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0
#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0
#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0
#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0
#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0
#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0
#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0
#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0
#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0
#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0
#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0
#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0
#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0
#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0
#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0
#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0
#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0
#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0
#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0
#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0
#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0
#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0
#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0
#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0
#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0
#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0
#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0
#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0
#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0
#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0
#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0
#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0
#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0
#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0
#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0
#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0
#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0
#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0
#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0
#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0
#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0
#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0
#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0
#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0
#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0
#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0
#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0
#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0
#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0
#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0
#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0
#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0
#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0
#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1
#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0
#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0
#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1
#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0
#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0
#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1
#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0
#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0
#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1
#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0
#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0
#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1
#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0
#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1
#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0
#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1
#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0
#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1
#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0
#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0
#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0
#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0
#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1
#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0
#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0
#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0
#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0
#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0
#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0
#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0
#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0
#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0
#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0
#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0
#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0
#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0
#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0
#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0
#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0
#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0
#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0
#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0
#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0
#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0
#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0
#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0
#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1
#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2
#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0
#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2
#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0
#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2
#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0
#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2
#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0
#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1
#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0
#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0
#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1
#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0
#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0
#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1
#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1
#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1
#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0
#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3
#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0
#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3
#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0
#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0
#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2
#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0
#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0
#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0
#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0
#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0
#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0
#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0
#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0
#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0
#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0
#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0
#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0
#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1
#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0
#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0
#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0
#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0
#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0
#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0
#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3
#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1
#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0
#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0
#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0
#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0
#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3
#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1
#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0
#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0
#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0
#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0
#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3
#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0
#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0
#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0
#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0
#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1
#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3
#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0
#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0
#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0
#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0
#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0
#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0
#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2
#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0
#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0
#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0
#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0
#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0
#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0
#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0
#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1
#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0
#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1
#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0
#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0
#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0
#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0
#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0
#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1
#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1
#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1
#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0
#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0
#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0
#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0
#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1
#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0
#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0
#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0
#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0
#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0
#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0
#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0
#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0
#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0
#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0
#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0
#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1
#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0
#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0
#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0
#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0
#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0
#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0
#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0
#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1
#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1
#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1
#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0
#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0
#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0
#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0
#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1
#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1
#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1
#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1
#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0
#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0
#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0
#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0
#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0
#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0
#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0
#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0
#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0
#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0
#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0
#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0
#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1
#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0
#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0
#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0
#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0
#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0
#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0
#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0
#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0
#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1
#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1
#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1
#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0
#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0
#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0
#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0
#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1
#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0
#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2
#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0
#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0
#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0
#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0
#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0
#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0
#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0
#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0
#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0
#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0
#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1
#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0
#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0
#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3
#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0
#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0
#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0
#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0
#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0
#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0
#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0
#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0
#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0
#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0
#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0
#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0
#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0
#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0
#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0
#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0
#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0
#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0
#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0
#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0
#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0
#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0
#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0
#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0
#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0
#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0
#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0
#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0
#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0
#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0
#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0
#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0
#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0
#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0
#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0
#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0
#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0
#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0
#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0
#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0
#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0
#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0
#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0
#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0
#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0
#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0
#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0
#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0
#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0
#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0
#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0
#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0
#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0
#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0
#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2
#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0
#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0
#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0
#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2
#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0
#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0
#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0
#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2
#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0
#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0
#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0
#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0
#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2
#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0
#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0
#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0
#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0
#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1
#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0
#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0
#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0
#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0
#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0
#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0
#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0
#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0
#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0
#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0
#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0
#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0
#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0
#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0
#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0
#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0
#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0
#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0
#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0
#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0
#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0
#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0
#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0
#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0
#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0
#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0
#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0
#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0
#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0
#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0
#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0
#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0
#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0
#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0
#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0
#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0
#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0
#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0
#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0
#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0
#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0
#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0
#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0
#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0
#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0
#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0
#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0
#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0
#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0
#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0
#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0
#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0
#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0
#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0
#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0
#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0
#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0
#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0
#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0
#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0
#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0
#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0
#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0
#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0
#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0
#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0
#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1
#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0
#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0
#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0
#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0
#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1
#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0
#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0
#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0
#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1
#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0
#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0
#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0
#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1
#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0
#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0
#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0
#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0
#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0
#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0
#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0
#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0
#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0
#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0
#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0
#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0
#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0
#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0
#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0
#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0
#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0
#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0
#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0
#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0
#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0
#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0
#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0
#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0
#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0
#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0
#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0
#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0
#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0
#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0
#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0
#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0
#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0
#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0
#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0
#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0
#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0
#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0
#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0
#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0
#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0
#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0
#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0
#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0
#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0
#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0
#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0
#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0
#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0
#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0
#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0
#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0
#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0
#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0
#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0
#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0
#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0
#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0
#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0
#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0
#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0
#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0
#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0
#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0
#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0
#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0
#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0
#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0
#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0
#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0
#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0
#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0
#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0
#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0
#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0
#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1
#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0
#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0
#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1
#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0
#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0
#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0
#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0
#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0
#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0
#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0
#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0
#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0
#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0
#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0
#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1
#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0
#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0
#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0
#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0
#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0
#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0
#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0
#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1
#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0
#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0
#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0
#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0
#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0
#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0
#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0
#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0
#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0
#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0
#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0
#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1
#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0
#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0
#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0
#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0
#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0
#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0
#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0
#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0
#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1
#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0
#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0
#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0
#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0
#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0
#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0
#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0
#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0
#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3
#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0
#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0
#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0
#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0
#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0
#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0
#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0
#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0
#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3
#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0
#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0
#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0
#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0
#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0
#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0
#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0
#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0
#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0
#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0
#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3
#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1
#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0
#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0
#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0
#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0
#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0
#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0
#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0
#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0
#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0
#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0
#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3
#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1
#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0
#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0
#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0
#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0
#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0
#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0
#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0
#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0
#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0
#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0
#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0
#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0
#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0
#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0
#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5
#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0
#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0
#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0
#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0
#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0
#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0
#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0
#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3
#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0
#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0
#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0
#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0
#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0
#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0
#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0
#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0
#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0
#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0
#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0
#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0
#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0
#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0
#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0
#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0
#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0
#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0
#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0
#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0
#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2
#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0
#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0
#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0
#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0
#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3
#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1
#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0
#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0
#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0
#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2
#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0
#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0
#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0
#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0
#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0
#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0
#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2
#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0
#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0
#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0
#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0
#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0
#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0
#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2
#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0
#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0
#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0
#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0
#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0
#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0
#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2
#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0
#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0
#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0
#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0
#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2
#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1
#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3
#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0
#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0
#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0
#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1
#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1
#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3
#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0
#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0
#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0
#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1
#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1
#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3
#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0
#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0
#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0
#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1
#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1
#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3
#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0
#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0
#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0
#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1
#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x0
#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4
#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0
#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0
#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0
#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1
#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1
#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3
#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0
#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0
#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0
#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3
#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0
#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0
#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0
#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0
#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0
#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1
#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0
#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2
#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0
#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0
#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0
#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0
#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0
#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1
#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0
#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2
#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0
#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0
#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0
#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1
#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0
#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1
#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0
#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1
#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0
#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0
#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0
#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1
#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2
#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1
#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0
#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1
#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0
#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0
#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0
#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0
#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2
#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1
#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0
#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2
#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0
#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0
#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0
#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0
#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2
#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1
#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0
#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2
#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0
#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0
#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0
#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0
#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0
#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1
#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0
#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2
#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0
#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0
#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0
#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2
#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1
#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1
#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0
#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0
#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0
#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0
#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1
#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0
#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1
#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1
#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0
#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0
#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2
#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5
#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0
#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0
#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1
#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1
#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0
#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0
#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0
#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1
#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2
#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0
#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1
#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0
#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1
#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1
#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0
#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0
#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0
#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0
#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1
#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0
#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1
#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1
#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0
#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1
#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0
#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0
#endif /* __DTS_IMX53_PINFUNC_H */
......@@ -110,21 +110,21 @@ &iomuxc {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
MX53_PAD_GPIO_8__GPIO1_8 0x80000000
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
>;
};
led_pin_gpio7_7: led_gpio7_7@0 {
fsl,pins = <
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
>;
};
};
......
......@@ -107,13 +107,13 @@ &iomuxc {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
MX53_PAD_EIM_D19__GPIO3_19 0x80000000
MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
>;
};
};
......
......@@ -72,11 +72,11 @@ &iomuxc {
i2s {
pinctrl_i2s_1: i2s-grp1 {
fsl,pins = <
1 0x10000 /* I2S_MCLK */
10 0x10000 /* I2S_SCLK */
17 0x10000 /* I2S_DOUT */
23 0x10000 /* I2S_LRCLK*/
30 0x10000 /* I2S_DIN */
MX53_PAD_GPIO_19__GPIO4_5 0x10000 /* I2S_MCLK */
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x10000 /* I2S_SCLK */
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x10000 /* I2S_DOUT */
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x10000 /* I2S_DIN */
>;
};
};
......@@ -84,16 +84,16 @@ pinctrl_i2s_1: i2s-grp1 {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
610 0x10000 /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (VSYNC)*/
711 0x10000 /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (HSYNC)*/
873 0x10000 /* MX53_PAD_PATA_DA_1__GPIO7_7 (LCD_BLT_EN)*/
878 0x10000 /* MX53_PAD_PATA_DA_2__GPIO7_8 (LCD_RESET)*/
922 0x10000 /* MX53_PAD_PATA_DATA5__GPIO2_5 (LCD_POWER)*/
928 0x10000 /* MX53_PAD_PATA_DATA6__GPIO2_6 (PMIC_INT)*/
982 0x10000 /* MX53_PAD_PATA_DATA14__GPIO2_14 (CSI_RST)*/
989 0x10000 /* MX53_PAD_PATA_DATA15__GPIO2_15 (CSI_PWDN)*/
1069 0x10000 /* MX53_PAD_GPIO_0__GPIO1_0 (SYSTEM_DOWN)*/
1093 0x10000 /* MX53_PAD_GPIO_3__GPIO1_3 */
MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x10000 /* VSYNC */
MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */
MX53_PAD_PATA_DA_1__GPIO7_7 0x10000 /* LCD_BLT_EN */
MX53_PAD_PATA_DA_2__GPIO7_8 0x10000 /* LCD_RESET */
MX53_PAD_PATA_DATA5__GPIO2_5 0x10000 /* LCD_POWER */
MX53_PAD_PATA_DATA6__GPIO2_6 0x10000 /* PMIC_INT */
MX53_PAD_PATA_DATA14__GPIO2_14 0x10000 /* CSI_RST */
MX53_PAD_PATA_DATA15__GPIO2_15 0x10000 /* CSI_PWDN */
MX53_PAD_GPIO_0__GPIO1_0 0x10000 /* SYSTEM_DOWN */
MX53_PAD_GPIO_3__GPIO1_3 0x10000
>;
};
};
......
......@@ -11,6 +11,7 @@
*/
#include "skeleton.dtsi"
#include "imx53-pinfunc.h"
/ {
aliases {
......@@ -249,10 +250,10 @@ iomuxc: iomuxc@53fa8000 {
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
>;
};
};
......@@ -260,16 +261,16 @@ pinctrl_audmux_1: audmuxgrp-1 {
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
>;
};
};
......@@ -277,27 +278,27 @@ pinctrl_fec_1: fecgrp-1 {
csi {
pinctrl_csi_1: csigrp-1 {
fsl,pins = <
286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
>;
};
};
......@@ -305,9 +306,9 @@ pinctrl_csi_1: csigrp-1 {
cspi {
pinctrl_cspi_1: cspigrp-1 {
fsl,pins = <
998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */
1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */
1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */
MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
>;
};
};
......@@ -315,9 +316,9 @@ pinctrl_cspi_1: cspigrp-1 {
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
>;
};
};
......@@ -325,27 +326,27 @@ pinctrl_ecspi1_1: ecspi1grp-1 {
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp-1 {
fsl,pins = <
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_esdhc1_2: esdhc1grp-2 {
fsl,pins = <
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
};
......@@ -353,12 +354,12 @@ pinctrl_esdhc1_2: esdhc1grp-2 {
esdhc2 {
pinctrl_esdhc2_1: esdhc2grp-1 {
fsl,pins = <
1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
>;
};
};
......@@ -366,16 +367,16 @@ pinctrl_esdhc2_1: esdhc2grp-1 {
esdhc3 {
pinctrl_esdhc3_1: esdhc3grp-1 {
fsl,pins = <
943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
>;
};
};
......@@ -383,15 +384,15 @@ pinctrl_esdhc3_1: esdhc3grp-1 {
can1 {
pinctrl_can1_1: can1grp-1 {
fsl,pins = <
847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
>;
};
pinctrl_can1_2: can1grp-2 {
fsl,pins = <
37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
>;
};
};
......@@ -399,8 +400,8 @@ pinctrl_can1_2: can1grp-2 {
can2 {
pinctrl_can2_1: can2grp-1 {
fsl,pins = <
67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
>;
};
};
......@@ -408,8 +409,8 @@ pinctrl_can2_1: can2grp-1 {
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
>;
};
};
......@@ -417,8 +418,8 @@ pinctrl_i2c1_1: i2c1grp-1 {
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
>;
};
};
......@@ -426,8 +427,8 @@ pinctrl_i2c2_1: i2c2grp-1 {
i2c3 {
pinctrl_i2c3_1: i2c3grp-1 {
fsl,pins = <
1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
>;
};
};
......@@ -435,7 +436,7 @@ pinctrl_i2c3_1: i2c3grp-1 {
owire {
pinctrl_owire_1: owiregrp-1 {
fsl,pins = <
1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */
MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
>;
};
};
......@@ -443,15 +444,15 @@ pinctrl_owire_1: owiregrp-1 {
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
>;
};
pinctrl_uart1_2: uart1grp-2 {
fsl,pins = <
828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
>;
};
};
......@@ -459,8 +460,8 @@ pinctrl_uart1_2: uart1grp-2 {
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
>;
};
};
......@@ -468,17 +469,17 @@ pinctrl_uart2_1: uart2grp-1 {
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
>;
};
pinctrl_uart3_2: uart3grp-2 {
fsl,pins = <
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
>;
};
......@@ -487,8 +488,8 @@ pinctrl_uart3_2: uart3grp-2 {
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
>;
};
};
......@@ -496,8 +497,8 @@ pinctrl_uart4_1: uart4grp-1 {
uart5 {
pinctrl_uart5_1: uart5grp-1 {
fsl,pins = <
24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
>;
};
};
......
......@@ -57,7 +57,7 @@ &iomuxc {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000
>;
};
};
......@@ -65,8 +65,8 @@ pinctrl_hog: hoggrp {
arm2 {
pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
fsl,pins = <
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
>;
};
};
......
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX6Q_PINFUNC_H
#define __DTS_IMX6Q_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
#define MX6Q_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
#define MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
#define MX6Q_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
#define MX6Q_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
#define MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
#define MX6Q_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
#define MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
#define MX6Q_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0
#define MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0
#define MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0
#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0
#define MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0
#define MX6Q_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0
#define MX6Q_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0
#define MX6Q_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0
#define MX6Q_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
#define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
#define MX6Q_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0
#define MX6Q_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
#define MX6Q_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
#define MX6Q_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
#define MX6Q_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
#define MX6Q_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0
#define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0
#define MX6Q_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0
#define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0
#define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0
#define MX6Q_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0
#define MX6Q_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0
#define MX6Q_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0
#define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0
#define MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0
#define MX6Q_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0
#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0
#define MX6Q_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0
#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0
#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0
#define MX6Q_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0
#define MX6Q_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0
#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0
#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0
#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0
#define MX6Q_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0
#define MX6Q_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0
#define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0
#define MX6Q_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0
#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0
#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0
#define MX6Q_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0
#define MX6Q_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0
#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0
#define MX6Q_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0
#define MX6Q_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0
#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0
#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0
#define MX6Q_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0
#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0
#define MX6Q_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0
#define MX6Q_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0
#define MX6Q_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0
#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0
#define MX6Q_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1
#define MX6Q_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0
#define MX6Q_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0
#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0
#define MX6Q_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0
#define MX6Q_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0
#define MX6Q_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0
#define MX6Q_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0
#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0
#define MX6Q_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0
#define MX6Q_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0
#define MX6Q_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0
#define MX6Q_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0
#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0
#define MX6Q_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0
#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0
#define MX6Q_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0
#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0
#define MX6Q_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1
#define MX6Q_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0
#define MX6Q_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0
#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0
#define MX6Q_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0
#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0
#define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0
#define MX6Q_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0
#define MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0
#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0
#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0
#define MX6Q_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0
#define MX6Q_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0
#define MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1
#define MX6Q_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0
#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0
#define MX6Q_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0
#define MX6Q_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0
#define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0
#define MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0
#define MX6Q_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0
#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0
#define MX6Q_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0
#define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0
#define MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1
#define MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0
#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0
#define MX6Q_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0
#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0
#define MX6Q_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0
#define MX6Q_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0
#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0
#define MX6Q_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0
#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
#define MX6Q_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
#define MX6Q_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
#define MX6Q_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0
#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0
#define MX6Q_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2
#define MX6Q_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0
#define MX6Q_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0
#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0
#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0
#define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0
#define MX6Q_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3
#define MX6Q_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0
#define MX6Q_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0
#define MX6Q_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0
#define MX6Q_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0
#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0
#define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1
#define MX6Q_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0
#define MX6Q_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0
#define MX6Q_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0
#define MX6Q_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0
#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
#define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1
#define MX6Q_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0
#define MX6Q_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0
#define MX6Q_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0
#define MX6Q_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0
#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0
#define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1
#define MX6Q_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0
#define MX6Q_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0
#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0
#define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1
#define MX6Q_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0
#define MX6Q_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0
#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0
#define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1
#define MX6Q_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0
#define MX6Q_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0
#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0
#define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1
#define MX6Q_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0
#define MX6Q_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0
#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0
#define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1
#define MX6Q_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0
#define MX6Q_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0
#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0
#define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1
#define MX6Q_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0
#define MX6Q_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0
#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0
#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1
#define MX6Q_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0
#define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0
#define MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0
#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0
#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0
#define MX6Q_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0
#define MX6Q_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0
#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0
#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0
#define MX6Q_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0
#define MX6Q_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0
#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0
#define MX6Q_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0
#define MX6Q_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0
#define MX6Q_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0
#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0
#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0
#define MX6Q_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0
#define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0
#define MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0
#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0
#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0
#define MX6Q_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0
#define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0
#define MX6Q_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0
#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0
#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1
#define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0
#define MX6Q_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0
#define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0
#define MX6Q_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0
#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0
#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1
#define MX6Q_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0
#define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1
#define MX6Q_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1
#define MX6Q_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1
#define MX6Q_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0
#define MX6Q_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0
#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0
#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0
#define MX6Q_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0
#define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0
#define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0
#define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0
#define MX6Q_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0
#define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0
#define MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0
#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0
#define MX6Q_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0
#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0
#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0
#define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0
#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0
#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0
#define MX6Q_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0
#define MX6Q_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0
#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0
#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0
#define MX6Q_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0
#define MX6Q_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0
#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0
#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0
#define MX6Q_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0
#define MX6Q_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0
#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0
#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0
#define MX6Q_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0
#define MX6Q_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0
#define MX6Q_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0
#define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0
#define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0
#define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0
#define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0
#define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0
#define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0
#define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0
#define MX6Q_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0
#define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0
#define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0
#define MX6Q_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0
#define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0
#define MX6Q_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0
#define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1
#define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1
#define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1
#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1
#define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1
#define MX6Q_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0
#define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0
#define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1
#define MX6Q_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0
#define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0
#define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1
#define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0
#define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0
#define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0
#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1
#define MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0
#define MX6Q_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0
#define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0
#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1
#define MX6Q_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0
#define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1
#define MX6Q_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1
#define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1
#define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1
#define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0
#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0
#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0
#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1
#define MX6Q_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1
#define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0
#define MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0
#define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0
#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0
#define MX6Q_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0
#define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0
#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0
#define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
#define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0
#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0
#define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0
#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0
#define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1
#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
#define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0
#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1
#define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0
#define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1
#define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0
#define MX6Q_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0
#define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1
#define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0
#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0
#define MX6Q_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0
#define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1
#define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0
#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0
#define MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0
#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0
#define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0
#define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0
#define MX6Q_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0
#define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0
#define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0
#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0
#define MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0
#define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0
#define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0
#define MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0
#define MX6Q_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0
#define MX6Q_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0
#define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0
#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0
#define MX6Q_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0
#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2
#define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1
#define MX6Q_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1
#define MX6Q_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0
#define MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0
#define MX6Q_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0
#define MX6Q_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0
#define MX6Q_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0
#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2
#define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0
#define MX6Q_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1
#define MX6Q_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0
#define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1
#define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0
#define MX6Q_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0
#define MX6Q_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0
#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2
#define MX6Q_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1
#define MX6Q_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1
#define MX6Q_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0
#define MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0
#define MX6Q_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0
#define MX6Q_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0
#define MX6Q_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0
#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2
#define MX6Q_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0
#define MX6Q_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1
#define MX6Q_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0
#define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1
#define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0
#define MX6Q_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0
#define MX6Q_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0
#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2
#define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1
#define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0
#define MX6Q_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0
#define MX6Q_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0
#define MX6Q_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0
#define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0
#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1
#define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0
#define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0
#define MX6Q_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0
#define MX6Q_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0
#define MX6Q_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0
#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1
#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1
#define MX6Q_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0
#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1
#define MX6Q_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0
#define MX6Q_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1
#define MX6Q_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0
#define MX6Q_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2
#define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0
#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1
#define MX6Q_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0
#define MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1
#define MX6Q_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0
#define MX6Q_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0
#define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0
#define MX6Q_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0
#define MX6Q_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1
#define MX6Q_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0
#define MX6Q_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0
#define MX6Q_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0
#define MX6Q_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0
#define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0
#define MX6Q_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0
#define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0
#define MX6Q_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0
#define MX6Q_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0
#define MX6Q_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1
#define MX6Q_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0
#define MX6Q_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0
#define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1
#define MX6Q_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0
#define MX6Q_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0
#define MX6Q_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0
#define MX6Q_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
#define MX6Q_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
#define MX6Q_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
#define MX6Q_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0
#define MX6Q_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
#define MX6Q_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
#define MX6Q_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1
#define MX6Q_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0
#define MX6Q_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0
#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0
#define MX6Q_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0
#define MX6Q_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1
#define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1
#define MX6Q_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1
#define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0
#define MX6Q_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0
#define MX6Q_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
#define MX6Q_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
#define MX6Q_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
#define MX6Q_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
#define MX6Q_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
#define MX6Q_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1
#define MX6Q_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1
#define MX6Q_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1
#define MX6Q_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0
#define MX6Q_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1
#define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1
#define MX6Q_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1
#define MX6Q_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0
#define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1
#define MX6Q_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1
#define MX6Q_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0
#define MX6Q_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2
#define MX6Q_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0
#define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1
#define MX6Q_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0
#define MX6Q_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0
#define MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0
#define MX6Q_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0
#define MX6Q_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2
#define MX6Q_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0
#define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0
#define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1
#define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0
#define MX6Q_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0
#define MX6Q_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1
#define MX6Q_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3
#define MX6Q_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0
#define MX6Q_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0
#define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0
#define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1
#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0
#define MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1
#define MX6Q_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0
#define MX6Q_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3
#define MX6Q_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2
#define MX6Q_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0
#define MX6Q_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0
#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0
#define MX6Q_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1
#define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1
#define MX6Q_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0
#define MX6Q_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0
#define MX6Q_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1
#define MX6Q_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0
#define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1
#define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2
#define MX6Q_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0
#define MX6Q_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1
#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0
#define MX6Q_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0
#define MX6Q_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0
#define MX6Q_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0
#define MX6Q_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0
#define MX6Q_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0
#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3
#define MX6Q_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2
#define MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0
#define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3
#define MX6Q_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1
#define MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0
#define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3
#define MX6Q_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1
#define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0
#define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3
#define MX6Q_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2
#define MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0
#define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2
#define MX6Q_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2
#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1
#define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2
#define MX6Q_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2
#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1
#define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2
#define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0
#define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2
#define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1
#define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2
#define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3
#define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2
#define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3
#define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0
#define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1
#define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2
#define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0
#define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0
#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0
#define MX6Q_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0
#define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0
#define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3
#define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0
#define MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0
#define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0
#define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2
#define MX6Q_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0
#define MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0
#define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3
#define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0
#define MX6Q_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0
#define MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0
#define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0
#define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4
#define MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0
#define MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0
#define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5
#define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0
#define MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0
#define MX6Q_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0
#define MX6Q_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0
#define MX6Q_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2
#define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0
#define MX6Q_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0
#define MX6Q_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0
#define MX6Q_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3
#define MX6Q_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0
#define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2
#define MX6Q_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0
#define MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0
#define MX6Q_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0
#define MX6Q_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2
#define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0
#define MX6Q_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0
#define MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0
#define MX6Q_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3
#define MX6Q_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0
#define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1
#define MX6Q_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0
#define MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0
#define MX6Q_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0
#define MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0
#define MX6Q_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0
#define MX6Q_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4
#define MX6Q_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0
#define MX6Q_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0
#define MX6Q_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5
#define MX6Q_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0
#define MX6Q_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0
#define MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1
#define MX6Q_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0
#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0
#define MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0
#define MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1
#define MX6Q_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0
#define MX6Q_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0
#define MX6Q_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0
#define MX6Q_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0
#define MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0
#define MX6Q_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2
#define MX6Q_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0
#define MX6Q_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0
#define MX6Q_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0
#define MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3
#define MX6Q_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0
#define MX6Q_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0
#define MX6Q_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0
#define MX6Q_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0
#define MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0
#define MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0
#define MX6Q_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0
#define MX6Q_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0
#define MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0
#define MX6Q_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0
#define MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0
#define MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0
#define MX6Q_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0
#define MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0
#define MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0
#define MX6Q_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0
#define MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0
#define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6
#define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0
#define MX6Q_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0
#define MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0
#define MX6Q_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4
#define MX6Q_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0
#define MX6Q_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0
#define MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0
#define MX6Q_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0
#define MX6Q_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5
#define MX6Q_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0
#define MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0
#define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0
#define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7
#define MX6Q_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0
#define MX6Q_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0
#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1
#define MX6Q_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0
#define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0
#define MX6Q_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0
#define MX6Q_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0
#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1
#define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0
#define MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0
#define MX6Q_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0
#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0
#define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0
#define MX6Q_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0
#define MX6Q_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0
#define MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0
#define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0
#define MX6Q_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0
#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0
#define MX6Q_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
#define MX6Q_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0
#define MX6Q_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0
#define MX6Q_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0
#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1
#define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0
#define MX6Q_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0
#define MX6Q_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0
#define MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0
#define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0
#define MX6Q_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0
#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0
#define MX6Q_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0
#define MX6Q_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0
#define MX6Q_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0
#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1
#define MX6Q_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3
#define MX6Q_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1
#define MX6Q_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0
#define MX6Q_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0
#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1
#define MX6Q_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2
#define MX6Q_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1
#define MX6Q_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0
#define MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0
#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0
#define MX6Q_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2
#define MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1
#define MX6Q_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0
#endif /* __DTS_IMX6Q_PINFUNC_H */
......@@ -29,8 +29,8 @@ &iomuxc {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
>;
};
};
......
......@@ -91,14 +91,14 @@ &iomuxc {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
>;
};
};
......
......@@ -64,12 +64,12 @@ &iomuxc {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000
MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
>;
};
};
......
......@@ -9,6 +9,7 @@
*/
#include "imx6qdl.dtsi"
#include "imx6q-pinfunc.h"
/ {
cpus {
......@@ -78,10 +79,10 @@ iomuxc: iomuxc@020e0000 {
audmux {
pinctrl_audmux_1: audmux-1 {
fsl,pins = <
18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
>;
};
};
......@@ -89,9 +90,9 @@ pinctrl_audmux_1: audmux-1 {
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
};
......@@ -99,42 +100,42 @@ pinctrl_ecspi1_1: ecspi1grp-1 {
enet {
pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_enet_2: enetgrp-2 {
fsl,pins = <
890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};
};
......@@ -142,25 +143,25 @@ pinctrl_enet_2: enetgrp-2 {
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
};
......@@ -168,8 +169,8 @@ pinctrl_gpmi_nand_1: gpmi-nand-1 {
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
};
......@@ -177,8 +178,8 @@ pinctrl_i2c1_1: i2c1grp-1 {
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
};
......@@ -186,8 +187,8 @@ pinctrl_uart1_1: uart1grp-1 {
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
};
......@@ -195,8 +196,8 @@ pinctrl_uart2_1: uart2grp-1 {
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
......@@ -204,13 +205,13 @@ pinctrl_uart4_1: uart4grp-1 {
usbotg {
pinctrl_usbotg_1: usbotggrp-1 {
fsl,pins = <
1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
1591 0x17059 /* MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID */
MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
};
......@@ -218,16 +219,16 @@ pinctrl_usbotg_2: usbotggrp-2 {
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
};
......@@ -235,27 +236,27 @@ pinctrl_usdhc2_1: usdhc2grp-1 {
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3_2: usdhc3grp-2 {
fsl,pins = <
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
};
......@@ -263,27 +264,27 @@ pinctrl_usdhc3_2: usdhc3grp-2 {
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
pinctrl_usdhc4_2: usdhc4grp-2 {
fsl,pins = <
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
>;
};
};
......
......@@ -54,32 +54,6 @@ struct imx_pinctrl {
const struct imx_pinctrl_soc_info *info;
};
static const struct imx_pin_reg *imx_find_pin_reg(
const struct imx_pinctrl_soc_info *info,
unsigned pin, bool is_mux, unsigned mux)
{
const struct imx_pin_reg *pin_reg = NULL;
int i;
for (i = 0; i < info->npin_regs; i++) {
pin_reg = &info->pin_regs[i];
if (pin_reg->pid != pin)
continue;
if (!is_mux)
break;
else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
break;
}
if (i == info->npin_regs) {
dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
info->pins[pin].name);
return NULL;
}
return pin_reg;
}
static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
const struct imx_pinctrl_soc_info *info,
const char *name)
......@@ -223,7 +197,8 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
const unsigned *pins, *mux;
const unsigned *pins, *mux, *input_val;
u16 *input_reg;
unsigned int npins, pin_id;
int i;
......@@ -234,18 +209,17 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
pins = info->groups[group].pins;
npins = info->groups[group].npins;
mux = info->groups[group].mux_mode;
input_val = info->groups[group].input_val;
input_reg = info->groups[group].input_reg;
WARN_ON(!pins || !npins || !mux);
WARN_ON(!pins || !npins || !mux || !input_val || !input_reg);
dev_dbg(ipctl->dev, "enable function %s group %s\n",
info->functions[selector].name, info->groups[group].name);
for (i = 0; i < npins; i++) {
pin_id = pins[i];
pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
if (!pin_reg)
return -EINVAL;
pin_reg = &info->pin_regs[pin_id];
if (!pin_reg->mux_reg) {
dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
......@@ -258,11 +232,11 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
pin_reg->mux_reg, mux[i]);
/* some pins also need select input setting, set it if found */
if (pin_reg->input_reg) {
writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
if (input_reg[i]) {
writel(input_val[i], ipctl->base + input_reg[i]);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin_reg->input_reg, pin_reg->input_val);
input_reg[i], input_val[i]);
}
}
......@@ -311,11 +285,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
if (!pin_reg)
return -EINVAL;
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
if (!pin_reg->conf_reg) {
dev_err(info->dev, "Pin(%s) does not support config function\n",
......@@ -333,11 +303,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
if (!pin_reg)
return -EINVAL;
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
if (!pin_reg->conf_reg) {
dev_err(info->dev, "Pin(%s) does not support config function\n",
......@@ -360,10 +326,9 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
unsigned long config;
pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
if (!pin_reg || !pin_reg->conf_reg) {
seq_printf(s, "N/A");
return;
......@@ -411,29 +376,20 @@ static struct pinctrl_desc imx_pinctrl_desc = {
.owner = THIS_MODULE,
};
/* decode pin id and mux from pin function id got from device tree*/
static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
unsigned int pin_func_id, unsigned int *pin_id,
unsigned int *mux)
{
if (pin_func_id > info->npin_regs)
return -EINVAL;
*pin_id = info->pin_regs[pin_func_id].pid;
*mux = info->pin_regs[pin_func_id].mux_mode;
return 0;
}
/*
* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
* 1 u32 CONFIG, so 24 types in total for each pin.
*/
#define FSL_PIN_SIZE 24
static int imx_pinctrl_parse_groups(struct device_node *np,
struct imx_pin_group *grp,
struct imx_pinctrl_soc_info *info,
u32 index)
{
unsigned int pin_func_id;
int ret, size;
int size;
const __be32 *list;
int i, j;
int i;
u32 config;
dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
......@@ -447,32 +403,40 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
*/
list = of_get_property(np, "fsl,pins", &size);
/* we do not check return since it's safe node passed down */
size /= sizeof(*list);
if (!size || size % 2) {
dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
if (!size || size % FSL_PIN_SIZE) {
dev_err(info->dev, "Invalid fsl,pins property\n");
return -EINVAL;
}
grp->npins = size / 2;
grp->npins = size / FSL_PIN_SIZE;
grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
GFP_KERNEL);
grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
GFP_KERNEL);
grp->input_reg = devm_kzalloc(info->dev, grp->npins * sizeof(u16),
GFP_KERNEL);
grp->input_val = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
GFP_KERNEL);
grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
GFP_KERNEL);
for (i = 0, j = 0; i < size; i += 2, j++) {
pin_func_id = be32_to_cpu(*list++);
ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
&grp->pins[j], &grp->mux_mode[j]);
if (ret) {
dev_err(info->dev, "get invalid pin function id\n");
return -EINVAL;
}
for (i = 0; i < grp->npins; i++) {
u32 mux_reg = be32_to_cpu(*list++);
u32 conf_reg = be32_to_cpu(*list++);
unsigned int pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
grp->pins[i] = pin_id;
pin_reg->mux_reg = mux_reg;
pin_reg->conf_reg = conf_reg;
grp->input_reg[i] = be32_to_cpu(*list++);
grp->mux_mode[i] = be32_to_cpu(*list++);
grp->input_val[i] = be32_to_cpu(*list++);
/* SION bit is in mux register */
config = be32_to_cpu(*list++);
if (config & IMX_PAD_SION)
grp->mux_mode[j] |= IOMUXC_CONFIG_SION;
grp->configs[j] = config & ~IMX_PAD_SION;
grp->mux_mode[i] |= IOMUXC_CONFIG_SION;
grp->configs[i] = config & ~IMX_PAD_SION;
}
#ifdef DEBUG
......@@ -568,8 +532,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
struct resource *res;
int ret;
if (!info || !info->pins || !info->npins
|| !info->pin_regs || !info->npin_regs) {
if (!info || !info->pins || !info->npins) {
dev_err(&pdev->dev, "wrong pinctrl info\n");
return -EINVAL;
}
......@@ -580,6 +543,11 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!ipctl)
return -ENOMEM;
info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) *
info->npins, GFP_KERNEL);
if (!info->pin_regs)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
......
......@@ -26,6 +26,10 @@ struct platform_device;
* elements in .pins so we can iterate over that array
* @mux_mode: the mux mode for each pin in this group. The size of this
* array is the same as pins.
* @input_reg: select input register offset for this mux if any
* 0 if no select input setting needed.
* @input_val: the select input value for each pin in this group. The size of
* this array is the same as pins.
* @configs: the config for each pin in this group. The size of this
* array is the same as pins.
*/
......@@ -34,6 +38,8 @@ struct imx_pin_group {
unsigned int *pins;
unsigned npins;
unsigned int *mux_mode;
u16 *input_reg;
unsigned int *input_val;
unsigned long *configs;
};
......@@ -51,30 +57,19 @@ struct imx_pmx_func {
/**
* struct imx_pin_reg - describe a pin reg map
* The last 3 members are used for select input setting
* @pid: pin id
* @mux_reg: mux register offset
* @conf_reg: config register offset
* @mux_mode: mux mode
* @input_reg: select input register offset for this mux if any
* 0 if no select input setting needed.
* @input_val: the value set to select input register
*/
struct imx_pin_reg {
u16 pid;
u16 mux_reg;
u16 conf_reg;
u8 mux_mode;
u16 input_reg;
u8 input_val;
};
struct imx_pinctrl_soc_info {
struct device *dev;
const struct pinctrl_pin_desc *pins;
unsigned int npins;
const struct imx_pin_reg *pin_regs;
unsigned int npin_regs;
struct imx_pin_reg *pin_regs;
struct imx_pin_group *groups;
unsigned int ngroups;
struct imx_pmx_func *functions;
......@@ -84,16 +79,6 @@ struct imx_pinctrl_soc_info {
#define NO_MUX 0x0
#define NO_PAD 0x0
#define IMX_PIN_REG(id, conf, mux, mode, input, val) \
{ \
.pid = id, \
.conf_reg = conf, \
.mux_reg = mux, \
.mux_mode = mode, \
.input_reg = input, \
.input_val = val, \
}
#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
#define PAD_CTL_MASK(len) ((1 << len) - 1)
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -23,1015 +23,400 @@
#include "pinctrl-imx.h"
enum imx51_pads {
MX51_PAD_EIM_D16 = 0,
MX51_PAD_EIM_D17 = 1,
MX51_PAD_EIM_D18 = 2,
MX51_PAD_EIM_D19 = 3,
MX51_PAD_EIM_D20 = 4,
MX51_PAD_EIM_D21 = 5,
MX51_PAD_EIM_D22 = 6,
MX51_PAD_EIM_D23 = 7,
MX51_PAD_EIM_D24 = 8,
MX51_PAD_EIM_D25 = 9,
MX51_PAD_EIM_D26 = 10,
MX51_PAD_EIM_D27 = 11,
MX51_PAD_EIM_D28 = 12,
MX51_PAD_EIM_D29 = 13,
MX51_PAD_EIM_D30 = 14,
MX51_PAD_EIM_D31 = 15,
MX51_PAD_EIM_A16 = 16,
MX51_PAD_EIM_A17 = 17,
MX51_PAD_EIM_A18 = 18,
MX51_PAD_EIM_A19 = 19,
MX51_PAD_EIM_A20 = 20,
MX51_PAD_EIM_A21 = 21,
MX51_PAD_EIM_A22 = 22,
MX51_PAD_EIM_A23 = 23,
MX51_PAD_EIM_A24 = 24,
MX51_PAD_EIM_A25 = 25,
MX51_PAD_EIM_A26 = 26,
MX51_PAD_EIM_A27 = 27,
MX51_PAD_EIM_EB0 = 28,
MX51_PAD_EIM_EB1 = 29,
MX51_PAD_EIM_EB2 = 30,
MX51_PAD_EIM_EB3 = 31,
MX51_PAD_EIM_OE = 32,
MX51_PAD_EIM_CS0 = 33,
MX51_PAD_EIM_CS1 = 34,
MX51_PAD_EIM_CS2 = 35,
MX51_PAD_EIM_CS3 = 36,
MX51_PAD_EIM_CS4 = 37,
MX51_PAD_EIM_CS5 = 38,
MX51_PAD_EIM_DTACK = 39,
MX51_PAD_EIM_LBA = 40,
MX51_PAD_EIM_CRE = 41,
MX51_PAD_DRAM_CS1 = 42,
MX51_PAD_NANDF_WE_B = 43,
MX51_PAD_NANDF_RE_B = 44,
MX51_PAD_NANDF_ALE = 45,
MX51_PAD_NANDF_CLE = 46,
MX51_PAD_NANDF_WP_B = 47,
MX51_PAD_NANDF_RB0 = 48,
MX51_PAD_NANDF_RB1 = 49,
MX51_PAD_NANDF_RB2 = 50,
MX51_PAD_NANDF_RB3 = 51,
MX51_PAD_GPIO_NAND = 52,
MX51_PAD_NANDF_CS0 = 53,
MX51_PAD_NANDF_CS1 = 54,
MX51_PAD_NANDF_CS2 = 55,
MX51_PAD_NANDF_CS3 = 56,
MX51_PAD_NANDF_CS4 = 57,
MX51_PAD_NANDF_CS5 = 58,
MX51_PAD_NANDF_CS6 = 59,
MX51_PAD_NANDF_CS7 = 60,
MX51_PAD_NANDF_RDY_INT = 61,
MX51_PAD_NANDF_D15 = 62,
MX51_PAD_NANDF_D14 = 63,
MX51_PAD_NANDF_D13 = 64,
MX51_PAD_NANDF_D12 = 65,
MX51_PAD_NANDF_D11 = 66,
MX51_PAD_NANDF_D10 = 67,
MX51_PAD_NANDF_D9 = 68,
MX51_PAD_NANDF_D8 = 69,
MX51_PAD_NANDF_D7 = 70,
MX51_PAD_NANDF_D6 = 71,
MX51_PAD_NANDF_D5 = 72,
MX51_PAD_NANDF_D4 = 73,
MX51_PAD_NANDF_D3 = 74,
MX51_PAD_NANDF_D2 = 75,
MX51_PAD_NANDF_D1 = 76,
MX51_PAD_NANDF_D0 = 77,
MX51_PAD_CSI1_D8 = 78,
MX51_PAD_CSI1_D9 = 79,
MX51_PAD_CSI1_D10 = 80,
MX51_PAD_CSI1_D11 = 81,
MX51_PAD_CSI1_D12 = 82,
MX51_PAD_CSI1_D13 = 83,
MX51_PAD_CSI1_D14 = 84,
MX51_PAD_CSI1_D15 = 85,
MX51_PAD_CSI1_D16 = 86,
MX51_PAD_CSI1_D17 = 87,
MX51_PAD_CSI1_D18 = 88,
MX51_PAD_CSI1_D19 = 89,
MX51_PAD_CSI1_VSYNC = 90,
MX51_PAD_CSI1_HSYNC = 91,
MX51_PAD_CSI1_PIXCLK = 92,
MX51_PAD_CSI1_MCLK = 93,
MX51_PAD_CSI2_D12 = 94,
MX51_PAD_CSI2_D13 = 95,
MX51_PAD_CSI2_D14 = 96,
MX51_PAD_CSI2_D15 = 97,
MX51_PAD_CSI2_D16 = 98,
MX51_PAD_CSI2_D17 = 99,
MX51_PAD_CSI2_D18 = 100,
MX51_PAD_CSI2_D19 = 101,
MX51_PAD_CSI2_VSYNC = 102,
MX51_PAD_CSI2_HSYNC = 103,
MX51_PAD_CSI2_PIXCLK = 104,
MX51_PAD_I2C1_CLK = 105,
MX51_PAD_I2C1_DAT = 106,
MX51_PAD_AUD3_BB_TXD = 107,
MX51_PAD_AUD3_BB_RXD = 108,
MX51_PAD_AUD3_BB_CK = 109,
MX51_PAD_AUD3_BB_FS = 110,
MX51_PAD_CSPI1_MOSI = 111,
MX51_PAD_CSPI1_MISO = 112,
MX51_PAD_CSPI1_SS0 = 113,
MX51_PAD_CSPI1_SS1 = 114,
MX51_PAD_CSPI1_RDY = 115,
MX51_PAD_CSPI1_SCLK = 116,
MX51_PAD_UART1_RXD = 117,
MX51_PAD_UART1_TXD = 118,
MX51_PAD_UART1_RTS = 119,
MX51_PAD_UART1_CTS = 120,
MX51_PAD_UART2_RXD = 121,
MX51_PAD_UART2_TXD = 122,
MX51_PAD_UART3_RXD = 123,
MX51_PAD_UART3_TXD = 124,
MX51_PAD_OWIRE_LINE = 125,
MX51_PAD_KEY_ROW0 = 126,
MX51_PAD_KEY_ROW1 = 127,
MX51_PAD_KEY_ROW2 = 128,
MX51_PAD_KEY_ROW3 = 129,
MX51_PAD_KEY_COL0 = 130,
MX51_PAD_KEY_COL1 = 131,
MX51_PAD_KEY_COL2 = 132,
MX51_PAD_KEY_COL3 = 133,
MX51_PAD_KEY_COL4 = 134,
MX51_PAD_KEY_COL5 = 135,
MX51_PAD_USBH1_CLK = 136,
MX51_PAD_USBH1_DIR = 137,
MX51_PAD_USBH1_STP = 138,
MX51_PAD_USBH1_NXT = 139,
MX51_PAD_USBH1_DATA0 = 140,
MX51_PAD_USBH1_DATA1 = 141,
MX51_PAD_USBH1_DATA2 = 142,
MX51_PAD_USBH1_DATA3 = 143,
MX51_PAD_USBH1_DATA4 = 144,
MX51_PAD_USBH1_DATA5 = 145,
MX51_PAD_USBH1_DATA6 = 146,
MX51_PAD_USBH1_DATA7 = 147,
MX51_PAD_DI1_PIN11 = 148,
MX51_PAD_DI1_PIN12 = 149,
MX51_PAD_DI1_PIN13 = 150,
MX51_PAD_DI1_D0_CS = 151,
MX51_PAD_DI1_D1_CS = 152,
MX51_PAD_DISPB2_SER_DIN = 153,
MX51_PAD_DISPB2_SER_DIO = 154,
MX51_PAD_DISPB2_SER_CLK = 155,
MX51_PAD_DISPB2_SER_RS = 156,
MX51_PAD_DISP1_DAT0 = 157,
MX51_PAD_DISP1_DAT1 = 158,
MX51_PAD_DISP1_DAT2 = 159,
MX51_PAD_DISP1_DAT3 = 160,
MX51_PAD_DISP1_DAT4 = 161,
MX51_PAD_DISP1_DAT5 = 162,
MX51_PAD_DISP1_DAT6 = 163,
MX51_PAD_DISP1_DAT7 = 164,
MX51_PAD_DISP1_DAT8 = 165,
MX51_PAD_DISP1_DAT9 = 166,
MX51_PAD_DISP1_DAT10 = 167,
MX51_PAD_DISP1_DAT11 = 168,
MX51_PAD_DISP1_DAT12 = 169,
MX51_PAD_DISP1_DAT13 = 170,
MX51_PAD_DISP1_DAT14 = 171,
MX51_PAD_DISP1_DAT15 = 172,
MX51_PAD_DISP1_DAT16 = 173,
MX51_PAD_DISP1_DAT17 = 174,
MX51_PAD_DISP1_DAT18 = 175,
MX51_PAD_DISP1_DAT19 = 176,
MX51_PAD_DISP1_DAT20 = 177,
MX51_PAD_DISP1_DAT21 = 178,
MX51_PAD_DISP1_DAT22 = 179,
MX51_PAD_DISP1_DAT23 = 180,
MX51_PAD_DI1_PIN3 = 181,
MX51_PAD_DI1_PIN2 = 182,
MX51_PAD_DI_GP2 = 183,
MX51_PAD_DI_GP3 = 184,
MX51_PAD_DI2_PIN4 = 185,
MX51_PAD_DI2_PIN2 = 186,
MX51_PAD_DI2_PIN3 = 187,
MX51_PAD_DI2_DISP_CLK = 188,
MX51_PAD_DI_GP4 = 189,
MX51_PAD_DISP2_DAT0 = 190,
MX51_PAD_DISP2_DAT1 = 191,
MX51_PAD_DISP2_DAT2 = 192,
MX51_PAD_DISP2_DAT3 = 193,
MX51_PAD_DISP2_DAT4 = 194,
MX51_PAD_DISP2_DAT5 = 195,
MX51_PAD_DISP2_DAT6 = 196,
MX51_PAD_DISP2_DAT7 = 197,
MX51_PAD_DISP2_DAT8 = 198,
MX51_PAD_DISP2_DAT9 = 199,
MX51_PAD_DISP2_DAT10 = 200,
MX51_PAD_DISP2_DAT11 = 201,
MX51_PAD_DISP2_DAT12 = 202,
MX51_PAD_DISP2_DAT13 = 203,
MX51_PAD_DISP2_DAT14 = 204,
MX51_PAD_DISP2_DAT15 = 205,
MX51_PAD_SD1_CMD = 206,
MX51_PAD_SD1_CLK = 207,
MX51_PAD_SD1_DATA0 = 208,
MX51_PAD_EIM_DA0 = 209,
MX51_PAD_EIM_DA1 = 210,
MX51_PAD_EIM_DA2 = 211,
MX51_PAD_EIM_DA3 = 212,
MX51_PAD_SD1_DATA1 = 213,
MX51_PAD_EIM_DA4 = 214,
MX51_PAD_EIM_DA5 = 215,
MX51_PAD_EIM_DA6 = 216,
MX51_PAD_EIM_DA7 = 217,
MX51_PAD_SD1_DATA2 = 218,
MX51_PAD_EIM_DA10 = 219,
MX51_PAD_EIM_DA11 = 220,
MX51_PAD_EIM_DA8 = 221,
MX51_PAD_EIM_DA9 = 222,
MX51_PAD_SD1_DATA3 = 223,
MX51_PAD_GPIO1_0 = 224,
MX51_PAD_GPIO1_1 = 225,
MX51_PAD_EIM_DA12 = 226,
MX51_PAD_EIM_DA13 = 227,
MX51_PAD_EIM_DA14 = 228,
MX51_PAD_EIM_DA15 = 229,
MX51_PAD_SD2_CMD = 230,
MX51_PAD_SD2_CLK = 231,
MX51_PAD_SD2_DATA0 = 232,
MX51_PAD_SD2_DATA1 = 233,
MX51_PAD_SD2_DATA2 = 234,
MX51_PAD_SD2_DATA3 = 235,
MX51_PAD_GPIO1_2 = 236,
MX51_PAD_GPIO1_3 = 237,
MX51_PAD_PMIC_INT_REQ = 238,
MX51_PAD_GPIO1_4 = 239,
MX51_PAD_GPIO1_5 = 240,
MX51_PAD_GPIO1_6 = 241,
MX51_PAD_GPIO1_7 = 242,
MX51_PAD_GPIO1_8 = 243,
MX51_PAD_GPIO1_9 = 244,
};
/* imx51 register maps */
static struct imx_pin_reg imx51_pin_regs[] = {
IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /* MX51_PAD_EIM_D16__AUD4_RXFS */
IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 7, 0x8d8, 0), /* MX51_PAD_EIM_D16__AUD5_TXD */
IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 0, 0x000, 0), /* MX51_PAD_EIM_D16__EIM_D16 */
IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 1, 0x000, 0), /* MX51_PAD_EIM_D16__GPIO2_0 */
IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 4, 0x9b4, 0), /* MX51_PAD_EIM_D16__I2C1_SDA */
IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 3, 0x000, 0), /* MX51_PAD_EIM_D16__UART2_CTS */
IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 2, 0x000, 0), /* MX51_PAD_EIM_D16__USBH2_DATA0 */
IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 7, 0x8d4, 0), /* MX51_PAD_EIM_D17__AUD5_RXD */
IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 0, 0x000, 0), /* MX51_PAD_EIM_D17__EIM_D17 */
IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 1, 0x000, 0), /* MX51_PAD_EIM_D17__GPIO2_1 */
IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 3, 0x9ec, 0), /* MX51_PAD_EIM_D17__UART2_RXD */
IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 4, 0x000, 0), /* MX51_PAD_EIM_D17__UART3_CTS */
IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 2, 0x000, 0), /* MX51_PAD_EIM_D17__USBH2_DATA1 */
IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 7, 0x8e4, 0), /* MX51_PAD_EIM_D18__AUD5_TXC */
IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 0, 0x000, 0), /* MX51_PAD_EIM_D18__EIM_D18 */
IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 1, 0x000, 0), /* MX51_PAD_EIM_D18__GPIO2_2 */
IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 3, 0x000, 0), /* MX51_PAD_EIM_D18__UART2_TXD */
IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 4, 0x9f0, 1), /* MX51_PAD_EIM_D18__UART3_RTS */
IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 2, 0x000, 0), /* MX51_PAD_EIM_D18__USBH2_DATA2 */
IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 5, 0x000, 0), /* MX51_PAD_EIM_D19__AUD4_RXC */
IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 7, 0x8e8, 0), /* MX51_PAD_EIM_D19__AUD5_TXFS */
IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 0, 0x000, 0), /* MX51_PAD_EIM_D19__EIM_D19 */
IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 1, 0x000, 0), /* MX51_PAD_EIM_D19__GPIO2_3 */
IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 4, 0x9b0, 0), /* MX51_PAD_EIM_D19__I2C1_SCL */
IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 3, 0x9e8, 1), /* MX51_PAD_EIM_D19__UART2_RTS */
IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 2, 0x000, 0), /* MX51_PAD_EIM_D19__USBH2_DATA3 */
IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 5, 0x8c8, 0), /* MX51_PAD_EIM_D20__AUD4_TXD */
IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 0, 0x000, 0), /* MX51_PAD_EIM_D20__EIM_D20 */
IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 1, 0x000, 0), /* MX51_PAD_EIM_D20__GPIO2_4 */
IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 4, 0x000, 0), /* MX51_PAD_EIM_D20__SRTC_ALARM_DEB */
IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 2, 0x000, 0), /* MX51_PAD_EIM_D20__USBH2_DATA4 */
IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 5, 0x8c4, 0), /* MX51_PAD_EIM_D21__AUD4_RXD */
IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 0, 0x000, 0), /* MX51_PAD_EIM_D21__EIM_D21 */
IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 1, 0x000, 0), /* MX51_PAD_EIM_D21__GPIO2_5 */
IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 3, 0x000, 0), /* MX51_PAD_EIM_D21__SRTC_ALARM_DEB */
IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 2, 0x000, 0), /* MX51_PAD_EIM_D21__USBH2_DATA5 */
IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 5, 0x8cc, 0), /* MX51_PAD_EIM_D22__AUD4_TXC */
IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 0, 0x000, 0), /* MX51_PAD_EIM_D22__EIM_D22 */
IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 1, 0x000, 0), /* MX51_PAD_EIM_D22__GPIO2_6 */
IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 2, 0x000, 0), /* MX51_PAD_EIM_D22__USBH2_DATA6 */
IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 5, 0x8d0, 0), /* MX51_PAD_EIM_D23__AUD4_TXFS */
IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 0, 0x000, 0), /* MX51_PAD_EIM_D23__EIM_D23 */
IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 1, 0x000, 0), /* MX51_PAD_EIM_D23__GPIO2_7 */
IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 4, 0x000, 0), /* MX51_PAD_EIM_D23__SPDIF_OUT1 */
IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 2, 0x000, 0), /* MX51_PAD_EIM_D23__USBH2_DATA7 */
IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 5, 0x8f8, 0), /* MX51_PAD_EIM_D24__AUD6_RXFS */
IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 0, 0x000, 0), /* MX51_PAD_EIM_D24__EIM_D24 */
IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 1, 0x000, 0), /* MX51_PAD_EIM_D24__GPIO2_8 */
IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 4, 0x9bc, 0), /* MX51_PAD_EIM_D24__I2C2_SDA */
IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 3, 0x000, 0), /* MX51_PAD_EIM_D24__UART3_CTS */
IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 2, 0x000, 0), /* MX51_PAD_EIM_D24__USBOTG_DATA0 */
IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 0, 0x000, 0), /* MX51_PAD_EIM_D25__EIM_D25 */
IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 1, 0x9c8, 0), /* MX51_PAD_EIM_D25__KEY_COL6 */
IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 4, 0x000, 0), /* MX51_PAD_EIM_D25__UART2_CTS */
IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 3, 0x9f4, 0), /* MX51_PAD_EIM_D25__UART3_RXD */
IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 2, 0x000, 0), /* MX51_PAD_EIM_D25__USBOTG_DATA1 */
IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 0, 0x000, 0), /* MX51_PAD_EIM_D26__EIM_D26 */
IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 1, 0x9cc, 0), /* MX51_PAD_EIM_D26__KEY_COL7 */
IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 4, 0x9e8, 3), /* MX51_PAD_EIM_D26__UART2_RTS */
IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 3, 0x000, 0), /* MX51_PAD_EIM_D26__UART3_TXD */
IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 2, 0x000, 0), /* MX51_PAD_EIM_D26__USBOTG_DATA2 */
IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 5, 0x8f4, 0), /* MX51_PAD_EIM_D27__AUD6_RXC */
IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 0, 0x000, 0), /* MX51_PAD_EIM_D27__EIM_D27 */
IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 1, 0x000, 0), /* MX51_PAD_EIM_D27__GPIO2_9 */
IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 4, 0x9b8, 0), /* MX51_PAD_EIM_D27__I2C2_SCL */
IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 3, 0x9f0, 3), /* MX51_PAD_EIM_D27__UART3_RTS */
IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 2, 0x000, 0), /* MX51_PAD_EIM_D27__USBOTG_DATA3 */
IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 5, 0x8f0, 0), /* MX51_PAD_EIM_D28__AUD6_TXD */
IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 0, 0x000, 0), /* MX51_PAD_EIM_D28__EIM_D28 */
IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 1, 0x9d0, 0), /* MX51_PAD_EIM_D28__KEY_ROW4 */
IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 2, 0x000, 0), /* MX51_PAD_EIM_D28__USBOTG_DATA4 */
IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 5, 0x8ec, 0), /* MX51_PAD_EIM_D29__AUD6_RXD */
IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 0, 0x000, 0), /* MX51_PAD_EIM_D29__EIM_D29 */
IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 1, 0x9d4, 0), /* MX51_PAD_EIM_D29__KEY_ROW5 */
IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 2, 0x000, 0), /* MX51_PAD_EIM_D29__USBOTG_DATA5 */
IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 5, 0x8fc, 0), /* MX51_PAD_EIM_D30__AUD6_TXC */
IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 0, 0x000, 0), /* MX51_PAD_EIM_D30__EIM_D30 */
IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 1, 0x9d8, 0), /* MX51_PAD_EIM_D30__KEY_ROW6 */
IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 2, 0x000, 0), /* MX51_PAD_EIM_D30__USBOTG_DATA6 */
IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 5, 0x900, 0), /* MX51_PAD_EIM_D31__AUD6_TXFS */
IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 0, 0x000, 0), /* MX51_PAD_EIM_D31__EIM_D31 */
IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 1, 0x9dc, 0), /* MX51_PAD_EIM_D31__KEY_ROW7 */
IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 2, 0x000, 0), /* MX51_PAD_EIM_D31__USBOTG_DATA7 */
IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 0, 0x000, 0), /* MX51_PAD_EIM_A16__EIM_A16 */
IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 1, 0x000, 0), /* MX51_PAD_EIM_A16__GPIO2_10 */
IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 7, 0x000, 0), /* MX51_PAD_EIM_A16__OSC_FREQ_SEL0 */
IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 0, 0x000, 0), /* MX51_PAD_EIM_A17__EIM_A17 */
IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 1, 0x000, 0), /* MX51_PAD_EIM_A17__GPIO2_11 */
IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 7, 0x000, 0), /* MX51_PAD_EIM_A17__OSC_FREQ_SEL1 */
IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 7, 0x000, 0), /* MX51_PAD_EIM_A18__BOOT_LPB0 */
IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 0, 0x000, 0), /* MX51_PAD_EIM_A18__EIM_A18 */
IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 1, 0x000, 0), /* MX51_PAD_EIM_A18__GPIO2_12 */
IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 7, 0x000, 0), /* MX51_PAD_EIM_A19__BOOT_LPB1 */
IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 0, 0x000, 0), /* MX51_PAD_EIM_A19__EIM_A19 */
IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 1, 0x000, 0), /* MX51_PAD_EIM_A19__GPIO2_13 */
IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 7, 0x000, 0), /* MX51_PAD_EIM_A20__BOOT_UART_SRC0 */
IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 0, 0x000, 0), /* MX51_PAD_EIM_A20__EIM_A20 */
IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 1, 0x000, 0), /* MX51_PAD_EIM_A20__GPIO2_14 */
IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 7, 0x000, 0), /* MX51_PAD_EIM_A21__BOOT_UART_SRC1 */
IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 0, 0x000, 0), /* MX51_PAD_EIM_A21__EIM_A21 */
IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 1, 0x000, 0), /* MX51_PAD_EIM_A21__GPIO2_15 */
IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 0, 0x000, 0), /* MX51_PAD_EIM_A22__EIM_A22 */
IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 1, 0x000, 0), /* MX51_PAD_EIM_A22__GPIO2_16 */
IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 7, 0x000, 0), /* MX51_PAD_EIM_A23__BOOT_HPN_EN */
IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 0, 0x000, 0), /* MX51_PAD_EIM_A23__EIM_A23 */
IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 1, 0x000, 0), /* MX51_PAD_EIM_A23__GPIO2_17 */
IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 0, 0x000, 0), /* MX51_PAD_EIM_A24__EIM_A24 */
IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 1, 0x000, 0), /* MX51_PAD_EIM_A24__GPIO2_18 */
IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 2, 0x000, 0), /* MX51_PAD_EIM_A24__USBH2_CLK */
IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 6, 0x000, 0), /* MX51_PAD_EIM_A25__DISP1_PIN4 */
IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 0, 0x000, 0), /* MX51_PAD_EIM_A25__EIM_A25 */
IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 1, 0x000, 0), /* MX51_PAD_EIM_A25__GPIO2_19 */
IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 2, 0x000, 0), /* MX51_PAD_EIM_A25__USBH2_DIR */
IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 5, 0x9a0, 0), /* MX51_PAD_EIM_A26__CSI1_DATA_EN */
IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 6, 0x908, 0), /* MX51_PAD_EIM_A26__DISP2_EXT_CLK */
IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 0, 0x000, 0), /* MX51_PAD_EIM_A26__EIM_A26 */
IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 1, 0x000, 0), /* MX51_PAD_EIM_A26__GPIO2_20 */
IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 2, 0x000, 0), /* MX51_PAD_EIM_A26__USBH2_STP */
IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 5, 0x99c, 0), /* MX51_PAD_EIM_A27__CSI2_DATA_EN */
IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 6, 0x9a4, 0), /* MX51_PAD_EIM_A27__DISP1_PIN1 */
IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 0, 0x000, 0), /* MX51_PAD_EIM_A27__EIM_A27 */
IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 1, 0x000, 0), /* MX51_PAD_EIM_A27__GPIO2_21 */
IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 2, 0x000, 0), /* MX51_PAD_EIM_A27__USBH2_NXT */
IMX_PIN_REG(MX51_PAD_EIM_EB0, 0x460, 0x0cc, 0, 0x000, 0), /* MX51_PAD_EIM_EB0__EIM_EB0 */
IMX_PIN_REG(MX51_PAD_EIM_EB1, 0x464, 0x0d0, 0, 0x000, 0), /* MX51_PAD_EIM_EB1__EIM_EB1 */
IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 6, 0x8e0, 0), /* MX51_PAD_EIM_EB2__AUD5_RXFS */
IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 5, 0x000, 0), /* MX51_PAD_EIM_EB2__CSI1_D2 */
IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 0, 0x000, 0), /* MX51_PAD_EIM_EB2__EIM_EB2 */
IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 3, 0x954, 0), /* MX51_PAD_EIM_EB2__FEC_MDIO */
IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 1, 0x000, 0), /* MX51_PAD_EIM_EB2__GPIO2_22 */
IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 7, 0x000, 0), /* MX51_PAD_EIM_EB2__GPT_CMPOUT1 */
IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 6, 0x8dc, 0), /* MX51_PAD_EIM_EB3__AUD5_RXC */
IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 5, 0x000, 0), /* MX51_PAD_EIM_EB3__CSI1_D3 */
IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 0, 0x000, 0), /* MX51_PAD_EIM_EB3__EIM_EB3 */
IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 3, 0x95c, 0), /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 1, 0x000, 0), /* MX51_PAD_EIM_EB3__GPIO2_23 */
IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 7, 0x000, 0), /* MX51_PAD_EIM_EB3__GPT_CMPOUT2 */
IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 0, 0x000, 0), /* MX51_PAD_EIM_OE__EIM_OE */
IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 1, 0x000, 0), /* MX51_PAD_EIM_OE__GPIO2_24 */
IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 0, 0x000, 0), /* MX51_PAD_EIM_CS0__EIM_CS0 */
IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 1, 0x000, 0), /* MX51_PAD_EIM_CS0__GPIO2_25 */
IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 0, 0x000, 0), /* MX51_PAD_EIM_CS1__EIM_CS1 */
IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 1, 0x000, 0), /* MX51_PAD_EIM_CS1__GPIO2_26 */
IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 6, 0x8d8, 1), /* MX51_PAD_EIM_CS2__AUD5_TXD */
IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 5, 0x000, 0), /* MX51_PAD_EIM_CS2__CSI1_D4 */
IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 0, 0x000, 0), /* MX51_PAD_EIM_CS2__EIM_CS2 */
IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 3, 0x960, 0), /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 1, 0x000, 0), /* MX51_PAD_EIM_CS2__GPIO2_27 */
IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 2, 0x000, 0), /* MX51_PAD_EIM_CS2__USBOTG_STP */
IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 6, 0x8d4, 1), /* MX51_PAD_EIM_CS3__AUD5_RXD */
IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 5, 0x000, 0), /* MX51_PAD_EIM_CS3__CSI1_D5 */
IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 0, 0x000, 0), /* MX51_PAD_EIM_CS3__EIM_CS3 */
IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 3, 0x964, 0), /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 1, 0x000, 0), /* MX51_PAD_EIM_CS3__GPIO2_28 */
IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 2, 0x000, 0), /* MX51_PAD_EIM_CS3__USBOTG_NXT */
IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 6, 0x8e4, 1), /* MX51_PAD_EIM_CS4__AUD5_TXC */
IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 5, 0x000, 0), /* MX51_PAD_EIM_CS4__CSI1_D6 */
IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 0, 0x000, 0), /* MX51_PAD_EIM_CS4__EIM_CS4 */
IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 3, 0x970, 0), /* MX51_PAD_EIM_CS4__FEC_RX_ER */
IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 1, 0x000, 0), /* MX51_PAD_EIM_CS4__GPIO2_29 */
IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 2, 0x000, 0), /* MX51_PAD_EIM_CS4__USBOTG_CLK */
IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 6, 0x8e8, 1), /* MX51_PAD_EIM_CS5__AUD5_TXFS */
IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 5, 0x000, 0), /* MX51_PAD_EIM_CS5__CSI1_D7 */
IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 4, 0x904, 0), /* MX51_PAD_EIM_CS5__DISP1_EXT_CLK */
IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 0, 0x000, 0), /* MX51_PAD_EIM_CS5__EIM_CS5 */
IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 3, 0x950, 0), /* MX51_PAD_EIM_CS5__FEC_CRS */
IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 1, 0x000, 0), /* MX51_PAD_EIM_CS5__GPIO2_30 */
IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 2, 0x000, 0), /* MX51_PAD_EIM_CS5__USBOTG_DIR */
IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 0, 0x000, 0), /* MX51_PAD_EIM_DTACK__EIM_DTACK */
IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 1, 0x000, 0), /* MX51_PAD_EIM_DTACK__GPIO2_31 */
IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 0, 0x000, 0), /* MX51_PAD_EIM_LBA__EIM_LBA */
IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 1, 0x978, 0), /* MX51_PAD_EIM_LBA__GPIO3_1 */
IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 0, 0x000, 0), /* MX51_PAD_EIM_CRE__EIM_CRE */
IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 1, 0x97c, 0), /* MX51_PAD_EIM_CRE__GPIO3_2 */
IMX_PIN_REG(MX51_PAD_DRAM_CS1, 0x4d0, 0x104, 0, 0x000, 0), /* MX51_PAD_DRAM_CS1__DRAM_CS1 */
IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 3, 0x980, 0), /* MX51_PAD_NANDF_WE_B__GPIO3_3 */
IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 0, 0x000, 0), /* MX51_PAD_NANDF_WE_B__NANDF_WE_B */
IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 1, 0x000, 0), /* MX51_PAD_NANDF_WE_B__PATA_DIOW */
IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 2, 0x93c, 0), /* MX51_PAD_NANDF_WE_B__SD3_DATA0 */
IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 3, 0x984, 0), /* MX51_PAD_NANDF_RE_B__GPIO3_4 */
IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 0, 0x000, 0), /* MX51_PAD_NANDF_RE_B__NANDF_RE_B */
IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 1, 0x000, 0), /* MX51_PAD_NANDF_RE_B__PATA_DIOR */
IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 2, 0x940, 0), /* MX51_PAD_NANDF_RE_B__SD3_DATA1 */
IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 3, 0x988, 0), /* MX51_PAD_NANDF_ALE__GPIO3_5 */
IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 0, 0x000, 0), /* MX51_PAD_NANDF_ALE__NANDF_ALE */
IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 1, 0x000, 0), /* MX51_PAD_NANDF_ALE__PATA_BUFFER_EN */
IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 3, 0x98c, 0), /* MX51_PAD_NANDF_CLE__GPIO3_6 */
IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 0, 0x000, 0), /* MX51_PAD_NANDF_CLE__NANDF_CLE */
IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 1, 0x000, 0), /* MX51_PAD_NANDF_CLE__PATA_RESET_B */
IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 3, 0x990, 0), /* MX51_PAD_NANDF_WP_B__GPIO3_7 */
IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 0, 0x000, 0), /* MX51_PAD_NANDF_WP_B__NANDF_WP_B */
IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 1, 0x000, 0), /* MX51_PAD_NANDF_WP_B__PATA_DMACK */
IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 2, 0x944, 0), /* MX51_PAD_NANDF_WP_B__SD3_DATA2 */
IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 5, 0x930, 0), /* MX51_PAD_NANDF_RB0__ECSPI2_SS1 */
IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 3, 0x994, 0), /* MX51_PAD_NANDF_RB0__GPIO3_8 */
IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 0, 0x000, 0), /* MX51_PAD_NANDF_RB0__NANDF_RB0 */
IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 1, 0x000, 0), /* MX51_PAD_NANDF_RB0__PATA_DMARQ */
IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 2, 0x948, 0), /* MX51_PAD_NANDF_RB0__SD3_DATA3 */
IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 6, 0x91c, 0), /* MX51_PAD_NANDF_RB1__CSPI_MOSI */
IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 2, 0x000, 0), /* MX51_PAD_NANDF_RB1__ECSPI2_RDY */
IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 3, 0x000, 0), /* MX51_PAD_NANDF_RB1__GPIO3_9 */
IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 0, 0x000, 0), /* MX51_PAD_NANDF_RB1__NANDF_RB1 */
IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 1, 0x000, 0), /* MX51_PAD_NANDF_RB1__PATA_IORDY */
IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 5, 0x000, 0), /* MX51_PAD_NANDF_RB1__SD4_CMD */
IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 5, 0x9a8, 0), /* MX51_PAD_NANDF_RB2__DISP2_WAIT */
IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 2, 0x000, 0), /* MX51_PAD_NANDF_RB2__ECSPI2_SCLK */
IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 1, 0x94c, 0), /* MX51_PAD_NANDF_RB2__FEC_COL */
IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 3, 0x000, 0), /* MX51_PAD_NANDF_RB2__GPIO3_10 */
IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 0, 0x000, 0), /* MX51_PAD_NANDF_RB2__NANDF_RB2 */
IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 7, 0x000, 0), /* MX51_PAD_NANDF_RB2__USBH3_H3_DP */
IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 6, 0xa20, 0), /* MX51_PAD_NANDF_RB2__USBH3_NXT */
IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 5, 0x000, 0), /* MX51_PAD_NANDF_RB3__DISP1_WAIT */
IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 2, 0x000, 0), /* MX51_PAD_NANDF_RB3__ECSPI2_MISO */
IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 1, 0x968, 0), /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 3, 0x000, 0), /* MX51_PAD_NANDF_RB3__GPIO3_11 */
IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 0, 0x000, 0), /* MX51_PAD_NANDF_RB3__NANDF_RB3 */
IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 6, 0x9f8, 0), /* MX51_PAD_NANDF_RB3__USBH3_CLK */
IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 7, 0x000, 0), /* MX51_PAD_NANDF_RB3__USBH3_H3_DM */
IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 0, 0x998, 0), /* MX51_PAD_GPIO_NAND__GPIO_NAND */
IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 1, 0x000, 0), /* MX51_PAD_GPIO_NAND__PATA_INTRQ */
IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 3, 0x000, 0), /* MX51_PAD_NANDF_CS0__GPIO3_16 */
IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 0, 0x000, 0), /* MX51_PAD_NANDF_CS0__NANDF_CS0 */
IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 3, 0x000, 0), /* MX51_PAD_NANDF_CS1__GPIO3_17 */
IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 0, 0x000, 0), /* MX51_PAD_NANDF_CS1__NANDF_CS1 */
IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 6, 0x914, 0), /* MX51_PAD_NANDF_CS2__CSPI_SCLK */
IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 2, 0x000, 0), /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 3, 0x000, 0), /* MX51_PAD_NANDF_CS2__GPIO3_18 */
IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 0, 0x000, 0), /* MX51_PAD_NANDF_CS2__NANDF_CS2 */
IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 1, 0x000, 0), /* MX51_PAD_NANDF_CS2__PATA_CS_0 */
IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 5, 0x000, 0), /* MX51_PAD_NANDF_CS2__SD4_CLK */
IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 7, 0x000, 0), /* MX51_PAD_NANDF_CS2__USBH3_H1_DP */
IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 2, 0x000, 0), /* MX51_PAD_NANDF_CS3__FEC_MDC */
IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS3__GPIO3_19 */
IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS3__NANDF_CS3 */
IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS3__PATA_CS_1 */
IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS3__SD4_DAT0 */
IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 7, 0x000, 0), /* MX51_PAD_NANDF_CS3__USBH3_H1_DM */
IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 2, 0x000, 0), /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 3, 0x000, 0), /* MX51_PAD_NANDF_CS4__GPIO3_20 */
IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 0, 0x000, 0), /* MX51_PAD_NANDF_CS4__NANDF_CS4 */
IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 1, 0x000, 0), /* MX51_PAD_NANDF_CS4__PATA_DA_0 */
IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 5, 0x000, 0), /* MX51_PAD_NANDF_CS4__SD4_DAT1 */
IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 7, 0xa24, 0), /* MX51_PAD_NANDF_CS4__USBH3_STP */
IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 2, 0x000, 0), /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 3, 0x000, 0), /* MX51_PAD_NANDF_CS5__GPIO3_21 */
IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 0, 0x000, 0), /* MX51_PAD_NANDF_CS5__NANDF_CS5 */
IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 1, 0x000, 0), /* MX51_PAD_NANDF_CS5__PATA_DA_1 */
IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 5, 0x000, 0), /* MX51_PAD_NANDF_CS5__SD4_DAT2 */
IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 7, 0xa1c, 0), /* MX51_PAD_NANDF_CS5__USBH3_DIR */
IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 7, 0x928, 0), /* MX51_PAD_NANDF_CS6__CSPI_SS3 */
IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 2, 0x000, 0), /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 3, 0x000, 0), /* MX51_PAD_NANDF_CS6__GPIO3_22 */
IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 0, 0x000, 0), /* MX51_PAD_NANDF_CS6__NANDF_CS6 */
IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 1, 0x000, 0), /* MX51_PAD_NANDF_CS6__PATA_DA_2 */
IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 5, 0x000, 0), /* MX51_PAD_NANDF_CS6__SD4_DAT3 */
IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS7__GPIO3_23 */
IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS7__NANDF_CS7 */
IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS7__SD3_CLK */
IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 2, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 */
IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 1, 0x974, 0), /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 3, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__GPIO3_24 */
IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 0, 0x938, 0), /* MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT */
IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 5, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__SD3_CMD */
IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 2, 0x000, 0), /* MX51_PAD_NANDF_D15__ECSPI2_MOSI */
IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 3, 0x000, 0), /* MX51_PAD_NANDF_D15__GPIO3_25 */
IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 0, 0x000, 0), /* MX51_PAD_NANDF_D15__NANDF_D15 */
IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 1, 0x000, 0), /* MX51_PAD_NANDF_D15__PATA_DATA15 */
IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 5, 0x000, 0), /* MX51_PAD_NANDF_D15__SD3_DAT7 */
IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 2, 0x934, 0), /* MX51_PAD_NANDF_D14__ECSPI2_SS3 */
IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 3, 0x000, 0), /* MX51_PAD_NANDF_D14__GPIO3_26 */
IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 0, 0x000, 0), /* MX51_PAD_NANDF_D14__NANDF_D14 */
IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 1, 0x000, 0), /* MX51_PAD_NANDF_D14__PATA_DATA14 */
IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 5, 0x000, 0), /* MX51_PAD_NANDF_D14__SD3_DAT6 */
IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 2, 0x000, 0), /* MX51_PAD_NANDF_D13__ECSPI2_SS2 */
IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 3, 0x000, 0), /* MX51_PAD_NANDF_D13__GPIO3_27 */
IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 0, 0x000, 0), /* MX51_PAD_NANDF_D13__NANDF_D13 */
IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 1, 0x000, 0), /* MX51_PAD_NANDF_D13__PATA_DATA13 */
IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 5, 0x000, 0), /* MX51_PAD_NANDF_D13__SD3_DAT5 */
IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 2, 0x930, 1), /* MX51_PAD_NANDF_D12__ECSPI2_SS1 */
IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 3, 0x000, 0), /* MX51_PAD_NANDF_D12__GPIO3_28 */
IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 0, 0x000, 0), /* MX51_PAD_NANDF_D12__NANDF_D12 */
IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 1, 0x000, 0), /* MX51_PAD_NANDF_D12__PATA_DATA12 */
IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 5, 0x000, 0), /* MX51_PAD_NANDF_D12__SD3_DAT4 */
IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 2, 0x96c, 0), /* MX51_PAD_NANDF_D11__FEC_RX_DV */
IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 3, 0x000, 0), /* MX51_PAD_NANDF_D11__GPIO3_29 */
IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 0, 0x000, 0), /* MX51_PAD_NANDF_D11__NANDF_D11 */
IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 1, 0x000, 0), /* MX51_PAD_NANDF_D11__PATA_DATA11 */
IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 5, 0x948, 1), /* MX51_PAD_NANDF_D11__SD3_DATA3 */
IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 3, 0x000, 0), /* MX51_PAD_NANDF_D10__GPIO3_30 */
IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 0, 0x000, 0), /* MX51_PAD_NANDF_D10__NANDF_D10 */
IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 1, 0x000, 0), /* MX51_PAD_NANDF_D10__PATA_DATA10 */
IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 5, 0x944, 1), /* MX51_PAD_NANDF_D10__SD3_DATA2 */
IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 2, 0x958, 0), /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 3, 0x000, 0), /* MX51_PAD_NANDF_D9__GPIO3_31 */
IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 0, 0x000, 0), /* MX51_PAD_NANDF_D9__NANDF_D9 */
IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 1, 0x000, 0), /* MX51_PAD_NANDF_D9__PATA_DATA9 */
IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 5, 0x940, 1), /* MX51_PAD_NANDF_D9__SD3_DATA1 */
IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 2, 0x000, 0), /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 3, 0x000, 0), /* MX51_PAD_NANDF_D8__GPIO4_0 */
IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 0, 0x000, 0), /* MX51_PAD_NANDF_D8__NANDF_D8 */
IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 1, 0x000, 0), /* MX51_PAD_NANDF_D8__PATA_DATA8 */
IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 5, 0x93c, 1), /* MX51_PAD_NANDF_D8__SD3_DATA0 */
IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 3, 0x000, 0), /* MX51_PAD_NANDF_D7__GPIO4_1 */
IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 0, 0x000, 0), /* MX51_PAD_NANDF_D7__NANDF_D7 */
IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 1, 0x000, 0), /* MX51_PAD_NANDF_D7__PATA_DATA7 */
IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 5, 0x9fc, 0), /* MX51_PAD_NANDF_D7__USBH3_DATA0 */
IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 3, 0x000, 0), /* MX51_PAD_NANDF_D6__GPIO4_2 */
IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 0, 0x000, 0), /* MX51_PAD_NANDF_D6__NANDF_D6 */
IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 1, 0x000, 0), /* MX51_PAD_NANDF_D6__PATA_DATA6 */
IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 2, 0x000, 0), /* MX51_PAD_NANDF_D6__SD4_LCTL */
IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 5, 0xa00, 0), /* MX51_PAD_NANDF_D6__USBH3_DATA1 */
IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 3, 0x000, 0), /* MX51_PAD_NANDF_D5__GPIO4_3 */
IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 0, 0x000, 0), /* MX51_PAD_NANDF_D5__NANDF_D5 */
IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 1, 0x000, 0), /* MX51_PAD_NANDF_D5__PATA_DATA5 */
IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 2, 0x000, 0), /* MX51_PAD_NANDF_D5__SD4_WP */
IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 5, 0xa04, 0), /* MX51_PAD_NANDF_D5__USBH3_DATA2 */
IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 3, 0x000, 0), /* MX51_PAD_NANDF_D4__GPIO4_4 */
IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 0, 0x000, 0), /* MX51_PAD_NANDF_D4__NANDF_D4 */
IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 1, 0x000, 0), /* MX51_PAD_NANDF_D4__PATA_DATA4 */
IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 2, 0x000, 0), /* MX51_PAD_NANDF_D4__SD4_CD */
IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 5, 0xa08, 0), /* MX51_PAD_NANDF_D4__USBH3_DATA3 */
IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 3, 0x000, 0), /* MX51_PAD_NANDF_D3__GPIO4_5 */
IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 0, 0x000, 0), /* MX51_PAD_NANDF_D3__NANDF_D3 */
IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 1, 0x000, 0), /* MX51_PAD_NANDF_D3__PATA_DATA3 */
IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 2, 0x000, 0), /* MX51_PAD_NANDF_D3__SD4_DAT4 */
IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 5, 0xa0c, 0), /* MX51_PAD_NANDF_D3__USBH3_DATA4 */
IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 3, 0x000, 0), /* MX51_PAD_NANDF_D2__GPIO4_6 */
IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 0, 0x000, 0), /* MX51_PAD_NANDF_D2__NANDF_D2 */
IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 1, 0x000, 0), /* MX51_PAD_NANDF_D2__PATA_DATA2 */
IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 2, 0x000, 0), /* MX51_PAD_NANDF_D2__SD4_DAT5 */
IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 5, 0xa10, 0), /* MX51_PAD_NANDF_D2__USBH3_DATA5 */
IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 3, 0x000, 0), /* MX51_PAD_NANDF_D1__GPIO4_7 */
IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 0, 0x000, 0), /* MX51_PAD_NANDF_D1__NANDF_D1 */
IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 1, 0x000, 0), /* MX51_PAD_NANDF_D1__PATA_DATA1 */
IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 2, 0x000, 0), /* MX51_PAD_NANDF_D1__SD4_DAT6 */
IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 5, 0xa14, 0), /* MX51_PAD_NANDF_D1__USBH3_DATA6 */
IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 3, 0x000, 0), /* MX51_PAD_NANDF_D0__GPIO4_8 */
IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 0, 0x000, 0), /* MX51_PAD_NANDF_D0__NANDF_D0 */
IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 1, 0x000, 0), /* MX51_PAD_NANDF_D0__PATA_DATA0 */
IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 2, 0x000, 0), /* MX51_PAD_NANDF_D0__SD4_DAT7 */
IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 5, 0xa18, 0), /* MX51_PAD_NANDF_D0__USBH3_DATA7 */
IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 0, 0x000, 0), /* MX51_PAD_CSI1_D8__CSI1_D8 */
IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 3, 0x998, 1), /* MX51_PAD_CSI1_D8__GPIO3_12 */
IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 0, 0x000, 0), /* MX51_PAD_CSI1_D9__CSI1_D9 */
IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 3, 0x000, 0), /* MX51_PAD_CSI1_D9__GPIO3_13 */
IMX_PIN_REG(MX51_PAD_CSI1_D10, 0x584, 0x19c, 0, 0x000, 0), /* MX51_PAD_CSI1_D10__CSI1_D10 */
IMX_PIN_REG(MX51_PAD_CSI1_D11, 0x588, 0x1a0, 0, 0x000, 0), /* MX51_PAD_CSI1_D11__CSI1_D11 */
IMX_PIN_REG(MX51_PAD_CSI1_D12, 0x58c, 0x1a4, 0, 0x000, 0), /* MX51_PAD_CSI1_D12__CSI1_D12 */
IMX_PIN_REG(MX51_PAD_CSI1_D13, 0x590, 0x1a8, 0, 0x000, 0), /* MX51_PAD_CSI1_D13__CSI1_D13 */
IMX_PIN_REG(MX51_PAD_CSI1_D14, 0x594, 0x1ac, 0, 0x000, 0), /* MX51_PAD_CSI1_D14__CSI1_D14 */
IMX_PIN_REG(MX51_PAD_CSI1_D15, 0x598, 0x1b0, 0, 0x000, 0), /* MX51_PAD_CSI1_D15__CSI1_D15 */
IMX_PIN_REG(MX51_PAD_CSI1_D16, 0x59c, 0x1b4, 0, 0x000, 0), /* MX51_PAD_CSI1_D16__CSI1_D16 */
IMX_PIN_REG(MX51_PAD_CSI1_D17, 0x5a0, 0x1b8, 0, 0x000, 0), /* MX51_PAD_CSI1_D17__CSI1_D17 */
IMX_PIN_REG(MX51_PAD_CSI1_D18, 0x5a4, 0x1bc, 0, 0x000, 0), /* MX51_PAD_CSI1_D18__CSI1_D18 */
IMX_PIN_REG(MX51_PAD_CSI1_D19, 0x5a8, 0x1c0, 0, 0x000, 0), /* MX51_PAD_CSI1_D19__CSI1_D19 */
IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 0, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__CSI1_VSYNC */
IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 3, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__GPIO3_14 */
IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 0, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__CSI1_HSYNC */
IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 3, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__GPIO3_15 */
IMX_PIN_REG(MX51_PAD_CSI1_PIXCLK, 0x5b4, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK */
IMX_PIN_REG(MX51_PAD_CSI1_MCLK, 0x5b8, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_MCLK__CSI1_MCLK */
IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 0, 0x000, 0), /* MX51_PAD_CSI2_D12__CSI2_D12 */
IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 3, 0x000, 0), /* MX51_PAD_CSI2_D12__GPIO4_9 */
IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 0, 0x000, 0), /* MX51_PAD_CSI2_D13__CSI2_D13 */
IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 3, 0x000, 0), /* MX51_PAD_CSI2_D13__GPIO4_10 */
IMX_PIN_REG(MX51_PAD_CSI2_D14, 0x5c4, 0x1d4, 0, 0x000, 0), /* MX51_PAD_CSI2_D14__CSI2_D14 */
IMX_PIN_REG(MX51_PAD_CSI2_D15, 0x5c8, 0x1d8, 0, 0x000, 0), /* MX51_PAD_CSI2_D15__CSI2_D15 */
IMX_PIN_REG(MX51_PAD_CSI2_D16, 0x5cc, 0x1dc, 0, 0x000, 0), /* MX51_PAD_CSI2_D16__CSI2_D16 */
IMX_PIN_REG(MX51_PAD_CSI2_D17, 0x5d0, 0x1e0, 0, 0x000, 0), /* MX51_PAD_CSI2_D17__CSI2_D17 */
IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 0, 0x000, 0), /* MX51_PAD_CSI2_D18__CSI2_D18 */
IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 3, 0x000, 0), /* MX51_PAD_CSI2_D18__GPIO4_11 */
IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 0, 0x000, 0), /* MX51_PAD_CSI2_D19__CSI2_D19 */
IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 3, 0x000, 0), /* MX51_PAD_CSI2_D19__GPIO4_12 */
IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 0, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__CSI2_VSYNC */
IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 3, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__GPIO4_13 */
IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 0, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__CSI2_HSYNC */
IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 3, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__GPIO4_14 */
IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 0, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK */
IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 3, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__GPIO4_15 */
IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 3, 0x000, 0), /* MX51_PAD_I2C1_CLK__GPIO4_16 */
IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 0, 0x000, 0), /* MX51_PAD_I2C1_CLK__I2C1_CLK */
IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 3, 0x000, 0), /* MX51_PAD_I2C1_DAT__GPIO4_17 */
IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 0, 0x000, 0), /* MX51_PAD_I2C1_DAT__I2C1_DAT */
IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__GPIO4_18 */
IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__GPIO4_19 */
IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 1, 0x9f4, 2), /* MX51_PAD_AUD3_BB_RXD__UART3_RXD */
IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__GPIO4_20 */
IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__GPIO4_21 */
IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 1, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__UART3_TXD */
IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 0, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 3, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__GPIO4_22 */
IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 1, 0x9b4, 1), /* MX51_PAD_CSPI1_MOSI__I2C1_SDA */
IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 1, 0x8c4, 1), /* MX51_PAD_CSPI1_MISO__AUD4_RXD */
IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 0, 0x000, 0), /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 3, 0x000, 0), /* MX51_PAD_CSPI1_MISO__GPIO4_23 */
IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 1, 0x8cc, 1), /* MX51_PAD_CSPI1_SS0__AUD4_TXC */
IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS0__ECSPI1_SS0 */
IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 1, 0x8c8, 1), /* MX51_PAD_CSPI1_SS1__AUD4_TXD */
IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS1__ECSPI1_SS1 */
IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 1, 0x8d0, 1), /* MX51_PAD_CSPI1_RDY__AUD4_TXFS */
IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 0, 0x000, 0), /* MX51_PAD_CSPI1_RDY__ECSPI1_RDY */
IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 3, 0x000, 0), /* MX51_PAD_CSPI1_RDY__GPIO4_26 */
IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 0, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 3, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__GPIO4_27 */
IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 1, 0x9b0, 1), /* MX51_PAD_CSPI1_SCLK__I2C1_SCL */
IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 3, 0x000, 0), /* MX51_PAD_UART1_RXD__GPIO4_28 */
IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 0, 0x9e4, 0), /* MX51_PAD_UART1_RXD__UART1_RXD */
IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 3, 0x000, 0), /* MX51_PAD_UART1_TXD__GPIO4_29 */
IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 1, 0x000, 0), /* MX51_PAD_UART1_TXD__PWM2_PWMO */
IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 0, 0x000, 0), /* MX51_PAD_UART1_TXD__UART1_TXD */
IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 3, 0x000, 0), /* MX51_PAD_UART1_RTS__GPIO4_30 */
IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 0, 0x9e0, 0), /* MX51_PAD_UART1_RTS__UART1_RTS */
IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 3, 0x000, 0), /* MX51_PAD_UART1_CTS__GPIO4_31 */
IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 0, 0x000, 0), /* MX51_PAD_UART1_CTS__UART1_CTS */
IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 1, 0x000, 0), /* MX51_PAD_UART2_RXD__FIRI_TXD */
IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 3, 0x000, 0), /* MX51_PAD_UART2_RXD__GPIO1_20 */
IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 0, 0x9ec, 2), /* MX51_PAD_UART2_RXD__UART2_RXD */
IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 1, 0x000, 0), /* MX51_PAD_UART2_TXD__FIRI_RXD */
IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 3, 0x000, 0), /* MX51_PAD_UART2_TXD__GPIO1_21 */
IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 0, 0x000, 0), /* MX51_PAD_UART2_TXD__UART2_TXD */
IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 2, 0x000, 0), /* MX51_PAD_UART3_RXD__CSI1_D0 */
IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 3, 0x000, 0), /* MX51_PAD_UART3_RXD__GPIO1_22 */
IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 0, 0x000, 0), /* MX51_PAD_UART3_RXD__UART1_DTR */
IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 1, 0x9f4, 4), /* MX51_PAD_UART3_RXD__UART3_RXD */
IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 2, 0x000, 0), /* MX51_PAD_UART3_TXD__CSI1_D1 */
IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 3, 0x000, 0), /* MX51_PAD_UART3_TXD__GPIO1_23 */
IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 0, 0x000, 0), /* MX51_PAD_UART3_TXD__UART1_DSR */
IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 1, 0x000, 0), /* MX51_PAD_UART3_TXD__UART3_TXD */
IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 3, 0x000, 0), /* MX51_PAD_OWIRE_LINE__GPIO1_24 */
IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 0, 0x000, 0), /* MX51_PAD_OWIRE_LINE__OWIRE_LINE */
IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 6, 0x000, 0), /* MX51_PAD_OWIRE_LINE__SPDIF_OUT */
IMX_PIN_REG(MX51_PAD_KEY_ROW0, 0x63c, 0x24c, 0, 0x000, 0), /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
IMX_PIN_REG(MX51_PAD_KEY_ROW1, 0x640, 0x250, 0, 0x000, 0), /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
IMX_PIN_REG(MX51_PAD_KEY_ROW2, 0x644, 0x254, 0, 0x000, 0), /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
IMX_PIN_REG(MX51_PAD_KEY_ROW3, 0x648, 0x258, 0, 0x000, 0), /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 0, 0x000, 0), /* MX51_PAD_KEY_COL0__KEY_COL0 */
IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 7, 0x90c, 0), /* MX51_PAD_KEY_COL0__PLL1_BYP */
IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 0, 0x000, 0), /* MX51_PAD_KEY_COL1__KEY_COL1 */
IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 7, 0x910, 0), /* MX51_PAD_KEY_COL1__PLL2_BYP */
IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 0, 0x000, 0), /* MX51_PAD_KEY_COL2__KEY_COL2 */
IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 7, 0x000, 0), /* MX51_PAD_KEY_COL2__PLL3_BYP */
IMX_PIN_REG(MX51_PAD_KEY_COL3, 0x658, 0x268, 0, 0x000, 0), /* MX51_PAD_KEY_COL3__KEY_COL3 */
IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 3, 0x9b8, 1), /* MX51_PAD_KEY_COL4__I2C2_SCL */
IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 0, 0x000, 0), /* MX51_PAD_KEY_COL4__KEY_COL4 */
IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 6, 0x000, 0), /* MX51_PAD_KEY_COL4__SPDIF_OUT1 */
IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 1, 0x000, 0), /* MX51_PAD_KEY_COL4__UART1_RI */
IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 2, 0x9f0, 4), /* MX51_PAD_KEY_COL4__UART3_RTS */
IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 3, 0x9bc, 1), /* MX51_PAD_KEY_COL5__I2C2_SDA */
IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 0, 0x000, 0), /* MX51_PAD_KEY_COL5__KEY_COL5 */
IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 1, 0x000, 0), /* MX51_PAD_KEY_COL5__UART1_DCD */
IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 2, 0x000, 0), /* MX51_PAD_KEY_COL5__UART3_CTS */
IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 1, 0x914, 1), /* MX51_PAD_USBH1_CLK__CSPI_SCLK */
IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 2, 0x000, 0), /* MX51_PAD_USBH1_CLK__GPIO1_25 */
IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 5, 0x9b8, 2), /* MX51_PAD_USBH1_CLK__I2C2_SCL */
IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 0, 0x000, 0), /* MX51_PAD_USBH1_CLK__USBH1_CLK */
IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 1, 0x91c, 1), /* MX51_PAD_USBH1_DIR__CSPI_MOSI */
IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 2, 0x000, 0), /* MX51_PAD_USBH1_DIR__GPIO1_26 */
IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 5, 0x9bc, 2), /* MX51_PAD_USBH1_DIR__I2C2_SDA */
IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 0, 0x000, 0), /* MX51_PAD_USBH1_DIR__USBH1_DIR */
IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 1, 0x000, 0), /* MX51_PAD_USBH1_STP__CSPI_RDY */
IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 2, 0x000, 0), /* MX51_PAD_USBH1_STP__GPIO1_27 */
IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 5, 0x9f4, 6), /* MX51_PAD_USBH1_STP__UART3_RXD */
IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 0, 0x000, 0), /* MX51_PAD_USBH1_STP__USBH1_STP */
IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 1, 0x918, 0), /* MX51_PAD_USBH1_NXT__CSPI_MISO */
IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 2, 0x000, 0), /* MX51_PAD_USBH1_NXT__GPIO1_28 */
IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 5, 0x000, 0), /* MX51_PAD_USBH1_NXT__UART3_TXD */
IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 0, 0x000, 0), /* MX51_PAD_USBH1_NXT__USBH1_NXT */
IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA0__GPIO1_11 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA0__UART2_CTS */
IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA0__USBH1_DATA0 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA1__GPIO1_12 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 1, 0x9ec, 4), /* MX51_PAD_USBH1_DATA1__UART2_RXD */
IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA1__USBH1_DATA1 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA2__GPIO1_13 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA2__UART2_TXD */
IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA2__USBH1_DATA2 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA3__GPIO1_14 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 1, 0x9e8, 5), /* MX51_PAD_USBH1_DATA3__UART2_RTS */
IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA3__USBH1_DATA3 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA4__CSPI_SS0 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA4__GPIO1_15 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA4__USBH1_DATA4 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 1, 0x920, 0), /* MX51_PAD_USBH1_DATA5__CSPI_SS1 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA5__GPIO1_16 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA5__USBH1_DATA5 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 1, 0x928, 1), /* MX51_PAD_USBH1_DATA6__CSPI_SS3 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA6__GPIO1_17 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA6__USBH1_DATA6 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA7__ECSPI1_SS3 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 5, 0x934, 1), /* MX51_PAD_USBH1_DATA7__ECSPI2_SS3 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA7__GPIO1_18 */
IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA7__USBH1_DATA7 */
IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 0, 0x000, 0), /* MX51_PAD_DI1_PIN11__DI1_PIN11 */
IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 7, 0x000, 0), /* MX51_PAD_DI1_PIN11__ECSPI1_SS2 */
IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 4, 0x000, 0), /* MX51_PAD_DI1_PIN11__GPIO3_0 */
IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 0, 0x000, 0), /* MX51_PAD_DI1_PIN12__DI1_PIN12 */
IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 4, 0x978, 1), /* MX51_PAD_DI1_PIN12__GPIO3_1 */
IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 0, 0x000, 0), /* MX51_PAD_DI1_PIN13__DI1_PIN13 */
IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 4, 0x97c, 1), /* MX51_PAD_DI1_PIN13__GPIO3_2 */
IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 0, 0x000, 0), /* MX51_PAD_DI1_D0_CS__DI1_D0_CS */
IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 4, 0x980, 1), /* MX51_PAD_DI1_D0_CS__GPIO3_3 */
IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 0, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DI1_D1_CS */
IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 2, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN14 */
IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 3, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN5 */
IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 4, 0x984, 1), /* MX51_PAD_DI1_D1_CS__GPIO3_4 */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 2, 0x9a4, 1), /* MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 0, 0x9c4, 0), /* MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 4, 0x988, 1), /* MX51_PAD_DISPB2_SER_DIN__GPIO3_5 */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 0, 0x9c4, 1), /* MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 4, 0x98c, 1), /* MX51_PAD_DISPB2_SER_DIO__GPIO3_6 */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 4, 0x990, 1), /* MX51_PAD_DISPB2_SER_CLK__GPIO3_7 */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */
IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 4, 0x994, 1), /* MX51_PAD_DISPB2_SER_RS__GPIO3_8 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT0, 0x6cc, 0x2cc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT1, 0x6d0, 0x2d0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT2, 0x6d4, 0x2d4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT3, 0x6d8, 0x2d8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT4, 0x6dc, 0x2dc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT5, 0x6e0, 0x2e0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT6__BOOT_USB_SRC */
IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG */
IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT8__BOOT_SRC0 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT9__BOOT_SRC1 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE */
IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL */
IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH */
IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN11 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN5 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN12 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN6 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN13 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN7 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN14 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN8 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_D0_CS */
IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_DAT16 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_D1_CS */
IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_DAT17 */
IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_SER_CS */
IMX_PIN_REG(MX51_PAD_DI1_PIN3, 0x72c, 0x32c, 0, 0x000, 0), /* MX51_PAD_DI1_PIN3__DI1_PIN3 */
IMX_PIN_REG(MX51_PAD_DI1_PIN2, 0x734, 0x330, 0, 0x000, 0), /* MX51_PAD_DI1_PIN2__DI1_PIN2 */
IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 0, 0x000, 0), /* MX51_PAD_DI_GP2__DISP1_SER_CLK */
IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 2, 0x9a8, 1), /* MX51_PAD_DI_GP2__DISP2_WAIT */
IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 3, 0x9a0, 1), /* MX51_PAD_DI_GP3__CSI1_DATA_EN */
IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 0, 0x9c0, 0), /* MX51_PAD_DI_GP3__DISP1_SER_DIO */
IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 2, 0x000, 0), /* MX51_PAD_DI_GP3__FEC_TX_ER */
IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 3, 0x99c, 1), /* MX51_PAD_DI2_PIN4__CSI2_DATA_EN */
IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 0, 0x000, 0), /* MX51_PAD_DI2_PIN4__DI2_PIN4 */
IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 2, 0x950, 1), /* MX51_PAD_DI2_PIN4__FEC_CRS */
IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 0, 0x000, 0), /* MX51_PAD_DI2_PIN2__DI2_PIN2 */
IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 2, 0x000, 0), /* MX51_PAD_DI2_PIN2__FEC_MDC */
IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 0, 0x000, 0), /* MX51_PAD_DI2_PIN3__DI2_PIN3 */
IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 2, 0x954, 1), /* MX51_PAD_DI2_PIN3__FEC_MDIO */
IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 0, 0x000, 0), /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 2, 0x95c, 1), /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 4, 0x000, 0), /* MX51_PAD_DI_GP4__DI2_PIN15 */
IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 0, 0x9c0, 1), /* MX51_PAD_DI_GP4__DISP1_SER_DIN */
IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 3, 0x000, 0), /* MX51_PAD_DI_GP4__DISP2_PIN1 */
IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 2, 0x960, 1), /* MX51_PAD_DI_GP4__FEC_RDATA2 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 2, 0x964, 1), /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 4, 0x9c8, 1), /* MX51_PAD_DISP2_DAT0__KEY_COL6 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 5, 0x9f4, 8), /* MX51_PAD_DISP2_DAT0__UART3_RXD */
IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 3, 0x9f8, 1), /* MX51_PAD_DISP2_DAT0__USBH3_CLK */
IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 2, 0x970, 1), /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 4, 0x9cc, 1), /* MX51_PAD_DISP2_DAT1__KEY_COL7 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT1__UART3_TXD */
IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 3, 0xa1c, 1), /* MX51_PAD_DISP2_DAT1__USBH3_DIR */
IMX_PIN_REG(MX51_PAD_DISP2_DAT2, 0x764, 0x35c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT3, 0x768, 0x360, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT4, 0x76c, 0x364, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT5, 0x770, 0x368, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT6__GPIO1_19 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 4, 0x9d0, 1), /* MX51_PAD_DISP2_DAT6__KEY_ROW4 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 3, 0xa24, 1), /* MX51_PAD_DISP2_DAT6__USBH3_STP */
IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT7__GPIO1_29 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 4, 0x9d4, 1), /* MX51_PAD_DISP2_DAT7__KEY_ROW5 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 3, 0xa20, 1), /* MX51_PAD_DISP2_DAT7__USBH3_NXT */
IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT8__GPIO1_30 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 4, 0x9d8, 1), /* MX51_PAD_DISP2_DAT8__KEY_ROW6 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 3, 0x9fc, 1), /* MX51_PAD_DISP2_DAT8__USBH3_DATA0 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 4, 0x8f4, 1), /* MX51_PAD_DISP2_DAT9__AUD6_RXC */
IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT9__GPIO1_31 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 3, 0xa00, 1), /* MX51_PAD_DISP2_DAT9__USBH3_DATA1 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_SER_CS */
IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 2, 0x94c, 1), /* MX51_PAD_DISP2_DAT10__FEC_COL */
IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 4, 0x9dc, 1), /* MX51_PAD_DISP2_DAT10__KEY_ROW7 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 3, 0xa04, 1), /* MX51_PAD_DISP2_DAT10__USBH3_DATA2 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 4, 0x8f0, 1), /* MX51_PAD_DISP2_DAT11__AUD6_TXD */
IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 2, 0x968, 1), /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 7, 0x000, 0), /* MX51_PAD_DISP2_DAT11__GPIO1_10 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 3, 0xa08, 1), /* MX51_PAD_DISP2_DAT11__USBH3_DATA3 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 4, 0x8ec, 1), /* MX51_PAD_DISP2_DAT12__AUD6_RXD */
IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 2, 0x96c, 1), /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 3, 0xa0c, 1), /* MX51_PAD_DISP2_DAT12__USBH3_DATA4 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 4, 0x8fc, 1), /* MX51_PAD_DISP2_DAT13__AUD6_TXC */
IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 2, 0x974, 1), /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 3, 0xa10, 1), /* MX51_PAD_DISP2_DAT13__USBH3_DATA5 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 4, 0x900, 1), /* MX51_PAD_DISP2_DAT14__AUD6_TXFS */
IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 2, 0x958, 1), /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 3, 0xa14, 1), /* MX51_PAD_DISP2_DAT14__USBH3_DATA6 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 4, 0x8f8, 1), /* MX51_PAD_DISP2_DAT15__AUD6_RXFS */
IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP1_SER_CS */
IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 3, 0xa18, 1), /* MX51_PAD_DISP2_DAT15__USBH3_DATA7 */
IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 1, 0x8e0, 1), /* MX51_PAD_SD1_CMD__AUD5_RXFS */
IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 2, 0x91c, 2), /* MX51_PAD_SD1_CMD__CSPI_MOSI */
IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 0, 0x000, 0), /* MX51_PAD_SD1_CMD__SD1_CMD */
IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 1, 0x8dc, 1), /* MX51_PAD_SD1_CLK__AUD5_RXC */
IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 2, 0x914, 2), /* MX51_PAD_SD1_CLK__CSPI_SCLK */
IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 0, 0x000, 0), /* MX51_PAD_SD1_CLK__SD1_CLK */
IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 1, 0x8d8, 2), /* MX51_PAD_SD1_DATA0__AUD5_TXD */
IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 2, 0x918, 1), /* MX51_PAD_SD1_DATA0__CSPI_MISO */
IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 0, 0x000, 0), /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
IMX_PIN_REG(MX51_PAD_EIM_DA0, NO_PAD, 0x01c, 0, 0x000, 0), /* MX51_PAD_EIM_DA0__EIM_DA0 */
IMX_PIN_REG(MX51_PAD_EIM_DA1, NO_PAD, 0x020, 0, 0x000, 0), /* MX51_PAD_EIM_DA1__EIM_DA1 */
IMX_PIN_REG(MX51_PAD_EIM_DA2, NO_PAD, 0x024, 0, 0x000, 0), /* MX51_PAD_EIM_DA2__EIM_DA2 */
IMX_PIN_REG(MX51_PAD_EIM_DA3, NO_PAD, 0x028, 0, 0x000, 0), /* MX51_PAD_EIM_DA3__EIM_DA3 */
IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 1, 0x8d4, 2), /* MX51_PAD_SD1_DATA1__AUD5_RXD */
IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 0, 0x000, 0), /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
IMX_PIN_REG(MX51_PAD_EIM_DA4, NO_PAD, 0x02c, 0, 0x000, 0), /* MX51_PAD_EIM_DA4__EIM_DA4 */
IMX_PIN_REG(MX51_PAD_EIM_DA5, NO_PAD, 0x030, 0, 0x000, 0), /* MX51_PAD_EIM_DA5__EIM_DA5 */
IMX_PIN_REG(MX51_PAD_EIM_DA6, NO_PAD, 0x034, 0, 0x000, 0), /* MX51_PAD_EIM_DA6__EIM_DA6 */
IMX_PIN_REG(MX51_PAD_EIM_DA7, NO_PAD, 0x038, 0, 0x000, 0), /* MX51_PAD_EIM_DA7__EIM_DA7 */
IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 1, 0x8e4, 2), /* MX51_PAD_SD1_DATA2__AUD5_TXC */
IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 0, 0x000, 0), /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
IMX_PIN_REG(MX51_PAD_EIM_DA10, NO_PAD, 0x044, 0, 0x000, 0), /* MX51_PAD_EIM_DA10__EIM_DA10 */
IMX_PIN_REG(MX51_PAD_EIM_DA11, NO_PAD, 0x048, 0, 0x000, 0), /* MX51_PAD_EIM_DA11__EIM_DA11 */
IMX_PIN_REG(MX51_PAD_EIM_DA8, NO_PAD, 0x03c, 0, 0x000, 0), /* MX51_PAD_EIM_DA8__EIM_DA8 */
IMX_PIN_REG(MX51_PAD_EIM_DA9, NO_PAD, 0x040, 0, 0x000, 0), /* MX51_PAD_EIM_DA9__EIM_DA9 */
IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 1, 0x8e8, 2), /* MX51_PAD_SD1_DATA3__AUD5_TXFS */
IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 2, 0x920, 1), /* MX51_PAD_SD1_DATA3__CSPI_SS1 */
IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 0, 0x000, 0), /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 2, 0x924, 0), /* MX51_PAD_GPIO1_0__CSPI_SS2 */
IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 1, 0x000, 0), /* MX51_PAD_GPIO1_0__GPIO1_0 */
IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 0, 0x000, 0), /* MX51_PAD_GPIO1_0__SD1_CD */
IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 2, 0x918, 2), /* MX51_PAD_GPIO1_1__CSPI_MISO */
IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 1, 0x000, 0), /* MX51_PAD_GPIO1_1__GPIO1_1 */
IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 0, 0x000, 0), /* MX51_PAD_GPIO1_1__SD1_WP */
IMX_PIN_REG(MX51_PAD_EIM_DA12, NO_PAD, 0x04c, 0, 0x000, 0), /* MX51_PAD_EIM_DA12__EIM_DA12 */
IMX_PIN_REG(MX51_PAD_EIM_DA13, NO_PAD, 0x050, 0, 0x000, 0), /* MX51_PAD_EIM_DA13__EIM_DA13 */
IMX_PIN_REG(MX51_PAD_EIM_DA14, NO_PAD, 0x054, 0, 0x000, 0), /* MX51_PAD_EIM_DA14__EIM_DA14 */
IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /* MX51_PAD_EIM_DA15__EIM_DA15 */
IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */
IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 1, 0x9b0, 2), /* MX51_PAD_SD2_CMD__I2C1_SCL */
IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 0, 0x000, 0), /* MX51_PAD_SD2_CMD__SD2_CMD */
IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 2, 0x914, 3), /* MX51_PAD_SD2_CLK__CSPI_SCLK */
IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 1, 0x9b4, 2), /* MX51_PAD_SD2_CLK__I2C1_SDA */
IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 0, 0x000, 0), /* MX51_PAD_SD2_CLK__SD2_CLK */
IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 2, 0x918, 3), /* MX51_PAD_SD2_DATA0__CSPI_MISO */
IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 1, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD1_DAT4 */
IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 0, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 1, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD1_DAT5 */
IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 0, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 2, 0x000, 0), /* MX51_PAD_SD2_DATA1__USBH3_H2_DP */
IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 1, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD1_DAT6 */
IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 0, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 2, 0x000, 0), /* MX51_PAD_SD2_DATA2__USBH3_H2_DM */
IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 2, 0x924, 1), /* MX51_PAD_SD2_DATA3__CSPI_SS2 */
IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 1, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD1_DAT7 */
IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 0, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 5, 0x000, 0), /* MX51_PAD_GPIO1_2__CCM_OUT_2 */
IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 0, 0x000, 0), /* MX51_PAD_GPIO1_2__GPIO1_2 */
IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 2, 0x9b8, 3), /* MX51_PAD_GPIO1_2__I2C2_SCL */
IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 7, 0x90c, 1), /* MX51_PAD_GPIO1_2__PLL1_BYP */
IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 1, 0x000, 0), /* MX51_PAD_GPIO1_2__PWM1_PWMO */
IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 0, 0x000, 0), /* MX51_PAD_GPIO1_3__GPIO1_3 */
IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 2, 0x9bc, 3), /* MX51_PAD_GPIO1_3__I2C2_SDA */
IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 7, 0x910, 1), /* MX51_PAD_GPIO1_3__PLL2_BYP */
IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 1, 0x000, 0), /* MX51_PAD_GPIO1_3__PWM2_PWMO */
IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 0, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ */
IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 1, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B */
IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 4, 0x908, 1), /* MX51_PAD_GPIO1_4__DISP2_EXT_CLK */
IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 3, 0x938, 1), /* MX51_PAD_GPIO1_4__EIM_RDY */
IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 0, 0x000, 0), /* MX51_PAD_GPIO1_4__GPIO1_4 */
IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 2, 0x000, 0), /* MX51_PAD_GPIO1_4__WDOG1_WDOG_B */
IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 6, 0x000, 0), /* MX51_PAD_GPIO1_5__CSI2_MCLK */
IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 3, 0x000, 0), /* MX51_PAD_GPIO1_5__DISP2_PIN16 */
IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 0, 0x000, 0), /* MX51_PAD_GPIO1_5__GPIO1_5 */
IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 2, 0x000, 0), /* MX51_PAD_GPIO1_5__WDOG2_WDOG_B */
IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 4, 0x000, 0), /* MX51_PAD_GPIO1_6__DISP2_PIN17 */
IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 0, 0x000, 0), /* MX51_PAD_GPIO1_6__GPIO1_6 */
IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 3, 0x000, 0), /* MX51_PAD_GPIO1_6__REF_EN_B */
IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 3, 0x000, 0), /* MX51_PAD_GPIO1_7__CCM_OUT_0 */
IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 0, 0x000, 0), /* MX51_PAD_GPIO1_7__GPIO1_7 */
IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 6, 0x000, 0), /* MX51_PAD_GPIO1_7__SD2_WP */
IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 2, 0x000, 0), /* MX51_PAD_GPIO1_7__SPDIF_OUT1 */
IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 2, 0x99c, 2), /* MX51_PAD_GPIO1_8__CSI2_DATA_EN */
IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 0, 0x000, 0), /* MX51_PAD_GPIO1_8__GPIO1_8 */
IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 6, 0x000, 0), /* MX51_PAD_GPIO1_8__SD2_CD */
IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 1, 0x000, 0), /* MX51_PAD_GPIO1_8__USBH3_PWR */
IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 3, 0x000, 0), /* MX51_PAD_GPIO1_9__CCM_OUT_1 */
IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 2, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_D1_CS */
IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 7, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_SER_CS */
IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 0, 0x000, 0), /* MX51_PAD_GPIO1_9__GPIO1_9 */
IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 6, 0x000, 0), /* MX51_PAD_GPIO1_9__SD2_LCTL */
IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 1, 0x000, 0), /* MX51_PAD_GPIO1_9__USBH3_OC */
MX51_PAD_RESERVE0 = 0,
MX51_PAD_RESERVE1 = 1,
MX51_PAD_RESERVE2 = 2,
MX51_PAD_RESERVE3 = 3,
MX51_PAD_RESERVE4 = 4,
MX51_PAD_RESERVE5 = 5,
MX51_PAD_RESERVE6 = 6,
MX51_PAD_EIM_DA0 = 7,
MX51_PAD_EIM_DA1 = 8,
MX51_PAD_EIM_DA2 = 9,
MX51_PAD_EIM_DA3 = 10,
MX51_PAD_EIM_DA4 = 11,
MX51_PAD_EIM_DA5 = 12,
MX51_PAD_EIM_DA6 = 13,
MX51_PAD_EIM_DA7 = 14,
MX51_PAD_EIM_DA8 = 15,
MX51_PAD_EIM_DA9 = 16,
MX51_PAD_EIM_DA10 = 17,
MX51_PAD_EIM_DA11 = 18,
MX51_PAD_EIM_DA12 = 19,
MX51_PAD_EIM_DA13 = 20,
MX51_PAD_EIM_DA14 = 21,
MX51_PAD_EIM_DA15 = 22,
MX51_PAD_EIM_D16 = 23,
MX51_PAD_EIM_D17 = 24,
MX51_PAD_EIM_D18 = 25,
MX51_PAD_EIM_D19 = 26,
MX51_PAD_EIM_D20 = 27,
MX51_PAD_EIM_D21 = 28,
MX51_PAD_EIM_D22 = 29,
MX51_PAD_EIM_D23 = 30,
MX51_PAD_EIM_D24 = 31,
MX51_PAD_EIM_D25 = 32,
MX51_PAD_EIM_D26 = 33,
MX51_PAD_EIM_D27 = 34,
MX51_PAD_EIM_D28 = 35,
MX51_PAD_EIM_D29 = 36,
MX51_PAD_EIM_D30 = 37,
MX51_PAD_EIM_D31 = 38,
MX51_PAD_EIM_A16 = 39,
MX51_PAD_EIM_A17 = 40,
MX51_PAD_EIM_A18 = 41,
MX51_PAD_EIM_A19 = 42,
MX51_PAD_EIM_A20 = 43,
MX51_PAD_EIM_A21 = 44,
MX51_PAD_EIM_A22 = 45,
MX51_PAD_EIM_A23 = 46,
MX51_PAD_EIM_A24 = 47,
MX51_PAD_EIM_A25 = 48,
MX51_PAD_EIM_A26 = 49,
MX51_PAD_EIM_A27 = 50,
MX51_PAD_EIM_EB0 = 51,
MX51_PAD_EIM_EB1 = 52,
MX51_PAD_EIM_EB2 = 53,
MX51_PAD_EIM_EB3 = 54,
MX51_PAD_EIM_OE = 55,
MX51_PAD_EIM_CS0 = 56,
MX51_PAD_EIM_CS1 = 57,
MX51_PAD_EIM_CS2 = 58,
MX51_PAD_EIM_CS3 = 59,
MX51_PAD_EIM_CS4 = 60,
MX51_PAD_EIM_CS5 = 61,
MX51_PAD_EIM_DTACK = 62,
MX51_PAD_EIM_LBA = 63,
MX51_PAD_EIM_CRE = 64,
MX51_PAD_DRAM_CS1 = 65,
MX51_PAD_NANDF_WE_B = 66,
MX51_PAD_NANDF_RE_B = 67,
MX51_PAD_NANDF_ALE = 68,
MX51_PAD_NANDF_CLE = 69,
MX51_PAD_NANDF_WP_B = 70,
MX51_PAD_NANDF_RB0 = 71,
MX51_PAD_NANDF_RB1 = 72,
MX51_PAD_NANDF_RB2 = 73,
MX51_PAD_NANDF_RB3 = 74,
MX51_PAD_GPIO_NAND = 75,
MX51_PAD_NANDF_CS0 = 76,
MX51_PAD_NANDF_CS1 = 77,
MX51_PAD_NANDF_CS2 = 78,
MX51_PAD_NANDF_CS3 = 79,
MX51_PAD_NANDF_CS4 = 80,
MX51_PAD_NANDF_CS5 = 81,
MX51_PAD_NANDF_CS6 = 82,
MX51_PAD_NANDF_CS7 = 83,
MX51_PAD_NANDF_RDY_INT = 84,
MX51_PAD_NANDF_D15 = 85,
MX51_PAD_NANDF_D14 = 86,
MX51_PAD_NANDF_D13 = 87,
MX51_PAD_NANDF_D12 = 88,
MX51_PAD_NANDF_D11 = 89,
MX51_PAD_NANDF_D10 = 90,
MX51_PAD_NANDF_D9 = 91,
MX51_PAD_NANDF_D8 = 92,
MX51_PAD_NANDF_D7 = 93,
MX51_PAD_NANDF_D6 = 94,
MX51_PAD_NANDF_D5 = 95,
MX51_PAD_NANDF_D4 = 96,
MX51_PAD_NANDF_D3 = 97,
MX51_PAD_NANDF_D2 = 98,
MX51_PAD_NANDF_D1 = 99,
MX51_PAD_NANDF_D0 = 100,
MX51_PAD_CSI1_D8 = 101,
MX51_PAD_CSI1_D9 = 102,
MX51_PAD_CSI1_D10 = 103,
MX51_PAD_CSI1_D11 = 104,
MX51_PAD_CSI1_D12 = 105,
MX51_PAD_CSI1_D13 = 106,
MX51_PAD_CSI1_D14 = 107,
MX51_PAD_CSI1_D15 = 108,
MX51_PAD_CSI1_D16 = 109,
MX51_PAD_CSI1_D17 = 110,
MX51_PAD_CSI1_D18 = 111,
MX51_PAD_CSI1_D19 = 112,
MX51_PAD_CSI1_VSYNC = 113,
MX51_PAD_CSI1_HSYNC = 114,
MX51_PAD_CSI2_D12 = 115,
MX51_PAD_CSI2_D13 = 116,
MX51_PAD_CSI2_D14 = 117,
MX51_PAD_CSI2_D15 = 118,
MX51_PAD_CSI2_D16 = 119,
MX51_PAD_CSI2_D17 = 120,
MX51_PAD_CSI2_D18 = 121,
MX51_PAD_CSI2_D19 = 122,
MX51_PAD_CSI2_VSYNC = 123,
MX51_PAD_CSI2_HSYNC = 124,
MX51_PAD_CSI2_PIXCLK = 125,
MX51_PAD_I2C1_CLK = 126,
MX51_PAD_I2C1_DAT = 127,
MX51_PAD_AUD3_BB_TXD = 128,
MX51_PAD_AUD3_BB_RXD = 129,
MX51_PAD_AUD3_BB_CK = 130,
MX51_PAD_AUD3_BB_FS = 131,
MX51_PAD_CSPI1_MOSI = 132,
MX51_PAD_CSPI1_MISO = 133,
MX51_PAD_CSPI1_SS0 = 134,
MX51_PAD_CSPI1_SS1 = 135,
MX51_PAD_CSPI1_RDY = 136,
MX51_PAD_CSPI1_SCLK = 137,
MX51_PAD_UART1_RXD = 138,
MX51_PAD_UART1_TXD = 139,
MX51_PAD_UART1_RTS = 140,
MX51_PAD_UART1_CTS = 141,
MX51_PAD_UART2_RXD = 142,
MX51_PAD_UART2_TXD = 143,
MX51_PAD_UART3_RXD = 144,
MX51_PAD_UART3_TXD = 145,
MX51_PAD_OWIRE_LINE = 146,
MX51_PAD_KEY_ROW0 = 147,
MX51_PAD_KEY_ROW1 = 148,
MX51_PAD_KEY_ROW2 = 149,
MX51_PAD_KEY_ROW3 = 150,
MX51_PAD_KEY_COL0 = 151,
MX51_PAD_KEY_COL1 = 152,
MX51_PAD_KEY_COL2 = 153,
MX51_PAD_KEY_COL3 = 154,
MX51_PAD_KEY_COL4 = 155,
MX51_PAD_KEY_COL5 = 156,
MX51_PAD_RESERVE7 = 157,
MX51_PAD_USBH1_CLK = 158,
MX51_PAD_USBH1_DIR = 159,
MX51_PAD_USBH1_STP = 160,
MX51_PAD_USBH1_NXT = 161,
MX51_PAD_USBH1_DATA0 = 162,
MX51_PAD_USBH1_DATA1 = 163,
MX51_PAD_USBH1_DATA2 = 164,
MX51_PAD_USBH1_DATA3 = 165,
MX51_PAD_USBH1_DATA4 = 166,
MX51_PAD_USBH1_DATA5 = 167,
MX51_PAD_USBH1_DATA6 = 168,
MX51_PAD_USBH1_DATA7 = 169,
MX51_PAD_DI1_PIN11 = 170,
MX51_PAD_DI1_PIN12 = 171,
MX51_PAD_DI1_PIN13 = 172,
MX51_PAD_DI1_D0_CS = 173,
MX51_PAD_DI1_D1_CS = 174,
MX51_PAD_DISPB2_SER_DIN = 175,
MX51_PAD_DISPB2_SER_DIO = 176,
MX51_PAD_DISPB2_SER_CLK = 177,
MX51_PAD_DISPB2_SER_RS = 178,
MX51_PAD_DISP1_DAT0 = 179,
MX51_PAD_DISP1_DAT1 = 180,
MX51_PAD_DISP1_DAT2 = 181,
MX51_PAD_DISP1_DAT3 = 182,
MX51_PAD_DISP1_DAT4 = 183,
MX51_PAD_DISP1_DAT5 = 184,
MX51_PAD_DISP1_DAT6 = 185,
MX51_PAD_DISP1_DAT7 = 186,
MX51_PAD_DISP1_DAT8 = 187,
MX51_PAD_DISP1_DAT9 = 188,
MX51_PAD_DISP1_DAT10 = 189,
MX51_PAD_DISP1_DAT11 = 190,
MX51_PAD_DISP1_DAT12 = 191,
MX51_PAD_DISP1_DAT13 = 192,
MX51_PAD_DISP1_DAT14 = 193,
MX51_PAD_DISP1_DAT15 = 194,
MX51_PAD_DISP1_DAT16 = 195,
MX51_PAD_DISP1_DAT17 = 196,
MX51_PAD_DISP1_DAT18 = 197,
MX51_PAD_DISP1_DAT19 = 198,
MX51_PAD_DISP1_DAT20 = 199,
MX51_PAD_DISP1_DAT21 = 200,
MX51_PAD_DISP1_DAT22 = 201,
MX51_PAD_DISP1_DAT23 = 202,
MX51_PAD_DI1_PIN3 = 203,
MX51_PAD_DI1_PIN2 = 204,
MX51_PAD_RESERVE8 = 205,
MX51_PAD_DI_GP2 = 206,
MX51_PAD_DI_GP3 = 207,
MX51_PAD_DI2_PIN4 = 208,
MX51_PAD_DI2_PIN2 = 209,
MX51_PAD_DI2_PIN3 = 210,
MX51_PAD_DI2_DISP_CLK = 211,
MX51_PAD_DI_GP4 = 212,
MX51_PAD_DISP2_DAT0 = 213,
MX51_PAD_DISP2_DAT1 = 214,
MX51_PAD_DISP2_DAT2 = 215,
MX51_PAD_DISP2_DAT3 = 216,
MX51_PAD_DISP2_DAT4 = 217,
MX51_PAD_DISP2_DAT5 = 218,
MX51_PAD_DISP2_DAT6 = 219,
MX51_PAD_DISP2_DAT7 = 220,
MX51_PAD_DISP2_DAT8 = 221,
MX51_PAD_DISP2_DAT9 = 222,
MX51_PAD_DISP2_DAT10 = 223,
MX51_PAD_DISP2_DAT11 = 224,
MX51_PAD_DISP2_DAT12 = 225,
MX51_PAD_DISP2_DAT13 = 226,
MX51_PAD_DISP2_DAT14 = 227,
MX51_PAD_DISP2_DAT15 = 228,
MX51_PAD_SD1_CMD = 229,
MX51_PAD_SD1_CLK = 230,
MX51_PAD_SD1_DATA0 = 231,
MX51_PAD_SD1_DATA1 = 232,
MX51_PAD_SD1_DATA2 = 233,
MX51_PAD_SD1_DATA3 = 234,
MX51_PAD_GPIO1_0 = 235,
MX51_PAD_GPIO1_1 = 236,
MX51_PAD_SD2_CMD = 237,
MX51_PAD_SD2_CLK = 238,
MX51_PAD_SD2_DATA0 = 239,
MX51_PAD_SD2_DATA1 = 240,
MX51_PAD_SD2_DATA2 = 241,
MX51_PAD_SD2_DATA3 = 242,
MX51_PAD_GPIO1_2 = 243,
MX51_PAD_GPIO1_3 = 244,
MX51_PAD_PMIC_INT_REQ = 245,
MX51_PAD_GPIO1_4 = 246,
MX51_PAD_GPIO1_5 = 247,
MX51_PAD_GPIO1_6 = 248,
MX51_PAD_GPIO1_7 = 249,
MX51_PAD_GPIO1_8 = 250,
MX51_PAD_GPIO1_9 = 251,
MX51_PAD_RESERVE9 = 252,
MX51_PAD_RESERVE10 = 253,
MX51_PAD_RESERVE11 = 254,
MX51_PAD_RESERVE12 = 255,
MX51_PAD_RESERVE13 = 256,
MX51_PAD_RESERVE14 = 257,
MX51_PAD_RESERVE15 = 258,
MX51_PAD_RESERVE16 = 259,
MX51_PAD_RESERVE17 = 260,
MX51_PAD_RESERVE18 = 261,
MX51_PAD_RESERVE19 = 262,
MX51_PAD_RESERVE20 = 263,
MX51_PAD_RESERVE21 = 264,
MX51_PAD_RESERVE22 = 265,
MX51_PAD_RESERVE23 = 266,
MX51_PAD_RESERVE24 = 267,
MX51_PAD_RESERVE25 = 268,
MX51_PAD_RESERVE26 = 269,
MX51_PAD_RESERVE27 = 270,
MX51_PAD_RESERVE28 = 271,
MX51_PAD_RESERVE29 = 272,
MX51_PAD_RESERVE30 = 273,
MX51_PAD_RESERVE31 = 274,
MX51_PAD_RESERVE32 = 275,
MX51_PAD_RESERVE33 = 276,
MX51_PAD_RESERVE34 = 277,
MX51_PAD_RESERVE35 = 278,
MX51_PAD_RESERVE36 = 279,
MX51_PAD_RESERVE37 = 280,
MX51_PAD_RESERVE38 = 281,
MX51_PAD_RESERVE39 = 282,
MX51_PAD_RESERVE40 = 283,
MX51_PAD_RESERVE41 = 284,
MX51_PAD_RESERVE42 = 285,
MX51_PAD_RESERVE43 = 286,
MX51_PAD_RESERVE44 = 287,
MX51_PAD_RESERVE45 = 288,
MX51_PAD_RESERVE46 = 289,
MX51_PAD_RESERVE47 = 290,
MX51_PAD_RESERVE48 = 291,
MX51_PAD_RESERVE49 = 292,
MX51_PAD_RESERVE50 = 293,
MX51_PAD_RESERVE51 = 294,
MX51_PAD_RESERVE52 = 295,
MX51_PAD_RESERVE53 = 296,
MX51_PAD_RESERVE54 = 297,
MX51_PAD_RESERVE55 = 298,
MX51_PAD_RESERVE56 = 299,
MX51_PAD_RESERVE57 = 300,
MX51_PAD_RESERVE58 = 301,
MX51_PAD_RESERVE59 = 302,
MX51_PAD_RESERVE60 = 303,
MX51_PAD_RESERVE61 = 304,
MX51_PAD_RESERVE62 = 305,
MX51_PAD_RESERVE63 = 306,
MX51_PAD_RESERVE64 = 307,
MX51_PAD_RESERVE65 = 308,
MX51_PAD_RESERVE66 = 309,
MX51_PAD_RESERVE67 = 310,
MX51_PAD_RESERVE68 = 311,
MX51_PAD_RESERVE69 = 312,
MX51_PAD_RESERVE70 = 313,
MX51_PAD_RESERVE71 = 314,
MX51_PAD_RESERVE72 = 315,
MX51_PAD_RESERVE73 = 316,
MX51_PAD_RESERVE74 = 317,
MX51_PAD_RESERVE75 = 318,
MX51_PAD_RESERVE76 = 319,
MX51_PAD_RESERVE77 = 320,
MX51_PAD_RESERVE78 = 321,
MX51_PAD_RESERVE79 = 322,
MX51_PAD_RESERVE80 = 323,
MX51_PAD_RESERVE81 = 324,
MX51_PAD_RESERVE82 = 325,
MX51_PAD_RESERVE83 = 326,
MX51_PAD_RESERVE84 = 327,
MX51_PAD_RESERVE85 = 328,
MX51_PAD_RESERVE86 = 329,
MX51_PAD_RESERVE87 = 330,
MX51_PAD_RESERVE88 = 331,
MX51_PAD_RESERVE89 = 332,
MX51_PAD_RESERVE90 = 333,
MX51_PAD_RESERVE91 = 334,
MX51_PAD_RESERVE92 = 335,
MX51_PAD_RESERVE93 = 336,
MX51_PAD_RESERVE94 = 337,
MX51_PAD_RESERVE95 = 338,
MX51_PAD_RESERVE96 = 339,
MX51_PAD_RESERVE97 = 340,
MX51_PAD_RESERVE98 = 341,
MX51_PAD_RESERVE99 = 342,
MX51_PAD_RESERVE100 = 343,
MX51_PAD_RESERVE101 = 344,
MX51_PAD_RESERVE102 = 345,
MX51_PAD_RESERVE103 = 346,
MX51_PAD_RESERVE104 = 347,
MX51_PAD_RESERVE105 = 348,
MX51_PAD_RESERVE106 = 349,
MX51_PAD_RESERVE107 = 350,
MX51_PAD_RESERVE108 = 351,
MX51_PAD_RESERVE109 = 352,
MX51_PAD_RESERVE110 = 353,
MX51_PAD_RESERVE111 = 354,
MX51_PAD_RESERVE112 = 355,
MX51_PAD_RESERVE113 = 356,
MX51_PAD_RESERVE114 = 357,
MX51_PAD_RESERVE115 = 358,
MX51_PAD_RESERVE116 = 359,
MX51_PAD_RESERVE117 = 360,
MX51_PAD_RESERVE118 = 361,
MX51_PAD_RESERVE119 = 362,
MX51_PAD_RESERVE120 = 363,
MX51_PAD_RESERVE121 = 364,
MX51_PAD_CSI1_PIXCLK = 365,
MX51_PAD_CSI1_MCLK = 366,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX51_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D16),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D17),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D18),
......@@ -1124,8 +509,6 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14),
......@@ -1168,6 +551,7 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP),
......@@ -1215,6 +599,7 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX51_PAD_DI_GP2),
IMX_PINCTRL_PIN(MX51_PAD_DI_GP3),
IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4),
......@@ -1241,27 +626,11 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0),
......@@ -1277,13 +646,126 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE17),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE18),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE19),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE20),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE21),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE22),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE23),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE24),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE25),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE26),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE27),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE28),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE29),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE30),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE31),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE32),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE33),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE34),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE35),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE36),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE37),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE38),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE39),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE40),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE41),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE42),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE43),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE44),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE45),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE46),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE47),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE48),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE49),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE50),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE51),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE52),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE53),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE54),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE55),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE56),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE57),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE58),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE59),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE60),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE61),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE62),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE63),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE64),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE65),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE66),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE67),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE68),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE69),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE70),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE71),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE72),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE73),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE74),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE75),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE76),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE77),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE78),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE79),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE80),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE81),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE82),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE83),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE84),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE85),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE86),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE87),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE88),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE89),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE90),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE91),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE92),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE93),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE94),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE95),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE96),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE97),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE98),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE99),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE100),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE101),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE102),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE103),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE104),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE105),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE106),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE107),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE108),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE109),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE110),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE111),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE112),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE113),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE114),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE115),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE116),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE117),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE118),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE119),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE120),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE121),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
};
static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
.pins = imx51_pinctrl_pads,
.npins = ARRAY_SIZE(imx51_pinctrl_pads),
.pin_regs = imx51_pin_regs,
.npin_regs = ARRAY_SIZE(imx51_pin_regs),
};
static struct of_device_id imx51_pinctrl_of_match[] = {
......
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