Skip to content

L
linux
Commit e1b2de6e authored by Mark A. Greer's avatar Mark A. Greer Committed by Linus Torvalds
Browse files
Options

[PATCH] ppc32: support for Artesyn Katana cPCI boards 

This patch adds support for the Artesyn Katana 750i, 752i, and 3750.
Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent c7033ab5
Show whitespace changes
Inline Side-by-side
Showing with 1574 additions and 0 deletions
arch/ppc/Kconfig
View file @ e1b2de6e
...@@ -500,6 +500,12 @@ config APUS ...@@ -500,6 +500,12 @@ config APUS
More information is available at: More information is available at:
<http://linux-apus.sourceforge.net/>. <http://linux-apus.sourceforge.net/>.
config KATANA
bool "Artesyn-Katana"
help
Select KATANA if configuring an Artesyn KATANA 750i or 3750
cPCI board.
config WILLOW config WILLOW
bool "Cogent-Willow" bool "Cogent-Willow"
...@@ -701,6 +707,11 @@ config GT64260 ...@@ -701,6 +707,11 @@ config GT64260
depends on EV64260 || CPCI690 depends on EV64260 || CPCI690
default y default y
config MV64360
bool
depends on KATANA
default y
config MV64X60 config MV64X60
bool bool
depends on (GT64260 || MV64360) depends on (GT64260 || MV64360)
......
arch/ppc/boot/simple/Makefile
View file @ e1b2de6e
...@@ -84,6 +84,10 @@ zimageinitrd-$(CONFIG_GEMINI) := zImage.initrd-STRIPELF ...@@ -84,6 +84,10 @@ zimageinitrd-$(CONFIG_GEMINI) := zImage.initrd-STRIPELF
end-$(CONFIG_K2) := k2 end-$(CONFIG_K2) := k2
cacheflag-$(CONFIG_K2) := -include $(clear_L2_L3) cacheflag-$(CONFIG_K2) := -include $(clear_L2_L3)
extra.o-$(CONFIG_KATANA) := misc-katana.o mv64x60_stub.o
end-$(CONFIG_KATANA) := katana
cacheflag-$(CONFIG_KATANA) := -include $(clear_L2_L3)
# kconfig 'feature', only one of these will ever be 'y' at a time. # kconfig 'feature', only one of these will ever be 'y' at a time.
# The rest will be unset. # The rest will be unset.
motorola := $(CONFIG_MCPN765)$(CONFIG_MVME5100)$(CONFIG_PRPMC750) \ motorola := $(CONFIG_MCPN765)$(CONFIG_MVME5100)$(CONFIG_PRPMC750) \
......
arch/ppc/boot/simple/misc-katana.c 0 → 100644
View file @ e1b2de6e
/*
* arch/ppc/boot/simple/misc-katana.c
*
* Add birec data for Artesyn KATANA board.
*
* Author: Mark A. Greer <source@mvista.com>
*
* 2004 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/types.h>
long mv64x60_mpsc_clk_freq = 133333333;
arch/ppc/configs/katana_defconfig 0 → 100644
View file @ e1b2de6e
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.10-rc2
# Fri Nov 19 15:17:10 2004
#
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_HAVE_DEC_LOCK=y
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_GENERIC_NVRAM=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_HOTPLUG is not set
CONFIG_KOBJECT_UEVENT=y
# CONFIG_IKCONFIG is not set
# CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SHMEM=y
CONFIG_CC_ALIGN_FUNCTIONS=0
CONFIG_CC_ALIGN_LABELS=0
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# Processor
#
CONFIG_6xx=y
# CONFIG_40x is not set
# CONFIG_44x is not set
# CONFIG_POWER3 is not set
# CONFIG_POWER4 is not set
# CONFIG_8xx is not set
# CONFIG_E500 is not set
CONFIG_ALTIVEC=y
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
CONFIG_PPC_STD_MMU=y
CONFIG_NOT_COHERENT_CACHE=y
#
# Platform options
#
# CONFIG_PPC_MULTIPLATFORM is not set
# CONFIG_APUS is not set
CONFIG_KATANA=y
# CONFIG_WILLOW is not set
# CONFIG_PCORE is not set
# CONFIG_POWERPMC250 is not set
# CONFIG_SPRUCE is not set
# CONFIG_EV64260 is not set
# CONFIG_LOPEC is not set
# CONFIG_MCPN765 is not set
# CONFIG_MVME5100 is not set
# CONFIG_PPLUS is not set
# CONFIG_PRPMC750 is not set
# CONFIG_PRPMC800 is not set
# CONFIG_SANDPOINT is not set
# CONFIG_ADIR is not set
# CONFIG_K2 is not set
# CONFIG_PAL4 is not set
# CONFIG_GEMINI is not set
# CONFIG_EST8260 is not set
# CONFIG_SBC82xx is not set
# CONFIG_SBS8260 is not set
# CONFIG_RPX8260 is not set
# CONFIG_TQM8260 is not set
# CONFIG_ADS8272 is not set
# CONFIG_LITE5200 is not set
CONFIG_MV64360=y
CONFIG_MV64X60=y
#
# Set bridge options
#
CONFIG_MV64X60_BASE=0xf8100000
CONFIG_MV64X60_NEW_BASE=0xf8100000
# CONFIG_SMP is not set
# CONFIG_PREEMPT is not set
# CONFIG_HIGHMEM is not set
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_MISC=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyMM0,9600 ip=on"
#
# Bus options
#
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_LEGACY_PROC=y
CONFIG_PCI_NAMES=y
#
# Advanced setup
#
CONFIG_ADVANCED_OPTIONS=y
CONFIG_HIGHMEM_START=0xfe000000
# CONFIG_LOWMEM_SIZE_BOOL is not set
CONFIG_LOWMEM_SIZE=0x30000000
# CONFIG_KERNEL_START_BOOL is not set
CONFIG_KERNEL_START=0xc0000000
# CONFIG_TASK_SIZE_BOOL is not set
CONFIG_TASK_SIZE=0x80000000
CONFIG_CONSISTENT_START_BOOL=y
CONFIG_CONSISTENT_START=0xf0000000
# CONFIG_CONSISTENT_SIZE_BOOL is not set
CONFIG_CONSISTENT_SIZE=0x00200000
# CONFIG_BOOT_LOAD_BOOL is not set
CONFIG_BOOT_LOAD=0x00800000
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_LBD is not set
# CONFIG_CDROM_PKTCDVD is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
#
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Macintosh device drivers
#
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
# CONFIG_NETLINK_DEV is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_IP_TCPDIAG=y
# CONFIG_IP_TCPDIAG_IPV6 is not set
# CONFIG_IPV6 is not set
# CONFIG_NETFILTER is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
# CONFIG_NET_CLS_ROUTE is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
#
# Tulip family network device support
#
CONFIG_NET_TULIP=y
# CONFIG_DE2104X is not set
CONFIG_TULIP=y
# CONFIG_TULIP_MWI is not set
# CONFIG_TULIP_MMIO is not set
# CONFIG_TULIP_NAPI is not set
# CONFIG_DE4X5 is not set
# CONFIG_WINBOND_840 is not set
# CONFIG_DM9102 is not set
# CONFIG_HP100 is not set
CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
# CONFIG_FORCEDETH is not set
# CONFIG_DGRS is not set
# CONFIG_EEPRO100 is not set
CONFIG_E100=y
# CONFIG_E100_NAPI is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SK98LIN is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
#
# Token Ring devices
#
# CONFIG_TR is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
# CONFIG_SERIO is not set
# CONFIG_SERIO_I8042 is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
CONFIG_GEN_RTC=y
# CONFIG_GEN_RTC_X is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Misc devices
#
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# Graphics support
#
# CONFIG_FB is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_SYSFS=y
CONFIG_DEVFS_FS=y
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
# CONFIG_DEVPTS_FS_XATTR is not set
CONFIG_TMPFS=y
# CONFIG_TMPFS_XATTR is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_DEBUG_KERNEL is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
arch/ppc/platforms/Makefile
View file @ e1b2de6e
...@@ -28,6 +28,7 @@ obj-$(CONFIG_EV64260) += ev64260.o ...@@ -28,6 +28,7 @@ obj-$(CONFIG_EV64260) += ev64260.o
obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o
obj-$(CONFIG_K2) += k2.o obj-$(CONFIG_K2) += k2.o
obj-$(CONFIG_LOPEC) += lopec.o obj-$(CONFIG_LOPEC) += lopec.o
obj-$(CONFIG_KATANA) += katana.o
obj-$(CONFIG_MCPN765) += mcpn765.o obj-$(CONFIG_MCPN765) += mcpn765.o
obj-$(CONFIG_MENF1) += menf1_setup.o menf1_pci.o obj-$(CONFIG_MENF1) += menf1_setup.o menf1_pci.o
obj-$(CONFIG_MVME5100) += mvme5100.o obj-$(CONFIG_MVME5100) += mvme5100.o
......
arch/ppc/platforms/katana.c 0 → 100644
View file @ e1b2de6e
/*
* arch/ppc/platforms/katana.c
*
* Board setup routines for the Artesyn Katana 750 based boards.
*
* Tim Montgomery <timm@artesyncp.com>
*
* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
* Based on code done by - Mark A. Greer <mgreer@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
* Supports the Artesyn 750i, 752i, and 3750. The 752i is virtually identical
* to the 750i except that it has an mv64460 bridge.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/console.h>
#include <linux/initrd.h>
#include <linux/root_dev.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/smp.h>
#include <linux/mv643xx.h>
#ifdef CONFIG_BOOTIMG
#include <linux/bootimg.h>
#endif
#include <asm/page.h>
#include <asm/time.h>
#include <asm/smp.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include <asm/mv64x60.h>
#include <platforms/katana.h>
static struct mv64x60_handle bh;
static katana_id_t katana_id;
static u32 cpld_base;
static u32 sram_base;
/* PCI Interrupt routing */
static int __init
katana_irq_lookup_750i(unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] = {
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
/* IDSEL 4 (PMC 1) */
{ KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i,
KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i },
/* IDSEL 5 (PMC 2) */
{ KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i,
KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i },
/* IDSEL 6 (T8110) */
{KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
};
const long min_idsel = 4, max_idsel = 6, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
static int __init
katana_irq_lookup_3750(unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] = {
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{ KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 }, /* IDSEL 3 (BCM5691) */
{ KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 }, /* IDSEL 4 (MV64360 #2)*/
{ KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 }, /* IDSEL 5 (MV64360 #3)*/
};
const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
static int __init
katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
switch (katana_id) {
case KATANA_ID_750I:
case KATANA_ID_752I:
return katana_irq_lookup_750i(idsel, pin);
case KATANA_ID_3750:
return katana_irq_lookup_3750(idsel, pin);
default:
printk(KERN_ERR "Bogus board ID\n");
return 0;
}
}
/* Board info retrieval routines */
void __init
katana_get_board_id(void)
{
switch (in_8((volatile char *)(cpld_base + KATANA_CPLD_PRODUCT_ID))) {
case KATANA_PRODUCT_ID_3750:
katana_id = KATANA_ID_3750;
break;
case KATANA_PRODUCT_ID_750i:
katana_id = KATANA_ID_750I;
break;
case KATANA_PRODUCT_ID_752i:
katana_id = KATANA_ID_752I;
break;
default:
printk(KERN_ERR "Unsupported board\n");
}
}
int __init
katana_get_proc_num(void)
{
u16 val;
u8 save_exclude;
static int proc = -1;
static u8 first_time = 1;
if (first_time) {
if (katana_id != KATANA_ID_3750)
proc = 0;
else {
save_exclude = mv64x60_pci_exclude_bridge;
mv64x60_pci_exclude_bridge = 0;
early_read_config_word(bh.hose_a, 0,
PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
mv64x60_pci_exclude_bridge = save_exclude;
switch(val) {
case PCI_DEVICE_ID_KATANA_3750_PROC0:
proc = 0;
break;
case PCI_DEVICE_ID_KATANA_3750_PROC1:
proc = 1;
break;
case PCI_DEVICE_ID_KATANA_3750_PROC2:
proc = 2;
break;
default:
printk(KERN_ERR "Bogus Device ID\n");
}
}
first_time = 0;
}
return proc;
}
static inline int
katana_is_monarch(void)
{
return in_8((volatile char *)(cpld_base + KATANA_CPLD_BD_CFG_3)) &
KATANA_CPLD_BD_CFG_3_MONARCH;
}
static void __init
katana_enable_ipmi(void)
{
u8 reset_out;
/* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
reset_out = in_8((volatile char *)(cpld_base + KATANA_CPLD_RESET_OUT));
reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
out_8((volatile void *)(cpld_base + KATANA_CPLD_RESET_OUT), reset_out);
return;
}
static unsigned long
katana_bus_freq(void)
{
u8 bd_cfg_0;
bd_cfg_0 = in_8((volatile char *)(cpld_base + KATANA_CPLD_BD_CFG_0));
switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) {
case KATANA_CPLD_BD_CFG_0_SYSCLK_133:
return 133333333;
break;
case KATANA_CPLD_BD_CFG_0_SYSCLK_100:
return 100000000;
break;
default:
return 133333333;
break;
}
}
/* Bridge & platform setup routines */
void __init
katana_intr_setup(void)
{
/* MPP 8, 9, and 10 */
mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
/* MPP 14 */
if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I))
mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000);
/*
* Define GPP 8,9,and 10 interrupt polarity as active low
* input signal and level triggered
*/
mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14));
mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14));
}
/* Config GPP intr ctlr to respond to level trigger */
mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
/* XXXX Erranum FEr PCI-#8 */
mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
/*
* Dismiss and then enable interrupt on GPP interrupt cause
* for CPU #0
*/
mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14));
mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
}
/*
* Dismiss and then enable interrupt on CPU #0 high cause reg
* BIT25 summarizes GPP interrupts 8-15
*/
mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
return;
}
void __init
katana_setup_peripherals(void)
{
u32 base, size_0, size_1;
/* Set up windows for boot CS, soldered & socketed flash, and CPLD */
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
/* Assume firmware set up window sizes correctly for dev 0 & 1 */
mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base, &size_0);
if (size_0 > 0) {
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
KATANA_SOLDERED_FLASH_BASE, size_0, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
}
mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base, &size_1);
if (size_1 > 0) {
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
(KATANA_SOLDERED_FLASH_BASE + size_0), size_1, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
}
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
cpld_base = (u32)ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
sram_base = (u32)ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
/* Set up Enet->SRAM window */
mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
/* Give enet r/w access to memory region */
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
/* Must wait until window set up before retrieving board id */
katana_get_board_id();
/* Enumerate pci bus (must know board id before getting proc number) */
if (katana_get_proc_num() == 0)
bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
#if defined(CONFIG_NOT_COHERENT_CACHE)
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
#else
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
/*
* Setting the SRAM to 0. Note that this generates parity errors on
* internal data path in SRAM since it's first time accessing it
* while after reset it's not configured.
*/
memset((void *)sram_base, 0, MV64360_SRAM_SIZE);
/* Only processor zero [on 3750] is an PCI interrupt controller */
if (katana_get_proc_num() == 0)
katana_intr_setup();
return;
}
static void __init
katana_setup_bridge(void)
{
struct mv64x60_setup_info si;
int i;
memset(&si, 0, sizeof(si));
si.phys_reg_base = KATANA_BRIDGE_REG_BASE;
si.pci_1.enable_bus = 1;
si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
si.pci_1.pci_io.pci_base_hi = 0;
si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
si.pci_1.pci_cmd_bits = 0;
si.pci_1.latency_timer = 0x80;
for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
#if defined(CONFIG_NOT_COHERENT_CACHE)
si.cpu_prot_options[i] = 0;
si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
si.pci_1.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_NONE |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
si.cpu_prot_options[i] = 0;
si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
si.pci_1.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_WB |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
#endif
}
/* Lookup PCI host bridges */
if (mv64x60_init(&bh, &si))
printk("Bridge initialization failed.\n");
pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = katana_map_irq;
ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
mv64x60_set_bus(&bh, 1, 0);
bh.hose_b->first_busno = 0;
bh.hose_b->last_busno = 0xff;
return;
}
static void __init
katana_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("katana_setup_arch: enter", 0);
set_tb(0, 0);
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
/*
* Set up the L2CR register.
*
* 750FX has only L2E, L2PE (bits 2-8 are reserved)
* DD2.0 has bug that requires the L2 to be in WRT mode
* avoid dirty data in cache
*/
if (PVR_REV(mfspr(PVR)) == 0x0200) {
printk("DD2.0 detected. Setting L2 cache"
"to Writethrough mode\n");
_set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
}
else
_set_L2CR(L2CR_L2E | L2CR_L2PE);
if (ppc_md.progress)
ppc_md.progress("katana_setup_arch: calling setup_bridge", 0);
katana_setup_bridge();
katana_setup_peripherals();
katana_enable_ipmi();
printk("Artesyn Communication Products, LLC - Katana(TM)\n");
if (ppc_md.progress)
ppc_md.progress("katana_setup_arch: exit", 0);
return;
}
/* Platform device data fixup routine. */
static int __init
katana_fixup_pd(void)
{
struct list_head *entry;
struct platform_device *pd;
struct device *dev;
#if defined(CONFIG_SERIAL_MPSC)
struct mpsc_pd_dd *dd;
#endif
#if defined(CONFIG_MV643XX_ETH)
struct mv64xxx_eth_pd_dd *eth_dd;
static u16 phy_addr[] = {
KATANA_ETH0_PHY_ADDR,
KATANA_ETH1_PHY_ADDR,
KATANA_ETH2_PHY_ADDR,
};
struct resource *rx_r;
struct resource *tx_r;
int rx_size = KATANA_ETH_RX_QUEUE_SIZE * ETH_DESC_SIZE;
int tx_size = KATANA_ETH_TX_QUEUE_SIZE * ETH_DESC_SIZE;
#endif
list_for_each(entry, &platform_bus_type.devices.list) {
dev = container_of(entry, struct device, bus_list);
pd = container_of(dev, struct platform_device, dev);
#if defined(CONFIG_SERIAL_MPSC)
if (!strncmp(pd->name, MPSC_CTLR_NAME, BUS_ID_SIZE)) {
dd = (struct mpsc_pd_dd *)dev_get_drvdata(&pd->dev);
dd->max_idle = 40; /* XXXX what should be? */
dd->default_baud = KATANA_DEFAULT_BAUD;
dd->brg_clk_src = KATANA_MPSC_CLK_SRC;
dd->brg_clk_freq = KATANA_MPSC_CLK_FREQ;
}
#endif
#if defined(CONFIG_MV643XX_ETH)
if (!strncmp(pd->name, MV64XXX_ETH_NAME, BUS_ID_SIZE)) {
eth_dd = (struct mv64xxx_eth_pd_dd *)
dev_get_drvdata(&pd->dev);
eth_dd->phy_addr = phy_addr[pd->id];
eth_dd->port_config = KATANA_ETH_PORT_CONFIG_VALUE;
eth_dd->port_config_extend =
KATANA_ETH_PORT_CONFIG_EXTEND_VALUE;
eth_dd->port_sdma_config =
KATANA_ETH_PORT_SDMA_CONFIG_VALUE;
eth_dd->port_serial_control =
KATANA_ETH_PORT_SERIAL_CONTROL_VALUE;
eth_dd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
eth_dd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
rx_r = &pd->resource[5];
rx_r->start = KATANA_INTERNAL_SRAM_BASE +
(rx_size + tx_size) * pd->id;
rx_r->end = rx_r->start + rx_size - 1;
rx_r->flags = IORESOURCE_MEM;
tx_r = &pd->resource[6];
tx_r->start = rx_r->start + rx_size;
tx_r->end = tx_r->start + tx_size - 1;
tx_r->flags = IORESOURCE_MEM;
}
#endif
}
return 0;
}
subsys_initcall(katana_fixup_pd);
static void
katana_restart(char *cmd)
{
volatile ulong i = 10000000;
/* issue hard reset to the reset command register */
out_8((volatile char *)(cpld_base + KATANA_CPLD_RST_CMD),
KATANA_CPLD_RST_CMD_HR);
while (i-- > 0) ;
panic("restart failed\n");
}
static void
katana_halt(void)
{
while (1) ;
/* NOTREACHED */
}
static void
katana_power_off(void)
{
katana_halt();
/* NOTREACHED */
}
static int
katana_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n");
seq_printf(m, "board\t\t: ");
switch (katana_id) {
case KATANA_ID_3750:
seq_printf(m, "Katana 3750\n");
break;
case KATANA_ID_750I:
seq_printf(m, "Katana 750i\n");
break;
case KATANA_ID_752I:
seq_printf(m, "Katana 752i\n");
break;
default:
seq_printf(m, "Unknown\n");
break;
}
seq_printf(m, "product ID\t: 0x%x\n",
in_8((volatile char *)(cpld_base + KATANA_CPLD_PRODUCT_ID)));
seq_printf(m, "hardware rev\t: 0x%x\n",
in_8((volatile char *)(cpld_base+KATANA_CPLD_HARDWARE_VER)));
seq_printf(m, "PLD rev\t\t: 0x%x\n",
in_8((volatile char *)(cpld_base + KATANA_CPLD_PLD_VER)));
seq_printf(m, "PLB freq\t: %ldMhz\n", katana_bus_freq() / 1000000);
seq_printf(m, "PCI\t\t: %sMonarch\n", katana_is_monarch()? "" : "Non-");
return 0;
}
static void __init
katana_calibrate_decr(void)
{
ulong freq;
freq = katana_bus_freq() / 4;
printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
freq / 1000000, freq % 1000000);
tb_ticks_per_jiffy = freq / HZ;
tb_to_us = mulhwu_scale_factor(freq, 1000000);
return;
}
unsigned long __init
katana_find_end_of_memory(void)
{
return mv64x60_get_mem_size(KATANA_BRIDGE_REG_BASE,
MV64x60_TYPE_MV64360);
}
static inline void
katana_set_bat(void)
{
mb();
mtspr(DBAT2U, 0xf0001ffe);
mtspr(DBAT2L, 0xf000002a);
mb();
return;
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
static void __init
katana_map_io(void)
{
io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO);
}
#endif
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
isa_mem_base = 0;
ppc_md.setup_arch = katana_setup_arch;
ppc_md.show_cpuinfo = katana_show_cpuinfo;
ppc_md.init_IRQ = mv64360_init_irq;
ppc_md.get_irq = mv64360_get_irq;
ppc_md.restart = katana_restart;
ppc_md.power_off = katana_power_off;
ppc_md.halt = katana_halt;
ppc_md.find_end_of_memory = katana_find_end_of_memory;
ppc_md.calibrate_decr = katana_calibrate_decr;
#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
ppc_md.setup_io_mappings = katana_map_io;
ppc_md.progress = mv64x60_mpsc_progress;
mv64x60_progress_init(KATANA_BRIDGE_REG_BASE);
#endif
katana_set_bat(); /* Need for katana_find_end_of_memory and progress */
return;
}
arch/ppc/platforms/katana.h 0 → 100644
View file @ e1b2de6e
/*
* arch/ppc/platforms/katana.h
*
* Definitions for Artesyn Katana750i/3750 board.
*
* Tim Montgomery <timm@artesyncp.com>
*
* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
* Based on code done by Mark A. Greer <mgreer@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
* The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
* PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
* We'll only use one PCI MEM window on each PCI bus.
*
* This is the CPU physical memory map (windows must be at least 1MB and start
* on a boundary that is a multiple of the window size):
*
* 0xff800000-0xffffffff - Boot window
* 0xf8400000-0xf85fffff - Internal SRAM
* 0xf8200000-0xf823ffff - CPLD
* 0xf8100000-0xf810ffff - MV64360 Registers
* 0xf8000000-0xf80fffff - PLCC socket
* 0xf0000000-0xf01fffff - Consistent memory pool
* 0xe8000000-0xefffffff - soldered flash
* 0xc0000000-0xc0ffffff - PCI I/O
* 0x80000000-0xbfffffff - PCI MEM
*/
#ifndef __PPC_PLATFORMS_KATANA_H
#define __PPC_PLATFORMS_KATANA_H
/* CPU Physical Memory Map setup. */
#define KATANA_BOOT_WINDOW_BASE 0xff800000
#define KATANA_INTERNAL_SRAM_BASE 0xf8400000
#define KATANA_CPLD_BASE 0xf8200000
#define KATANA_BRIDGE_REG_BASE 0xf8100000
#define KATANA_SOCKET_BASE 0xf8000000
#define KATANA_SOLDERED_FLASH_BASE 0xe8000000
#define KATANA_BOOT_WINDOW_SIZE_ACTUAL 0x00800000 /* 8MB */
#define KATANA_CPLD_SIZE_ACTUAL 0x00020000 /* 128KB */
#define KATANA_SOCKETED_FLASH_SIZE_ACTUAL 0x00080000 /* 512KB */
#define KATANA_SOLDERED_FLASH_SIZE_ACTUAL 0x02000000 /* 32MB */
#define KATANA_BOOT_WINDOW_SIZE max(MV64360_WINDOW_SIZE_MIN, \
KATANA_BOOT_WINDOW_SIZE_ACTUAL)
#define KATANA_CPLD_SIZE max(MV64360_WINDOW_SIZE_MIN, \
KATANA_CPLD_SIZE_ACTUAL)
#define KATANA_SOCKETED_FLASH_SIZE max(MV64360_WINDOW_SIZE_MIN, \
KATANA_SOCKETED_FLASH_SIZE_ACTUAL)
#define KATANA_SOLDERED_FLASH_SIZE max(MV64360_WINDOW_SIZE_MIN, \
KATANA_SOLDERED_FLASH_SIZE_ACTUAL)
#define KATANA_PCI1_MEM_START_PROC_ADDR 0x80000000
#define KATANA_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
#define KATANA_PCI1_MEM_START_PCI_LO_ADDR 0x80000000
#define KATANA_PCI1_MEM_SIZE 0x40000000
#define KATANA_PCI1_IO_START_PROC_ADDR 0xc0000000
#define KATANA_PCI1_IO_START_PCI_ADDR 0x00000000
#define KATANA_PCI1_IO_SIZE 0x01000000
/* Board-specific IRQ info */
#define KATANA_PCI_INTA_IRQ_3750 64+8
#define KATANA_PCI_INTB_IRQ_3750 64+9
#define KATANA_PCI_INTC_IRQ_3750 64+10
#define KATANA_PCI_INTA_IRQ_750i 64+8
#define KATANA_PCI_INTB_IRQ_750i 64+9
#define KATANA_PCI_INTC_IRQ_750i 64+10
#define KATANA_PCI_INTD_IRQ_750i 64+14
#define KATANA_CPLD_RST_EVENT 0x00000000
#define KATANA_CPLD_RST_CMD 0x00001000
#define KATANA_CPLD_PCI_ERR_INT_EN 0x00002000
#define KATANA_CPLD_PCI_ERR_INT_PEND 0x00003000
#define KATANA_CPLD_PRODUCT_ID 0x00004000
#define KATANA_CPLD_EREADY 0x00005000
#define KATANA_CPLD_HARDWARE_VER 0x00007000
#define KATANA_CPLD_PLD_VER 0x00008000
#define KATANA_CPLD_BD_CFG_0 0x00009000
#define KATANA_CPLD_BD_CFG_1 0x0000a000
#define KATANA_CPLD_BD_CFG_3 0x0000c000
#define KATANA_CPLD_LED 0x0000d000
#define KATANA_CPLD_RESET_OUT 0x0000e000
#define KATANA_CPLD_RST_EVENT_INITACT 0x80
#define KATANA_CPLD_RST_EVENT_SW 0x40
#define KATANA_CPLD_RST_EVENT_WD 0x20
#define KATANA_CPLD_RST_EVENT_COPS 0x10
#define KATANA_CPLD_RST_EVENT_COPH 0x08
#define KATANA_CPLD_RST_EVENT_CPCI 0x02
#define KATANA_CPLD_RST_EVENT_FP 0x01
#define KATANA_CPLD_RST_CMD_SCL 0x80
#define KATANA_CPLD_RST_CMD_SDA 0x40
#define KATANA_CPLD_RST_CMD_I2C 0x10
#define KATANA_CPLD_RST_CMD_FR 0x08
#define KATANA_CPLD_RST_CMD_SR 0x04
#define KATANA_CPLD_RST_CMD_HR 0x01
#define KATANA_CPLD_BD_CFG_0_SYSCLK_MASK 0xc0
#define KATANA_CPLD_BD_CFG_0_SYSCLK_133 0xc0
#define KATANA_CPLD_BD_CFG_0_SYSCLK_100 0x40
#define KATANA_CPLD_BD_CFG_1_FL_BANK_MASK 0x03
#define KATANA_CPLD_BD_CFG_1_FL_BANK_16MB 0x00
#define KATANA_CPLD_BD_CFG_1_FL_BANK_32MB 0x01
#define KATANA_CPLD_BD_CFG_1_FL_BANK_64MB 0x02
#define KATANA_CPLD_BD_CFG_1_FL_BANK_128MB 0x03
#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_MASK 0x04
#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_ONE 0x00
#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_TWO 0x04
#define KATANA_CPLD_BD_CFG_3_MONARCH 0x04
#define KATANA_CPLD_RESET_OUT_PORTSEL 0x80
#define KATANA_CPLD_RESET_OUT_WD 0x20
#define KATANA_CPLD_RESET_OUT_COPH 0x08
#define KATANA_CPLD_RESET_OUT_PCI_RST_PCI 0x02
#define KATANA_CPLD_RESET_OUT_PCI_RST_FP 0x01
#define KATANA_MBOX_RESET_REQUEST 0xC83A
#define KATANA_MBOX_RESET_ACK 0xE430
#define KATANA_MBOX_RESET_DONE 0x32E5
#define HSL_PLD_BASE 0x00010000
#define HSL_PLD_J4SGA_REG_OFF 0
#define HSL_PLD_J4GA_REG_OFF 1
#define HSL_PLD_J2GA_REG_OFF 2
#define GA_MASK 0x1f
#define HSL_PLD_SIZE 0x1000
#define K3750_GPP_GEO_ADDR_PINS 0xf8000000
#define K3750_GPP_GEO_ADDR_SHIFT 27
#define K3750_GPP_EVENT_PROC_0 (1 << 21)
#define K3750_GPP_EVENT_PROC_1_2 (1 << 2)
#define PCI_VENDOR_ID_ARTESYN 0x1223
#define PCI_DEVICE_ID_KATANA_3750_PROC0 0x0041
#define PCI_DEVICE_ID_KATANA_3750_PROC1 0x0042
#define PCI_DEVICE_ID_KATANA_3750_PROC2 0x0043
#define COPROC_MEM_FUNCTION 0
#define COPROC_MEM_BAR 0
#define COPROC_REGS_FUNCTION 0
#define COPROC_REGS_BAR 4
#define COPROC_FLASH_FUNCTION 2
#define COPROC_FLASH_BAR 4
#define KATANA_IPMB_LOCAL_I2C_ADDR 0x08
#define KATANA_DEFAULT_BAUD 9600
#define KATANA_MPSC_CLK_SRC 8 /* TCLK */
#define KATANA_MPSC_CLK_FREQ 133333333 /* 133.3333... MHz */
#define KATANA_ETH0_PHY_ADDR 12
#define KATANA_ETH1_PHY_ADDR 11
#define KATANA_ETH2_PHY_ADDR 4
#define KATANA_PRODUCT_ID_3750 0x01
#define KATANA_PRODUCT_ID_750i 0x02
#define KATANA_PRODUCT_ID_752i 0x04
#define KATANA_ETH_TX_QUEUE_SIZE 1050
#define KATANA_ETH_RX_QUEUE_SIZE 450
#define KATANA_ETH_PORT_CONFIG_VALUE \
ETH_UNICAST_NORMAL_MODE | \
ETH_DEFAULT_RX_QUEUE_0 | \
ETH_DEFAULT_RX_ARP_QUEUE_0 | \
ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
ETH_RECEIVE_BC_IF_IP | \
ETH_RECEIVE_BC_IF_ARP | \
ETH_CAPTURE_TCP_FRAMES_DIS | \
ETH_CAPTURE_UDP_FRAMES_DIS | \
ETH_DEFAULT_RX_TCP_QUEUE_0 | \
ETH_DEFAULT_RX_UDP_QUEUE_0 | \
ETH_DEFAULT_RX_BPDU_QUEUE_0
#define KATANA_ETH_PORT_CONFIG_EXTEND_VALUE \
ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
ETH_PARTITION_DISABLE
#define GT_ETH_IPG_INT_RX(value) \
((value & 0x3fff) << 8)
#define KATANA_ETH_PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_4_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_4_64BIT
#define KATANA_ETH_PORT_SERIAL_CONTROL_VALUE \
ETH_FORCE_LINK_PASS | \
ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
ETH_ADV_SYMMETRIC_FLOW_CTRL | \
ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
ETH_FORCE_BP_MODE_NO_JAM | \
BIT9 | \
ETH_DO_NOT_FORCE_LINK_FAIL | \
ETH_RETRANSMIT_16_ATTEMPTS | \
ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
ETH_DTE_ADV_0 | \
ETH_DISABLE_AUTO_NEG_BYPASS | \
ETH_AUTO_NEG_NO_CHANGE | \
ETH_MAX_RX_PACKET_9700BYTE | \
ETH_CLR_EXT_LOOPBACK | \
ETH_SET_FULL_DUPLEX_MODE | \
ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
#ifndef __ASSEMBLY__
typedef enum {
KATANA_ID_3750,
KATANA_ID_750I,
KATANA_ID_752I,
KATANA_ID_MAX
} katana_id_t;
#endif
#endif /* __PPC_PLATFORMS_KATANA_H */
arch/ppc/syslib/Makefile
View file @ e1b2de6e
...@@ -47,6 +47,7 @@ obj-$(CONFIG_GT64260) += gt64260_pic.o ...@@ -47,6 +47,7 @@ obj-$(CONFIG_GT64260) += gt64260_pic.o
obj-$(CONFIG_K2) += i8259.o indirect_pci.o todc_time.o \ obj-$(CONFIG_K2) += i8259.o indirect_pci.o todc_time.o \
pci_auto.o pci_auto.o
obj-$(CONFIG_LOPEC) += i8259.o pci_auto.o todc_time.o obj-$(CONFIG_LOPEC) += i8259.o pci_auto.o todc_time.o
obj-$(CONFIG_KATANA) += pci_auto.o
obj-$(CONFIG_MCPN765) += todc_time.o indirect_pci.o pci_auto.o \ obj-$(CONFIG_MCPN765) += todc_time.o indirect_pci.o pci_auto.o \
open_pic.o i8259.o hawk_common.o open_pic.o i8259.o hawk_common.o
obj-$(CONFIG_MENF1) += todc_time.o i8259.o mpc10x_common.o \ obj-$(CONFIG_MENF1) += todc_time.o i8259.o mpc10x_common.o \
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7