Commit e795dd42 authored by Sukadev Bhattiprolu's avatar Sukadev Bhattiprolu Committed by Arnaldo Carvalho de Melo

perf vendor events powerpc: Update POWER9 events

The POWER9 hardware has dropped support for several events, added
a few new events and changed the category for a couple of events.

Update the POWER9 events in Linux to reflect these changes.
Signed-off-by: default avatarSukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/r/20171108201938.GA10985@us.ibm.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent fa48c892
...@@ -124,11 +124,6 @@ ...@@ -124,11 +124,6 @@
"EventName": "PM_CMPLU_STALL_LARX", "EventName": "PM_CMPLU_STALL_LARX",
"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied" "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
}, },
{,
"EventCode": "0x3006C",
"EventName": "PM_RUN_CYC_SMT2_MODE",
"BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode"
},
{, {,
"EventCode": "0x1C058", "EventCode": "0x1C058",
"EventName": "PM_DTLB_MISS_16G", "EventName": "PM_DTLB_MISS_16G",
......
[ [
{,
"EventCode": "0x3E15C",
"EventName": "PM_MRK_L2_TM_ST_ABORT_SISTER",
"BriefDescription": "TM marked store abort for this thread"
},
{, {,
"EventCode": "0x25044", "EventCode": "0x25044",
"EventName": "PM_IPTEG_FROM_L31_MOD", "EventName": "PM_IPTEG_FROM_L31_MOD",
......
[ [
{,
"EventCode": "0x3C052",
"EventName": "PM_DATA_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load"
},
{, {,
"EventCode": "0x3013E", "EventCode": "0x3013E",
"EventName": "PM_MRK_STALL_CMPLU_CYC", "EventName": "PM_MRK_STALL_CMPLU_CYC",
...@@ -254,6 +249,11 @@ ...@@ -254,6 +249,11 @@
"EventName": "PM_RADIX_PWC_L1_PDE_FROM_L3", "EventName": "PM_RADIX_PWC_L1_PDE_FROM_L3",
"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache" "BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache"
}, },
{,
"EventCode": "0x3C052",
"EventName": "PM_DATA_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load"
},
{, {,
"EventCode": "0x4D142", "EventCode": "0x4D142",
"EventName": "PM_MRK_DATA_FROM_L3", "EventName": "PM_MRK_DATA_FROM_L3",
...@@ -434,21 +434,6 @@ ...@@ -434,21 +434,6 @@
"EventName": "PM_ITLB_MISS", "EventName": "PM_ITLB_MISS",
"BriefDescription": "ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed" "BriefDescription": "ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed"
}, },
{,
"EventCode": "0x2D024",
"EventName": "PM_RADIX_PWC_L2_HIT",
"BriefDescription": "A radix translation attempt missed in the TLB but hit on both the first and second levels of page walk cache."
},
{,
"EventCode": "0x3F056",
"EventName": "PM_RADIX_PWC_L3_HIT",
"BriefDescription": "A radix translation attempt missed in the TLB but hit on the first, second, and third levels of page walk cache."
},
{,
"EventCode": "0x4E014",
"EventName": "PM_TM_TX_PASS_RUN_INST",
"BriefDescription": "Run instructions spent in successful transactions"
},
{, {,
"EventCode": "0x1E044", "EventCode": "0x1E044",
"EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT", "EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT",
......
...@@ -124,6 +124,11 @@ ...@@ -124,6 +124,11 @@
"EventName": "PM_PMC5_OVERFLOW", "EventName": "PM_PMC5_OVERFLOW",
"BriefDescription": "Overflow from counter 5" "BriefDescription": "Overflow from counter 5"
}, },
{,
"EventCode": "0x4505E",
"EventName": "PM_FLOP_CMPL",
"BriefDescription": "Floating Point Operation Finished"
},
{, {,
"EventCode": "0x2C018", "EventCode": "0x2C018",
"EventName": "PM_CMPLU_STALL_DMISS_L21_L31", "EventName": "PM_CMPLU_STALL_DMISS_L21_L31",
...@@ -389,11 +394,6 @@ ...@@ -389,11 +394,6 @@
"EventName": "PM_ICT_NOSLOT_BR_MPRED", "EventName": "PM_ICT_NOSLOT_BR_MPRED",
"BriefDescription": "Ict empty for this thread due to branch mispred" "BriefDescription": "Ict empty for this thread due to branch mispred"
}, },
{,
"EventCode": "0x3405E",
"EventName": "PM_IFETCH_THROTTLE",
"BriefDescription": "Cycles in which Instruction fetch throttle was active."
},
{, {,
"EventCode": "0x1F148", "EventCode": "0x1F148",
"EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE", "EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
...@@ -422,7 +422,7 @@ ...@@ -422,7 +422,7 @@
{, {,
"EventCode": "0xD0A8", "EventCode": "0xD0A8",
"EventName": "PM_DSLB_MISS", "EventName": "PM_DSLB_MISS",
"BriefDescription": "Data SLB Miss - Total of all segment sizes" "BriefDescription": "gate_and(sd_pc_c0_comp_valid AND sd_pc_c0_comp_thread(0:1)=tid,sd_pc_c0_comp_ppc_count(0:3)) + gate_and(sd_pc_c1_comp_valid AND sd_pc_c1_comp_thread(0:1)=tid,sd_pc_c1_comp_ppc_count(0:3))"
}, },
{, {,
"EventCode": "0x4C058", "EventCode": "0x4C058",
......
...@@ -89,11 +89,6 @@ ...@@ -89,11 +89,6 @@
"EventName": "PM_STCX_FAIL", "EventName": "PM_STCX_FAIL",
"BriefDescription": "stcx failed" "BriefDescription": "stcx failed"
}, },
{,
"EventCode": "0x20112",
"EventName": "PM_MRK_NTF_FIN",
"BriefDescription": "Marked next to finish instruction finished"
},
{, {,
"EventCode": "0x300F0", "EventCode": "0x300F0",
"EventName": "PM_ST_MISS_L1", "EventName": "PM_ST_MISS_L1",
......
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