Commit e8186eec authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/psp: flush HDP write fifo after submitting cmds to the psp

We need to make sure the fifo is flushed before we ask the psp to
process the commands.
Reviewed-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5222d261
...@@ -266,6 +266,7 @@ static int psp_v10_0_cmd_submit(struct psp_context *psp, ...@@ -266,6 +266,7 @@ static int psp_v10_0_cmd_submit(struct psp_context *psp,
write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
write_frame->fence_value = index; write_frame->fence_value = index;
amdgpu_asic_flush_hdp(adev, NULL);
/* Update the write Pointer in DWORDs */ /* Update the write Pointer in DWORDs */
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
......
...@@ -549,6 +549,7 @@ static int psp_v11_0_cmd_submit(struct psp_context *psp, ...@@ -549,6 +549,7 @@ static int psp_v11_0_cmd_submit(struct psp_context *psp,
write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
write_frame->fence_value = index; write_frame->fence_value = index;
amdgpu_asic_flush_hdp(adev, NULL);
/* Update the write Pointer in DWORDs */ /* Update the write Pointer in DWORDs */
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
......
...@@ -378,6 +378,7 @@ static int psp_v12_0_cmd_submit(struct psp_context *psp, ...@@ -378,6 +378,7 @@ static int psp_v12_0_cmd_submit(struct psp_context *psp,
write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
write_frame->fence_value = index; write_frame->fence_value = index;
amdgpu_asic_flush_hdp(adev, NULL);
/* Update the write Pointer in DWORDs */ /* Update the write Pointer in DWORDs */
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
......
...@@ -454,6 +454,7 @@ static int psp_v3_1_cmd_submit(struct psp_context *psp, ...@@ -454,6 +454,7 @@ static int psp_v3_1_cmd_submit(struct psp_context *psp,
write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
write_frame->fence_value = index; write_frame->fence_value = index;
amdgpu_asic_flush_hdp(adev, NULL);
/* Update the write Pointer in DWORDs */ /* Update the write Pointer in DWORDs */
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
......
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