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Commit ef1dfa73 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'at91-cleanup5' of... 

Merge tag 'at91-cleanup5' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/cleanup

Pull "Fifth batch of cleanup/SoC for 3.19" from Nicolas Ferre:

- removal of now dead code and AT91-specific driver
- removal of !DT initialization in some core AT91 drivers
- simplification of Kconfig DT board file selection: now automatic

* tag 'at91-cleanup5' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
  ARM: at91: remove unused board.h file
  ARM: at91: remove unneeded header files
  ARM: at91/clocksource: remove !DT PIT initializations
  ARM: at91: at91rm9200 ST initialization is now DT only
  ARM: at91: remove old AT91-specific drivers
  ARM: at91: cleanup initilisation code by removing dead code
  ARM: at91/Kconfig: select board files automatically
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 3d266069 ba62a859
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arch/arm/mach-at91/Kconfig
View file @ ef1dfa73
......@@ -174,21 +174,11 @@ config SOC_AT91SAM9N12
# ----------------------------------------------------------
endif # SOC_SAM_V4_V5
comment "Generic Board Type"
config MACH_AT91RM9200_DT
bool "Atmel AT91RM9200 Evaluation Kits with device-tree support"
depends on SOC_AT91RM9200
help
Select this if you want to experiment device-tree with
an Atmel RM9200 Evaluation Kit.
def_bool SOC_AT91RM9200
config MACH_AT91SAM9_DT
bool "Atmel AT91SAM Evaluation Kits with device-tree support"
depends on SOC_AT91SAM9
help
Select this if you want to experiment device-tree with
an Atmel Evaluation Kit.
def_bool SOC_AT91SAM9
# ----------------------------------------------------------
......
arch/arm/mach-at91/Makefile
View file @ ef1dfa73
......@@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
obj-y := gpio.o setup.o sysirq_mask.o
obj-y := setup.o sysirq_mask.o
obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
......@@ -25,9 +25,6 @@ obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
# SAMA5 board with device-tree
obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o
# Drivers
obj-y += leds.o
# Power Management
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
......
arch/arm/mach-at91/at91_tc.h deleted 100644 → 0
View file @ 3d266069
/*
* arch/arm/mach-at91/include/mach/at91_tc.h
*
* Copyright (C) SAN People
*
* Timer/Counter Unit (TC) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_TC_H
#define AT91_TC_H
#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
#define AT91_TC_TC0XC0S_NONE (1 << 0)
#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
#define AT91_TC_TC1XC1S_NONE (1 << 2)
#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
#define AT91_TC_TC2XC2S_NONE (1 << 4)
#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
#define AT91_TC_CCR 0x00 /* Channel Control Register */
#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
#define AT91_TC_CMR 0x04 /* Channel Mode Register */
#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
#define AT91_TC_TIMER_CLOCK1 (0 << 0)
#define AT91_TC_TIMER_CLOCK2 (1 << 0)
#define AT91_TC_TIMER_CLOCK3 (2 << 0)
#define AT91_TC_TIMER_CLOCK4 (3 << 0)
#define AT91_TC_TIMER_CLOCK5 (4 << 0)
#define AT91_TC_XC0 (5 << 0)
#define AT91_TC_XC1 (6 << 0)
#define AT91_TC_XC2 (7 << 0)
#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
#define AT91_TC_EEVTEDG_NONE (0 << 8)
#define AT91_TC_EEVTEDG_RISING (1 << 8)
#define AT91_TC_EEVTEDG_FALLING (2 << 8)
#define AT91_TC_EEVTEDG_BOTH (3 << 8)
#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
#define AT91_TC_EEVT_TIOB (0 << 10)
#define AT91_TC_EEVT_XC0 (1 << 10)
#define AT91_TC_EEVT_XC1 (2 << 10)
#define AT91_TC_EEVT_XC2 (3 << 10)
#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
#define AT91_TC_WAVESEL_UP (0 << 13)
#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
#define AT91_TC_ACPA_NONE (0 << 16)
#define AT91_TC_ACPA_SET (1 << 16)
#define AT91_TC_ACPA_CLEAR (2 << 16)
#define AT91_TC_ACPA_TOGGLE (3 << 16)
#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
#define AT91_TC_ACPC_NONE (0 << 18)
#define AT91_TC_ACPC_SET (1 << 18)
#define AT91_TC_ACPC_CLEAR (2 << 18)
#define AT91_TC_ACPC_TOGGLE (3 << 18)
#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
#define AT91_TC_AEEVT_NONE (0 << 20)
#define AT91_TC_AEEVT_SET (1 << 20)
#define AT91_TC_AEEVT_CLEAR (2 << 20)
#define AT91_TC_AEEVT_TOGGLE (3 << 20)
#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
#define AT91_TC_ASWTRG_NONE (0 << 22)
#define AT91_TC_ASWTRG_SET (1 << 22)
#define AT91_TC_ASWTRG_CLEAR (2 << 22)
#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
#define AT91_TC_BCPB_NONE (0 << 24)
#define AT91_TC_BCPB_SET (1 << 24)
#define AT91_TC_BCPB_CLEAR (2 << 24)
#define AT91_TC_BCPB_TOGGLE (3 << 24)
#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
#define AT91_TC_BCPC_NONE (0 << 26)
#define AT91_TC_BCPC_SET (1 << 26)
#define AT91_TC_BCPC_CLEAR (2 << 26)
#define AT91_TC_BCPC_TOGGLE (3 << 26)
#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
#define AT91_TC_BEEVT_NONE (0 << 28)
#define AT91_TC_BEEVT_SET (1 << 28)
#define AT91_TC_BEEVT_CLEAR (2 << 28)
#define AT91_TC_BEEVT_TOGGLE (3 << 28)
#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
#define AT91_TC_BSWTRG_NONE (0 << 30)
#define AT91_TC_BSWTRG_SET (1 << 30)
#define AT91_TC_BSWTRG_CLEAR (2 << 30)
#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
#define AT91_TC_CV 0x10 /* Counter Value */
#define AT91_TC_RA 0x14 /* Register A */
#define AT91_TC_RB 0x18 /* Register B */
#define AT91_TC_RC 0x1c /* Register C */
#define AT91_TC_SR 0x20 /* Status Register */
#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
#endif
arch/arm/mach-at91/at91rm9200_time.c
View file @ ef1dfa73
......@@ -183,7 +183,6 @@ static struct clock_event_device clkevt = {
void __iomem *at91_st_base;
EXPORT_SYMBOL_GPL(at91_st_base);
#ifdef CONFIG_OF
static struct of_device_id at91rm9200_st_timer_ids[] = {
{ .compatible = "atmel,at91rm9200-st" },
{ /* sentinel */ }
......@@ -219,28 +218,6 @@ static int __init of_at91rm9200_st_init(void)
err:
return -EINVAL;
}
#else
static int __init of_at91rm9200_st_init(void)
{
return -EINVAL;
}
#endif
void __init at91rm9200_ioremap_st(u32 addr)
{
#ifdef CONFIG_OF
struct device_node *np;
np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
if (np) {
of_node_put(np);
return;
}
#endif
at91_st_base = ioremap(addr, 256);
if (!at91_st_base)
panic("Impossible to ioremap ST\n");
}
/*
* ST (system timer) module supports both clockevents and clocksource.
......
arch/arm/mach-at91/board-dt-rm9200.c
View file @ ef1dfa73
......@@ -26,9 +26,7 @@
static void __init at91rm9200_dt_timer_init(void)
{
#if defined(CONFIG_COMMON_CLK)
of_clk_init(NULL);
#endif
at91rm9200_timer_init();
}
......
arch/arm/mach-at91/board-dt-sam9.c
View file @ ef1dfa73
......@@ -21,7 +21,6 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include "board.h"
#include "generic.h"
static const char *at91_dt_board_compat[] __initdata = {
......
arch/arm/mach-at91/board.h deleted 100644 → 0
View file @ 3d266069
/*
* arch/arm/mach-at91/include/mach/board.h
*
* Copyright (C) 2005 HP Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* These are data structures found in platform_device.dev.platform_data,
* and describing board-specific data needed by drivers. For example,
* which pin is used for a given GPIO role.
*
* In 2.6, drivers should strongly avoid board-specific knowledge so
* that supporting new boards normally won't require driver patches.
* Most board-specific knowledge should be in arch/.../board-*.c files.
*/
#ifndef __ASM_ARCH_BOARD_H
#define __ASM_ARCH_BOARD_H
#include <linux/platform_data/atmel.h>
/* USB Device */
extern void __init at91_add_device_udc(struct at91_udc_data *data);
/* USB High Speed Device */
extern void __init at91_add_device_usba(struct usba_platform_data *data);
/* Compact Flash */
extern void __init at91_add_device_cf(struct at91_cf_data *data);
/* MMC / SD */
/* atmel-mci platform config */
extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data);
extern void __init at91_add_device_eth(struct macb_platform_data *data);
/* USB Host */
extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
extern void __init at91_add_device_nand(struct atmel_nand_data *data);
/* I2C*/
extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
/* SPI */
extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
/* Serial */
#define ATMEL_UART_CTS 0x01
#define ATMEL_UART_RTS 0x02
#define ATMEL_UART_DSR 0x04
#define ATMEL_UART_DTR 0x08
#define ATMEL_UART_DCD 0x10
#define ATMEL_UART_RI 0x20
extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
extern struct platform_device *atmel_default_console_device;
extern void __init at91_add_device_serial(void);
/*
* PWM
*/
#define AT91_PWM0 0
#define AT91_PWM1 1
#define AT91_PWM2 2
#define AT91_PWM3 3
extern void __init at91_add_device_pwm(u32 mask);
/*
* SSC -- accessed through ssc_request(id). Drivers don't bind to SSC
* platform devices. Their SSC ID is part of their configuration data,
* along with information about which SSC signals they should use.
*/
#define ATMEL_SSC_TK 0x01
#define ATMEL_SSC_TF 0x02
#define ATMEL_SSC_TD 0x04
#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
#define ATMEL_SSC_RK 0x10
#define ATMEL_SSC_RF 0x20
#define ATMEL_SSC_RD 0x40
#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
/* LCD Controller */
struct atmel_lcdfb_pdata;
extern void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data);
/* AC97 */
extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
/* ISI */
struct isi_platform_data;
extern void __init at91_add_device_isi(struct isi_platform_data *data,
bool use_pck_as_mck);
/* CAN */
extern void __init at91_add_device_can(struct at91_can_data *data);
/* LEDs */
extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
#endif
arch/arm/mach-at91/generic.h
View file @ ef1dfa73
......@@ -22,52 +22,19 @@ extern void __init at91_init_sram(int bank, unsigned long base,
/* Processors */
extern void __init at91rm9200_set_type(int type);
extern void __init at91_initialize(unsigned long main_clock);
extern void __init at91rm9200_dt_initialize(void);
extern void __init at91_dt_initialize(void);
/* Interrupts */
extern void __init at91_init_irq_default(void);
extern void __init at91_init_interrupts(unsigned int priority[]);
extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
/* Devices */
extern void __init at91_register_devices(void);
/* Timer */
extern void __init at91_init_time(void);
extern void at91rm9200_ioremap_st(u32 addr);
extern void at91rm9200_timer_init(void);
extern void at91sam926x_ioremap_pit(u32 addr);
extern void at91sam926x_pit_init(int irq);
/* Power Management */
extern void at91_irq_suspend(void);
extern void at91_irq_resume(void);
/* idle */
extern void at91sam9_idle(void);
/* Matrix */
extern void at91_ioremap_matrix(u32 base_addr);
/* Ram Controler */
extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
/* GPIO */
#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
struct at91_gpio_bank {
unsigned short id; /* peripheral ID */
unsigned long regbase; /* offset from system peripheral base */
};
extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
extern void __init at91_gpio_irq_setup(void);
extern int __init at91_gpio_of_irq_setup(struct device_node *node,
struct device_node *parent);
extern u32 at91_get_extern_irq(void);
#endif /* _AT91_GENERIC_H */
arch/arm/mach-at91/gpio.c deleted 100644 → 0
View file @ 3d266069
This diff is collapsed.
arch/arm/mach-at91/gpio.h deleted 100644 → 0
View file @ 3d266069
/*
* arch/arm/mach-at91/include/mach/gpio.h
*
* Copyright (C) 2005 HP Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
#define __ASM_ARCH_AT91RM9200_GPIO_H
#include <linux/kernel.h>
#include <asm/irq.h>
#define MAX_GPIO_BANKS 5
#define NR_BUILTIN_GPIO (MAX_GPIO_BANKS * 32)
/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
#define AT91_PIN_PA0 (0x00 + 0)
#define AT91_PIN_PA1 (0x00 + 1)
#define AT91_PIN_PA2 (0x00 + 2)
#define AT91_PIN_PA3 (0x00 + 3)
#define AT91_PIN_PA4 (0x00 + 4)
#define AT91_PIN_PA5 (0x00 + 5)
#define AT91_PIN_PA6 (0x00 + 6)
#define AT91_PIN_PA7 (0x00 + 7)
#define AT91_PIN_PA8 (0x00 + 8)
#define AT91_PIN_PA9 (0x00 + 9)
#define AT91_PIN_PA10 (0x00 + 10)
#define AT91_PIN_PA11 (0x00 + 11)
#define AT91_PIN_PA12 (0x00 + 12)
#define AT91_PIN_PA13 (0x00 + 13)
#define AT91_PIN_PA14 (0x00 + 14)
#define AT91_PIN_PA15 (0x00 + 15)
#define AT91_PIN_PA16 (0x00 + 16)
#define AT91_PIN_PA17 (0x00 + 17)
#define AT91_PIN_PA18 (0x00 + 18)
#define AT91_PIN_PA19 (0x00 + 19)
#define AT91_PIN_PA20 (0x00 + 20)
#define AT91_PIN_PA21 (0x00 + 21)
#define AT91_PIN_PA22 (0x00 + 22)
#define AT91_PIN_PA23 (0x00 + 23)
#define AT91_PIN_PA24 (0x00 + 24)
#define AT91_PIN_PA25 (0x00 + 25)
#define AT91_PIN_PA26 (0x00 + 26)
#define AT91_PIN_PA27 (0x00 + 27)
#define AT91_PIN_PA28 (0x00 + 28)
#define AT91_PIN_PA29 (0x00 + 29)
#define AT91_PIN_PA30 (0x00 + 30)
#define AT91_PIN_PA31 (0x00 + 31)
#define AT91_PIN_PB0 (0x20 + 0)
#define AT91_PIN_PB1 (0x20 + 1)
#define AT91_PIN_PB2 (0x20 + 2)
#define AT91_PIN_PB3 (0x20 + 3)
#define AT91_PIN_PB4 (0x20 + 4)
#define AT91_PIN_PB5 (0x20 + 5)
#define AT91_PIN_PB6 (0x20 + 6)
#define AT91_PIN_PB7 (0x20 + 7)
#define AT91_PIN_PB8 (0x20 + 8)
#define AT91_PIN_PB9 (0x20 + 9)
#define AT91_PIN_PB10 (0x20 + 10)
#define AT91_PIN_PB11 (0x20 + 11)
#define AT91_PIN_PB12 (0x20 + 12)
#define AT91_PIN_PB13 (0x20 + 13)
#define AT91_PIN_PB14 (0x20 + 14)
#define AT91_PIN_PB15 (0x20 + 15)
#define AT91_PIN_PB16 (0x20 + 16)
#define AT91_PIN_PB17 (0x20 + 17)
#define AT91_PIN_PB18 (0x20 + 18)
#define AT91_PIN_PB19 (0x20 + 19)
#define AT91_PIN_PB20 (0x20 + 20)
#define AT91_PIN_PB21 (0x20 + 21)
#define AT91_PIN_PB22 (0x20 + 22)
#define AT91_PIN_PB23 (0x20 + 23)
#define AT91_PIN_PB24 (0x20 + 24)
#define AT91_PIN_PB25 (0x20 + 25)
#define AT91_PIN_PB26 (0x20 + 26)
#define AT91_PIN_PB27 (0x20 + 27)
#define AT91_PIN_PB28 (0x20 + 28)
#define AT91_PIN_PB29 (0x20 + 29)
#define AT91_PIN_PB30 (0x20 + 30)
#define AT91_PIN_PB31 (0x20 + 31)
#define AT91_PIN_PC0 (0x40 + 0)
#define AT91_PIN_PC1 (0x40 + 1)
#define AT91_PIN_PC2 (0x40 + 2)
#define AT91_PIN_PC3 (0x40 + 3)
#define AT91_PIN_PC4 (0x40 + 4)
#define AT91_PIN_PC5 (0x40 + 5)
#define AT91_PIN_PC6 (0x40 + 6)
#define AT91_PIN_PC7 (0x40 + 7)
#define AT91_PIN_PC8 (0x40 + 8)
#define AT91_PIN_PC9 (0x40 + 9)
#define AT91_PIN_PC10 (0x40 + 10)
#define AT91_PIN_PC11 (0x40 + 11)
#define AT91_PIN_PC12 (0x40 + 12)
#define AT91_PIN_PC13 (0x40 + 13)
#define AT91_PIN_PC14 (0x40 + 14)
#define AT91_PIN_PC15 (0x40 + 15)
#define AT91_PIN_PC16 (0x40 + 16)
#define AT91_PIN_PC17 (0x40 + 17)
#define AT91_PIN_PC18 (0x40 + 18)
#define AT91_PIN_PC19 (0x40 + 19)
#define AT91_PIN_PC20 (0x40 + 20)
#define AT91_PIN_PC21 (0x40 + 21)
#define AT91_PIN_PC22 (0x40 + 22)
#define AT91_PIN_PC23 (0x40 + 23)
#define AT91_PIN_PC24 (0x40 + 24)
#define AT91_PIN_PC25 (0x40 + 25)
#define AT91_PIN_PC26 (0x40 + 26)
#define AT91_PIN_PC27 (0x40 + 27)
#define AT91_PIN_PC28 (0x40 + 28)
#define AT91_PIN_PC29 (0x40 + 29)
#define AT91_PIN_PC30 (0x40 + 30)
#define AT91_PIN_PC31 (0x40 + 31)
#define AT91_PIN_PD0 (0x60 + 0)
#define AT91_PIN_PD1 (0x60 + 1)
#define AT91_PIN_PD2 (0x60 + 2)
#define AT91_PIN_PD3 (0x60 + 3)
#define AT91_PIN_PD4 (0x60 + 4)
#define AT91_PIN_PD5 (0x60 + 5)
#define AT91_PIN_PD6 (0x60 + 6)
#define AT91_PIN_PD7 (0x60 + 7)
#define AT91_PIN_PD8 (0x60 + 8)
#define AT91_PIN_PD9 (0x60 + 9)
#define AT91_PIN_PD10 (0x60 + 10)
#define AT91_PIN_PD11 (0x60 + 11)
#define AT91_PIN_PD12 (0x60 + 12)
#define AT91_PIN_PD13 (0x60 + 13)
#define AT91_PIN_PD14 (0x60 + 14)
#define AT91_PIN_PD15 (0x60 + 15)
#define AT91_PIN_PD16 (0x60 + 16)
#define AT91_PIN_PD17 (0x60 + 17)
#define AT91_PIN_PD18 (0x60 + 18)
#define AT91_PIN_PD19 (0x60 + 19)
#define AT91_PIN_PD20 (0x60 + 20)
#define AT91_PIN_PD21 (0x60 + 21)
#define AT91_PIN_PD22 (0x60 + 22)
#define AT91_PIN_PD23 (0x60 + 23)
#define AT91_PIN_PD24 (0x60 + 24)
#define AT91_PIN_PD25 (0x60 + 25)
#define AT91_PIN_PD26 (0x60 + 26)
#define AT91_PIN_PD27 (0x60 + 27)
#define AT91_PIN_PD28 (0x60 + 28)
#define AT91_PIN_PD29 (0x60 + 29)
#define AT91_PIN_PD30 (0x60 + 30)
#define AT91_PIN_PD31 (0x60 + 31)
#define AT91_PIN_PE0 (0x80 + 0)
#define AT91_PIN_PE1 (0x80 + 1)
#define AT91_PIN_PE2 (0x80 + 2)
#define AT91_PIN_PE3 (0x80 + 3)
#define AT91_PIN_PE4 (0x80 + 4)
#define AT91_PIN_PE5 (0x80 + 5)
#define AT91_PIN_PE6 (0x80 + 6)
#define AT91_PIN_PE7 (0x80 + 7)
#define AT91_PIN_PE8 (0x80 + 8)
#define AT91_PIN_PE9 (0x80 + 9)
#define AT91_PIN_PE10 (0x80 + 10)
#define AT91_PIN_PE11 (0x80 + 11)
#define AT91_PIN_PE12 (0x80 + 12)
#define AT91_PIN_PE13 (0x80 + 13)
#define AT91_PIN_PE14 (0x80 + 14)
#define AT91_PIN_PE15 (0x80 + 15)
#define AT91_PIN_PE16 (0x80 + 16)
#define AT91_PIN_PE17 (0x80 + 17)
#define AT91_PIN_PE18 (0x80 + 18)
#define AT91_PIN_PE19 (0x80 + 19)
#define AT91_PIN_PE20 (0x80 + 20)
#define AT91_PIN_PE21 (0x80 + 21)
#define AT91_PIN_PE22 (0x80 + 22)
#define AT91_PIN_PE23 (0x80 + 23)
#define AT91_PIN_PE24 (0x80 + 24)
#define AT91_PIN_PE25 (0x80 + 25)
#define AT91_PIN_PE26 (0x80 + 26)
#define AT91_PIN_PE27 (0x80 + 27)
#define AT91_PIN_PE28 (0x80 + 28)
#define AT91_PIN_PE29 (0x80 + 29)
#define AT91_PIN_PE30 (0x80 + 30)
#define AT91_PIN_PE31 (0x80 + 31)
#ifndef __ASSEMBLY__
/* setup setup routines, called from board init or driver probe() */
extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
/* callable at any time */
extern int at91_set_gpio_value(unsigned pin, int value);
extern int at91_get_gpio_value(unsigned pin);
/* callable only from core power-management code */
extern void at91_gpio_suspend(void);
extern void at91_gpio_resume(void);
#endif /* __ASSEMBLY__ */
#endif
arch/arm/mach-at91/gsia18s.h deleted 100644 → 0
View file @ 3d266069
/* Buttons */
#define GPIO_TRIG_NET_IN AT91_PIN_PB21
#define GPIO_CARD_UNMOUNT_0 AT91_PIN_PB13
#define GPIO_CARD_UNMOUNT_1 AT91_PIN_PB12
#define GPIO_KEY_POWER AT91_PIN_PA25
/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
#define GS_IA18_S_PCF_GPIO_BASE0 NR_BUILTIN_GPIO
#define PCF_GPIO_HDC_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 0)
#define PCF_GPIO_WIFI_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 1)
#define PCF_GPIO_WIFI_ENABLE (GS_IA18_S_PCF_GPIO_BASE0 + 2)
#define PCF_GPIO_WIFI_RESET (GS_IA18_S_PCF_GPIO_BASE0 + 3)
#define PCF_GPIO_ETH_DETECT 4 /* this is a GPI */
#define PCF_GPIO_GPS_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 5)
#define PCF_GPIO_GPS_STANDBY (GS_IA18_S_PCF_GPIO_BASE0 + 6)
#define PCF_GPIO_GPS_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 7)
/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
#define GS_IA18_S_PCF_GPIO_BASE1 (GS_IA18_S_PCF_GPIO_BASE0 + 8)
#define PCF_GPIO_ALARM1 (GS_IA18_S_PCF_GPIO_BASE1 + 0)
#define PCF_GPIO_ALARM2 (GS_IA18_S_PCF_GPIO_BASE1 + 1)
#define PCF_GPIO_ALARM3 (GS_IA18_S_PCF_GPIO_BASE1 + 2)
#define PCF_GPIO_ALARM4 (GS_IA18_S_PCF_GPIO_BASE1 + 3)
/* bits 4, 5, 6 not used */
#define PCF_GPIO_ALARM_V_RELAY_ON (GS_IA18_S_PCF_GPIO_BASE1 + 7)
/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
#define GS_IA18_S_PCF_GPIO_BASE2 (GS_IA18_S_PCF_GPIO_BASE1 + 8)
#define PCF_GPIO_MODEM_POWER (GS_IA18_S_PCF_GPIO_BASE2 + 0)
#define PCF_GPIO_MODEM_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 3)
/* bits 1, 2, 4, 5 not used */
#define PCF_GPIO_TRX_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 6)
/* bit 7 not used */
arch/arm/mach-at91/include/mach/hardware.h
View file @ ef1dfa73
......@@ -127,13 +127,8 @@
* called as part of the generic suspend/resume path.
*/
#ifndef __ASSEMBLY__
#ifdef CONFIG_PINCTRL_AT91
extern void at91_pinctrl_gpio_suspend(void);
extern void at91_pinctrl_gpio_resume(void);
#else
static inline void at91_pinctrl_gpio_suspend(void) {}
static inline void at91_pinctrl_gpio_resume(void) {}
#endif
#endif
#endif
arch/arm/mach-at91/leds.c deleted 100644 → 0
View file @ 3d266069
/*
* LED driver for Atmel AT91-based boards.
*
* Copyright (C) SAN People (Pty) Ltd
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include "board.h"
#include "gpio.h"
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_NEW_LEDS)
/*
* New cross-platform LED support.
*/
static struct gpio_led_platform_data led_data;
static struct platform_device at91_gpio_leds_device = {
.name = "leds-gpio",
.id = -1,
.dev.platform_data = &led_data,
};
void __init at91_gpio_leds(struct gpio_led *leds, int nr)
{
int i;
if (!nr)
return;
for (i = 0; i < nr; i++)
at91_set_gpio_output(leds[i].gpio, leds[i].active_low);
led_data.leds = leds;
led_data.num_leds = nr;
platform_device_register(&at91_gpio_leds_device);
}
#else
void __init at91_gpio_leds(struct gpio_led *leds, int nr) {}
#endif
arch/arm/mach-at91/pm.c
View file @ ef1dfa73
......@@ -31,7 +31,6 @@
#include "generic.h"
#include "pm.h"
#include "gpio.h"
static void (*at91_pm_standby)(void);
......@@ -130,10 +129,7 @@ extern u32 at91_slow_clock_sz;
static int at91_pm_enter(suspend_state_t state)
{
if (of_have_populated_dt())
at91_pinctrl_gpio_suspend();
else
at91_gpio_suspend();
switch (state) {
/*
......@@ -201,10 +197,7 @@ static int at91_pm_enter(suspend_state_t state)
error:
target_state = PM_SUSPEND_ON;
if (of_have_populated_dt())
at91_pinctrl_gpio_resume();
else
at91_gpio_resume();
return 0;
}
......
arch/arm/mach-at91/setup.c
View file @ ef1dfa73
......@@ -42,31 +42,9 @@ void __init at91rm9200_set_type(int type)
at91_get_soc_subtype(&at91_soc_initdata));
}
void __init at91_init_irq_default(void)
{
at91_init_interrupts(at91_boot_soc.default_irq_priority);
}
void __init at91_init_interrupts(unsigned int *priority)
{
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
void __iomem *at91_ramc_base[2];
EXPORT_SYMBOL_GPL(at91_ramc_base);
void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
{
if (id < 0 || id > 1) {
pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
BUG();
}
at91_ramc_base[id] = ioremap(addr, size);
if (!at91_ramc_base[id])
panic(pr_fmt("Impossible to ioremap ramc.%d 0x%x\n"), id, addr);
}
static struct map_desc sram_desc[2] __initdata;
void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
......@@ -414,7 +392,6 @@ void __init at91_ioremap_matrix(u32 base_addr)
panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
}
#if defined(CONFIG_OF)
static struct of_device_id ramc_ids[] = {
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
......@@ -456,10 +433,6 @@ void __init at91rm9200_dt_initialize(void)
{
at91_dt_ramc();
/* Register the processor-specific clocks */
if (at91_boot_soc.register_clocks)
at91_boot_soc.register_clocks();
at91_boot_soc.init();
}
......@@ -467,33 +440,6 @@ void __init at91_dt_initialize(void)
{
at91_dt_ramc();
/* Register the processor-specific clocks */
if (at91_boot_soc.register_clocks)
at91_boot_soc.register_clocks();
if (at91_boot_soc.init)
at91_boot_soc.init();
}
#endif
void __init at91_initialize(unsigned long main_clock)
{
at91_boot_soc.ioremap_registers();
/* Register the processor-specific clocks */
at91_boot_soc.register_clocks();
at91_boot_soc.init();
pinctrl_provide_dummies();
}
void __init at91_register_devices(void)
{
at91_boot_soc.register_devices();
}
void __init at91_init_time(void)
{
at91_boot_soc.init_time();
}
arch/arm/mach-at91/soc.h
View file @ ef1dfa73
......@@ -6,14 +6,8 @@
struct at91_init_soc {
int builtin;
u32 extern_irq;
unsigned int *default_irq_priority;
void (*map_io)(void);
void (*ioremap_registers)(void);
void (*register_clocks)(void);
void (*register_devices)(void);
void (*init)(void);
void (*init_time)(void);
};
extern struct at91_init_soc at91_boot_soc;
......
drivers/clocksource/timer-atmel-pit.c
View file @ ef1dfa73
......@@ -262,35 +262,3 @@ static void __init at91sam926x_pit_dt_init(struct device_node *node)
}
CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
at91sam926x_pit_dt_init);
static void __iomem *pit_base_addr;
void __init at91sam926x_pit_init(int irq)
{
struct pit_data *data;
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
panic(pr_fmt("Unable to allocate memory\n"));
data->base = pit_base_addr;
data->mck = clk_get(NULL, "mck");
if (IS_ERR(data->mck))
panic(pr_fmt("Unable to get mck clk\n"));
data->irq = irq;
at91sam926x_pit_common_init(data);
}
void __init at91sam926x_ioremap_pit(u32 addr)
{
if (of_have_populated_dt())
return;
pit_base_addr = ioremap(addr, 16);
if (!pit_base_addr)
panic(pr_fmt("Impossible to ioremap PIT\n"));
}
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