Commit f34c48e0 authored by Dave Airlie's avatar Dave Airlie

Merge branch 'drm-fixes-5.0' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

- Powerplay fixes
- Virtual display pinning fixes
- Golden register updates for vega
- Pitch and gem size validation fixes
- Fix for error case in sr-iov init
- Disable page tables in system memory on RV due to issues with IOMMU
  reported on some platforms
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190109204336.3315-1-alexander.deucher@amd.com
parents bd86c9e6 1c1eba86
...@@ -1701,8 +1701,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) ...@@ -1701,8 +1701,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
amdgpu_xgmi_add_device(adev); amdgpu_xgmi_add_device(adev);
amdgpu_amdkfd_device_init(adev); amdgpu_amdkfd_device_init(adev);
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev)) {
amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true); amdgpu_virt_release_full_gpu(adev, true);
}
return 0; return 0;
} }
...@@ -2632,9 +2634,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, ...@@ -2632,9 +2634,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
goto failed; goto failed;
} }
if (amdgpu_sriov_vf(adev))
amdgpu_virt_init_data_exchange(adev);
amdgpu_fbdev_init(adev); amdgpu_fbdev_init(adev);
r = amdgpu_pm_sysfs_init(adev); r = amdgpu_pm_sysfs_init(adev);
...@@ -2798,7 +2797,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) ...@@ -2798,7 +2797,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
struct drm_framebuffer *fb = crtc->primary->fb; struct drm_framebuffer *fb = crtc->primary->fb;
struct amdgpu_bo *robj; struct amdgpu_bo *robj;
if (amdgpu_crtc->cursor_bo) { if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
r = amdgpu_bo_reserve(aobj, true); r = amdgpu_bo_reserve(aobj, true);
if (r == 0) { if (r == 0) {
...@@ -2906,7 +2905,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) ...@@ -2906,7 +2905,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
if (amdgpu_crtc->cursor_bo) { if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
r = amdgpu_bo_reserve(aobj, true); r = amdgpu_bo_reserve(aobj, true);
if (r == 0) { if (r == 0) {
...@@ -3226,6 +3225,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, ...@@ -3226,6 +3225,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
r = amdgpu_ib_ring_tests(adev); r = amdgpu_ib_ring_tests(adev);
error: error:
amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true); amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
atomic_inc(&adev->vram_lost_counter); atomic_inc(&adev->vram_lost_counter);
......
...@@ -188,11 +188,13 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, ...@@ -188,11 +188,13 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
goto cleanup; goto cleanup;
} }
if (!adev->enable_virtual_display) {
r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev)); r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
if (unlikely(r != 0)) { if (unlikely(r != 0)) {
DRM_ERROR("failed to pin new abo buffer before flip\n"); DRM_ERROR("failed to pin new abo buffer before flip\n");
goto unreserve; goto unreserve;
} }
}
r = amdgpu_ttm_alloc_gart(&new_abo->tbo); r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
if (unlikely(r != 0)) { if (unlikely(r != 0)) {
...@@ -211,6 +213,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, ...@@ -211,6 +213,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
amdgpu_bo_unreserve(new_abo); amdgpu_bo_unreserve(new_abo);
if (!adev->enable_virtual_display)
work->base = amdgpu_bo_gpu_offset(new_abo); work->base = amdgpu_bo_gpu_offset(new_abo);
work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
amdgpu_get_vblank_counter_kms(dev, work->crtc_id); amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
...@@ -242,9 +245,10 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, ...@@ -242,9 +245,10 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
goto cleanup; goto cleanup;
} }
unpin: unpin:
if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { if (!adev->enable_virtual_display)
if (unlikely(amdgpu_bo_unpin(new_abo) != 0))
DRM_ERROR("failed to unpin new abo in error path\n"); DRM_ERROR("failed to unpin new abo in error path\n");
}
unreserve: unreserve:
amdgpu_bo_unreserve(new_abo); amdgpu_bo_unreserve(new_abo);
...@@ -527,6 +531,17 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, ...@@ -527,6 +531,17 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,
struct drm_gem_object *obj; struct drm_gem_object *obj;
struct amdgpu_framebuffer *amdgpu_fb; struct amdgpu_framebuffer *amdgpu_fb;
int ret; int ret;
int height;
struct amdgpu_device *adev = dev->dev_private;
int cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
int pitch = mode_cmd->pitches[0] / cpp;
pitch = amdgpu_align_pitch(adev, pitch, cpp, false);
if (mode_cmd->pitches[0] != pitch) {
DRM_DEBUG_KMS("Invalid pitch: expecting %d but got %d\n",
pitch, mode_cmd->pitches[0]);
return ERR_PTR(-EINVAL);
}
obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
if (obj == NULL) { if (obj == NULL) {
...@@ -541,6 +556,13 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, ...@@ -541,6 +556,13 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,
return ERR_PTR(-EINVAL); return ERR_PTR(-EINVAL);
} }
height = ALIGN(mode_cmd->height, 8);
if (obj->size < pitch * height) {
DRM_DEBUG_KMS("Invalid GEM size: expecting >= %d but got %zu\n",
pitch * height, obj->size);
return ERR_PTR(-EINVAL);
}
amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
if (amdgpu_fb == NULL) { if (amdgpu_fb == NULL) {
drm_gem_object_put_unlocked(obj); drm_gem_object_put_unlocked(obj);
......
...@@ -2008,6 +2008,7 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev) ...@@ -2008,6 +2008,7 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
{ {
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret; int ret;
if (adev->pm.sysfs_initialized) if (adev->pm.sysfs_initialized)
...@@ -2091,6 +2092,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) ...@@ -2091,6 +2092,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
"pp_power_profile_mode\n"); "pp_power_profile_mode\n");
return ret; return ret;
} }
if (hwmgr->od_enabled) {
ret = device_create_file(adev->dev, ret = device_create_file(adev->dev,
&dev_attr_pp_od_clk_voltage); &dev_attr_pp_od_clk_voltage);
if (ret) { if (ret) {
...@@ -2098,6 +2100,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) ...@@ -2098,6 +2100,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
"pp_od_clk_voltage\n"); "pp_od_clk_voltage\n");
return ret; return ret;
} }
}
ret = device_create_file(adev->dev, ret = device_create_file(adev->dev,
&dev_attr_gpu_busy_percent); &dev_attr_gpu_busy_percent);
if (ret) { if (ret) {
...@@ -2118,6 +2121,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) ...@@ -2118,6 +2121,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
{ {
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
if (adev->pm.dpm_enabled == 0) if (adev->pm.dpm_enabled == 0)
return; return;
...@@ -2138,6 +2143,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) ...@@ -2138,6 +2143,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
device_remove_file(adev->dev, &dev_attr_pp_mclk_od); device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
device_remove_file(adev->dev, device_remove_file(adev->dev,
&dev_attr_pp_power_profile_mode); &dev_attr_pp_power_profile_mode);
if (hwmgr->od_enabled)
device_remove_file(adev->dev, device_remove_file(adev->dev,
&dev_attr_pp_od_clk_voltage); &dev_attr_pp_od_clk_voltage);
device_remove_file(adev->dev, &dev_attr_gpu_busy_percent); device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
......
...@@ -847,9 +847,6 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, ...@@ -847,9 +847,6 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
bp->size = amdgpu_vm_bo_size(adev, level); bp->size = amdgpu_vm_bo_size(adev, level);
bp->byte_align = AMDGPU_GPU_PAGE_SIZE; bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
bp->domain = AMDGPU_GEM_DOMAIN_VRAM; bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
if (bp->size <= PAGE_SIZE && adev->asic_type >= CHIP_VEGA10 &&
adev->flags & AMD_IS_APU)
bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain); bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC; AMDGPU_GEM_CREATE_CPU_GTT_USWC;
......
...@@ -167,19 +167,6 @@ static void dce_virtual_crtc_disable(struct drm_crtc *crtc) ...@@ -167,19 +167,6 @@ static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
if (crtc->primary->fb) {
int r;
struct amdgpu_bo *abo;
abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
r = amdgpu_bo_reserve(abo, true);
if (unlikely(r))
DRM_ERROR("failed to reserve abo before unpin\n");
else {
amdgpu_bo_unpin(abo);
amdgpu_bo_unreserve(abo);
}
}
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
amdgpu_crtc->encoder = NULL; amdgpu_crtc->encoder = NULL;
...@@ -692,7 +679,9 @@ static int dce_virtual_pageflip(struct amdgpu_device *adev, ...@@ -692,7 +679,9 @@ static int dce_virtual_pageflip(struct amdgpu_device *adev,
spin_unlock_irqrestore(&adev->ddev->event_lock, flags); spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
drm_crtc_vblank_put(&amdgpu_crtc->base); drm_crtc_vblank_put(&amdgpu_crtc->base);
schedule_work(&works->unpin_work); amdgpu_bo_unref(&works->old_abo);
kfree(works->shared);
kfree(works);
return 0; return 0;
} }
......
...@@ -4233,7 +4233,6 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) ...@@ -4233,7 +4233,6 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
u32 tmp; u32 tmp;
u32 rb_bufsz; u32 rb_bufsz;
u64 rb_addr, rptr_addr, wptr_gpu_addr; u64 rb_addr, rptr_addr, wptr_gpu_addr;
int r;
/* Set the write pointer delay */ /* Set the write pointer delay */
WREG32(mmCP_RB_WPTR_DELAY, 0); WREG32(mmCP_RB_WPTR_DELAY, 0);
...@@ -4278,9 +4277,8 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) ...@@ -4278,9 +4277,8 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
amdgpu_ring_clear_ring(ring); amdgpu_ring_clear_ring(ring);
gfx_v8_0_cp_gfx_start(adev); gfx_v8_0_cp_gfx_start(adev);
ring->sched.ready = true; ring->sched.ready = true;
r = amdgpu_ring_test_helper(ring);
return r; return 0;
} }
static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
...@@ -4369,10 +4367,9 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev) ...@@ -4369,10 +4367,9 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
} }
r = amdgpu_ring_test_helper(kiq_ring); amdgpu_ring_commit(kiq_ring);
if (r)
DRM_ERROR("KCQ enable failed\n"); return 0;
return r;
} }
static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req) static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
...@@ -4709,16 +4706,32 @@ static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev) ...@@ -4709,16 +4706,32 @@ static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
if (r) if (r)
goto done; goto done;
/* Test KCQs - reversing the order of rings seems to fix ring test failure done:
* after GPU reset return r;
*/ }
for (i = adev->gfx.num_compute_rings - 1; i >= 0; i--) {
ring = &adev->gfx.compute_ring[i]; static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)
{
int r, i;
struct amdgpu_ring *ring;
/* collect all the ring_tests here, gfx, kiq, compute */
ring = &adev->gfx.gfx_ring[0];
r = amdgpu_ring_test_helper(ring); r = amdgpu_ring_test_helper(ring);
} if (r)
return r;
done: ring = &adev->gfx.kiq.ring;
r = amdgpu_ring_test_helper(ring);
if (r)
return r; return r;
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
amdgpu_ring_test_helper(ring);
}
return 0;
} }
static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
...@@ -4739,6 +4752,11 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) ...@@ -4739,6 +4752,11 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
r = gfx_v8_0_kcq_resume(adev); r = gfx_v8_0_kcq_resume(adev);
if (r) if (r)
return r; return r;
r = gfx_v8_0_cp_test_all_rings(adev);
if (r)
return r;
gfx_v8_0_enable_gui_idle_interrupt(adev, true); gfx_v8_0_enable_gui_idle_interrupt(adev, true);
return 0; return 0;
...@@ -5086,6 +5104,8 @@ static int gfx_v8_0_post_soft_reset(void *handle) ...@@ -5086,6 +5104,8 @@ static int gfx_v8_0_post_soft_reset(void *handle)
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX)) REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
gfx_v8_0_cp_gfx_resume(adev); gfx_v8_0_cp_gfx_resume(adev);
gfx_v8_0_cp_test_all_rings(adev);
adev->gfx.rlc.funcs->start(adev); adev->gfx.rlc.funcs->start(adev);
return 0; return 0;
......
...@@ -113,7 +113,10 @@ static const struct soc15_reg_golden golden_settings_gc_9_0[] = ...@@ -113,7 +113,10 @@ static const struct soc15_reg_golden golden_settings_gc_9_0[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
}; };
static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
...@@ -135,10 +138,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = ...@@ -135,10 +138,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
}; };
static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
...@@ -3587,6 +3587,8 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev ...@@ -3587,6 +3587,8 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
{ {
uint32_t data, def; uint32_t data, def;
amdgpu_gfx_rlc_enter_safe_mode(adev);
/* It is disabled by HW by default */ /* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 1 - RLC_CGTT_MGCG_OVERRIDE */ /* 1 - RLC_CGTT_MGCG_OVERRIDE */
...@@ -3651,6 +3653,8 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev ...@@ -3651,6 +3653,8 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
} }
} }
amdgpu_gfx_rlc_exit_safe_mode(adev);
} }
static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
......
...@@ -174,7 +174,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev, ...@@ -174,7 +174,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
return r; return r;
} }
/* Retrieve checksum from mailbox2 */ /* Retrieve checksum from mailbox2 */
if (req == IDH_REQ_GPU_INIT_ACCESS) { if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {
adev->virt.fw_reserve.checksum_key = adev->virt.fw_reserve.checksum_key =
RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2)); mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
......
...@@ -78,7 +78,6 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = { ...@@ -78,7 +78,6 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
...@@ -96,6 +95,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = { ...@@ -96,6 +95,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = {
static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
}; };
...@@ -103,6 +103,7 @@ static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { ...@@ -103,6 +103,7 @@ static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
}; };
......
...@@ -127,12 +127,13 @@ enum amd_pp_task { ...@@ -127,12 +127,13 @@ enum amd_pp_task {
}; };
enum PP_SMC_POWER_PROFILE { enum PP_SMC_POWER_PROFILE {
PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x0, PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
PP_SMC_POWER_PROFILE_POWERSAVING = 0x1, PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
PP_SMC_POWER_PROFILE_VIDEO = 0x2, PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
PP_SMC_POWER_PROFILE_VR = 0x3, PP_SMC_POWER_PROFILE_VIDEO = 0x3,
PP_SMC_POWER_PROFILE_COMPUTE = 0x4, PP_SMC_POWER_PROFILE_VR = 0x4,
PP_SMC_POWER_PROFILE_CUSTOM = 0x5, PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
}; };
enum { enum {
......
...@@ -64,17 +64,19 @@ static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr); ...@@ -64,17 +64,19 @@ static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr) static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
{ {
hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2; hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0; hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1; hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3; hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4; hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO; hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR; hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE; hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
} }
int hwmgr_early_init(struct pp_hwmgr *hwmgr) int hwmgr_early_init(struct pp_hwmgr *hwmgr)
......
...@@ -77,8 +77,9 @@ ...@@ -77,8 +77,9 @@
#define PCIE_BUS_CLK 10000 #define PCIE_BUS_CLK 10000
#define TCLK (PCIE_BUS_CLK / 10) #define TCLK (PCIE_BUS_CLK / 10)
static const struct profile_mode_setting smu7_profiling[6] = static const struct profile_mode_setting smu7_profiling[7] =
{{1, 0, 100, 30, 1, 0, 100, 10}, {{0, 0, 0, 0, 0, 0, 0, 0},
{1, 0, 100, 30, 1, 0, 100, 10},
{1, 10, 0, 30, 0, 0, 0, 0}, {1, 10, 0, 30, 0, 0, 0, 0},
{0, 0, 0, 0, 1, 10, 16, 31}, {0, 0, 0, 0, 1, 10, 16, 31},
{1, 0, 11, 50, 1, 0, 100, 10}, {1, 0, 11, 50, 1, 0, 100, 10},
...@@ -4889,7 +4890,8 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) ...@@ -4889,7 +4890,8 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
uint32_t i, size = 0; uint32_t i, size = 0;
uint32_t len; uint32_t len;
static const char *profile_name[6] = {"3D_FULL_SCREEN", static const char *profile_name[7] = {"BOOTUP_DEFAULT",
"3D_FULL_SCREEN",
"POWER_SAVING", "POWER_SAVING",
"VIDEO", "VIDEO",
"VR", "VR",
......
...@@ -804,9 +804,9 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) ...@@ -804,9 +804,9 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->backend = data; hwmgr->backend = data;
hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO]; hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO; hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO; hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
vega10_set_default_registry_data(hwmgr); vega10_set_default_registry_data(hwmgr);
data->disable_dpm_mask = 0xff; data->disable_dpm_mask = 0xff;
...@@ -4668,13 +4668,15 @@ static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) ...@@ -4668,13 +4668,15 @@ static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
{ {
struct vega10_hwmgr *data = hwmgr->backend; struct vega10_hwmgr *data = hwmgr->backend;
uint32_t i, size = 0; uint32_t i, size = 0;
static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,}, static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,},
{70, 60, 1, 3,},
{90, 60, 0, 0,}, {90, 60, 0, 0,},
{70, 60, 0, 0,}, {70, 60, 0, 0,},
{70, 90, 0, 0,}, {70, 90, 0, 0,},
{30, 60, 0, 6,}, {30, 60, 0, 6,},
}; };
static const char *profile_name[6] = {"3D_FULL_SCREEN", static const char *profile_name[7] = {"BOOTUP_DEFAULT",
"3D_FULL_SCREEN",
"POWER_SAVING", "POWER_SAVING",
"VIDEO", "VIDEO",
"VR", "VR",
......
...@@ -390,9 +390,9 @@ static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr) ...@@ -390,9 +390,9 @@ static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->backend = data; hwmgr->backend = data;
hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO]; hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO; hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO; hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
vega20_set_default_registry_data(hwmgr); vega20_set_default_registry_data(hwmgr);
...@@ -980,6 +980,9 @@ static int vega20_od8_set_feature_capabilities( ...@@ -980,6 +980,9 @@ static int vega20_od8_set_feature_capabilities(
pp_table->FanZeroRpmEnable) pp_table->FanZeroRpmEnable)
od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL; od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
if (!od_settings->overdrive8_capabilities)
hwmgr->od_enabled = false;
return 0; return 0;
} }
...@@ -1689,13 +1692,6 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_ ...@@ -1689,13 +1692,6 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_
(PPCLK_UCLK << 16) | (min_freq & 0xffff))), (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
"Failed to set soft min memclk !", "Failed to set soft min memclk !",
return ret); return ret);
min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
hwmgr, PPSMC_MSG_SetHardMinByFreq,
(PPCLK_UCLK << 16) | (min_freq & 0xffff))),
"Failed to set hard min memclk !",
return ret);
} }
if (data->smu_features[GNLD_DPM_UVD].enabled && if (data->smu_features[GNLD_DPM_UVD].enabled &&
...@@ -2248,6 +2244,13 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr, ...@@ -2248,6 +2244,13 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
soft_min_level = mask ? (ffs(mask) - 1) : 0; soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0; soft_max_level = mask ? (fls(mask) - 1) : 0;
if (soft_max_level >= data->dpm_table.gfx_table.count) {
pr_err("Clock level specified %d is over max allowed %d\n",
soft_max_level,
data->dpm_table.gfx_table.count - 1);
return -EINVAL;
}
data->dpm_table.gfx_table.dpm_state.soft_min_level = data->dpm_table.gfx_table.dpm_state.soft_min_level =
data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
data->dpm_table.gfx_table.dpm_state.soft_max_level = data->dpm_table.gfx_table.dpm_state.soft_max_level =
...@@ -2268,6 +2271,13 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr, ...@@ -2268,6 +2271,13 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
soft_min_level = mask ? (ffs(mask) - 1) : 0; soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0; soft_max_level = mask ? (fls(mask) - 1) : 0;
if (soft_max_level >= data->dpm_table.mem_table.count) {
pr_err("Clock level specified %d is over max allowed %d\n",
soft_max_level,
data->dpm_table.mem_table.count - 1);
return -EINVAL;
}
data->dpm_table.mem_table.dpm_state.soft_min_level = data->dpm_table.mem_table.dpm_state.soft_min_level =
data->dpm_table.mem_table.dpm_levels[soft_min_level].value; data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
data->dpm_table.mem_table.dpm_state.soft_max_level = data->dpm_table.mem_table.dpm_state.soft_max_level =
...@@ -3261,6 +3271,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile) ...@@ -3261,6 +3271,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)
int pplib_workload = 0; int pplib_workload = 0;
switch (power_profile) { switch (power_profile) {
case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
pplib_workload = WORKLOAD_DEFAULT_BIT;
break;
case PP_SMC_POWER_PROFILE_FULLSCREEN3D: case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
break; break;
...@@ -3290,6 +3303,7 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) ...@@ -3290,6 +3303,7 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
uint32_t i, size = 0; uint32_t i, size = 0;
uint16_t workload_type = 0; uint16_t workload_type = 0;
static const char *profile_name[] = { static const char *profile_name[] = {
"BOOTUP_DEFAULT",
"3D_FULL_SCREEN", "3D_FULL_SCREEN",
"POWER_SAVING", "POWER_SAVING",
"VIDEO", "VIDEO",
......
...@@ -705,7 +705,7 @@ enum PP_TABLE_VERSION { ...@@ -705,7 +705,7 @@ enum PP_TABLE_VERSION {
/** /**
* The main hardware manager structure. * The main hardware manager structure.
*/ */
#define Workload_Policy_Max 5 #define Workload_Policy_Max 6
struct pp_hwmgr { struct pp_hwmgr {
void *adev; void *adev;
......
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