drm/amd/display: move number of memory channel calc out of pplib call

Move number of memory channel calculation out of dcn_bw_update_from_pplib

Fill in fabric_and_dram_bandwidth for single channel case.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

@@ -1215,10 +1215,6 @@ void dcn_bw_update_from_pplib(struct core_dc *dc)
 	struct dm_pp_clock_levels_with_voltage clks2 = {0};
 
 	kernel_fpu_begin();
-	dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
-	ASSERT(dc->dcn_soc.number_of_channels && dc->dcn_soc.number_of_channels < 3);
-	if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/
-		dc->dcn_soc.number_of_channels = 2;
 
 	if (dm_pp_get_clock_levels_by_type_with_voltage(
 				ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, &clks2) &&

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

@@ -1358,6 +1358,19 @@ static bool construct(
 	dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
 	dc->dcn_ip = dcn10_ip_defaults;
 	dc->dcn_soc = dcn10_soc_defaults;
+
+	dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
+	ASSERT(dc->dcn_soc.number_of_channels < 3);
+	if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/
+		dc->dcn_soc.number_of_channels = 2;
+
+	if (dc->dcn_soc.number_of_channels == 1) {
+		dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
+		dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
+		dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
+		dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
+	}
+
 	if (!dc->public.debug.disable_pplib_clock_request)
 		dcn_bw_update_from_pplib(dc);
 	dcn_bw_sync_calcs_and_dml(dc);